A method, a processor, an electronic device, and a storage medium for performing FFT

Abstract

An embodiment of the present invention provides a method, a processor, an electronic device, and a storage medium for performing FFT. The method includes: obtaining the number of points N corresponding to the FFT operation to be performed; dividing the FFT operation into M-level operations according to the number of points N; dividing each level of the FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to the respective butterfly operation units in the FFT operation; in each level of operation, sequentially performing each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; determining the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation according to the butterfly operation output sequence corresponding to the m-th level of operation, and continuing to perform each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are completed, obtaining a result sequence corresponding to the FFT operation. The embodiment of the present invention can reduce the operation cost of FFT and improve the operation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a method for performing FFT, a processor, an electronic device, and a storage medium. Background Art

[0002] Fast Fourier Transform (FFT) is a common algorithm in digital signal processing. There are usually two ways to implement the FFT algorithm: (1) adding a heterogeneous processor or peripheral module outside the main processor to implement FFT calculation. This method is essentially customizing hardware for FFT, with low scalability and high R & D and production costs; (2) converting the FFT operation into a calculation process of several levels of multiply-accumulate, and using the Multiply Accumulate (MAC) unit inside RSIC-V for parallel operation to calculate the target value respectively. This design needs to convert the original calculation into the form of multiply-accumulate, but there are still some independent multiplications that cannot be converted, and additional division calculations need to be introduced during the conversion process, resulting in low execution efficiency. Summary of the Invention

[0003] Embodiments of the present invention provide a method for performing FFT, a processor, an electronic device, and a storage medium, which can solve the problems of high implementation cost and low execution efficiency of the FFT algorithm in related technologies.

[0004] On the one hand, embodiments of the present invention disclose a method for performing FFT, and the method includes:

[0005] Obtain the number of points N corresponding to the Fast Fourier Transform (FFT) operation to be performed;

[0006] Divide the FFT operation into M levels of operations according to the number of points N; M is the logarithm of N to the base 2;

[0007] According to the rotation factors corresponding to each butterfly operation unit in the FFT operation, divide each level of FFT operation into at least one group of butterfly operations; the rotation factors corresponding to the butterfly operation units in the same group are the same;

[0008] In each level of operation, successively perform each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence;

[0009] According to the butterfly operation output sequence corresponding to the m-th level of operation, determine the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation, and continue to perform each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are completed, to obtain the result sequence corresponding to the FFT operation; where 0 ≤ m ≤ (M - 1), and m is an integer.

[0010] Optionally, in each level of operation, according to the first input value, the second input value and the rotation factor of each butterfly operation unit, perform each group of butterfly operations in sequence to obtain a butterfly operation output sequence, including:

[0011] In each level of operation, for each group of butterfly operations, obtain the FFT instructions corresponding to each butterfly operation unit within the group; the FFT instructions carry the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs;

[0012] In the decoding stage, according to the first input value and the level m, determine the second input value and the rotation factor corresponding to the butterfly operation unit, and write the first input value, the second input value and the rotation factor into registers respectively;

[0013] In the execution stage, execute the FFT instructions to perform butterfly operations according to the first input value, the second input value and the rotation factor recorded in the registers, to obtain the first operation result and the second operation result corresponding to the butterfly operation unit, until each group of butterfly operations is completed, to obtain a butterfly operation output sequence.

[0014] Optionally, the determining the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m includes:

[0015] According to the number of points N and the level m to which the butterfly operation unit belongs, determine the first distance between the butterfly operation unit and other adjacent butterfly operation units within the group;

[0016] Determine the second input value of the butterfly operation unit according to the first input value and the first distance;

[0017] According to the number of points N and the level m to which the butterfly operation unit belongs, determine the second distance between two adjacent groups of butterfly operations in the m-th level of operation;

[0018] Determine the rotation factor corresponding to the butterfly operation unit according to the second distance.

[0019] Optionally, the determining the rotation factor corresponding to the butterfly operation unit according to the second distance includes:

[0020] Obtain the storage base address of the rotation factor corresponding to the FFT operation;

[0021] Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second distance;

[0022] Read the rotation factor corresponding to the butterfly operation unit from the memory based on the storage base address and the offset address.

[0023] Optionally, in each level of operation, according to the first input value, the second input value, and the rotation factor of each butterfly operation unit, perform each group of butterfly operations in sequence to obtain a butterfly operation output sequence, including:

[0024] In each level of operation, for each butterfly operation unit, read the first input value of the butterfly operation unit from the first register and read the second input value of the butterfly operation unit from the second register;

[0025] Calculate the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit;

[0026] Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register;

[0027] Read the rotation factor corresponding to the butterfly operation unit from the third register and read the intermediate result from the temporary register;

[0028] Perform a complex multiplication operation on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until each group of butterfly operations is completed, to obtain a butterfly operation output sequence.

[0029] Optionally, the method further includes:

[0030] In the m-th level of operation, sort the first operation result and the second operation result corresponding to the butterfly operation unit according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level of operation, to obtain a butterfly operation output sequence corresponding to the m-th level of operation.

[0031] On the other hand, an embodiment of the present invention discloses a processor for performing FFT. The processor includes an instruction fetch unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit, and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file;

[0032] The number of points N and the number of levels M corresponding to the fast Fourier transform (FFT) operation to be executed are stored in the general register file;

[0033] The decoding unit is configured to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factor corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the butterfly operation units in the same group are the same;

[0034] The FFT execution unit is configured to perform each group of butterfly operations in sequence according to the first input value, the second input value, and the rotation factor of each butterfly operation unit in each level of operation, so as to obtain a butterfly operation output sequence;

[0035] The decoding unit is further configured to determine the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation according to the butterfly operation output sequence corresponding to the m-th level of operation;

[0036] The FFT execution unit is further configured to continue to perform each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are completed, so as to obtain the result sequence corresponding to the FFT operation; where 0 ≤ m ≤ (M - 1) and m is an integer.

[0037] Optionally, the instruction reading unit is configured to obtain, for each group of butterfly operations in each level of operation, the FFT instructions corresponding to each butterfly operation unit within the group; the FFT instructions carry the first input value of the butterfly operation unit and the level number m to which the butterfly operation unit belongs;

[0038] Specifically, the decoding unit is configured to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level number m, and write the first input value, the second input value, and the rotation factor into registers respectively;

[0039] Specifically, the FFT execution unit is configured to: in the execution stage, execute the FFT instructions to perform butterfly operations according to the first input value, the second input value, and the rotation factor recorded in the registers, so as to obtain the first operation result and the second operation result corresponding to the butterfly operation unit until all groups of butterfly operations are completed, thereby obtaining a butterfly operation output sequence.

[0040] Optionally, specifically, the decoding unit is configured to:

[0041] Determine a first pitch between the butterfly operation unit and other adjacent butterfly operation units within the group according to the number of points N and the level number m to which the butterfly operation unit belongs;

[0042] Determine the second input value of the butterfly operation unit according to the first input value and the first pitch;

[0043] Determine a second pitch between two adjacent groups of butterfly operations in the m-th level of operation according to the number of points N and the level number m to which the butterfly operation unit belongs;

[0044] Determine the rotation factor corresponding to the butterfly operation unit according to the second pitch.

[0045] Optionally, the decoding unit is specifically configured to:

[0046] Obtain the storage base address of the rotation factor corresponding to the FFT operation;

[0047] Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second pitch;

[0048] Based on the storage base address and the offset address, read the rotation factor corresponding to the butterfly operation unit from the memory.

[0049] Optionally, the FFT execution unit is specifically configured to:

[0050] In each level of operation, for each butterfly operation unit, read the first input value of the butterfly operation unit from the first register and read the second input value of the butterfly operation unit from the second register;

[0051] Calculate the sum of the first input value and the second input value to obtain the first operation result corresponding to the butterfly operation unit;

[0052] Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a scratch register;

[0053] Read the rotation factor corresponding to the butterfly operation unit from the third register and read the intermediate result from the scratch register;

[0054] Perform a complex multiplication operation on the intermediate result and the rotation factor to obtain the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed, to obtain a butterfly operation output sequence.

[0055] Optionally, the memory access processing unit is configured to:

[0056] In the m-th level of operation, sort the first operation result and the second operation result corresponding to the butterfly operation unit according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level of operation, to obtain the butterfly operation output sequence corresponding to the m-th level of operation.

[0057] In another aspect, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions cause the processor to execute the foregoing method for performing FFT.

[0058] An embodiment of the present invention also discloses a readable storage medium. When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the foregoing method for performing FFT.

[0059] The embodiments of the present invention include the following advantages:

[0060] The embodiments of the present invention provide a method for performing FFT. The FFT operation can be split into M-level operations according to the number of points N of the FFT operation, and each level of FFT operation is divided into at least one group of butterfly operations. By sequentially and cyclically executing each group of butterfly operations in each level of operation, the result sequence corresponding to the FFT operation can be obtained. There is no need to customize a corresponding hardware module for the FFT operation additionally, nor is it necessary to convert the original calculation into the form of multiply-accumulate, which reduces the operation cost of the FFT and improves the operation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required to be used in the description of the embodiments of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0062] Figure 1 is a flowchart of the steps of an embodiment of a method for performing FFT according to the present invention;

[0063] Figure 2 is a data flow diagram of an FFT according to the present invention;

[0064] Figure 3 is a schematic diagram of a butterfly operation unit according to the present invention;

[0065] Figure 4 is a schematic structural diagram of a processor according to the present invention;

[0066] Figure 5 is a schematic structural diagram of an FFT execution unit according to the present invention;

[0067] Figure 6 is a block diagram of the structure of an electronic device for performing FFT provided by an example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0068] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0069] The terms "first", "second", etc. in the description and claims of the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the description and claims is used to describe the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. In the embodiments of the present invention, the term "plurality" refers to two or more, and other quantifiers are similar.

[0070] Method embodiments

[0071] Refer to Figure 1 , which shows a step flowchart of a method embodiment for performing FFT of the present invention. The method may specifically include the following steps:

[0072] Step 101, obtain the number of points N corresponding to the fast Fourier transform (FFT) operation to be performed;

[0073] Step 102, divide the FFT operation into M-level operations according to the number of points N; M is the logarithm of N to the base 2;

[0074] Step 103, divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the butterfly operation units in the same group are the same;

[0075] Step 104, in each level of operation, sequentially perform each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence;

[0076] Step 105, determine the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation according to the butterfly operation output sequence corresponding to the m-th level of operation, and continue to perform each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are completed to obtain the result sequence corresponding to the FFT operation; where 0 ≤ m ≤ (M - 1) and m is an integer.

[0077] The embodiments of the present invention can be used to perform FFT operations and can be applied to processors, such as RSIC-V processors, ASIC processors, and so on.

[0078] The FFT operation is a fast algorithm for the Discrete Fourier Transform (DFT), which is used to calculate the spectrum of a signal.

[0079] According to the definition of the FFT, for a complex sequence x of length N, after performing the FFT, a complex sequence X of length N can be obtained. The corresponding FFT calculation formula is as follows:

[0080] (1)

[0081] where k represents the serial number of the calculated complex number in the complex sequence, and can also represent the serial number of the input data x in the complex sequence x; represents the rotation factor.

[0082] Since , then , so X(k) can be expressed as:

[0083] (2)

[0084] Divide k into odd and even numbers:

[0085] = , r = 0, 1, 2, ……, (3)

[0086] According to formula (3), X(k) can be divided into two parts:

[0087] (4)

[0088] (5)

[0089] Let , , and we can get:

[0090] (6)

[0091] Referring to Figure 2 , a data flow graph of an FFT is shown. As Figure 2 shown, taking an 8-point FFT (N = 8) as an example, combined with the above formula (6), the smallest butterfly operation unit can be extracted as Figure 3 shown.

[0092] Therefore, regardless of the value of N, the FFT algorithm can ultimately be simplified to:

[0093] = x(n1) + x(n2)

[0094] = [x(n1) - x(n2)] (7)

[0095] Wherein, x(n1) represents the first input value of the butterfly operation unit, and x(n2) represents the second input value of the butterfly operation unit. represents the rotation factor corresponding to the butterfly operation unit. represents the first operation result of the butterfly operation unit. represents the second operation result of the butterfly operation unit. The first operation result corresponds to the first input value, and the second operation result corresponds to the second input value.

[0096] In the embodiments of the present application, according to the number of points N corresponding to the FFT operation to be executed, the FFT operation is divided into M - level operations, where M is the logarithm of N to the base 2, that is: M = N. Exemplarily, taking the 8 - point FFT shown in Figure 2 as an example, it can be divided into 3 - level operations.

[0097] Next, according to the rotation factors corresponding to each butterfly operation unit in the FFT operation, each level of FFT operation is divided into at least one group of butterfly operations. Among them, the rotation factors corresponding to the butterfly operation units in the same group are the same.

[0098] It should be noted that the total number of butterfly operation units included in each level of operation is the same, and is all . Taking the 8 - point FFT shown in Figure 2 as an example, the first - level operation ( Figure 2 the left - most column of butterfly operations) includes a total of 4 butterfly operation units, which are used to operate on the original input data x(0) to x(7); the second - level operation ( Figure 2 the middle column of butterfly operations) includes a total of 4 butterfly operation units, which are used to operate on the output result of the first - level operation; the third - level operation ( Figure 2 the right - most column of butterfly operations) includes a total of 4 butterfly operation units, which are used to operate on the output result of the second - level operation to obtain the final result sequence X(0) to X(7).

[0099] In the embodiments of the present invention, the butterfly operation units included in each level of operation can be grouped according to the rotation factors corresponding to each butterfly operation unit, and the butterfly operation units with the same rotation factor are divided into a group of butterfly operations.

[0100] Taking the 8 - point FFT shown in Figure 2 as an example, starting from Figure 2It can be seen that the rotation factors corresponding to the 4 butterfly operation units in the first - level operation are all different. Therefore, these 4 butterfly operation units can be divided into 4 groups, with each group containing one butterfly operation unit. The rotation factors corresponding to the first butterfly operation unit and the third butterfly operation unit in the second - level operation are the same, both being , so these two butterfly operation units can be grouped together; the rotation factors corresponding to the second butterfly operation unit and the fourth butterfly operation unit are the same, both being , so these two butterfly operation units can be grouped together. In this way, the 4 butterfly operation units in the second - level operation are divided into 2 groups of butterfly operations. The rotation factors corresponding to the 4 butterfly operation units in the third - level operation are all the same, so these 4 butterfly operation units can be grouped together.

[0101] Furthermore, the number of groups of butterfly operation groups included in each level of operation can be determined according to the number of points N of the FFT and the current operation level m.

[0102] Exemplarily, the number of butterfly operation units included in each group of butterfly operations can be: Num_of_Group = , where m is the level to which the butterfly operation currently belongs, and 0 ≤ m ≤ (M - 1). Each level of operation contains butterfly operation units. Therefore, in the m - th level of operation, when dividing each butterfly operation unit according to the rotation factor, the number of groups of butterfly operations obtained is: .

[0103] Taking an 8 - point FFT as an example, it can be divided into 3 levels of operation. In the first - level operation, m = 0, and it contains 4 ( =1) groups of butterfly operations; in the second - level operation, m = 1, and it contains 2 ( =2) groups of butterfly operations; in the third - level operation, m = 2, and it contains 1 ( =4) group of butterfly operations.

[0104] Then, these M levels of operation are executed in a loop: in each level of operation, according to the first input value, the second input value, and the rotation factor of each butterfly operation unit, each butterfly operation unit in each group of butterfly operations is executed in sequence. After all the groups of butterfly operations in the current level of operation are executed, the butterfly operation output sequence corresponding to the current level of operation is obtained.

[0105] It should be noted that in the embodiments of the present invention, the output sequence of the butterfly operation corresponding to the m-th level of operation is the input sequence of the butterfly operation corresponding to the (m + 1)-th level of operation. Therefore, after the m-th level of operation is executed, according to the output sequence of the butterfly operation corresponding to the m-th level of operation, determine the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation, and continue to execute each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are executed, and the result sequence corresponding to the FFT operation is obtained.

[0106] It can be understood that the number of points N, the scaling factor, and the memory access address of the data block of the FFT operation are relatively fixed, and general registers in the general register file can be opened for the FFT operation to store these parameters. Further, in the decoding stage, the first input value, the second input value, and the rotation factor of the current butterfly operation unit can be written into the register, and in the execution stage, the first input value, the second input value, and the rotation factor are read from the register for the butterfly operation.

[0107] As an example, the FFT instruction corresponding to the butterfly operation unit can carry the first input value, the second input value, the rotation factor, and an operation code indicating the butterfly operation. In the decoding stage, the FFT instruction is parsed, and the first input value, the second input value, and the rotation factor are written into the register; in the execution stage, the FFT execution is performed to perform the butterfly operation according to the first input value, the second input value, and the rotation factor.

[0108] As another example, the second input value and the rotation factor of the butterfly operation unit are both related to the first input value and the level m corresponding to the current butterfly operation unit. Therefore, the FFT instruction corresponding to the butterfly operation unit can carry the first input value, the corresponding level m, and an operation code indicating the butterfly operation. In the decoding stage, the FFT instruction is parsed, the second input value and the rotation factor are determined according to the first input value and the corresponding level m, and the first input value, the second input value, and the rotation factor are written into the register; in the execution stage, the FFT execution is performed to perform the butterfly operation according to the first input value, the second input value, and the rotation factor. Among them, the second input value can be determined according to the first input value and the distance between the butterfly operation unit and other adjacent butterfly operation units in the group; the rotation factor can be determined according to the distance between groups in each level.

[0109] It should be noted that the specific operation process of performing the butterfly operation according to the first input value, the second input value, and the rotation factor can refer to the foregoing formula (7), where x(n1) can represent the first input value, x(n2) represents the second input value, represents the rotation factor, represents the first operation result corresponding to the butterfly operation unit, Represents the second operation result corresponding to the butterfly operation unit.

[0110] Taking Figure 2 The 8-point FFT shown as an example, denote the output sequence of the butterfly operation corresponding to the first-level operation as y(0) to y(7), the output sequence of the butterfly operation corresponding to the second-level operation as z(0) to z(7), and the output sequence of the butterfly operation corresponding to the third-level operation, that is, the result sequence corresponding to the FFT operation as X(0) to X(7). Performing the FFT operation according to the embodiments of the present invention, the operation process is as follows:

[0111] In the first-level operation, 4 groups of butterfly operations are sequentially performed. Each group of butterfly operations contains one butterfly operation unit. The operation processes of each butterfly operation unit are as follows:

[0112] 1. y(0) = x(0) + x(4), y(4) = [x(0) - x(4)]

[0113] 2. y(1) = x(1) + x(5), y(5) = [x(1) - x(5)]

[0114] 3. y(2) = x(2) + x(6), y(4) = [x(2) - x(6)]

[0115] 4. y(3) = x(3) + x(7), y(4) = [x(3) - x(7)]

[0116] In the second-level operation, 2 groups of butterfly operations are sequentially performed. Each group of butterfly operations contains 2 butterfly operation units. Among them, the operation processes of the 2 butterfly operation units in the first group are as follows:

[0117] 1. z(0) = y(0) + y(2), z(2) = [y(0) - y(2)]

[0118] 2. z(4) = y(4) + y(6), z(6) = [y(4) - y(6)]

[0119] In the second-level operation, the operation processes of the 2 butterfly operation units in the second group are as follows:

[0120] 1. z(1) = y(1) + y(3), z(3) = [y(1) - y(3)]

[0121] 2. z(5) = y(5) + y(7), z(7) = [y(5) - y(7)]

[0122] In the third - level operation, 4 butterfly operation units are grouped into a set of butterfly operations. The operation processes of each butterfly operation unit are as follows:

[0123] 1. X(0) = z(0)+z(1), X(4) = [z(0)-z(1)]

[0124] 2. X(2) = z(2)+z(3), X(6) = [z(2)-z(3)]

[0125] 3. X(1) = z(4)+z(5), X(5) = [z(4)-z(5)]

[0126] 4. X(3) = z(6)+z(7), X(7) = [z(6)-z(7)]

[0127] After the third - level operation is completed, the result sequence corresponding to the 8 - point FFT can be obtained.

[0128] In the embodiment of the present invention, by splitting the FFT operation into M - level operations, and according to the rotation factors corresponding to each butterfly operation unit, each butterfly operation unit in each level of FFT operation is divided into at least one set of butterfly operations. By sequentially and circularly executing each set of butterfly operations in each level of operation, the result sequence corresponding to the FFT operation can be obtained. There is no need to customize a corresponding hardware module for the FFT operation additionally, nor is it necessary to convert the original calculation into the form of multiply - accumulate, which reduces the operation cost of the FFT and improves the operation efficiency.

[0129] Furthermore, in the embodiment of the present invention, the FFT execution unit for executing the FFT operation can be tightly coupled with the processor core. Referring to Figure 4 , a schematic structural diagram of a processor provided by the embodiment of the present invention is shown. As Figure 4 shown, the processor includes an instruction fetch unit, a decoding unit, a general - purpose register file, an FFT execution unit, a memory access processing unit, and a data storage unit.

[0130] Among them, the FFT execution unit and the memory access processing unit share a general register file, and the number of points N and the number of levels M corresponding to the fast Fourier transform (FFT) operation to be executed are stored in the general register file. The decoding unit is used to determine the first input value, the second input value, and the rotation factor of each butterfly operation unit; and transmit the first input value, the second input value, and the rotation factor to the corresponding registers of the FFT execution unit. The FFT execution unit is used to sequentially execute each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit in each level of operation. The memory access processing unit is used to write the operation result corresponding to the butterfly operation unit into the data storage unit until all M levels of operations are completed, and the result sequence corresponding to the FFT operation is obtained.

[0131] Taking the RISC processor as an example, the processor may further include an ALU execution processing unit for executing ALU instructions. ALU instructions are mainly used to perform operations on two registers or one register and a sign extension processing technique and store the results in a third register. It should be noted that the interaction process between the FFT execution unit and the front and back stage units (or modules) is basically the same as that of other RSIC-V execution units, such as the interaction process between the ALU execution unit and the front and back stage units.

[0132] Exemplarily, in the instruction fetch cycle (IF), the instruction fetch unit reads the FFT instruction corresponding to the butterfly operation unit to be executed from the memory. In the instruction decode / register fetch cycle (ID), the decoding unit decodes the FFT instruction, determines the first input value, the second input value, and the rotation factor corresponding to the butterfly operation unit, and transmits the first input value, the second input value, and the rotation factor to the corresponding registers of the FFT execution unit. In the execute / effective address cycle (EX), the FFT execution unit reads the first input value, the second input value, and the rotation factor from the registers, performs butterfly operations, obtains the first operation result and the second operation result, and sends the first operation result and the second operation result to the memory access processing unit. In the memory access cycle (MEM), the memory access processing unit writes the first operation result and the second operation result into the memory or registers. In the write-back cycle (WB), the data storage unit writes the program result (from the FFT execution unit or ALU operation or load instruction) into the register file.

[0133] In an alternative embodiment of the present invention, in each level of operation in step 104, sequentially executing each group of butterfly operations according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence includes:

[0134] Step S11: In each level of operation, for each group of butterfly operations, obtain the FFT instructions corresponding to each butterfly operation unit within the group; the FFT instructions carry the first input value of the butterfly operation unit and the level number m to which the butterfly operation unit belongs.

[0135] Step S12: In the decoding stage, based on the first input value and the level number m, determine the second input value and the rotation factor corresponding to the butterfly operation unit, and write the first input value, the second input value, and the rotation factor into registers respectively.

[0136] Step S13: In the execution stage, execute the FFT instructions to perform butterfly operations based on the first input value, the second input value, and the rotation factor recorded in the registers, to obtain the first operation result and the second operation result corresponding to the butterfly operation unit. Until all groups of butterfly operations are executed, obtain the butterfly operation output sequence.

[0137] The second input value and the rotation factor of the butterfly operation unit are both related to the first input value and the level number m corresponding to the current butterfly operation unit. Therefore, in the embodiments of the present invention, the FFT instructions corresponding to the butterfly operation unit may carry the first input value, the corresponding level number m, and an operation code indicating to perform a butterfly operation. In the decoding stage, parse the FFT instructions, determine the second input value and the rotation factor based on the first input value and the corresponding level number m, and write the first input value, the second input value, and the rotation factor into registers; in the execution stage, execute the FFT execution to perform butterfly operations based on the first input value, the second input value, and the rotation factor.

[0138] Among them, the second input value can be determined based on the first input value and the spacing between the first input value and the second input value in each group; the rotation factor can be determined based on the spacing between groups in each level.

[0139] It should be noted that in the related art, if an instruction in the instruction set of the multiplexed system architecture is used to complete the FFT operation, the following instructions need to be executed for one butterfly operation:

[0140] (1) Loadx(n1): Load x(n1)

[0141] (2) Loadx(n2): Load x(n2)

[0142] (3) ADD ,x(n1),x(n2): Execute =x(n1)+x(n2)

[0143] SuBx21,x(n1),x(n2): Execute x21 =x(n1)-x(n2)

[0144] loadWn: Load the rotation factor Wn

[0145] (4) Store : Store

[0146] (5) Mul , x21, Wn: Execute = [x(n1) - x(n2)] Wn

[0147] (6) Store : Store

[0148] In the embodiment of the present invention, only one FFT instruction needs to be executed to complete one butterfly operation, and there is no need to execute ADD instruction, Sub instruction and Mul instruction anymore, reducing the number of instructions executed in the FFT operation process, thereby improving the operation efficiency of FFT.

[0149] In addition, in the embodiment of the present invention, only the first input value and the stage number m to which the butterfly operation unit belongs are carried in the FFT instruction. During the decoding stage, the second input value and the rotation factor are directly determined according to the first input value and the stage number m, and the second input value and the rotation factor are transmitted to the corresponding registers of the FFT execution unit. The FFT execution unit can directly obtain the first input value, the second input value and the rotation factor from the registers during the execution stage without accessing the memory, reducing the transmission complexity of the first input value, the second input value and the rotation factor, which is beneficial to further improving the operation efficiency of FFT.

[0150] Optionally, determining the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the stage number m includes:

[0151] Step S21, determine the first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the stage number m to which the butterfly operation unit belongs;

[0152] Step S22, determine the second input value of the butterfly operation unit according to the first input value and the first spacing;

[0153] Step S23, determine the second spacing between two adjacent groups of butterfly operations in the m-th stage operation according to the number of points N and the stage number m to which the butterfly operation unit belongs;

[0154] Step S24, determine the rotation factor corresponding to the butterfly operation unit according to the second spacing.

[0155] In an embodiment of the present invention, the distance between relevant operation units in each group of butterfly operations, that is, the first distance between a butterfly operation unit and other adjacent butterfly operation units within the group, can be determined according to the number of points N of the FFT and the stage m corresponding to the current butterfly operation unit. Exemplarily, the first distance Interval_of_Unit = .

[0156] The distance between groups in each stage, that is, the second distance between two adjacent groups of butterfly operations in the m-th stage operation, can also be determined according to the number of points N of the FFT and the stage m. Exemplarily, the second distance Interval_of_Group= .

[0157] The rotation factor is related to the second distance. Exemplarily, the rotation factor = ), where i is the imaginary unit, and the function exp(x) represents the natural exponential function, that is, the exponential function with the real number e as the base. pi is a constant representing π.

[0158] Optionally, determining the rotation factor corresponding to the butterfly operation unit according to the second distance includes:

[0159] Step S31: Obtain the storage base address of the rotation factor corresponding to the FFT operation;

[0160] Step S32: Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second distance;

[0161] Step S33: Based on the storage base address and the offset address, read the rotation factor corresponding to the butterfly operation unit from the memory.

[0162] In an embodiment of the present invention, the rotation factor can be stored in any area accessible by the processor core, and the FFT execution unit can read the rotation factor corresponding to the current butterfly operation unit based on the storage base address of the rotation factor and the offset address. Specifically, the storage address of the current rotation factor = storage base address + offset address.

[0163] Among them, the offset address of the rotation factor can be determined according to the first input value of the butterfly operation unit and the second distance.

[0164] Exemplarily, the offset address of the rotation factor can be expressed as:

[0165] = )(8) )(8)

[0166] Substitute the above formula (8) into Converted to N and m representation:

[0167] (9)

[0168] where r = 0, 1, 2, ……, ( )

[0169] Optionally, in each stage of operation described in step 104, according to the first input value, the second input value, and the rotation factor of each butterfly operation unit, perform each group of butterfly operations in sequence to obtain a butterfly operation output sequence, including:

[0170] Step S41: In each stage of operation, for each butterfly operation unit, read the first input value of the butterfly operation unit from the first register and read the second input value of the butterfly operation unit from the second register;

[0171] Step S42: Calculate the sum of the first input value and the second input value to obtain the first operation result corresponding to the butterfly operation unit;

[0172] Step S43: Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in the temporary register;

[0173] Step S44: Read the rotation factor corresponding to the butterfly operation unit from the third register and read the intermediate result from the temporary register;

[0174] Step S45: Perform a complex multiplication operation on the intermediate result and the rotation factor to obtain the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

[0175] In the embodiment of the present invention, the first input value, the second input value, and the rotation factor of the butterfly operation unit can be written into the register, and each time an operation is performed, the corresponding values are read from the register for the operation. Similarly, the intermediate results of the calculation can also be temporarily stored in the register for easy reading during subsequent operations.

[0176] Refer to Figure 5 , which shows a schematic structural diagram of an FFT execution unit provided by an embodiment of the present invention. As Figure 5 shown, the FFT execution unit in the present invention may include a first register, a second register, a third register, a temporary register, an adder, a subtractor, and a complex multiplication module. Among them, the first register is used to record the first input value, the second register is used to record the second input value, the third register is used to record the rotation factor, and the temporary register is used to record the intermediate result.

[0177] As an example, when the FFT execution unit executes an FFT instruction, it first reads the first input value x(n1), the second input value x(n2), and the rotation factor of the butterfly operation unit from the first register, the second register, and the third register respectively. The first input value and the second input value are input into an adder for summation operation to obtain a first operation result. The first input value and the second input value are input into a subtractor for subtraction operation to obtain an intermediate result. , =x(n1)-x(n2). Then, the intermediate result and the rotation factor are input into a complex multiplication module for complex multiplication operation to obtain a second output result = .

[0178] Furthermore, the FFT execution unit sends the first output result and the second output result to the memory access processing unit. In the memory access cycle (MEM), the memory access processing unit writes the first operation result and the second operation result into the memory or register.

[0179] Optionally, the method further includes:

[0180] In the m-th level operation, according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation, the first operation result and the second operation result corresponding to the butterfly operation unit are sorted to obtain a butterfly operation output sequence corresponding to the m-th level operation.

[0181] It should be noted that in the FFT operation, the positions of the first operation result and the second operation result of the butterfly operation unit in the result sequence are the same as the positions of the first input value and the second input value in the input data. Therefore, for each execution of a group of butterfly operations, the first operation result and the second operation result can be sorted according to the arrangement order of the first input value and the second input value of the butterfly operation unit in the input data corresponding to the m-th level operation to obtain a butterfly operation output sequence corresponding to the m-th level operation.

[0182] In summary, the embodiment of the present invention provides a method for executing FFT. The FFT operation is split into M-level operations according to the number of points N of the FFT operation, and each butterfly operation unit in each level of FFT operation is divided into at least one group of butterfly operations according to the corresponding rotation factor of each butterfly operation unit. By sequentially and cyclically executing each group of butterfly operations in each level of operation, the result sequence corresponding to the FFT operation can be obtained. There is no need to customize a corresponding hardware module for the FFT operation, nor is it necessary to convert the original calculation into a multiply-accumulate form, which reduces the operation cost of the FFT and improves the operation efficiency.

[0183] It should be noted that for the method embodiments, for the sake of simple description, they are all expressed as a series of action combinations. However, those skilled in the art should know that the embodiments of the present invention are not limited by the described action sequence, because according to the embodiments of the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily essential for the embodiments of the present invention.

[0184] Device embodiments

[0185] Referring to Figure 4 , a structural block diagram of a processor for performing FFT according to the present invention is shown. The processor includes an instruction fetch unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit, and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file;

[0186] The number of points N and the number of levels M corresponding to the fast Fourier transform (FFT) operation to be executed are stored in the general register file;

[0187] The decoding unit is configured to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the butterfly operation units in the same group are the same;

[0188] The FFT execution unit is configured to sequentially execute each group of butterfly operations in each level of operation according to the first input value, the second input value, and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence;

[0189] The decoding unit is further configured to determine the first input value, the second input value, and the rotation factor of each butterfly operation unit in the (m + 1)-th level of operation according to the butterfly operation output sequence corresponding to the m-th level of operation;

[0190] The FFT execution unit is further configured to continue to execute each group of butterfly operations in the (m + 1)-th level of operation until all M levels of operations are executed, to obtain the result sequence corresponding to the FFT operation; where 0 ≤ m ≤ (M - 1) and m is an integer.

[0191] Optionally, the instruction fetch unit is configured to obtain, for each group of butterfly operations in each level of operation, the FFT instructions corresponding to each butterfly operation unit in the group; the FFT instructions carry the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs;

[0192] The decoding unit is specifically configured to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the number of stages m, and write the first input value, the second input value, and the rotation factor into registers respectively;

[0193] The FFT execution unit is specifically configured to: in the execution stage, execute the FFT instruction to perform butterfly operations according to the first input value, the second input value, and the rotation factor recorded in the registers, so as to obtain the first operation result and the second operation result corresponding to the butterfly operation unit, and until the butterfly operations of each group are all executed, obtain the butterfly operation output sequence.

[0194] Optionally, the decoding unit is specifically configured to:

[0195] Determine the first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the number of stages m to which the butterfly operation unit belongs;

[0196] Determine the second input value of the butterfly operation unit according to the first input value and the first spacing;

[0197] Determine the second spacing between two adjacent groups of butterfly operations in the m-th stage operation according to the number of points N and the number of stages m to which the butterfly operation unit belongs;

[0198] Determine the rotation factor corresponding to the butterfly operation unit according to the second spacing.

[0199] Optionally, the decoding unit is specifically configured to:

[0200] Obtain the storage base address of the rotation factor corresponding to the FFT operation;

[0201] Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing;

[0202] Based on the storage base address and the offset address, read the rotation factor corresponding to the butterfly operation unit from the memory.

[0203] Optionally, the FFT execution unit is specifically configured to:

[0204] In each stage of operation, for each butterfly operation unit, read the first input value of the butterfly operation unit from the first register and read the second input value of the butterfly operation unit from the second register;

[0205] Calculate the sum of the first input value and the second input value to obtain the first operation result corresponding to the butterfly operation unit;

[0206] Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register;

[0207] Read the rotation factor corresponding to the butterfly operation unit from a third register, and read the intermediate result from the temporary register;

[0208] Perform a complex multiplication operation on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit. Until the execution of each group of butterfly operations is completed, a butterfly operation output sequence is obtained.

[0209] Optionally, the memory access processing unit is used for:

[0210] In the m-th level of operation, sort the first operation result and the second operation result corresponding to the butterfly operation unit according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level of operation, to obtain a butterfly operation output sequence corresponding to the m-th level of operation.

[0211] In summary, the embodiment of the present invention provides a processor for performing FFT, which can split the FFT operation into M levels of operations according to the number of points N of the FFT operation, and divide each level of FFT operation into at least one group of butterfly operations. By sequentially and cyclically executing each group of butterfly operations in each level of operation, the result sequence corresponding to the FFT operation can be obtained. There is no need to customize a corresponding hardware module for the FFT operation, nor to convert the original calculation into a multiply-accumulate form, which reduces the operation cost of the FFT and improves the operation efficiency.

[0212] For the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For related parts, refer to the partial description of the method embodiment.

[0213] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other.

[0214] Regarding the processor in the above embodiments, the specific manner in which each module performs operations has been described in detail in the embodiments related to the method, and will not be elaborated here.

[0215] Refer to Figure 6 , which is a structural block diagram of an electronic device for performing FFT provided by an embodiment of the present invention. As Figure 6As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface complete communication with each other through the communication bus. The memory is used to store executable instructions, and the executable instructions cause the processor to execute the method of performing FFT in the foregoing embodiments.

[0216] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable devices, transistor logic devices, hardware components, or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0217] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of representation, Figure 6 only one line is shown in the figure, but it does not mean that there is only one bus or one type of bus.

[0218] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory), or other types of dynamic storage devices that can store information and instructions. It may also be an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), magnetic tape, floppy disk, and optical data storage devices, etc.

[0219] An embodiment of the present invention also provides a non-transitory computer-readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor is enabled to execute Figure 1 the method for performing FFT shown.

[0220] Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0221] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a device, or a computer program product. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0222] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each flow and / or block in the flowcharts and / or block diagrams can be implemented by computer program instructions, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can also be implemented. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal devices generate a device for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0223] These computer program instructions can also be stored in a computer-readable memory that can guide a computer or other programmable data processing terminal devices to work in a predictive manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device implements the functions specified in Figure 1 one flow or multiple flows and / or blocks Figure 1 one block or multiple blocks.

[0224] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal devices, so that a series of operation steps are executed on the computer or other programmable terminal devices to generate a computer-implemented process. Therefore, the instructions executed on the computer or other programmable terminal devices provide for implementing the functions specified in Figure 1 one flow or multiple flows and / or blocksFigure 1 Steps of functions specified in one or more boxes.

[0225] Although the preferred embodiments of the embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications to these embodiments once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0226] Finally, it should also be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or terminal device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or terminal device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the existence of additional identical elements in the process, method, article or terminal device comprising the said element.

[0227] The above has introduced in detail a method, a processor, an electronic device and a storage medium for performing FFT provided by the present invention. Specific examples are used in this text to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A method for performing FFT, characterized in that The method comprises: Get the number of points N corresponding to the fast Fourier transform FFT operation to be performed; Dividing the FFT operation into M-level operations according to the number of points N; M is the logarithm of N with 2 as the base; According to the rotation factors corresponding to the butterfly operation units in the FFT operation, each level of FFT operation is divided into at least one group of butterfly operations; the rotation factors corresponding to the same group of butterfly operation units are the same; In each level of operation, each group of butterfly operations is performed in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence; In the m-th level operation, the first operation results and the second operation results corresponding to the butterfly operation units are sorted according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level operation, so as to obtain a butterfly operation output sequence corresponding to the m-th level operation; Determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation, and continue to execute each group of butterfly operations in the (m+1)th level operation until all M levels of operations are executed, and obtain the result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer; Among them, in the m-th level operation, each butterfly operation unit is divided according to the rotation factor, and the number of butterfly operation groups obtained is: ; According to the butterfly operation output sequence corresponding to the m-th level operation, the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation are determined, and each group of butterfly operations in the (m+1)-th level operation is continued to be executed until all M-level operations are completed, and the result sequence corresponding to the FFT operation is obtained, including: In the decoding stage, according to the butterfly operation output sequence corresponding to the m-th level operation, the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation are determined, and the first input value, the second input value and the rotation factor are written into the register; In the execution stage, the first input value, the second input value and the rotation factor are read from the register, and each group of butterfly operations in the (m+1)th level operation is continued to be executed until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation.

2. The method according to claim 1, characterized in that In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each level of operation, for each group of butterfly operations, an FFT instruction corresponding to each butterfly operation unit in the group is obtained; the FFT instruction carries the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; In the decoding stage, according to the first input value and the level m, the second input value and the rotation factor corresponding to the butterfly operation unit are determined, and the first input value, the second input value and the rotation factor are written into registers respectively; During the execution stage, the FFT instruction is executed to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register to obtain a first operation result and a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and a butterfly operation output sequence is obtained.

3. The method according to claim 2, characterized in that The determining, according to the first input value and the level m, the second input value and the rotation factor corresponding to the butterfly operation unit comprises: Determine a first spacing between the butterfly operation unit and other adjacent butterfly operation units in the group according to the number of points N and the level m to which the butterfly operation unit belongs; Determine a second input value of the butterfly operation unit according to the first input value and the first interval; Determine, according to the number of points N and the number of stages m to which the butterfly operation unit belongs, a second spacing between two adjacent groups of butterfly operations in the m-th stage operation; The rotation factor corresponding to the butterfly operation unit is determined according to the second spacing.

4. The method according to claim 3, characterized in that The determining, according to the second spacing, a rotation factor corresponding to the butterfly operation unit includes: Obtaining a storage base address of a rotation factor corresponding to the FFT operation; Determine the offset address of the rotation factor corresponding to the butterfly operation unit according to the second spacing; Based on the storage base address and the offset address, the rotation factor corresponding to the butterfly operation unit is read from the memory.

5. The method according to claim 1, characterized in that In each level of operation, each group of butterfly operations is sequentially performed according to the first input value, the second input value and the rotation factor of each butterfly operation unit to obtain a butterfly operation output sequence, including: In each stage of operation, for each butterfly operation unit, a first input value of the butterfly operation unit is read from a first register, and a second input value of the butterfly operation unit is read from a second register; Calculating the sum of the first input value and the second input value to obtain a first operation result corresponding to the butterfly operation unit; Calculate the difference between the first input value and the second input value to obtain an intermediate result, and record the intermediate result in a temporary register; Reading the rotation factor corresponding to the butterfly operation unit from the third register, and reading the intermediate result from the temporary register; A complex multiplication operation is performed on the intermediate result and the rotation factor to obtain a second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are completed to obtain a butterfly operation output sequence.

6. A processor for performing FFT, characterized in that The processor comprises an instruction fetch unit, a decoding unit, a general register file, an FFT execution unit, a memory access processing unit and a data storage unit; the FFT execution unit and the memory access processing unit share the general register file; The general register file stores the number of points N and the number of levels M corresponding to the Fast Fourier Transform FFT operation to be performed; The decoding unit is used to divide each level of FFT operation into at least one group of butterfly operations according to the rotation factors corresponding to each butterfly operation unit in the FFT operation; the rotation factors corresponding to the same group of butterfly operation units are the same; The FFT execution unit is used to perform each group of butterfly operations in sequence according to the first input value, the second input value and the rotation factor of each butterfly operation unit in each level of operation to obtain a butterfly operation output sequence; in the m-th level of operation, according to the arrangement order of the first input value and the second input value of each butterfly operation unit in the input data corresponding to the m-th level of operation, sort the first operation results and the second operation results corresponding to the butterfly operation unit to obtain a butterfly operation output sequence corresponding to the m-th level of operation; The decoding unit is further used to determine the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)th level operation according to the butterfly operation output sequence corresponding to the mth level operation; The FFT execution unit is further used to continue to execute each group of butterfly operations in the (m+1)th level operation until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation; wherein 0≤m≤(M-1), and m is an integer; Among them, in the m-th level operation, each butterfly operation unit is divided according to the rotation factor, and the number of butterfly operation groups obtained is: ; The decoding unit is specifically used for: In the decoding stage, according to the butterfly operation output sequence corresponding to the m-th level operation, the first input value, the second input value and the rotation factor of each butterfly operation unit in the (m+1)-th level operation are determined, and the first input value, the second input value and the rotation factor are written into the register; The FFT execution unit is specifically used for: In the execution stage, the first input value, the second input value and the rotation factor are read from the register, and each group of butterfly operations in the (m+1)th level operation is continued to be executed until all M levels of operations are completed, thereby obtaining a result sequence corresponding to the FFT operation.

7. The processor according to claim 6, characterized in that The instruction reading unit is used to obtain, in each level of operation, for each group of butterfly operations, the FFT instructions corresponding to each butterfly operation unit in the group; the FFT instructions carry the first input value of the butterfly operation unit and the level m to which the butterfly operation unit belongs; The decoding unit is specifically used to: in the decoding stage, determine the second input value and the rotation factor corresponding to the butterfly operation unit according to the first input value and the level m, and write the first input value, the second input value and the rotation factor into the register respectively; The FFT execution unit is specifically used to: in the execution stage, execute the FFT instruction to perform a butterfly operation according to the first input value, the second input value and the rotation factor recorded in the register, and obtain the first operation result and the second operation result corresponding to the butterfly operation unit, until all groups of butterfly operations are executed and completed, and a butterfly operation output sequence is obtained.

8. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the method for performing FFT as described in any one of claims 1 to 5.

9. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to execute the method for performing FFT as claimed in any one of claims 1 to 5.

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