A method and device for encoding and reading rotation factors, a medium and a chip

Abstract

The present application discloses a method and device for encoding and reading rotation factors, a medium and a chip. The encoding device includes: a first acquisition module, used to obtain the operation information of the data to be processed, the operation information includes the sequence length of the data to be processed and the degree of parallelism during the forward number theory transformation; based on the operation information, determine the various rotation factors required for the data to be processed during the forward number theory transformation; exclude the rotation factors of the data to be processed in the first preset number of stages of the forward number theory transformation; an encoding module, used to construct the storage mapping relationship between the various rotation factors in the remaining stages and the various static random access memories for storing the rotation factors. In an embodiment of the present application, after the storage mapping relationship is constructed based on the encoding device, when storing the various rotation factors based on the storage mapping relationship, the redundant rotation factors in the first b-1 stages do not need to be stored, thereby reducing the storage space overhead of the rotation factors.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method and device for encoding and reading a rotation factor, a medium and a chip. Background Art

[0002] With the continuous development of artificial intelligence and big data algorithms, protecting data security and privacy is becoming increasingly important. Using encryption algorithms to encrypt data is an important way to protect data security. At present, mainstream privacy computing technologies such as Fully Homomorphic Encryption (FHE) and Zero Knowledge Proof (ZKP) involve a large number of polynomial multiplication calculations. If calculated directly, the complexity is relatively high. For example, the time complexity of multiplying two polynomials of length N is O(N²). The forward fast number theoretic transform (NTT) can optimize the calculation of polynomial multiplication and reduce its time complexity to O(Nlog2N). Among them, NTT is an equivalent form of Fast Fourier Transform (FFT) in the field of number theory, which performs transformations under finite fields.

[0003] The calculation speed of NTT is an important factor affecting the efficiency of privacy computing. Currently, most hardware circuits are used to accelerate NTT in parallel. For example, field programmable gate arrays (FPGAs) are used to accelerate NTT in parallel. However, the on-chip resources of mainstream FPGA products on the market are limited. For large integer and large-scale NTT calculations, storage resources are often the bottleneck for improving their calculation speed. Static random access memory (SRAM) on FPGA can be divided into single-port and dual-port. Single-port SRAM has higher area efficiency than dual-port. Therefore, under the premise of limited resources, single-port SRAM is usually used. However, single-port SRAM can only be read and written once in the same clock cycle, and cannot be read and written multiple times, so the serial calculation speed is slow.

[0004] In order to improve the calculation speed and reduce the calculation cycle, the prior art often adopts a method of parallel operation of multiple single-port SRAMs. When parallel operation is performed, each single-port SRAM needs to obtain a rotation factor. Therefore, the rotation factor required for K parallelism is K times that of serial calculation. In the case of high parallelism, the storage space overhead of the rotation factor is huge. Summary of the invention

[0005] The main purpose of this application is to propose a method and device for encoding and reading rotation factors, a medium and a chip, aiming to solve the problem of large storage space overhead of rotation factors in the current forward number theory transformation.

[0006] To achieve the above object, the present application proposes a twiddle factor encoding device for a forward number theory transformation circuit, the encoding device comprising:

[0007] A first acquisition module is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during forward number theory transformation;

[0008] Based on the operation information, determining various rotation factors required for the data to be processed during forward number theory transformation;

[0009] Based on the parallelism, determining a stage of redundancy of twiddle factors;

[0010] The encoding module is used to construct a storage mapping relationship between each rotation factor in the target stage and each static random access memory for storing the rotation factor; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

[0011] In an embodiment of the present application, the first acquisition module is configured to determine the stage of rotation factor redundancy based on the following method:

[0012] The stage of the rotation factor redundancy is the first (b-1) stage of the data to be processed during the forward number theory transformation; wherein K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

[0013] In an embodiment of the present application, the encoding module is configured to construct a storage mapping relationship based on the following method:

[0014] Obtain candidate rotation factors from each rotation factor in the target stage;

[0015] Reversing the high and low bits of the binary code of the exponent of the candidate conversion factor to obtain a reversed binary code;

[0016] Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed;

[0017] Convert the flipped binary code into a decimal number;

[0018] Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

[0019] In the embodiment of the present application, the binary coded bits of the exponents of the candidate rotation factors are determined based on the largest rotation factor exponent required for the data to be processed.

[0020] In an embodiment of the present application, the encoding module is configured to determine the stage at which the candidate rotation factor first participates in the operation in the forward scalar transform of the data to be processed based on the following method:

[0021] The number of bits from low to high in the first code 1 from high to low in the flipped binary code is used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

[0022] In the embodiment of the present application, the encoding module is configured as follows:

[0023] When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and,

[0024] When x_w=2*i_rev, y_w=0;

[0025] When x_w=2*i_rev+1, y_w=0;

[0026] When x_w=i_rev / / When r∈[b,n-1], y_w= +i_rev-x_w* ;

[0027] When i_rev≥ , r∈[b,n-1], x_w=i_rev / / ,y_w= +i_rev-x_w* ;

[0028] in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the encoding of the static random access memory, and y_w represents the storage location in the static random access memory.

[0029] The present application also proposes a method for encoding a rotation factor, which is used in any of the above-mentioned encoding devices implementing the rotation factor, and the encoding method includes:

[0030] Based on the first acquisition module, obtain operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during forward number theory transformation;

[0031] Based on the operation information, determining various rotation factors required for the data to be processed during forward number theory transformation;

[0032] Based on the parallelism, determining a stage of redundancy of twiddle factors;

[0033] Based on the encoding module, a storage mapping relationship between each rotation factor in the target stage and each static random access memory for storing the rotation factor is constructed; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

[0034] In an embodiment of the present application, the stage of determining the redundancy of the rotation factors based on the degree of parallelism includes:

[0035] The stage of the rotation factor redundancy is the first (b-1) stage of the data to be processed during the forward number theory transformation; wherein K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

[0036] In an embodiment of the present application, the storage mapping relationship between each rotation factor in the target construction stage and each static random access memory for storing the rotation factor includes:

[0037] Obtain candidate rotation factors from each rotation factor in the target stage;

[0038] Reversing the high and low bits of the binary code of the exponent of the candidate conversion factor to obtain a reversed binary code;

[0039] Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed;

[0040] Convert the flipped binary code into a decimal number;

[0041] Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

[0042] In the embodiment of the present application, the binary coded bits of the exponents of the candidate rotation factors are determined based on the largest rotation factor exponent required for the data to be processed.

[0043] In the embodiment of the present application, the step of determining, based on the flipped binary code, the stage in which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed, includes:

[0044] The number of bits from low to high in the first code 1 from high to low in the flipped binary code is used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

[0045] In an embodiment of the present application, the determining of the static random access memory code corresponding to the candidate rotation factor based on the converted decimal number, and the storage location of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation, includes:

[0046] When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and,

[0047] When x_w=2*i_rev, y_w=0;

[0048] When x_w=2*i_rev+1, y_w=0;

[0049] When x_w=i_rev / / When r∈[b,n-1], y_w= +i_rev-x_w* ;

[0050] When i_rev≥ , r∈[b,n-1], x_w=i_rev / / ,y_w= +i_rev-x_w* ;

[0051] in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the encoding of the static random access memory, and y_w represents the storage location in the static random access memory.

[0052] The present application further proposes a reading device for a rotation factor, wherein the reading device is used to read the rotation factor from a preset storage module, and the rotation factor is stored in the preset storage module based on the storage mapping relationship constructed by the encoding device for the rotation factor described in any of the above embodiments, and the reading device includes:

[0053] The second acquisition module is used to obtain the parallelism and stage of the data to be processed when performing forward number theory transformation;

[0054] If r∈[0,b-1];

[0055] The second acquisition module is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation;

[0056] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory;

[0057] If r∈[b,n-1];

[0058] The second acquisition module is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs;

[0059] Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory;

[0060] A reading module, used for reading the rotation factors corresponding to each polynomial pair based on the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage position in the static random access memory;

[0061] Among them, r is the stage, K is the parallelism, .

[0062] In an embodiment of the present application, the second acquisition module is configured to determine the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory in the following manner:

[0063] When r∈[0,b-2], x_r=2*t / / , y_r=0;

[0064] When r=b-1, x_r=t, y_r=0;

[0065] Wherein, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the SRAM code, and y_r is the storage location in the SRAM.

[0066] In an embodiment of the present application, the second acquisition module is further configured to determine the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory in the following manner:

[0067] x_r=t,y_r= +j;

[0068] Among them, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the static random access memory where the rotation factor is located, and y_r is the storage location of the rotation factor in the static random access memory.

[0069] The present application also proposes a method for reading a rotation factor, which is applied to the device for reading a rotation factor described in any of the above embodiments. The method comprises:

[0070] Based on the second acquisition module, determining the parallelism and the stage when the forward number theory transformation is performed on the data to be processed;

[0071] If r∈[0,b-1];

[0072] Then, based on the second acquisition module, determining the static random access memory order corresponding to each polynomial pair participating in the same parallel operation;

[0073] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory;

[0074] If r∈[b,n-1];

[0075] Based on the second acquisition module, determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs;

[0076] Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory;

[0077] Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory, reading the rotation factors corresponding to each polynomial pair;

[0078] Among them, r is the stage, K is the parallelism, .

[0079] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory based on the static random access memory order corresponding to each polynomial pair participating in the operation in the same parallel operation, includes:

[0080] When r∈[0,b-2], x_r=2*t / / , y_r=0;

[0081] When r=b-1, x_r=t, y_r=0;

[0082] Wherein, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the SRAM code, and y_r is the storage location in the SRAM.

[0083] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial in the same parallel operation are located, and the storage location in the static random access memory based on the corresponding static random access memory order and the butterfly calculation order, includes:

[0084] x_r=t,y_r= +j;

[0085] Among them, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the static random access memory where the rotation factor is located, and y_r is the storage location of the rotation factor in the static random access memory.

[0086] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0087] An embodiment of the present application further provides a chip, comprising the rotation factor encoding device or the rotation factor reading device described in any one of the above embodiments.

[0088] In the embodiment of the present application, when a storage mapping relationship is constructed based on the encoding device, the rotation factors in the stage where the rotation factors are redundant are discarded, and the redundant rotation factors do not need to be stored, thereby reducing the storage space overhead of the rotation factors. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0090] Figure 1 is a module diagram of a rotation factor encoding device in an embodiment of the present application;

[0091] Figure 2 A schematic diagram of the forward number theory conversion of the data to be processed in one embodiment of the present application;

[0092] Figure 3 4 is a block diagram of a device for obtaining a rotation factor in an embodiment of the present application;

[0093] Figure 4 is a step diagram of a method for encoding a rotation factor in an embodiment of the present application;

[0094] Figure 5 is a step diagram of a method for obtaining a rotation factor in an embodiment of the present application;

[0095] Figure 6This is a module diagram of a computer-readable storage medium in one embodiment of the present application.

[0096] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0097] The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present application, and are not intended to limit the scope of the present application in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0098] Those skilled in the art know that the embodiments of the present application can be implemented as a system, device, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0099] According to the implementation manner of the present application, a method and device for encoding and reading a rotation factor, a medium and a chip are proposed.

[0100] It should be understood herein that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction rather than having any limiting meaning.

[0101] The following is a detailed explanation of the principles and spirit of the present application with reference to several representative embodiments of the present application.

[0102] Exemplary Devices

[0103] like Figure 1 As shown, the embodiment of the present application proposes a rotation factor encoding device 100, which is used in a forward number theory transformation circuit, and the encoding device 100 includes:

[0104] A first acquisition module 110 is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during forward number theory transformation;

[0105] Based on the operation information, determining various rotation factors required for the data to be processed during forward number theory transformation;

[0106] Based on the parallelism, determining a stage of redundancy of twiddle factors;

[0107] The encoding module 120 is used to construct a storage mapping relationship between each rotation factor in the target stage and each static random access memory used to store the rotation factor; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

[0108] In an embodiment of the present application, the data to be processed for forward number theory encoding includes multiple polynomials, and the number of polynomials is the sequence length of the data to be processed. The number of static random access memories (SRAMs) on the FPGA (field programmable logic circuit) used for forward number theory transformation determines the degree of parallelism. For example, if there are two SRAMs on the FPGA used for forward number theory transformation, the degree of parallelism is 2, and if there are four SRAMs on the FPGA used for forward number theory transformation, the degree of parallelism is 4.

[0109] In addition, in the embodiment of the present application, the SRAM on the FPGA used for forward number theory transformation can adopt a single-port SRAM, thereby having a larger area utilization rate.

[0110] In addition, in the forward number theory transformation, multiple butterfly calculations are performed in each stage, and the result of the forward number theory transformation is finally obtained after multiple stages. The number of stages required for the forward number theory transformation is related to the sequence length of the data to be processed. For example, in the embodiment of the present application, assuming that the sequence length of the data to be processed is N, , the degree of parallelism is K, K , then the data to be processed requires n stages to complete the forward number theory transformation. Assuming the number of stages is r, then r∈[0,n-1].

[0111] In the embodiment of the present application, the rotation factor W required for each butterfly operation in each stage can be determined based on the following formula (1):

[0112] (1)

[0113] in, Represents the rotation factor in the forward number theory transformation with a sequence length of N, r is the stage of the forward number theory transformation, r∈[0,n-1], m is the group order of each polynomial group in the same stage, and m starts from zero.

[0114] like Figure 2 As shown, Figure 2 A schematic diagram of the rotation factors required at each stage of the forward number theory transformation of the data to be processed with a sequence length of 8 is shown. Among them, x[0]- x[7] are 8 polynomials of the stage 0 of the forward number theory transformation of the data to be processed, that is, the original sequence, and x[0]- x[7] are in the same polynomial group; - are 8 polynomials in stage 1 of the forward number theory transformation of the data to be processed, in two polynomial groups; - These are the eight polynomials of stage 2 of the forward number theory transformation of the data to be processed, which are in four polynomial groups.

[0115] In stage 0, r=0, the initial data to be processed is the original sequence, all polynomials are in a polynomial group, m=0, and based on the above formula 1, the rotation factor involved in stage 0 can be determined as .

[0116] In stage 1, r=1, each polynomial is divided into two polynomial groups, - is a polynomial group, the corresponding polynomial group order m=0, based on the above formula (1), the corresponding rotation factor can be calculated ; - is another polynomial group, the corresponding polynomial group group order m=1, based on the above formula (1) we can calculate its corresponding rotation factor .

[0117] In stage 2, the individual polynomials are divided into four polynomial groups, - is a polynomial group, the corresponding polynomial group order m=0, based on the above formula (1), the corresponding rotation factor can be calculated as ;

[0118] - is a polynomial group, the corresponding polynomial group order m=1, based on the above formula (1), the corresponding rotation factor can be calculated as ;

[0119] - is a polynomial group, and the corresponding polynomial group order m=2. Based on the above formula (1), the corresponding rotation factor can be calculated as ;

[0120] - is a polynomial group, and the corresponding polynomial group order m=3. Based on the above formula (1), the corresponding rotation factor can be calculated as .

[0121] This allows the determination of the various rotation factors required for the data to be processed.

[0122] In the embodiment of the present application, after determining the various rotation factors required for the forward number theory transformation of the data to be processed, the first acquisition module 110 also needs to determine the stage of redundancy of the rotation factors based on the degree of parallelism.

[0123] For example, in Figure 2 The rotation factor at stage r=0 in the data to be processed with a sequence length of 8 and a parallelism of 4 is shown , and it appears again in the subsequent stages r=1 and 2, so stage r=0 is the stage of redundant rotation factors.

[0124] For another example, as shown in Table 1, Table 1 is the data to be processed with a sequence length of 64, and the 64 polynomials of the original sequence are A1-A64, and the polynomial groups in each stage of the forward number theory transformation according to the parallelism of 4 are shown in Table 1 below, where the parallelism of 4 means that four SRAMs are set on the FPGA used for number theory transformation, and the four SRAMs are numbered 0-3, as shown in Table 1 below:

[0125] Table 1

[0126]

[0127] Among them, in Table 1, 0-5 represent the various stages of the forward number theory transform, SRAM0-SRAM3 represent four single-port SRAMs used for parallel computing, A1-A64 represent 64 polynomials of the original sequence, which are in the same polynomial group; B1-B64 represent 64 polynomials in stage 1 of the forward number theory transform, which are in two polynomial groups; C1-C64 represent 64 polynomials in stage 2 of the forward number theory transform, which are in four polynomial groups; D1-D64 represent 64 polynomials in stage 3 of the forward number theory transform, which are in eight polynomial groups; E1-E64 represent 64 polynomials in stage 4 of the forward number theory transform, which are in sixteen polynomial groups; F1-F64 represent 64 polynomials in stage 5 of the forward number theory transform, which are in thirty-two polynomial groups.

[0128] Based on the above formula (1), the rotation factors required for each polynomial group in each stage can be determined, as shown in Table 2 below:

[0129] Table 2

[0130]

[0131] The above Table 2 shows the rotation factors required for each polynomial in each stage under the condition of parallelism of 4 for the data to be processed with a length of 64. Combined with Table 2, it can be determined that the corresponding rotation factors in each SRAM in stage 0 appear in the subsequent stages, that is, for stage 0, the rotation factors stored in each SRAM are redundant.

[0132] Therefore, in the embodiment of the present application, the first acquisition module 110 is configured to set the stage of the rotation factor redundancy to the first (b-1) stages of the forward number theory transformation of the data to be processed, where K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

[0133] As shown in Table 1, K=4, b=2, and b-1 is 1, that is, the data to be processed with a sequence length of 64 in Table 1 is a stage of rotation factor redundancy in the first stage of the forward number theory transformation, and the first stage is stage 0.

[0134] After determining the stage of redundant rotation factors of the data to be processed during the forward number theory transformation, the remaining stages are the target stages. For example, the data to be processed with a sequence length of 64 in Table 1 needs to have stages 0, 1, 2, 3, 4, and 5 during the forward number theory transformation, where stage 0 is the stage of redundant rotation factors. After discarding stage 0, stages 1, 2, 3, 4, and 5 are the target stages.

[0135] After the target stage is determined, a storage mapping relationship between each twiddle factor in the target stage and each SRAM for storing the twiddle factor can be constructed based on the encoding module 120 .

[0136] In the embodiment of the present application, the encoding module 120 is configured to construct a storage mapping relationship based on the following method:

[0137] Obtain candidate rotation factors from each rotation factor in the target stage;

[0138] Reversing the high and low bits of the binary code of the exponent of the candidate conversion factor to obtain a reversed binary code;

[0139] Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed;

[0140] Convert the flipped binary code into a decimal number;

[0141] Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

[0142] First, candidate rotation factors are obtained from each rotation factor in the target stage.

[0143] Based on the above formula (1), the rotation factors required for each polynomial group in each stage when the data to be processed is subjected to forward number theory transformation can be determined. In addition, it has been determined that the first b-1 stages are stages with redundant rotation factors. The rotation factors in the first b-1 stages appear again in the bth to nth stages. Therefore, the rotation factors in the first b-1 stages do not need to be stored. Therefore, each candidate rotation factor can be traversed in each rotation factor in the bth to nth stages to obtain each candidate rotation factor.

[0144] After obtaining any candidate rotation factor, the binary code of the exponent of the candidate rotation factor is flipped to obtain the flipped binary code.

[0145] In the embodiment of the present application, the rotation factor is , where N represents the sequence length of the data to be processed, This is the exponent of the rotation factor, which is a decimal number. For example, the rotation factor The exponent is 3, the rotation factor The exponent of is 2.

[0146] In addition, when performing binary code conversion on the exponents of the rotation factors, it is necessary to determine the bits of the binary code according to the largest exponent of each rotation factor during the forward number theory transformation of the data to be processed.

[0147] For example, for the length of 8 to be processed data, the required rotation factor is , , , , the maximum exponent is 3, and the binary code corresponding to 3 is 11, that is, two bits, so the exponents 0, 1, and 2 are also converted into two-bit binary codes.

[0148] For another example, in the embodiment of the present application, for the data to be processed with a length of 64, the various rotation factors required for the forward number theory transformation according to the parallelism of 4 are - , where all indices 0 to 31 are included. The maximum index is 31, so the binary conversion is performed according to the bit position of the binary code corresponding to 31. Among them, the binary code corresponding to 31 is 11111, and the bit position is 5, that is, the indices of the candidate rotation factors need to be converted into 5-bit binary codes when performing binary conversion. For example, for the rotation factor For example, its exponent is 30 and its corresponding binary code is 11110.

[0149] In the embodiment of the present application, after obtaining the binary code, the high and low bits thereof can be flipped. For example, after flipping the high and low bits of the binary code 11110 corresponding to 30, the flipped binary code 01111 can be obtained.

[0150] Then, based on the flipped binary code, the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed can be determined.

[0151] In an embodiment of the present application, the number of bits from low to high in the first code 1 from high to low in the flipped binary code can be used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

[0152] Still For example, the binary code 11110 corresponding to the index 30 is flipped to get the binary code 01111 after the high and low bits are flipped. The first code 1 from high to low in 01111 is the first 1 from the left to the right. The code 1 from low to high is the fourth bit from the right to the left, and the rotation factor can be determined. The first time it is involved in a calculation is at stage 4 of number theory transformations.

[0153] Based on the above Tables 1 and 2, the rotation factors can be Appear in the stage of number theory transformation for verification, and calculate the rotation factor The first time it participates in the operation is in stage 4 of the number theory transformation. Based on the above Tables 1 and 2, the rotation factors can be determined In stage 4, the polynomial group E61-E64 is involved in the operation, which is verified to be correct.

[0154] Then, the flipped binary code is converted into a decimal code.

[0155] Also For example, its corresponding binary code after flipping is 01111, which converts to decimal number is 15.

[0156] Then, based on the converted decimal digits, the static random access memory code corresponding to the candidate rotation factor and the storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation are determined.

[0157] The above has determined the stage at which the candidate rotation factor first participates in the operation in the forward number theory transform of the data to be processed. The candidate rotation factor will still appear in subsequent stages. Therefore, the SRAM code corresponding to the candidate rotation factor and the storage position in the SRAM can be determined according to the number of stages of the forward number theory transform.

[0158] In the embodiment of the present application, the encoding module 120 is configured to determine the SRAM encoding corresponding to the candidate rotation factor and the storage location in the SRAM based on the following method:

[0159] When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and,

[0160] When x_w=2*i_rev, y_w=0;

[0161] When x_w=2*i_rev+1, y_w=0;

[0162] When x_w=i_rev / / When r∈[b,n-1], y_w= +i_rev-x_w* ;

[0163] When i_rev≥ , r∈[b,n-1], x_w=i_rev / / ,y_w= +i_rev-x_w* ;

[0164] in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the SRAM code, and y_w represents the storage location in the SRAM.

[0165] Also For example, i=30, its corresponding binary code after flipping is 01111, which is converted into decimal code as 15, that is, i_rev=15;

[0166] And N=64, K=4, so we can know n=6, b=2, r∈[0,5];

[0167] The above has been confirmed The first stage of the operation is 4, and r∈[0,5], so It is required to participate in the calculation in both phase 4 and phase 5.

[0168] And i_rev=15>2= , so according to x_w=i_rev / / ,y_w= +i_rev-x_w* Calculate stage 4 and stage 5 separately.

[0169] When r=4, x_w=3, y_w=7;

[0170] When r=5, x_w=1, y_w=15;

[0171] That is, for a number-theoretic transformation with a sequence length of 64 and a parallelism of 4 (the corresponding SRAM codes are 0, 1, 2, and 3 respectively), the rotation factor The SRAM code in stage 4 is 3 and the storage location is 7. The SRAM code in stage 5 is 1 and the storage location is 15.

[0172] As shown in Table 3 below, Table 3 shows the SRAMs and their internal storage location numbers:

[0173] Table 3

[0174]

[0175] Among them, stages 0-5 in Table 3 represent the various stages of forward number theory transformation of the data to be processed, SRAM0-SRAM3 represent four parallel SRAMs, and 0-15 in each SRAM represents the storage location in each SRAM.

[0176] The above calculation obtains the rotation factor In stage 4, the SRAM code is 3, and the storage position is 7, that is, storage position 7 in SRAM3; in stage 5, the SRAM code is 1, and the storage position is 15, that is, storage position 15 in SRAM1.

[0177] In addition, when i_rev< When x_w and y_w use different For example, for the rotation factor , its index i is 0, the 5-bit binary code is 00000, the binary code after inversion is 00000, and then converted to decimal code is 0, that is, i_rev=0<2, at this time, x_w is 2*i_rev and 2*i_rev+1 and i_rev / / , which means that x_w needs to be replaced by 2*i_rev and 2*i_rev+1 and i_rev / / The three formulas are used to calculate three x_w. At the same time, the three x_w also correspond to the calculation methods of the three y_w, that is, the rotation factor is involved in the three SRAMs. The specific calculation is as follows:

[0178] For the formula x_w=2*i_rev

[0179] It can be calculated that x_w=0,y_w=0.

[0180] For the formula x_w=2*i_rev+1

[0181] It can be calculated that x_w=1, y_w=0.

[0182] For the formula x_w=i_rev / /

[0183] It can be calculated that x_w=0. If it needs to be explained, for the formula x_w=i_rev / / When , the calculation of y_w depends on the stage, r∈[b,n-1], y_w= +i_rev-x_w* , that is, it is necessary to calculate each y_w in each stage when r∈[b,n-1], as follows:

[0184] When r=2, y_w=1;

[0185] When r=3, y_w=2;

[0186] When r=4, y_w=4;

[0187] When r=5, y_w=8.

[0188] At this point, it can be determined that for the candidate rotation factors The calculation results include:

[0189] x_w=0,y_w=0;

[0190] x_w=1,y_w=0:

[0191] When x_w=0, r=2, y_w=1;

[0192] When r=3, y_w=2;

[0193] When r=4, y_w=4;

[0194] When r=5, y_w=8;

[0195] That is, the rotation factor The corresponding SRAM codes and storage locations include: storage location 0 of SRAM0, storage location 1 of SRAM1, and storage locations 1, 2, 4, and 8 of SRAM0.

[0196] According to the above method, the rotation factor can be determined - The mapping relationship between the encoding and storage location of each corresponding SRAM is obtained by storing each rotation factor in the storage space of the corresponding storage location of the SRAM according to the mapping relationship between the encoding and storage location of each rotation factor and the SRAM, and the following Table 4 is obtained:

[0197] Table 4

[0198]

[0199] As shown in Table 4 above, Table 4 shows a schematic diagram of storing various rotation factors using the storage mapping relationship constructed by the rotation factor encoding method in the embodiment of the present application. Compared with Table 2, the rotation factor corresponding to stage 0 in Table 4 is blank. For Table 4, K=4, b=2, b-1=1, the first b-1 stages are the previous stage, and the previous stage is stage 0, that is, after the encoding device 100 in the embodiment of the present application is used to construct the storage mapping relationship, when storing various rotation factors based on the storage mapping relationship, the redundant rotation factors in the first b-1 stages do not need to be stored, thereby reducing the storage space overhead of the rotation factor.

[0200] In addition, the above is only an example of a number theory transformation with a length of 64 and a parallelism of 4. In actual operations, the length of the data to be processed is longer and the corresponding parallelism is higher. As the parallelism increases, the effect of the encoding device of the present application in reducing the storage space overhead of the rotation factors is more significant.

[0201] When performing forward number theory transformations, the number of polynomial groups in any stage r is , each polynomial group requires a rotation factor, and the rotation factors corresponding to the same polynomial group are the same. <K (parallelism), that is < , r∈[0,b-1], each polynomial group needs to obtain the rotation factor from multiple SRAMs. Therefore, for a single SRAM, when r∈[0,b-1], each stage only needs to store 1 rotation factor, and there are b stages in r∈[0,b-1]. Then, a single SRAM needs to store a total of b rotation factors in r∈[0,b-1].

[0202] when ≥K, that is , that is, r∈[b,n-1], each polynomial group only needs to obtain the rotation factor from one SRAM. The number of polynomial groups at stage r is , that is, the total required The rotation factors are The rotation factors are evenly distributed to K SRAMs, so when r∈[b,n-1], for a single SRAM, each stage needs to store The rotation factors are summed up to get = -1, that is, when r∈[b,n-1], the rotation factor that a single SRAM needs to store is -1 pc.

[0203] When r∈[0, b-1], a single SRAM needs to store a total of b rotation factors. When r∈[b, n-1], a single SRAM needs to store a total of b rotation factors. -1 rotation factor, then when r∈[0,n-1], a single SRAM needs to store -1+b rotation factors.

[0204] Furthermore, in the embodiment of the present application, since the rotation factors required in the first b-1 stages need to appear again in the bth stage and thereafter, the rotation factors in the first b-1 stages are not stored in the embodiment of the present application. For the first b-1 stages, for a single SRAM, when r∈[0, b-1], only one rotation factor needs to be stored in each stage, and a single SRAM in the first b-1 stages has a total of (b-1)*1 rotation factors. Therefore, for a single SRAM, after discarding the redundant rotation factors in the first b-1 stages, only (b-1)*1 rotation factors need to be stored. Twist factors.

[0205] The parallelism is K. After discarding the redundant rotation factors of the first b-1 stages, K SRAMs can store a total of *K= Twist factors.

[0206] In the prior art, a method of storing all rotation factors is adopted. When the parallelism is K, a total of K*N / 2 rotation factors are required, that is, the storage space of the rotation factors required by this solution is reduced to 2 / K of the original.

[0207] In addition, in the prior art, for the length of the to-be-processed data N, the space required to store the polynomial and the rotation factor is N+ K*N / 2, while in the embodiment of the present application, the space required to store the polynomial and the rotation factor is N+ , (N+ ) / (N+ K*N / 2)=4 / (K+2), that is, by adopting the encoding method of the rotation factor in the present application, the storage space for storing the rotation factor and the polynomial can be reduced to 4 / (K+2) of the prior art.

[0208] like Figure 3As shown, the present application also proposes a reading device 200 for a rotation factor, the reading device 200 is used to read the rotation factor from a preset storage module, the rotation factor is based on the storage mapping relationship constructed by the encoding device 100 for the rotation factor described in any of the above embodiments, and is stored in the preset storage module, the reading device comprising:

[0209] The second acquisition module 210 is used to obtain the parallelism and stage of the forward number theory transformation of the data to be processed;

[0210] If r∈[0,b-1];

[0211] The second acquisition module 210 is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation;

[0212] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory;

[0213] If r∈[b,n-1];

[0214] The second acquisition module 210 is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs;

[0215] Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory;

[0216] A reading module 220, configured to read the twiddle factors corresponding to each polynomial pair based on the encoding of the static random access memory where the twiddle factors corresponding to each polynomial pair in the same parallel operation are located and the storage location in the static random access memory;

[0217] Among them, r is the stage, K is the parallelism, .

[0218] In the embodiment of the present application, the degree of parallelism when the data to be processed is subjected to forward number theory transformation is determined based on the number of SRAMs used to store the rotation factors, and the stage is determined based on the sequence length of the data to be processed. Taking the data to be processed shown in Table 1 above as an example, the length is 64, including stages 0-5, and the degree of parallelism is 4.

[0219] In the embodiment of the present application, the methods for reading the rotation factor are different at different stages, and can be divided into r∈[0,b-1] and r∈[b,n-1] according to the stage. The following describes the methods for obtaining the rotation factor according to scenario 1: r∈[0,b-1]; scenario 2: r∈[b,n-1].

[0220] For scenario 1: r∈[0,b-1]

[0221] Still taking the data to be processed shown in Table 1 as an example, when r=0, A1-A64 are in a polynomial group and the parallelism is 4.

[0222] Therefore, in the same parallel operation, 4 polynomial pairs need to be selected from A1-A64, and the rotation factors need to be obtained from 4 SRAMs respectively. For example, the following four polynomial pairs are selected in the first parallel operation: A1&A33, A2&A34, A3&A35, A4&A36; the following four polynomial pairs are selected in the second parallel operation: A5&A37, A6&A38, A7&A39, A8&A40, and so on. Four polynomial pairs are selected in each parallel operation, and a total of 8 parallel operations are performed.

[0223] Among them, the rotation factors corresponding to A1&A33, A2&A34, A3&A35, and A4&A36 are obtained from SRAM0, SRAM1, SRAM2, and SRAM3 respectively, so the SRAM order corresponding to A1&A33 is 0, the SRAM order corresponding to A2&A34 is 1, the SRAM order corresponding to A3&A35 is 2, and the SRAM order corresponding to A4&A36 is 3.

[0224] Similarly, the SRAM order corresponding to each polynomial pair in each parallel operation can be determined.

[0225] For example, in phase 0, the SRAM order corresponding to each polynomial pair during each parallel operation is as follows (where the order and the corresponding SRAM order both start from 0):

[0226] For A1&A33, A2&A34, A3&A35, and A4&A36, the SRAM order corresponding to A1&A33 by the polynomial is 0, the SRAM order corresponding to A2&A34 is 1, the SRAM order corresponding to A3&A35 is 2, and the SRAM order corresponding to A4&A36 is 3;

[0227] For A5&A37, A6&A38, A7&A39, and A8&A40, the SRAM order corresponding to the polynomial for A5&A37 is 0, the SRAM order corresponding to A6&A38 is 1, the SRAM order corresponding to A7&A39 is 2, and the SRAM order corresponding to A8&A40 is 3;

[0228] By analogy, for A29&A61, A30&A62, A31&A63, A32&A64, the SRAM order corresponding to A29&A61 is 0, the SRAM order corresponding to A30&A62 is 1, the SRAM order corresponding to A31&A63 is 2, and the SRAM order corresponding to A32&A64 is 3.

[0229] After determining the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage position in the static random access memory can be determined based on the static random access memory order and the butterfly calculation order.

[0230] In the embodiment of the present application, the second acquisition module 210 is configured to determine the encoding of the SRAM where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the SRAM in the following manner:

[0231] When r∈[0,b-2], x_r=2*t / / , y_r=0;

[0232] When r=b-1, x_r=t, y_r=0;

[0233] Among them, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the SRAM code, and y_r is the storage location in the SRAM.

[0234] In the embodiment of the present application, for the parallel operations A1&A33, A2&A34, A3&A35, A4&A36, they are in stage 0, that is, r=0;

[0235] The SRAM order corresponding to A1&A33 is 0, that is, t=0;

[0236] The SRAM order corresponding to A2&A34 is 1, that is, t=1;

[0237] The SRAM order corresponding to A3&A35 is 2, that is, t=2;

[0238] The SRAM order corresponding to A4&A36 is 3, that is, t=3;

[0239] r=0, that is, r∈[0,b-2];

[0240] Therefore, for A1&A33, x_r=0, y_r=0, which means that the SRAM number corresponding to the rotation factor required by the polynomial for A1&A33 is 0, and the storage position in the SRAM numbered 0 is 0;

[0241] For A2&A34, x_r=0, y_r=0; that is, the SRAM number corresponding to the rotation factor required by the polynomial for A2&A34 is 0, and the storage position in the SRAM numbered 0 is 0;

[0242] For A3&A35, x_r=1, y_r=0; that is, the SRAM number corresponding to the rotation factor required by the polynomial for A3&A35 is 1, and the storage position in the SRAM numbered 1 is 0;

[0243] For A4&A36, x_r=1, y_r=0t; that is, the SRAM number corresponding to the rotation factor required by the polynomial A3&A35 is 1, and the storage position in the SRAM numbered 1 is 0.

[0244] By referring to the storage positions of each SRAM in Table 3 and the schematic diagram of the rotation factors stored in each storage position of each SRAM in Table 4, the rotation factors corresponding to each polynomial pair in the parallel operations A1&A33, A2&A34, A3&A35, and A4&A36 can be obtained.

[0245] According to the above method, the SRAM code corresponding to each polynomial pair and the storage position therein can be determined during each parallel operation.

[0246] In addition, the above embodiment is described by taking r=0 as an example. In scenario 1, when r=1, that is, when r=b-1, x_r and y_r can be calculated according to x_r=t, y_r=0.

[0247] For scenario 2: r∈[b,n-1]

[0248] When r=b, in stage b we have polynomial group, and =K, K represents the number of SRAMs, so in phase b, each SRAM can be evenly allocated to a polynomial group;

[0249] When r>b, polynomial groups, and evenly distribute them to K SRAMs. Each SRAM can be evenly distributed to A group of polynomials.

[0250] As shown in Table 1 above, in phase 2, C1-C16 are allocated to SRAM0, C17-C32 are allocated to SRAM1, C33-C48 are allocated to SRAM2, and C49-C64 are allocated to SRAM3. When performing parallel operations, the polynomials of C1-C16 are in the same polynomial group and correspond to the same rotation factor, so the butterfly calculation order of each polynomial group in C1-C16 is the same. Similarly, the butterfly calculation order of each polynomial in C17-C32, C33-C48, and C49-C64 is also the same.

[0251] Continuing to refer to the above Table 1, in stage 3, D1-D8 and D9-D16 obtain the rotation factor from SRAM0; D17-D24 and D25-D32 obtain the rotation factor from SRAM1, D33-D40 and D41-D48 obtain the rotation factor from SRAM2; D49-D56 and D57-D64 obtain the rotation factor from SRAM3. For D1-D8 and D9-D16, although D1-D8 and D9-D16 both correspond to SRAM0, they are in two polynomial groups. The rotation factors of the two polynomial groups D1-D8 and D9-D16 are different when performing butterfly calculations, so the order of butterfly calculations of D1-D8 and D9-D16 is different. The butterfly calculation order starts from 0, so the butterfly calculation order of D1-D8 is 0, and the butterfly calculation order of D9-D16 is 1.

[0252] Similarly, the butterfly calculation order of D17-D24 is 0, the butterfly calculation order of D25-D32 is 1; the butterfly calculation order of D33-D40 is 0; the butterfly calculation order of D41-D48 is 1; the butterfly calculation order of D49-D56 is 0, and the butterfly calculation order of D57-D64 is 1.

[0253] According to this method, the butterfly calculation order of each polynomial in each stage can be determined when r∈[b,n-1].

[0254] In addition, still taking the data to be processed shown in Table 1 as an example, the parallelism is 4, when r=2, C1-C64 are in four polynomial groups. Therefore, in the same parallel operation, a polynomial pair needs to be selected from the four polynomial groups respectively, for example:

[0255] In the first parallel operation, select C1&C9 from the polynomial group C1-C16; select C17&C25 from the polynomial group C17-C32; select C33&C41 from the polynomial group C33-C48; select C49&C57 from the polynomial group C49-C64.

[0256] In the second parallel operation, select C2&C10 from the polynomial group C1-C16; select C18&C26 from the polynomial group C17-C32; select C34&C42 from the polynomial group C33-C48; select C50&C58 from the polynomial group C49-C64;

[0257] And so on, in the eighth parallel operation, C8&C16 are selected from the polynomial group C1-C16; C24&C32 are selected from the polynomial group C17-C32; C40&C48 are selected from the polynomial group C33-C48; and C56&C64 are selected from the polynomial group C49-C64.

[0258] For C1&C9, C17&C25, C33&C41, C49&C57, which are in the same parallel operation, according to the above polynomial pair corresponding SRAM order determination method, the SRAM order corresponding to C1&C9 is 0, the SRAM order corresponding to C17&C25 is 1, the SRAM order corresponding to C33&C41 is 2, and the SRAM order corresponding to C49&C57 is 3. Therefore, the SRAM order and butterfly calculation order corresponding to each polynomial group of C1&C9, C17&C25, C33&C41, C49&C57 in stage 2 are as follows:

[0259] The SRAM order corresponding to C1&C9 is 0, and the butterfly calculation order of the polynomial group C1-C16 in which it is located is 0;

[0260] The SRAM order corresponding to C17 & C25 is 1, and the butterfly calculation order of the polynomial group C17-S32 in which it is located is 0;

[0261] The SRAM order corresponding to C33 & C41 is 2, and the butterfly calculation order of the polynomial group C33-C48 in which it is located is 0;

[0262] The SRAM order corresponding to C49 & C57 is 3, and the butterfly calculation order of the polynomial group C49-C64 in which it is located is 0.

[0263] For another example, the SRAM order and butterfly calculation order corresponding to each polynomial group C2&C10, C18&C26, C34&C42, C50&C58 in stage 2 are as follows:

[0264] The SRAM order corresponding to C2 & C10 is 0, and the butterfly calculation order in the polynomial group C1-C16 is 0;

[0265] The SRAM order corresponding to C18 & C26 is 1, and the butterfly calculation order in the polynomial group C1-C16 is 0;

[0266] The SRAM order corresponding to C34 & C42 is 2, and the butterfly calculation order in the polynomial group C1-C16 is 0;

[0267] The SRAM order corresponding to C50 & C58 is 3, and the butterfly calculation order in the polynomial group C1-C16 is 0.

[0268] After determining the SRAM order corresponding to each polynomial pair, the SRAM encoding of the twiddle factors corresponding to each polynomial pair in the same parallel operation and the storage location in the SRAM can be determined based on the second acquisition module 210 in the following manner:

[0269] x_r=t,y_r= +j;

[0270] Among them, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the SRAM where the rotation factor is located, and y_r is the storage location of the rotation factor in the SRAM.

[0271] For example, for the parallel operations of C1&C9, C17&C25, C33&C41, C49&C57:

[0272] For C1&C9, r=2, t=0, j=0; then x_r=0, y_r=1;

[0273] For C17 & C25, r = 2, t = 1, j = 0; then x_r = 1, y_r = 1;

[0274] For C33 & C41, r = 2, t = 2, j = 0; then x_r = 2, y_r = 1;

[0275] For C49 & C57, r = 2, t = 3, j = 0; then x_r = 3, y_r = 1;

[0276] That is, in stage 2, during the first parallel operation, the rotation factors corresponding to the polynomial pair C1&C9 are stored in the SRAM numbered 0, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C17&C25 are stored in the SRAM numbered 1, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C33&C41 are stored in the SRAM numbered 2, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C49&C57 are stored in the SRAM numbered 3, and the storage position therein is numbered 1.

[0277] For example, for the parallel operations of C2&C10, C18&C26, C34&C42, C50&C58:

[0278] For C2&C10, r=2, t=0, j=0; x_r=0, y_r=1;

[0279] For C18 & C26, r = 2, t = 1, j = 0; x_r = 1, y_r = 1;

[0280] For C34 & C42, r = 2, t = 2, j = 0; x_r = 2, y_r = 1;

[0281] For C50&C58, r=2, t=3, j=0; x_r=3, y_r=1.

[0282] That is, in stage 2, during the second parallel operation, the rotation factors corresponding to the polynomial pair C2&C10 are stored in the SRAM numbered 0, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C18&C26 are stored in the SRAM numbered 1, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C34&C42 are stored in the SRAM numbered 2, and the storage position therein is numbered 1; the rotation factors corresponding to the polynomial pair C50&C58 are stored in the SRAM numbered 3, and the storage position therein is numbered 1.

[0283] The above scenario 1 and scenario 2 respectively illustrate the SRAM encoding of the corresponding rotation factor and its storage position in the polynomial in the same parallel operation when r∈[0,b-1] and r∈[b,n-1]. Next, the rotation factor can be obtained from the corresponding position based on the reading module 220.

[0284] For example, in phase 0, it is as follows:

[0285] For parallel operations A1&A33, A2&A34, A3&A35, A4&A36

[0286] For A1 & A33, x_r = 0, y_r = 0, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 0 of SRAM0 ,Compared with Table 2, the rotation factors are correct;

[0287] For A2 & A34, x_r = 0, y_r = 0, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 0 of SRAM0 ,Compared with Table 2, the rotation factors are correct;

[0288] For A3 & A35, x_r = 1, y_r = 0, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 0 of SRAM0 ,Compared with Table 2, the rotation factors are correct;

[0289] For A4 & A36, x_r = 1, y_r = 0, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 0 of SRAM0 , compared with Table 2, the rotation factors are correct.

[0290] For example, in stage 2, as follows:

[0291] For parallel operations of C1&C9, C17&C25, C33&C41, C49&C57:

[0292] For C1 & C9, x_r = 0, y_r = 1, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 1 of SRAM0 ,Compared with Table 2, the rotation factors are correct;

[0293] For C17 & C25, x_r = 1, y_r = 1, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 1 of SRAM1 ,Compared with Table 2, the rotation factors are correct;

[0294] For C33 & C41, x_r = 2, y_r = 1, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 1 of SRAM2 ,Compared with Table 2, the rotation factors are correct;

[0295] For C49 & C57, x_r = 3, y_r = 1, as shown in Table 3 and Table 4 above, the rotation factor can be obtained from the storage location 1 of SRAM3 , compared with Table 2, the rotation factors are correct.

[0296] In the embodiment of the present application, after the data to be processed is stored according to the storage mapping relationship constructed by the above-mentioned rotation factor encoding device, the rotation factor acquisition device in the embodiment of the present application can be used to determine the storage location of the required rotation factor based on the static random access memory order corresponding to the polynomial pair involved in the operation and the butterfly calculation order of the polynomial group in which it is located in each stage of the forward number theory transformation of the data to be processed, and then the corresponding rotation factor can be obtained from the storage location.

[0297] Exemplary Methods

[0298] like Figure 4As shown, this exemplary embodiment proposes a method for encoding a rotation factor, which is used in the device 100 for encoding a rotation factor described in any one of the above items. The encoding method includes the following steps S100-S400:

[0299] Step S100: Based on the first acquisition module, the operation information of the data to be processed is acquired, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the forward number theory transformation;

[0300] Step S200: Based on the operation information, determine the various rotation factors required for the forward number theory transformation of the data to be processed;

[0301] Step S300: determining the stage of redundancy of rotation factors based on the parallelism;

[0302] Step S400: Based on the encoding module, construct a storage mapping relationship between each rotation factor in the target stage and each static random access memory used to store the rotation factor; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

[0303] The specific implementation methods of steps S100-S400 may refer to the specific implementation methods of the above-mentioned rotation factor encoding device 100 in each embodiment, which will not be described in detail here.

[0304] In an embodiment of the present application, the stage of determining the redundancy of the rotation factors based on the degree of parallelism includes:

[0305] The stage of the rotation factor redundancy is the first (b-1) stage of the data to be processed during the forward number theory transformation; wherein K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

[0306] In an embodiment of the present application, the storage mapping relationship between each rotation factor in the target construction stage and each static random access memory for storing the rotation factor includes:

[0307] Obtain candidate rotation factors from each rotation factor in the target stage;

[0308] Reversing the high and low bits of the binary code of the exponent of the candidate conversion factor to obtain a reversed binary code;

[0309] Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed;

[0310] Convert the flipped binary code into a decimal number;

[0311] Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

[0312] In the embodiment of the present application, the binary coded bits of the exponents of the candidate rotation factors are determined based on the largest rotation factor exponent required for the data to be processed.

[0313] In the embodiment of the present application, the step of determining, based on the flipped binary code, the stage in which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed, includes:

[0314] The number of bits from low to high in the first code 1 from high to low in the flipped binary code is used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

[0315] In an embodiment of the present application, the determining of the static random access memory code corresponding to the candidate rotation factor based on the converted decimal number, and the storage location of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation, includes:

[0316] When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and,

[0317] When x_w=2*i_rev, y_w=0;

[0318] When x_w=2*i_rev+1, y_w=0;

[0319] When x_w=i_rev / / When r∈[b,n-1], y_w= +i_rev-x_w* ;

[0320] When i_rev≥ , r∈[b,n-1], x_w=i_rev / / ,y_w= +i_rev-x_w* ;

[0321] in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the encoding of the static random access memory, and y_w represents the storage location in the static random access memory.

[0322] In the embodiment of the present application, when constructing the storage mapping relationship of the rotation factors, the rotation factors in the stage of redundant rotation factors are discarded, that is, the redundant rotation factors do not need to be stored, thereby reducing the storage space overhead of the rotation factors.

[0323] like Figure 5 As shown, the present application further proposes a method for reading a rotation factor, which is applied to the rotation factor reading device 200 described in any of the above embodiments. In the embodiment of the present application, the reading method includes the following steps S500-S700:

[0324] Step S500: Based on the second acquisition module, determine the parallelism and stage of the forward number theory transformation of the data to be processed;

[0325] Step S600: if r∈[0,b-1];

[0326] Then, based on the second acquisition module, determining the static random access memory order corresponding to each polynomial pair participating in the same parallel operation;

[0327] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory;

[0328] If r∈[b,n-1];

[0329] Based on the second acquisition module, determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs;

[0330] Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory;

[0331] Step S700: Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage position in the static random access memory, read the rotation factors corresponding to each polynomial pair;

[0332] Among them, r is the stage, K is the parallelism, .

[0333] The specific implementation methods of steps S500-S700 may refer to the specific implementation methods of the above-mentioned rotation factor reading device 200 in each embodiment, which will not be described in detail here.

[0334] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory based on the static random access memory order corresponding to each polynomial pair participating in the operation in the same parallel operation, includes:

[0335] When r∈[0,b-2], x_r=2*t / / , y_r=0;

[0336] When r=b-1, x_r=t, y_r=0;

[0337] Wherein, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the SRAM code, and y_r is the storage location in the SRAM.

[0338] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial in the same parallel operation are located, and the storage location in the static random access memory based on the corresponding static random access memory order and the butterfly calculation order, includes:

[0339] x_r=t,y_r= +j;

[0340] Among them, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the static random access memory where the rotation factor is located, and y_r is the storage location of the rotation factor in the static random access memory.

[0341] In the embodiment of the present application, after the data to be processed is stored according to the storage mapping relationship constructed by the above-mentioned rotation factor encoding device 100, the rotation factor acquisition method in the embodiment of the present application can be used to determine the storage location of the required rotation factor based on the static random access memory order corresponding to the polynomial pair involved in the operation and the butterfly calculation order of the polynomial group in which it belongs in each stage of the forward number theory transformation of the data to be processed, and then the corresponding rotation factor can be obtained from the storage location.

[0342] Exemplary Media

[0343] After introducing the method, medium and system of the exemplary embodiments of the present application, next, reference is made to Figure 6 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 6 , the computer-readable storage medium shown is a CD-ROM 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, it will implement the steps described in the above method implementation, for example, based on the first acquisition module, the operation information of the data to be processed is obtained, the operation information includes the sequence length of the data to be processed and the degree of parallelism during the forward number theory transformation; based on the operation information, the various rotation factors required for the data to be processed during the forward number theory transformation are determined; based on the degree of parallelism, the stage of redundancy of the rotation factors is determined; based on the encoding module, the storage mapping relationship between the various rotation factors in the target stage and the various static random access memories used to store the rotation factors is constructed; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in the various stages required for the forward number theory transformation of the data to be processed. Alternatively, based on the second acquisition module, the degree of parallelism and stage when the data to be processed undergoes a forward number theory transformation are determined;

[0344] If r∈[0,b-1];

[0345] then determining, based on the second acquisition module, a static random access memory order corresponding to each polynomial pair participating in the same parallel operation;

[0346] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory;

[0347] If r∈[b,n-1];

[0348] then determining, based on the second acquisition module, a static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and a butterfly calculation order of the polynomial group to which each polynomial pair belongs;

[0349] Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory;

[0350] Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory, reading the rotation factors corresponding to each polynomial pair;

[0351] Among them, r is the stage, K is the parallelism, .

[0352] The specific implementation of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which will not be repeated here.

[0353] Exemplary Chips

[0354] After introducing the method, apparatus, and medium of the exemplary embodiment of the present application, next, the chip of the exemplary embodiment of the present application is introduced.

[0355] In an embodiment of the present application, a chip is proposed, including the rotation factor encoding device or the rotation factor reading device described in any of the above embodiments, and therefore has all the beneficial effects of the rotation factor encoding device or the rotation factor reading device described in the above embodiments, which are not described one by one here.

[0356] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0357] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A twiddle factor encoding device for a forward number theory transform circuit, the encoding device comprising: A first acquisition module is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during forward number theory transformation; Based on the operation information, determining various rotation factors required for the data to be processed during forward number theory transformation; Based on the parallelism, determining a stage of redundancy of twiddle factors; The encoding module is used to construct a storage mapping relationship between each rotation factor in the target stage and each static random access memory for storing the rotation factor; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

2. The apparatus for encoding a rotation factor according to claim 1, wherein: The first acquisition module is configured to determine the stage of redundancy of the rotation factors based on the following method: The stage of the rotation factor redundancy is the first (b-1) stage of the data to be processed during the forward number theory transformation; wherein, K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

3. The device for encoding a rotation factor according to claim 1, wherein the encoding module is configured to construct a storage mapping relationship based on the following method: Obtain candidate rotation factors from each rotation factor in the target stage; Flipping the high and low bits of the binary code of the exponent of the candidate rotation factor to obtain a flipped binary code; Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed; Convert the flipped binary code into a decimal number; Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

4. The device for encoding a rotation factor according to claim 3, wherein the bits of the binary code of the index of the candidate rotation factor are determined based on a rotation factor index required by the data to be processed that is the largest.

5. The device for encoding a rotation factor according to claim 3, wherein the encoding module is configured to determine the stage at which the candidate rotation factor first participates in the forward scalar transform of the data to be processed based on the following method: The number of bits from low to high in the first code 1 from high to low in the flipped binary code is used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

6. The apparatus for encoding a rotation factor according to claim 3, wherein the encoding module is configured to: When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and, When x_w=2*i_rev, y_w=0; When x_w=2*i_rev+1, y_w=0; When \(x_w = i_{rev}\) / / , \(r\in[b, n - 1]\), \(y_w=\) + \(i_{rev}-x_w\times\) ; When \(i\_rev\geq\) , \(r\in[b, n - 1]\), \(x\_w = i\_rev / / \) , \(y\_w =\) + \(i\_rev - x\_w*\) ; in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the encoding of the static random access memory, and y_w represents the storage location in the static random access memory.

7. A method for encoding a rotation factor, used in the device for encoding a rotation factor according to any one of claims 1 to 6, the encoding method comprising: Based on the first acquisition module, obtaining operation information of the data to be processed, the operation information including the sequence length of the data to be processed and the degree of parallelism during forward number theory transformation; Based on the operation information, determining various rotation factors required for the data to be processed during forward number theory transformation; Based on the parallelism, determining a stage of redundancy of twiddle factors; Based on the encoding module, a storage mapping relationship between each rotation factor in the target stage and each static random access memory for storing the rotation factor is constructed; wherein the target stage is the stage after the stage in which the redundant rotation factors are discarded in each stage required for the forward number theory transformation of the data to be processed.

8. The method for encoding a rotation factor according to claim 7, wherein: The stage of determining the redundancy of rotation factors based on the degree of parallelism includes: The stage of the rotation factor redundancy is the first (b-1) stage of the data to be processed during the forward number theory transformation; wherein K= , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation.

9. The method for encoding a rotation factor according to claim 7, wherein the storage mapping relationship between each rotation factor and each static random access memory for storing the rotation factor in the target construction stage comprises: Obtain candidate rotation factors from each rotation factor in the target stage; Flipping the high and low bits of the binary code of the exponent of the candidate rotation factor to obtain a flipped binary code; Based on the flipped binary code, determining the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed; Convert the flipped binary code into a decimal number; Based on the converted decimal digits, a static random access memory code corresponding to the candidate rotation factor is determined, as well as a storage position of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation.

10. The method for encoding a rotation factor according to claim 9, wherein the bits of the binary code of the index of the candidate rotation factor are determined based on a rotation factor index with the largest index required by the data to be processed.

11. The method for encoding a rotation factor according to claim 9, wherein the step of determining, based on the flipped binary code, the stage at which the candidate rotation factor first participates in the operation in the forward scalar transformation of the data to be processed, comprises: The number of bits from low to high in the first code 1 from high to low in the flipped binary code is used as the number of stages in which the candidate rotation factor first participates in the forward scalar transformation of the data to be processed.

12. The method for encoding a rotation factor according to claim 9, wherein the step of determining the static random access memory code corresponding to the candidate rotation factor based on the converted decimal code, and the storage location of the candidate rotation factor in the static random access memory in each stage of the forward number theory transformation comprises: When i_rev< When x_w is 2*i_rev and 2*i_rev+1 and i_rev / / ,and, When x_w=2*i_rev, y_w=0; When x_w=2*i_rev+1, y_w=0; When \(x_w = i_{rev}\parallel\) , \(r\in[b, n - 1]\), \(y_w = \) + \(i_{rev}-x_w\times\) ; When \(i\_rev\geq\) , \(r\in[b, n - 1]\), \(x\_w = i\_rev / / \) , \(y\_w =\) + \(i\_rev - x\_w*\) ; in, , N is the sequence length of the data to be processed, , K is the degree of parallelism when the data to be processed is subjected to forward number theory transformation, r is the stage when the data to be processed is subjected to forward number theory transformation, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the decimal number converted from the binary code after reversal, / / represents rounding down, x_w represents the encoding of the static random access memory, and y_w represents the storage location in the static random access memory.

13. A device for reading a rotation factor, wherein: The reading device is used to read the rotation factor from a preset storage module, the rotation factor is based on the storage mapping relationship constructed by the encoding device of the rotation factor according to any one of claims 1 to 6, and is stored in the preset storage module, the reading device includes: The second acquisition module is used to obtain the parallelism and stage of the data to be processed when performing forward number theory transformation; If r∈[0,b-1]; The second acquisition module is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation; Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory; If r∈[b,n-1]; The second acquisition module is used to determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs; Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory; A reading module, used for reading the rotation factors corresponding to each polynomial pair based on the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage position in the static random access memory; Among them, r is the stage, K is the parallelism, .

14. The apparatus for reading a rotation factor according to claim 13, wherein the second acquisition module is configured to determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial in the same parallel operation is located, and the storage position in the static random access memory by the following method: When r∈[0,b-2], x_r=2*t / / , y_r=0; When r=b-1, x_r=t, y_r=0; in, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the static random access memory code, and y_r is the storage location in the static random access memory.

15. The apparatus for reading a rotation factor according to claim 13, wherein the second acquisition module is further configured to determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial in the same parallel operation is located, and the storage position in the static random access memory by the following method: x_r=t,y_r= +j; in, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the static random access memory where the rotation factor is located, and y_r is the storage location of the rotation factor in the static random access memory.

16. A method for reading a rotation factor, applied to the device for reading a rotation factor according to any one of claims 13 to 15, the method comprising: Based on the second acquisition module, determining the parallelism and the stage when the forward number theory transformation is performed on the data to be processed; If r∈[0,b-1]; Then, based on the second acquisition module, determining the static random access memory order corresponding to each polynomial pair participating in the same parallel operation; Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage position in the static random access memory; If r∈[b,n-1]; Based on the second acquisition module, determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the butterfly calculation order of the polynomial group to which each polynomial pair belongs; Based on the static random access memory order and the butterfly calculation order, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage location in the static random access memory; Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage location in the static random access memory, reading the rotation factors corresponding to each polynomial pair; Among them, r is the stage, K is the parallelism, .

17. The method for reading a twiddle factor according to claim 16, wherein the step of determining the codes of the twiddle factors corresponding to the twiddle factors in the same parallel operation and the storage locations in the twiddle factors in the twiddle factors corresponding to the twiddle factors in the same parallel operation based on the twiddle factors corresponding to the twiddle factors in the same parallel operation, and the storage locations in the twiddle factors in the twiddle factors in the same parallel operation, comprises: When r∈[0,b-2], x_r=2*t / / , y_r=0; When r=b-1, x_r=t, y_r=0; Wherein, t represents the SRAM order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], x_r is the SRAM code, and y_r is the storage location in the SRAM.

18. The method for reading a twiddle factor according to claim 16, wherein the step of determining the encoding of the twiddle factor corresponding to each polynomial in the same parallel operation and the storage position in the twiddle factor based on the corresponding twiddle factor order and the butterfly calculation order comprises: x_r=t,y_r= +j; Among them, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K], j is the butterfly calculation order of the polynomial group to which the polynomial pair participating in the parallel operation belongs, j∈[0, -1], x_r is the code of the static random access memory where the rotation factor is located, and y_r is the storage location of the rotation factor in the static random access memory.

19. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to perform the method according to any one of claims 7 to 12 or 16 to 18.

20. A chip comprising the device according to any one of claims 1-6 or 13-15.

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