A method, device and computer-readable storage medium for optimizing logic of large-scale integrated circuit design with time-balanced timing

Abstract

The present invention belongs to the technical field of digital circuit design optimization, and more specifically, relates to a timing-balanced large-scale integrated circuit design logic optimization method, device and computer-readable storage medium. The method includes obtaining a netlist to be optimized, taking out a combinational logic chain with more than Z cascaded combinational logic devices of the same type in the netlist; analyzing the operational characteristics of the logic gates or logic blocks in the combinational logic chain, and designing the minimum logic unit; using the minimum logic unit to optimize the combinational logic circuit structure corresponding to the combinational logic chain to compare whether the functions of the combinational logic circuit structure generated by the minimum logic unit and the combinational logic chain before optimization are completely consistent. The present invention solves the problem that the logic gate optimization has the disadvantages of increasing complexity and extending the design cycle in the timing optimization of large-scale integrated circuit design.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital circuit design optimization, and more specifically, relates to a timing-balanced large-scale integrated circuit design logic optimization method, device and computer-readable storage medium. Background Art

[0002] At present, the complexity of large-scale integrated circuits continues to increase, containing more logic gates, registers and signal paths. At the same time, due to the introduction of sub-micron technology, the size of integrated circuit devices is getting smaller and smaller, and the signal transmission speed is getting faster and faster, but at the same time, it also brings more timing problems, such as signal jitter, cross-coupling, etc. In order to achieve higher performance and speed of products, timing optimization has become a necessary link. Among them, optimizing the critical path length is an important part of timing optimization, because the critical path represents the most critical and time-consuming path in the circuit, and determines the shortest response time of the entire circuit. In circuit design, optimizing the critical path length can shorten the delay of the critical path, help improve timing problems in the synthesis, layout and routing, and verification stages, and improve the operating frequency and timing stability of the circuit.

[0003] Chinese patent document CN102880744A discloses a logic timing unit and an automated design platform based on the timing unit, including: the logic timing unit of the present invention includes a data input port, a master latch output port, a slave latch output port and a clock input port and its internal structure. Through a certain program flow, when the logic system does not meet the timing, the logic chain in the system is optimized to make full use of the logic timing and greatly improve the maximum operating clock frequency of the logic circuit.

[0004] In summary, in large-scale integrated circuit design, there are tens of thousands of logic gates. Global logic gate optimization is a very complex problem. Logic gate optimization is often an iterative and computationally intensive process that requires a lot of time and resources. In the actual application of integrated circuit design, long critical paths are more susceptible to timing noise and signal interference, which may cause timing failures, jitter, clock deviation and other problems. In the design process, the length of the critical path should be shortened as much as possible to reduce the sensitivity of timing noise and improve the reliability and stability of the circuit. Logic gate optimization is an important method in timing optimization in large-scale integrated circuit design, but it also has shortcomings such as increasing complexity and extending the design cycle. The logic gate optimization method in timing optimization of large-scale integrated circuit design still needs to be further investigated to achieve the purpose of optimizing timing. Summary of the invention

[0005] The present invention aims to overcome at least one defect of the above-mentioned prior art and provide a timing-balanced large-scale integrated circuit design logic optimization method to overcome the shortcomings of the prior art in logic optimization timing in electronic design automation.

[0006] The detailed technical scheme of the present invention is as follows:

[0007] A timing balanced large-scale integrated circuit design logic optimization method, the method comprising:

[0008] S1. Obtain a netlist to be optimized, and extract a combinational logic chain in which the number of cascaded combinational logic devices of the same type exceeds Z in the netlist;

[0009] The same type of combinational logic devices refer to logic gates or logic blocks with the same logic functions. Logic gates are electronic devices used to implement basic logic operations, while logic blocks are functional modules composed of multiple logic gates.

[0010] The cascade connection refers to connecting multiple logic gates or logic blocks together, that is, the output signal of one logic gate or logic block is transmitted to the input signal of the next logic gate or logic block to form a more complex logic circuit. Cascade connection is usually used to build complex logic circuits, such as adders, multipliers, memories, and control circuits.

[0011] Flexible and diverse digital logic functions can be achieved through reasonable cascade design.

[0012] S2. Analyze the operation characteristics of the logic gates or logic blocks in the combinational logic chain and select the minimum logic unit;

[0013] Furthermore, the selection rule of the minimum logic unit is: using the least logic gates or logic blocks so that the number of input signals N and above of the input signals of a single logic gate or logic block on the combinational logic chain can be parallelized; the parallelization refers to the process of calculating or processing multiple input signals at the same time to improve the processing speed and efficiency;

[0014] The selection of the minimum logic unit will take into account the number of input signals in the logic chain, combined with the optimization goals at the time and the timing, power consumption, area and other indicators of the selected logic gate.

[0015] S3, according to the input signal of the combinational logic chain, using the minimum logic unit to optimize the combinational logic chain layer by layer, and generating a combinational logic circuit structure containing only one output terminal signal;

[0016] S4. Compare the combinational logic circuit structure generated by the minimum logic unit with the combinational logic chain before optimization to see if their functions are completely consistent. If they are completely consistent, the timing-balanced large-scale integrated circuit design logic optimization is completed; otherwise, the optimization is exited.

[0017] Furthermore, the S2 also includes calculating the minimum number of logic units required, sum, including:

[0018] If there are X input signals, a single logic gate can accept N input signals, the minimum number of logic units required is set to sum, the initial value sum=0, " / " represents integer calculation, "%" represents remainder calculation, and "+=" represents accumulation. The calculation method is as follows:

[0019] a. first=X / N, second=X%N, sum+=first;

[0020] b. After completing step a, the total number of signals becomes: X=first+second;

[0021] At this time, if X≤N, add another MUX with N inputs, that is, sum+=1;

[0022] c. If X>N, then a and b need to be repeated.

[0023] Furthermore, the step of optimizing the combinational logic chain layer by layer using the minimum logic unit includes:

[0024] S31, obtaining the input signal of the parallel calculation required to generate the minimum logic unit of the current layer; the initial value of the required parallel calculation input signal is all the input signals of the combinational logic chain;

[0025] S32, construct the minimum logic unit of the current layer according to the input signals of the current layer parallel calculation, the number of the minimum logic units of the current layer is first=X / N, where X input signals, the number of input signals that a single logic gate can accept is N, " / " represents rounding calculation, the input end signal and the selection end signal of the minimum logic unit of the current layer are the same as the combinational logic chain to be optimized, and the minimum logic units are arranged in parallel;

[0026] If the number of input signals required in S31 is not an integer multiple of the number of input signals required by the minimum logic unit, the remaining input signals are not processed and are used when generating the next minimum logic unit;

[0027] S33, setting the input signal of parallel calculation required for generating the minimum logic unit of the next layer to be: the sum of the output signal of the minimum logic unit generated in the current layer and the remaining input signal of the minimum logic unit that cannot be generated in the current layer;

[0028] S34, if the input signal required for the parallel calculation of the minimum logic unit of the next layer generates at least one minimum logic unit, then go to execution of S31 to S34;

[0029] Otherwise, the input signal required for parallel calculation of the minimum logic unit of the next layer is generated and implemented using the currently processed logic gate or logic block to generate a combinational logic circuit structure containing only one output terminal signal.

[0030] In another aspect of the present invention, there is provided a device for implementing a timing balanced large-scale integrated circuit design logic optimization method, the device comprising:

[0031] at least one processor; and

[0032] A memory stores instructions, and when the instructions are executed by the at least one processor, the at least one processor executes the timing-balanced large-scale integrated circuit design logic optimization method as described above.

[0033] In another aspect of the present invention, a machine-readable storage medium is provided, which stores executable instructions, and when the instructions are executed, the machine executes the timing-balanced large-scale integrated circuit design logic optimization method as described above.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] The present invention provides a timing-balanced large-scale integrated circuit design logic optimization method, device and computer-readable storage medium. The timing-balanced large-scale integrated circuit design logic optimization method provided by the present invention analyzes the operation characteristics of the logic gates or logic blocks in the combinational logic chain to design the corresponding minimum logic unit; converts the serial calculation of the combinational logic chain into a parallel calculation method realized by the minimum logic unit, effectively balances the path delay, and then reconstructs the circuit structure corresponding to the combinational logic chain. The length of the critical path is greatly shortened, so that the circuit can complete the calculation and data transmission faster, and the response speed and performance of the system are improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a schematic diagram of the process of the method of the present invention;

[0037] Figure 2 is a schematic diagram of the combinational logic chain to be optimized in Example 1;

[0038] Figure 3 is a schematic diagram of the minimum logic unit of the combinational logic chain to be optimized in Example 1;

[0039] Figure 4 is a schematic diagram of the first-layer minimum logical unit group constructed in Example 1;

[0040] Figure 5 It is a schematic diagram of the structure of the combinational logic circuit after optimization in Example 1. DETAILED DESCRIPTION

[0041] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0042] It should be noted that the following detailed descriptions are exemplary and are intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0043] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0044] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0045] Example 1

[0046] Ginseng Figure 1 This embodiment provides a timing-balanced large-scale integrated circuit design logic optimization method, including:

[0047] S1. Obtain a netlist to be optimized, and extract the combinational logic chains in which the number of cascaded combinational logic devices of the same type exceeds Z in the netlist. Preferably, Z=3:

[0048] The same type of combinational logic devices refer to logic gates or logic blocks with the same logical functions. Logic gates are electronic devices used to implement basic logical operations (such as AND gates, OR gates, NOT gates, etc.), while logic blocks are functional modules composed of multiple logic gates.

[0049] The cascade connection refers to connecting multiple logic gates or logic blocks together, that is, the output signal of one logic gate or logic block is transmitted to the input signal of the next logic gate or logic block to form a more complex logic circuit.

[0050] Cascade connections are often used to build complex logic circuits, such as adders, multipliers, memories, control circuits, etc. Through reasonable cascade design, flexible and diverse digital logic functions can be achieved.

[0051] The reason why the number of cascades exceeds 3 is that the scale of cascading logic gates or logic blocks within 3 is relatively small and does not need to be optimized.

[0052] In S1, for the convenience of describing and understanding this embodiment, it is assumed that the combinational logic chain to be optimized in the netlist is as shown in the attached figure. Figure 2As shown in the figure, the combinatorial logic chain to be optimized is composed of 12 logic gates (2-to-1 multiplexers (MUX)) of the same functional type in cascade. Among them, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11 and D12 represent the input signals of the combinatorial logic chain, and S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11 and S12 represent the selection end signals of the combinatorial logic chain.

[0053] S2. Analyze the operation characteristics of the logic gates or logic blocks in the combinational logic chain and select the minimum logic unit;

[0054] The selection rule of the minimum logic unit is: use the least logic gates or logic blocks to enable parallel calculation of the input signals N and above of a single logic gate or logic block on the combinational logic chain; parallel calculation refers to the process of calculating or processing multiple input signals at the same time to improve processing speed and efficiency.

[0055] Preferably, the logic gate in the combinatorial logic chain to be optimized is MUX, and its operation characteristics are known: MUX has two data input terminals (marked as D0 and D1) and a selection input terminal (marked as S). According to the value of the selection input terminal, the MUX selector will pass the value of one of the data input terminals to the output terminal.

[0056] When the selection input is 0, the output is D0; when the selection input is 1, the output is D1. In short, when the selection input is 0, MUX passes the value of D0 to the output;

[0057] When the selection input is 1, the value of D1 is transferred to the output terminal. Otherwise, the value of the non-selected input terminal is not transferred to the output terminal.

[0058] In addition, MUX is extensible and can realize higher-bit selection functions through cascade connection. For example, by connecting the outputs of multiple MUXs again to the data input of the next MUX, selectors with higher bits such as 4-to-1 and 8-to-1 can be realized. The function of the combinational logic chain to be optimized in this embodiment will not be further analyzed.

[0059] Preferably, the minimum logic unit is selected as follows: the number of input signals of a single logic gate (i.e., MUX) is 2. To calculate more than 2 signals at the same time, at least 2 MUXs are used. After using two MUXs to calculate 4 signals at the same time, 2 output signals will be generated, so another MUX is needed to calculate these 2 output signals. Therefore, the minimum logic unit requires 3 MUXs to be implemented, and its structure is as follows: Figure 3As shown, d0, d1, d2 and d3 represent data input terminals of the minimum logic unit, s0, s1 and s2 represent selection input terminals of the minimum logic unit, and out represents the output terminal of the minimum logic unit.

[0060] Specifically, S2 also includes calculating the number of minimum logic units required, sum, including:

[0061] If there are X input signals, a single logic gate can accept N input signals, the minimum number of logic units required is set to sum, the initial value sum=0, " / " represents integer calculation, "%" represents remainder calculation, and "+=" represents accumulation. The calculation method is as follows:

[0062] a. first=X / N, second=X%N, sum+=first;

[0063] b. After completing step a, the total number of signals becomes: X=first+second;

[0064] At this time, if X≤N, add another MUX with N inputs, that is, sum+=1;

[0065] c. If X>N, then a and b need to be repeated.

[0066] S3. According to the input signal of the combinational logic chain, the combinational logic chain is optimized layer by layer using the minimum logic unit to generate a combinational logic circuit structure containing only one output terminal signal.

[0067] The process of optimizing the combinatorial logic circuit structure corresponding to the combinatorial logic chain by using the minimum logic unit is as follows:

[0068] S31, obtaining the input signal of the parallel calculation required to generate the minimum logic unit of the current layer, where the initial value of the required parallel calculation input signal is all the input signals of the combinational logic chain;

[0069] Specifically, all input signals of the combinational logic chain are: D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11 and D12.

[0070] S32, construct the minimum logic unit of the current layer according to the input signals of the current layer calculated in parallel, the number of the minimum logic units of the current layer is first=X / N, where X input signals, the number of input signals that a single logic gate can accept is N, " / " represents rounding calculation, the input end signal and the selection end signal of the minimum logic unit of the current layer are the same as the combinational logic chain to be optimized; these minimum logic units are arranged in parallel so that as many input signals as possible can be calculated or processed simultaneously;

[0071] If the number of input signals required in S31 is not an integer multiple of the number of input signals required by the minimum logic unit, the remaining input signals are not processed and are used when generating the next minimum logic unit;

[0072] Specifically, in this embodiment, there are 13 input signals in total, 3 minimum logic units can be constructed and 1 input signal is left. The first layer minimum logic unit group constructed is as follows: Figure 4 As shown in the figure, the names and meanings of the input terminal signals and the selection terminal signals are the same as those in Figure 2 The same as in the above, where "|" in the selection terminal signals S2|S3, S6|S7 and S10|S11 represents logical OR. The logical OR gate has two or more input terminals to receive logical values ​​(0 or 1); as long as the logical value of one or more input terminals is 1, the output will be 1, and the output will be 0 only when the logical values ​​of all input terminals are 0. Figure 4 The output signals of the smallest logic unit constructed in are out0, out1 and out2 from top to bottom.

[0073] S33, setting the input signal of parallel calculation required for generating the minimum logic unit of the next layer to be: the sum of the output signal of the minimum logic unit generated in the current layer and the remaining input signal of the minimum logic unit that cannot be generated in the current layer;

[0074] According to S32, the input signals required for parallel calculation of the minimum logic unit group of the next layer (ie, the second layer) are: out0, out1, out2 and D12.

[0075] S34, if the input signal required for the parallel calculation of the minimum logic unit of the next layer generates at least one minimum logic unit, then go to execution of S31 to S34;

[0076] Otherwise, the input signal required for parallel calculation of the minimum logic unit of the next layer is generated by using the currently processed logic gate or logic block to generate a combinational logic circuit structure containing only one output terminal signal;

[0077] Specifically, in this embodiment, there are 4 input signals required for parallel calculation of the second-layer minimum logic unit group, and one minimum logic unit can be generated, so the above steps are repeated to generate one minimum logic unit of the second layer. The process of generating the second-layer minimum logic unit group is as follows:

[0078] S341. Obtain the input signal for parallel computing required to generate the second-layer minimum logic unit, that is, Figure 4 out0, out1, out2 and Figure 2 D12 in;

[0079] S342. There are 4 input signals in total, which can construct a minimum logic unit. The relationship between this minimum logic unit and the minimum logic unit group of the first layer is as follows: Figure 5 As shown in the figure, the names and meanings of the input terminal signals and the selection terminal signals are the same as those in Figure 2 The same as in the above, where “|” in the selection terminal signals S4|S5|S6|S7 and S8|S9|S10|S11|S12 represents a logical OR operation, Figure 5 The output signal of the second layer of the smallest logic unit constructed in is out3;

[0080] S343. According to the previous step, the input signal required for parallel calculation of the minimum logic unit group of the next layer (ie, the third layer) is: out3;

[0081] S344. The third-layer minimum logic unit group has only one input signal required for parallel calculation, which cannot be used to construct a minimum logic unit or a single MUX logic gate. So far, the optimization of the combinational logic circuit structure corresponding to the combinational logic chain is completed, and a combinational logic circuit structure containing only one output terminal signal is obtained, which is Figure 5 shown.

[0082] S4. Determine whether the functions before and after optimization are completely consistent:

[0083] Compare whether the functions of the combinational logic circuit structure generated by the minimum logic unit in S3 and the combinational logic chain before optimization are completely consistent. If they are completely consistent, the timing balanced large-scale integrated circuit design logic optimization is completed; otherwise, the optimization is exited.

[0084] Specifically, contrast Figure 5 The optimized combinational logic circuit structure and Figure 2 The combinational logic circuit structure before optimization is shown. It can be seen that the functions of the two are consistent and the optimization is completed.

[0085] Figure 2 The length of the critical path in the combinatorial logic chain to be optimized is 12. Figure 5 After the optimization is completed, the critical path length of the circuit structure is 4, compared with Figure 5 The combinational logic circuit structure shown in Figure 2 The critical path of the combinational logic circuit structure is longer, which means that the circuit takes longer to complete calculations or transmit data, affecting the response speed of the system. The signal is also more susceptible to timing noise during transmission, and timing noise may cause signal jitter, clock jitter or loss of signal integrity, which in turn causes uncertainty and stability problems in circuit performance. Figure 5The maximum operating speed of the combinational logic circuit structure shown in is better, the signal propagation time and the delay difference in the path are reduced, the sensitivity to timing noise is reduced, and the reliability and stability of the circuit are improved.

[0086] Example 2

[0087] This embodiment provides a device for implementing a timing-balanced large-scale integrated circuit design logic optimization method, the device comprising:

[0088] at least one processor; and

[0089] A memory stores instructions, and when the instructions are executed by the at least one processor, the at least one processor executes the timing-balanced large-scale integrated circuit design logic optimization method as described above.

[0090] In this embodiment, the device includes but is not limited to: personal computers, server computers, workstations, desktop computers, laptop computers, notebook computers, mobile computing devices, smart phones, tablet computers, cellular phones, personal digital assistants (PDAs), handheld devices, messaging devices, wearable computing devices, consumer electronic devices, etc.

[0091] Example 3

[0092] This embodiment also provides a computer-readable storage medium storing executable instructions, which, when executed, enable the machine to perform the above-mentioned timing-balanced large-scale integrated circuit design logic optimization method.

[0093] Specifically, a system or device equipped with a readable storage medium can be provided, on which software program codes that implement the functions of any of the above-mentioned embodiments are stored, and a computer or processor of the system or device can read and execute instructions stored in the readable storage medium.

[0094] In this case, the program code itself read from the machine-readable medium can realize the function of any one of the above embodiments, and thus the machine-readable code and the machine-readable storage medium storing the machine-readable code constitute part of this specification.

[0095] Examples of readable storage media include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD-RW), magnetic tapes, non-volatile memory cards, and ROMs. Optionally, the program code may be downloaded from a server computer or a cloud via a communication network.

[0096] It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0097] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0098] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0099] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0100] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the technical solution of the present invention, and are not intended to limit the specific implementation methods of the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the claims of the present invention shall be included in the protection scope of the claims of the present invention.

Claims

1. A timing balanced large-scale integrated circuit design logic optimization method, characterized in that: The method comprises: S1. Obtain a netlist to be optimized, and extract a combinational logic chain in which the number of cascaded combinational logic devices of the same type exceeds Z in the netlist; S2. Analyze the operation characteristics of the logic gates or logic blocks in the combinational logic chain and select the minimum logic unit; S3, according to the input signal of the combinational logic chain, using the minimum logic unit to optimize the combinational logic chain layer by layer, and generating a combinational logic circuit structure containing only one output terminal signal; The step-by-step optimization of the combinational logic chain using the minimum logic unit includes: S31, obtaining the input signal of the parallel calculation required to generate the minimum logic unit of the current layer; the initial value of the required parallel calculation input signal is all the input signals of the combinational logic chain; S32, construct the minimum logic unit of the current layer according to the input signals of the current layer parallel calculation, the number of the minimum logic units of the current layer is first=X / N, where X input signals, the number of input signals that a single logic gate can accept is N, " / " represents rounding calculation, the input end signal and the selection end signal of the minimum logic unit of the current layer are the same as the combinational logic chain to be optimized, and the minimum logic units are arranged in parallel; If the number of input signals required in S31 is not an integer multiple of the number of input signals required by the minimum logic unit, the remaining input signals are not processed and are used when generating the next minimum logic unit; S33, setting the input signal of parallel calculation required for generating the minimum logic unit of the next layer to be: the sum of the output signal of the minimum logic unit generated in the current layer and the remaining input signal of the minimum logic unit that cannot be generated in the current layer; S34, if the input signal required for the parallel calculation of the minimum logic unit of the next layer generates at least one minimum logic unit, then go to execution of S31 to S34; Otherwise, the input signal required for parallel calculation of the minimum logic unit of the next layer is generated by using the currently processed logic gate or logic block to generate a combinational logic circuit structure containing only one output terminal signal; S4. Compare the combinational logic circuit structure generated by using the minimum logic unit and the combinational logic chain before optimization to see whether their functions are completely consistent; If they are completely consistent, the timing balanced LSI design logic optimization is completed; otherwise, the optimization is exited.

2. The method for optimizing logic of LSI design with timing balance according to claim 1, characterized in that: The design rule of the minimum logic unit is: using the least number of logic gates or logic blocks so that the number of input signals N and above of input signals of a single logic gate or logic block on the combinational logic chain can be calculated in parallel; The parallel computing refers to the process of computing or processing multiple input signals simultaneously.

3. The method for optimizing logic of LSI design with timing balance according to claim 2, characterized in that: The S2 also includes calculating the minimum number of logic units required, which is: If there are X input signals, a single logic gate can accept N input signals, the minimum number of logic units required is set to sum, the initial value sum=0, " / " represents integer calculation, "%" represents remainder calculation, "+=" represents accumulation, the calculation method is as follows: a. first=X / N, second=X%N, sum+=first; b. After completing step a, the total number of signals becomes: X=first+second; At this time, if X≤N, add another MUX with N inputs, that is, sum+=1; c. If X>N, then a and b need to be repeated.

4. A timing balanced large-scale integrated circuit design logic optimization device, characterized in that: The device comprises: processor; a memory having stored thereon a computer program executable on the processor; Wherein, when the computer program is executed by the processor, the steps of a timing-balanced large-scale integrated circuit design logic optimization method as described in any one of claims 1 to 3 are implemented.

5. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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