Display panel and driving method thereof

Abstract

The application provides a display panel and a driving method thereof. The display panel comprises a storage capacitor electrically connected between a first node and a fifth node; a first transistor comprising a gate electrode electrically connected to a second scan line, one of a source electrode and a drain electrode electrically connected to a fourth power supply line, and the other of the source electrode and the drain electrode electrically connected to the fifth node; a fifth transistor comprising a gate electrode electrically connected to a third scan line, one of a source electrode and a drain electrode electrically connected to a first power supply line, and the other of the source electrode and the drain electrode electrically connected to the first node; the second scan line and the third scan line are connected to the same driving circuit, and in each frame of a display picture, the display panel comprises a first reset stage, in the first reset stage, the fifth transistor is used for resetting the first node, the first transistor is used for resetting the fifth node, and the first node and the fifth node are synchronously reset.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a driving method thereof. BACKGROUND

[0002] In the related art, a display panel includes a driving circuit and a light emitting device, the driving circuit is electrically connected with the light emitting device to drive the light emitting device to emit light. However, the display panel in the related art will cause the picture displayed by the display panel to have a ghosting effect, which affects the display effect. SUMMARY

[0003] Therefore, the present application provides a display panel and a driving method thereof to improve the problem that the picture displayed by the display panel has a ghosting effect.

[0004] The technical scheme adopted by the present application to solve the above technical problem is as follows:

[0005] In a first aspect, an embodiment of the present application provides a display panel, comprising:

[0006] a third transistor comprising a gate electrode electrically connected to a first node, one of a source electrode and a drain electrode electrically connected to a second node, and the other of the source electrode and the drain electrode electrically connected to a third node;

[0007] a seventh transistor comprising a gate electrode electrically connected to a second gate line, one of a source electrode and a drain electrode electrically connected to a fifth power supply line, and the other of the source electrode and the drain electrode electrically connected to the second node;

[0008] a sixth transistor comprising a gate electrode electrically connected to a first gate line, one of a source electrode and a drain electrode electrically connected to the third node, and the other of the source electrode and the drain electrode electrically connected to a fourth node;

[0009] a light emitting device electrically connected between the fourth node and a sixth power supply line;

[0010] a storage capacitor electrically connected between the first node and a fifth node;

[0011] a first transistor comprising a gate electrode electrically connected to a second scan line, one of a source electrode and a drain electrode electrically connected to a fourth power supply line, and the other of the source electrode and the drain electrode electrically connected to the fifth node;

[0012] a second transistor comprising a gate electrode electrically connected to a first scan line, one of a source electrode and a drain electrode electrically connected to a data line, and the other of the source electrode and the drain electrode electrically connected to the fifth node;

[0013] a fifth transistor comprising a gate electrode electrically connected to a third scan line, one of a source electrode and a drain electrode electrically connected to a first power supply line, and the other of the source electrode and the drain electrode electrically connected to the first node;

[0014] The second scan line and the third scan line are connected to a same driving circuit, and in each frame of a display picture, the display panel comprises a first reset stage, the fifth transistor is configured to reset the first node, the first transistor is configured to reset the fifth node, and the first node and the fifth node are reset synchronously.

[0015] In some embodiments of the present application, a scan signal of the second scan line has a same waveform as a scan signal of the third scan line, and a phase of the scan signal of the second scan line is behind a phase of the scan signal of the third scan line, the scan signal of the second scan line and the scan signal of the third scan line partially overlap in phase, and in the overlapping phase, at least a part of the scan signal of the second scan line and the scan signal of the third scan line are at a same level.

[0016] In some embodiments of the present application, the first reset stage comprises a first reset sub-stage and a second reset sub-stage, in the first reset sub-stage, the fifth transistor is turned on, in the second reset sub-stage, the fifth transistor and the first transistor are both turned on, and the seventh transistor is turned off.

[0017] In some embodiments of the present application, the display panel further comprises a fourth transistor, the fourth transistor comprising a gate electrode electrically connected to the second scan line, one of a source electrode and a drain electrode electrically connected to the first node, and the other of the source electrode and the drain electrode electrically connected to the third node;

[0018] In each frame of a display picture, the display panel comprises a compensation stage, in the compensation stage, the third transistor, the fourth transistor and the seventh transistor are all turned on, and the fifth transistor is turned off, for charging the first node.

[0019] In some embodiments of the present application, in each frame of a display picture, the display panel comprises a data writing stage, in the data writing stage, the second transistor is turned on, and the first transistor and the seventh transistor are both turned off.

[0020] In some embodiments of the present application, the display panel further comprises an eighth transistor and a ninth transistor, the eighth transistor comprises a gate electrode electrically connected to the third gate line, one of a source electrode and a drain electrode electrically connected to the second power supply line, and the other of the source electrode and the drain electrode electrically connected to the fourth node; the ninth transistor comprises a gate electrode electrically connected to the third gate line, one of a source electrode and a drain electrode electrically connected to the third power supply line, and the other of the source electrode and the drain electrode electrically connected to the second node;

[0021] In each frame of display picture, the display panel comprises a second reset stage, in the second reset stage, the eighth transistor is turned on for resetting the anode of the light emitting device, the ninth transistor is turned on to charge the second node, and the seventh transistor is turned off.

[0022] In a second aspect, embodiments of the present application provide a driving method of a display panel, the display panel comprising a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a light emitting device, and a storage capacitor, in each frame of display picture, the display panel comprises a first driving mode, the first driving mode comprising a first reset stage, a data writing stage, and a first light emitting stage; in the first driving mode, the driving method comprises:

[0023] In the first reset stage, a second scan line provides a turn-on signal to the first transistor, a third scan line provides a turn-on signal to the fifth transistor, a first node electrically connected to the storage capacitor is reset through the fifth transistor, a fifth node electrically connected to the storage capacitor is reset through the first transistor, and the second scan line and the third scan line are connected to the same driving circuit;

[0024] In the data writing stage, a first scan line provides a turn-on signal to the second transistor, and a data line writes a data signal into the storage capacitor through the second transistor;

[0025] In the first light emitting stage, a first gate line provides a turn-on signal to the sixth transistor, a second gate line provides a turn-on signal to the seventh transistor, and the third transistor is controlled to be turned on to make the current of the fifth power supply line flow into the light emitting device through the seventh transistor, the third transistor, and the sixth transistor.

[0026] In some embodiments of the present application, the first reset stage comprises a first reset sub-stage and a second reset sub-stage, and the steps of, in the first reset stage, the second scan line providing a turn-on signal to the first transistor, the third scan line providing a turn-on signal to the fifth transistor, the first node electrically connected to the storage capacitor being reset through the fifth transistor, and the fifth node electrically connected to the storage capacitor being reset through the first transistor, comprise:

[0027] In the first reset sub-stage, the third scan line provides a conductive signal to the fifth transistor;

[0028] In the second reset sub-stage, the third scan line provides a conductive signal to the fifth transistor, the first node electrically connected to the storage capacitor is reset through the fifth transistor, the second scan line provides a conductive signal to the first transistor, the fifth node electrically connected to the storage capacitor is reset through the first transistor, and the second gate line provides a cutoff signal to the seventh transistor.

[0029] In some embodiments of the present application, the display panel further comprises a fourth transistor, the fourth transistor comprising a gate electrode electrically connected to the second scan line, one of a source electrode and a drain electrode electrically connected to the first node, and the other of the source electrode and the drain electrode electrically connected to a third node; the first driving mode further comprises a compensation stage, the compensation stage being located between the first reset stage and the data writing stage, and the driving method further comprises:

[0030] In the compensation stage, the second scan line provides a conductive signal to the first transistor and the fourth transistor, the second gate line provides a conductive signal to the seventh transistor, and the third transistor is controlled to be turned on.

[0031] In some embodiments of the present application, the display panel further comprises an eighth transistor and a ninth transistor, the eighth transistor comprising a gate electrode electrically connected to a third gate line, one of a source electrode and a drain electrode electrically connected to a second power supply line, and the other of the source electrode and the drain electrode electrically connected to the fourth node; the ninth transistor comprising a gate electrode electrically connected to the third gate line, one of a source electrode and a drain electrode electrically connected to a third power supply line, and the other of the source electrode and the drain electrode electrically connected to the second node; the first driving mode further comprises a second reset stage, the second reset stage being located between the data writing stage and the first light emitting stage, and the driving method further comprises:

[0032] In the second reset stage, the third gate line provides a conductive signal to the eighth transistor, and the third gate line provides a conductive signal to the ninth transistor.

[0033] In some embodiments of the present application, in each frame of the display picture, the display panel further comprises a second driving mode, the first driving mode being followed by the second driving mode at least once, for maintaining the light emitting brightness of the light emitting device.

[0034] In summary, due to the adoption of the above technical solutions, the present application at least includes the following beneficial effects:

[0035] The embodiments of the present application provide a display panel and a driving method thereof. The embodiments primarily connect the second and third scan lines to the same drive circuit and synchronously reset the nodes at both ends of the storage capacitor, thereby ensuring that the voltage state of the display panel is consistent before refreshing, eliminating voltage hysteresis caused by asynchronous reset, and more effectively clearing the residual charge on the storage capacitor, so that the display panel can return to a consistent initial state before each refresh, thereby reducing the effect of smearing. Furthermore, because the second and third scan lines are connected to the same drive circuit, the number of drive circuits can be reduced, thereby providing conditions for a narrow bezel of the display panel. Specifically, in the related art, because the nodes at both ends of the storage capacitor are not synchronously reset, the nodes at both ends of the storage capacitor will return to the initial level at different times, and voltage will remain in the storage capacitor, resulting in voltage hysteresis when the screen is updated, which manifests itself in the screen display as smearing. In the present application, in the first reset phase, the second scan line provides a turn-on signal to the first transistor, turning on the first transistor, and resetting the fifth node connected to the storage capacitor through the first transistor. At the same time, the third scan line provides a turn-on signal to the fifth transistor, turning on the fifth transistor. The first node connected to the storage capacitor is reset through the fifth transistor, achieving synchronous reset of the nodes at both ends of the storage capacitor without a reset time difference, ensuring that the initial state of the storage capacitor is completely consistent in each frame, and ensuring that the storage capacitor is in a clean initial state before each data write, thereby making the dynamic image displayed by the display panel clearer and smoother, and effectively improving the problem of ghosting on the display image of the display panel. In addition, by connecting the second scan line and the third scan line to the same drive circuit, it is beneficial to reduce the setting of the drive circuit, reduce costs, simplify circuit complexity, and make it easier for the display panel to achieve a narrow frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 A circuit diagram of a display panel provided in an embodiment of the present application;

[0037] Figure 2 A control timing diagram of a display panel in a first driving mode provided by an embodiment of the present application;

[0038] Figure 3 A control timing diagram of a display panel in a second driving mode provided by an embodiment of the present application;

[0039] Figure 4 A flowchart of a method for driving a display panel provided in an embodiment of the present application;

[0040] Figure 5 A control timing diagram provided for comparative example;

[0041] Figure 6 A control timing diagram for comparison with the comparative example is provided in the present application. DETAILED DESCRIPTION

[0042] The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

[0043] In the description of the present application, it should be understood that the words "first", "second" are used only for descriptive purposes and are not to be construed as indicating or implying relative importance or indicating the number of the technical features indicated. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0044] In the present application, the word "exemplary" is used to mean "serving as an example, instance, or illustration". Any embodiment described as "exemplary" in the present application is not necessarily to be construed as preferred or advantageous over other embodiments.

[0045] The embodiments of the present application provide a display panel, specifically refer to Figures 1 to 3 The display panel comprises:

[0046] The third transistor T3 comprises a gate electrode electrically connected to the first node Q, one of a source electrode and a drain electrode electrically connected to the second node A, and the other of the source electrode and the drain electrode electrically connected to the third node B;

[0047] The seventh transistor T7 comprises a gate electrode electrically connected to the second gate line EM2, one of a source electrode and a drain electrode electrically connected to the fifth power supply line VDD, and the other of the source electrode and the drain electrode electrically connected to the second node A;

[0048] The sixth transistor T6 comprises a gate electrode electrically connected to the first gate line EM1, one of a source electrode and a drain electrode electrically connected to the third node B, and the other of the source electrode and the drain electrode electrically connected to the fourth node C;

[0049] The light emitting device LED is electrically connected between the fourth node C and the sixth power supply line VSS;

[0050] The storage capacitor C2 is electrically connected between the first node Q and the fifth node D;

[0051] The first transistor T1 comprises a gate electrode electrically connected to the second scan line SCAN2, one of a source electrode and a drain electrode electrically connected to the fourth power supply line VI4, and the other of the source electrode and the drain electrode electrically connected to the fifth node D;

[0052] The second transistor T2 includes a gate electrode electrically connected to the first scan line SCAN1, one of a source electrode and a drain electrode electrically connected to the data line data, and the other of the source electrode and the drain electrode electrically connected to the fifth node D;

[0053] The fifth transistor T5 includes a gate electrode electrically connected to the third scan line SCAN3, one of a source electrode and a drain electrode electrically connected to the first power supply line VI1, and the other of the source electrode and the drain electrode electrically connected to the first node Q;

[0054] The second scan line SCAN2 and the third scan line SCAN3 are connected to the same driving circuit, and in each frame of a display picture, the display panel includes a first reset stage, the fifth transistor T5 is configured to reset the first node Q, the first transistor T1 is configured to reset the fifth node D, and the first node Q and the fifth node D are synchronously reset.

[0055] The technical scheme provided in the present application mainly synchronously resets the two end nodes of the storage capacitor C2, ensures that the voltage state of the display panel is consistent before refreshing, eliminates the voltage lag phenomenon caused by different reset times, more effectively removes the residual charge on the storage capacitor C2, and makes the display panel return to a consistent initial state before each refreshing, thereby reducing the ghosting phenomenon. In detail, in the related art, because the two end nodes of the storage capacitor C2 are not synchronously reset, the two end nodes of the storage capacitor C2 recover to the initial level at different times, and there is voltage residue in the storage capacitor C2, which causes the voltage lag phenomenon when the picture is updated, and the phenomenon is reflected in the picture display, that is, the picture has the ghosting phenomenon. In the present application, in the first reset stage, the second scan line SCAN2 provides a conduction signal to the first transistor T1, so that the first transistor T1 is turned on, and the fifth node D connected to the storage capacitor C2 is reset through the first transistor T1. At the same time, the third scan line SCAN3 provides a conduction signal to the fifth transistor T5, so that the fifth transistor T5 is turned on, and the first node Q connected to the storage capacitor C2 is reset through the fifth transistor T5, the two end nodes of the storage capacitor C2 are synchronously reset, there is no reset time difference, the initial state of the storage capacitor C2 is completely consistent in each frame, and the storage capacitor C2 is in a clean initial state before each data writing, so that the dynamic picture displayed by the display panel is clearer and smoother, and the problem of ghosting in the display picture of the display panel is effectively improved.

[0056] It should be noted that the second scan line SCAN2 and the third scan line SCAN3 are connected to the same driving circuit, which is beneficial to reduce the number of driving circuits, simplify the circuit complexity, and facilitate the realization of a narrow frame of the display panel. In addition, the second scan line SCAN2 and the third scan line SCAN3 are different levels of scan lines, so that the second scan line and the third scan line have a certain phase difference in timing. Specifically, the phase of the third scan line is ahead of the phase of the second scan line, and the phase difference between the third scan line and the second scan line is less than one period of time. For the simultaneous conduction of the first transistor T1 and the fifth transistor T5 of the second scan line SCAN2 and the third scan line SCAN3 using the same driving circuit, it will be described in detail in subsequent embodiments. For the driving circuit, generally refers to the GOA (Gate On Array) circuit, which is mainly used to drive the pixel to emit light.

[0057] It should also be noted that the light emitting device LED can emit light having a brightness corresponding to a driving current provided from the display panel. The first power supply voltage can be applied to the fifth power supply line VDD, and the second power supply voltage can be applied to the sixth power supply line VSS. The first power supply voltage and the second power supply voltage can have a potential difference capable of causing the light emitting device LED to emit light. For example, the first power supply voltage can be a high-potential pixel power supply, and the second power supply voltage can be a low-potential pixel power supply having a potential lower than the threshold voltage of the light emitting device LED or more voltage than the first power supply voltage.

[0058] The light emitting device LED can be made of several types of light emitting materials. For example, the light emitting device LED can be an inorganic light emitting diode or can include an inorganic light emitting material. Alternatively, for example, the light emitting device LED can be an organic light emitting diode including an organic light emitting layer. In another example, the light emitting device LED can include an inorganic material based on GaN or AlGaInP, and be configured as an inorganic light emitting diode such as a micro LED (light emitting diode) or a quantum dot light emitting diode. In still another example, the light emitting device LED can be configured as a light emitting diode made of a combination of organic and inorganic materials. In the present embodiment, only a pixel including a single light emitting device LED is illustrated. However, in other embodiments, a pixel can include a plurality of light emitting devices LED, and the plurality of light emitting devices LED can be connected in series, connected in parallel, or connected in a combination of series and parallel.

[0059] The display panel can include at least one transistor and at least one capacitor. For example, the display panel can include transistors T1 to T9 and a storage capacitor C2, but is not limited to 9 transistors, as long as the two end nodes of the storage capacitor C2 can be simultaneously reset in the first reset stage. For example, the display panel can also include 5 transistors, 6 transistors, 7 transistors, 8 transistors, etc., which will not be exemplified too much here.

[0060] Each of the transistors T1 to T9 can be a P-type thin film transistor and include polysilicon semiconductor. However, the present disclosure is not limited thereto. For example, at least some of the transistors T1 to T9 can include an oxide semiconductor, or can be implemented with an N-type semiconductor or a P-type semiconductor. In the present application, for the sake of clear description of the technical solutions, the transistors T1 to T9 are all P-type thin film transistors, i.e., the transistors T1 to T9 all have the characteristics of low-level conduction and high-level cutoff.

[0061] The third transistor T3 can include one of a source electrode and a drain electrode connected to the second node A, the other of the source electrode and the drain electrode connected to the third node B, and a gate electrode connected to the first node Q. One of the source electrode and the drain electrode of the third transistor T3 can be one of the source electrode and the drain electrode, and the other of the source electrode and the drain electrode of the third transistor T3 can be the other of the source electrode and the drain electrode. For example, one of the source electrode and the drain electrode of the third transistor T3 can be the source electrode, and the other of the source electrode and the drain electrode of the third transistor T3 can be the drain electrode. The third transistor T3 can control the amount of drive current flowing through the light emitting device LED. The first node Q, the second node A, and the third node B can mean one of the gate electrode, the source electrode, and the drain electrode of the third transistor T3 and the other of the source electrode and the drain electrode, respectively.

[0062] The seventh transistor T7 can include one of a source electrode and a drain electrode connected to the fifth power supply line VDD, the other of the source electrode and the drain electrode connected to the second node A, and a gate electrode connected to the second gate line EM2, which is a first emission control line. The first emission control signal can be supplied to the second gate line EM2. The seventh transistor T7 can be turned on in response to the first emission control signal having a gate-on voltage level, and connect the fifth power supply line VDD and the second node A to each other or form a current flow path between the fifth power supply line VDD and the second node A.

[0063] The sixth transistor T6 can include one of a source electrode and a drain electrode connected to the third node B, the other of the source electrode and the drain electrode connected to the fourth node C, which is an anode electrode of the light emitting device LED, and a gate electrode connected to a first gate line EM1, which is a second emission control line. A second emission control signal can be provided to the first gate line EM1. The sixth transistor T6 can be turned on in response to the second emission control signal having a gate-on voltage level, and form a current flow path between the third node B and the light emitting device LED. That is, when the sixth transistor T6 is turned on (and when the seventh transistor T7 is turned on), a driving current can be provided to the light emitting device LED, and the light emitting device LED can emit light having a brightness corresponding to the driving current. When the sixth transistor T6 is turned off, the current flow path of the driving current can be blocked, and the light emitting device LED can not emit light.

[0064] The storage capacitor C2 can be connected or formed between the first node Q and the fifth node D. The storage capacitor C2 can store a voltage provided to the first node Q and the fifth node D.

[0065] The first transistor T1 can include one of a source electrode and a drain electrode connected to the fourth power line VI4, the other of the source electrode and the drain electrode connected to the fifth node D, and a gate electrode connected to a second scan line SCAN2. A first reset voltage can be applied to the fourth power line VI4. The first transistor T1 can be turned on in response to a compensation gate signal having a gate-on voltage level, and provide the first reset voltage to the fifth node D. The first reset voltage can be equal to or different from the first power voltage. For example, the first reset voltage can be a DC voltage having a specific voltage level. That is, the first transistor T1 can allow the fifth node D to be reset to the first reset voltage.

[0066] The second transistor T2 can include one of a source electrode and a drain electrode connected to a data line data, the other of the source electrode and the drain electrode connected to the fifth node D, and a gate electrode connected to a first scan line SCAN1. A data signal can be provided to the data line data, and a write scan signal can be provided to the first scan line SCAN1. The second transistor T2 can be turned on in response to the write scan signal having a gate-on voltage level (or a gate-on voltage, an on voltage level, or a logic low level), and provide the data signal (or a data voltage) to the fifth node D. The gate-on voltage level can allow a corresponding transistor to be turned on, or allow the corresponding transistor to operate as a turned-on switch.

[0067] The fifth transistor T5 can include one of a source electrode and a drain electrode connected to the first power line VI1, the other of the source electrode and the drain electrode connected to the first node Q, and a gate electrode connected to the third scan line SCAN3. The second reset voltage can be applied to the first power line VI1, and a reset gate signal can be applied to the third scan line SCAN3. The fifth transistor T5 can be turned on in response to the reset gate signal having a gate-on voltage level, and provide the second reset voltage to the first node Q. The second reset voltage can be set to be lower than a voltage of the data signal. For example, the second reset voltage can be set to be lower than a minimum voltage of the data signal. That is, the fifth transistor T5 can allow the first node Q to be initialized to the second reset voltage.

[0068] By utilizing the first transistor T1 and the fifth transistor T5, the first node Q and the fifth node D of the storage capacitor are simultaneously reset, i.e., simultaneously initialized, in the first reset stage, effectively clearing the voltage left in the storage capacitor from the previous frame of image, avoiding the influence of the storage capacitor on the display of the current frame of image, and effectively eliminating the trailing of the displayed image.

[0069] In some embodiments, the waveform of the scan signal of the second scan line SCAN2 is the same as that of the scan signal of the third scan line SCAN3, the phase of the scan signal of the second scan line SCAN2 is behind that of the scan signal of the third scan line SCAN3, and the phases of the scan signal of the second scan line SCAN2 and the scan signal of the third scan line SCAN3 partially overlap, in which the scan signal of the second scan line SCAN2 and the scan signal of the third scan line SCAN3 are at least partially at the same level. Since the second scan line SCAN2 and the third scan line SCAN3 are connected to the same driving circuit, the waveforms of the second scan line SCAN2 and the third scan line SCAN3 are the same. To avoid the situation that the scan signal of the second scan line SCAN2 and the scan signal of the third scan line SCAN3 are synchronously changed in level throughout the period, causing the first transistor T1, the fifth transistor T5, and the fourth transistor T4 to be synchronously turned on and turned off all the time, the embodiment sets the phases of the scan signal of the second scan line SCAN2 and the scan signal of the third scan line SCAN3 to be different, with a certain phase difference, and the scan signal of the second scan line SCAN2 and the scan signal of the third scan line SCAN3 partially overlap in phase, so that the first transistor T1 and the fifth transistor T5 can be synchronously turned on for a certain period of time, and then the first node Q and the fifth node D are simultaneously reset, without affecting the implementation of subsequent stages, such as the compensation stage.

[0070] Further, the first reset stage includes a first reset sub-stage and a second reset sub-stage. In the first reset sub-stage, the fifth transistor T5 is turned on, and the first node Q is reset, and the potential of the first node Q is equal to the potential of the first power supply line VI1. In the second reset sub-stage, the fifth transistor T5 and the first transistor T1 are both turned on, and the seventh transistor T7 is turned off, and the first node Q and the fifth node D are synchronously reset, the potential of the first node Q is equal to the potential of the first power supply line VI1, and the potential of the fifth node D is equal to the potential of the fourth power supply line VI4. The seventh transistor T7 is turned off, and thus, the circuit short circuit can be effectively avoided.

[0071] See Figure 1 and Figure 2, the specific timing control process is as follows: in the first reset sub-stage, the second reset voltage is applied to one of the source electrode and the drain electrode of the fifth transistor T5 through the first power line VI1, and a reset gate signal is output to the gate electrode of the fifth transistor T5 through the third scan line SCAN3, so that the fifth transistor T5 is turned on, thereby providing the second reset voltage to the first node Q and realizing the reset of the first node Q. In the second reset sub-stage, the first reset voltage is applied to one of the source electrode and the drain electrode of the first transistor T1 through the fourth power line VI4, and a compensation gate signal is output to the gate electrode of the first transistor T1 through the second scan line SCAN2, so that the first transistor T1 is turned on, thereby providing the first reset voltage to the fifth node D and realizing the reset of the fifth node D; the second reset voltage is also applied to one of the source electrode and the drain electrode of the fifth transistor T5 through the first power line VI1, and a reset gate signal is output to the gate electrode of the fifth transistor T5 through the third scan line SCAN3, so that the fifth transistor T5 is turned on, thereby providing the second reset voltage to the first node Q and realizing the reset of the first node Q. The reset of the first node Q and the second node A is completed synchronously in the first reset stage, that is, the first transistor T1 and the fifth transistor T5 are turned on synchronously, the synchronous reset of the first node Q and the fifth node D is completed, and then the voltage residual of the previous frame picture in the storage capacitor C2 is effectively avoided, thereby realizing the picture without trailing. It should be noted that during the process in the first reset stage, the second transistor T2, the third transistor T3, the sixth transistor T6 and the seventh transistor T7 are all cut off, so as to avoid the influence of the reset of the first node Q and the fifth node D caused by the turn-on of other circuits. The reason why there are two sub-reset stages in the first reset stage is mainly that the waveforms of the second power line VI2 and the third power line VI3 are the same and the phases are different, so that the third power line VI3 in the phase in advance will output a conduction signal to the fifth transistor T5, thereby completing the reset of the first node Q once. In order to realize the synchronous reset of the first node Q and the fifth node D, the waveforms of the second scan line SCAN2 and the third scan line SCAN3 are partially overlapped, that is, the phase difference is less than one waveform period. In the overlapped part of the waveforms of the second scan line SCAN2 and the third scan line SCAN3, the second scan line SCAN2 outputs a conduction signal to the first transistor T1, and the third scan line SCAN3 outputs a conduction signal to the fifth transistor T5, so that in the second reset sub-stage, the synchronous reset of the first node Q and the fifth node D can be effectively realized, and the use of a driving circuit such as a GOA circuit can be reduced, the circuit is simplified, and it is conducive to the realization of a narrow frame structure of the display panel.

[0072] In some embodiments, the display panel further comprises a fourth transistor T4 comprising a gate electrode electrically connected to the second scan line SCAN2, one of a source electrode and a drain electrode electrically connected to the first node Q, and the other of the source electrode and the drain electrode electrically connected to the third node B. A compensation gate signal can be provided to the second scan line SCAN2. The fourth transistor T4 can be turned on in response to the compensation gate signal having a gate turn-on voltage level, and connect the first node Q and the third node B to each other. The addition of the fourth transistor T4 enables the first node Q and the third node B to be connected to each other under certain conditions, thereby forming a diode structure for voltage sampling. This structure helps to more accurately control the turn-on voltage of the third transistor T3, improves the driving accuracy of the display panel, and further improves the stability and consistency of the display effect. Specifically, the display panel comprises a compensation stage, in which the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are all turned on, and the fifth transistor T5 is turned off, for charging the first node Q and voltage sampling.

[0073] In addition, in each frame of the display panel, a data writing stage is further included, in which the second transistor T2 is turned on, and the first transistor T1 and the seventh transistor T7 are both turned off, so that the signal of the data line can be written into the storage capacitor C2 through the second transistor T2.

[0074] In some embodiments, the display panel further comprises an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 comprises a gate electrode electrically connected to a third gate line SN, one of a source electrode and a drain electrode electrically connected to a second power supply line VI2, and the other of the source electrode and the drain electrode electrically connected to a fourth node C. In each frame of the display panel, a second reset stage is included, in which the eighth transistor T8 is turned on for resetting the anode of the light emitting device LED, the ninth transistor T9 is turned on for charging the second node A, and the seventh transistor T7 is turned off. The fourth node C is the anode electrode of the light emitting device LED. The second power supply line VI2 can be applied with a third reset voltage, and a bias control signal EB can be provided to the third gate line SN, which is a bias control line. The eighth transistor T8 can be turned on in response to the bias control signal having a gate turn-on voltage level, and provide the third reset voltage to the anode electrode of the light emitting device LED. The charge in the parasitic capacitor formed in the light emitting device LED (i.e., a parasitic capacitor generated due to the structure of the light emitting device LED) can be initialized by the third reset voltage. When the third reset voltage is transmitted to the anode electrode of the light emitting device LED before the emission period of the light emitting device LED, the influence caused by the parasitic capacitor can be eliminated or reduced, so that the pixel can exhibit more uniform brightness characteristics with respect to the data signal.

[0075] The ninth transistor T9 includes a gate electrode electrically connected to the third gate line SN, one of a source electrode and a drain electrode electrically connected to the third power supply line VI3, and the other of the source electrode and the drain electrode electrically connected to the second node A. A bias voltage can be applied to the third power supply line VI3. A bias control signal can be provided to the third gate line SN. The ninth transistor T9 can be turned on in response to the bias control signal having a gate-on voltage level, and connect the second node A and the third power supply line VI3 to each other. When the bias voltage is periodically applied to one of the source electrode and the drain electrode (or the source electrode) of the third transistor T3, the third transistor T3 can continuously maintain a specific on-bias state, and substantially constantly control the amount of drive current flowing through the light emitting device LED. The constant current avoids brightness fluctuations and flickering phenomena, making the display picture more stable and clear.

[0076] The configuration of the eighth transistor T8 and the ninth transistor T9 effectively initializes the parasitic capacitance charge in the light emitting device LED, so that the light emitting device LED is in a stable initial state before the light emitting period. Through this initialization process, the influence of the parasitic capacitance on the light emitting brightness is reduced, ensuring the uniformity of the pixel brightness, further improving the quality and consistency of the display picture.

[0077] In some embodiments, the display panel further includes a voltage stabilizing capacitor C1 electrically connected between the fifth power supply line VDD and the fifth node D, mainly used for storing the voltage of the fifth node D and keeping the voltage of the fifth node D stable. The setting of the voltage stabilizing capacitor C1 helps to stabilize the voltage of the fifth node D, avoiding the influence of voltage fluctuations on the display panel, and in turn making the voltage of the storage capacitor C2 more stable during data writing and driving, improving the stability and reliability of the display picture, reducing image distortion and flickering phenomena.

[0078] Please refer to Figure 4 The embodiments of the present application also provide a driving method of a display panel, the display panel including a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a light emitting device, and a storage capacitor. In each frame of display picture, the display panel 100 includes a first driving mode, the first driving mode including a first reset stage, a data writing stage, and a light emitting stage.

[0079] Specifically, in the first driving mode, the driving method includes:

[0080] S1, in the first reset stage, the second scan line provides a turn-on signal to the first transistor, the third scan line provides a turn-on signal to the fifth transistor, the first node to which the storage capacitor is electrically connected is reset through the fifth transistor, the fifth node to which the storage capacitor is connected is reset through the first transistor, and the second scan line and the third scan line are connected to the same driving circuit.

[0081] In the first reset stage, the second scan line SCAN2 and the third scan line SCAN3 provide conductive signals to the first transistor T1 and the fifth transistor T5 respectively, so that the two nodes of the storage capacitor C2 are reset through the fifth transistor T5 and the first transistor T1 respectively. The reset operation can clear the previous residual charge, ensure that the capacitor is in the initial state, and prepare for the subsequent data writing and light emitting stage. Through the first reset stage, it is ensured that the storage capacitor C2 is in the initial state at the beginning of each frame, avoiding the influence of residual charge of the previous frame on the display effect of the current frame, and improving the stability and consistency of the display. It should be noted that the connection of the second scan line SCAN2 and the third scan line SCAN3 to the same driving circuit is beneficial to reduce the number of driving circuits, simplify the circuit complexity, and facilitate the realization of narrow frame of the display panel. For the driving circuit, generally refers to the GOA (Gate On Array) circuit, mainly used for driving the pixel to emit light.

[0082] Further, the first reset stage includes a first reset sub-stage and a second reset sub-stage. In the first reset stage, the second scan line SCAN2 provides a conductive signal to the first transistor T1, and the third scan line SCAN3 provides a conductive signal to the fifth transistor T5. The first node Q connected to the storage capacitor C2 is reset through the fifth transistor T5, and the fifth node D connected to the storage capacitor C2 is reset through the first transistor T1. The steps include:

[0083] S11, in the first reset sub-stage, the third scan line provides a conductive signal to the fifth transistor.

[0084] Specifically, in the first reset sub-stage, since the phase of the third scan line SCAN3 is earlier than that of the second scan line, the third scan line SCAN3 will first provide a conductive signal to the first transistor T1, and the first power supply line VI1 outputs a reset voltage to the first node Q, so that the first node Q is reset in the first reset sub-stage. As for the second scan line SCAN2, its output conductive signal phase is later, that is, the fifth node D will not be reset at this time.

[0085] S12, in the second reset sub-stage, the third scan line provides a conductive signal to the fifth transistor, and the first node connected to the storage capacitor is reset through the fifth transistor. The second scan line provides a conductive signal to the first transistor, and the fifth node connected to the storage capacitor is reset through the first transistor. The second gate line provides a cutoff signal to the seventh transistor.

[0086] Specifically, in the second reset sub-stage, the partial waveforms of the second scan line SCAN2 and the third scan line SCAN3 coincide, at the coinciding waveforms, the second scan line SCAN2 outputs a conduction signal to the first transistor T1, and the third scan line SCAN3 outputs a conduction signal to the fifth transistor T5, so that the first transistor T1 and the fifth transistor T5 are still synchronously turned on while the second scan line SCAN2 and the third scan line SCAN3 are connected to the same driving circuit, thereby achieving the effect of synchronously resetting the first node Q and the fifth node D. It should be noted that, in order to achieve the effect of synchronously resetting the first node Q and the fifth node D, the second gate line EM2 needs to output a cutoff signal to the seventh transistor T7 to make the seventh transistor T7 cut off, otherwise the display panel will be short-circuited, affecting the resetting of the first node Q and the fifth node D.

[0087] S2, in the data writing stage, the first scan line provides a conduction signal to the second transistor, and the data line writes a data signal into the storage capacitor through the second transistor.

[0088] In the data writing stage, the first scan line SCAN1 provides a conduction signal to the second transistor T2, so that the data signal on the data line data can be written into the storage capacitor C2 through the second transistor T2. The storage capacitor C2 records the data level required for display of the current frame in this stage. The data writing stage can accurately write the data signal into the storage capacitor C2 through the cooperation of the scan line and the data line data, so that the storage capacitor C2 can accurately record the display data of each frame.

[0089] S3, in the first light emitting stage, the first gate line provides a conduction signal to the sixth transistor, the second gate line provides a conduction signal to the seventh transistor, and the third transistor is controlled to be turned on to make the current of the fifth power line flow into the light emitting device through the seventh transistor, the third transistor and the sixth transistor.

[0090] In the first light emitting stage, the first gate line EM1 and the second gate line EM2 provide conduction signals to the sixth transistor T6 and the seventh transistor T7 respectively, and control the third transistor T3 to be turned on. At this time, the current on the fifth power line VDD flows into the light emitting device LED through the seventh transistor T7, the third transistor T3 and the sixth transistor T6, thereby driving the light emitting device LED to emit light. The intensity and duration of the light emission are determined by the data signal stored in the storage capacitor C2. The light emitting stage cooperates with multiple gate lines and transistors to make the current flow stably into the light emitting device LED, ensuring that the light emitting device LED emits light with the expected brightness and duration. The current control in this process is accurate, which can ensure the brightness uniformity and color accuracy of the display picture.

[0091] The driving method provided by the present application mainly resets the two end nodes of the storage capacitor C2 synchronously by turning on the first transistor T1 and the fifth transistor T5 at the same time in the first reset stage. This process eliminates the residual voltage in the storage capacitor C2, thereby avoiding the voltage lag phenomenon, making the initial voltage state of each frame of picture consistent, and effectively reducing the ghosting phenomenon of the display picture. Synchronous reset ensures that the storage capacitor C2 is in a clean initial state before each refresh, ensuring the clarity and smoothness of the display picture. Specifically, by controlling the display panel to apply a first reset voltage to the fourth power supply line VI4 in the first reset stage, and inputting a compensation gate signal to the gate electrode of the first transistor T1 through the second scan line SCAN2, the first transistor T1 is turned on, thereby providing the first reset voltage to the fifth node D, realizing the voltage reset of the fifth node D at one end of the storage capacitor. Similarly, in the first reset stage, a second reset voltage is output to the first power supply line VI1, and a reset gate signal is provided to the gate electrode of the fifth transistor T5 through the third scan line SCAN3, so that the fifth transistor T5 can be turned on in response to the reset gate signal having a gate turn-on voltage level, thereby providing the second reset voltage to the first node Q, realizing the voltage reset of the first node Q at the other end of the storage capacitor. It should be noted that the turn-on of the first transistor T1 and the fifth transistor T5 is synchronous to ensure that the first node Q and the fifth node D can be reset synchronously. In addition, the operation of the first reset stage and the data writing stage can effectively reduce unnecessary current consumption, making the entire driving process more energy-efficient and prolonging the service life of the light-emitting device LED and the driving circuit.

[0092] See Figure 1 and Figure 2 In some embodiments, the display panel further comprises a fourth transistor T4, the fourth transistor T4 comprising a gate electrode electrically connected to the second scan line SCAN2, one of a source electrode and a drain electrode electrically connected to the first node Q, and the other of the source electrode and the drain electrode electrically connected to the third node B; the first driving mode further comprises a compensation stage between the first reset stage and the data writing stage, and the driving method further comprises:

[0093] In the compensation stage, the second scan line SCAN2 provides a conduction signal to both the first transistor T1 and the fourth transistor T4, the second gate line EM2 provides a conduction signal to the seventh transistor T7, and the first node Q provides a conduction signal to the third transistor T3 to control the third transistor T3 to turn on.

[0094] The compensation stage is between the first reset stage and the data writing stage. In this stage, by controlling the turn-on of the plurality of transistors, voltage or current compensation of the circuit can be realized.

[0095] The on signal of the second scan line SCAN2 turns on the first transistor T1 and the fourth transistor T4, the on signal of the second gate line EM2 turns on the seventh transistor T7, and the third transistor T3 is controlled to be turned on, forming a specific current path. This current path can compensate for errors caused by device characteristic changes (such as threshold voltage drift), ensuring that the voltage or current in the storage capacitor C2 reaches the expected value, making the voltage or current in the storage capacitor C2 more accurate, thereby improving the accuracy and consistency of the display picture. By adding a compensation stage between the reset and data writing, the display non-uniformity caused by transistor aging or process differences in the display panel can be reduced, and the display uniformity can be improved. The introduction of the compensation stage enables the display panel to better adapt to device characteristic changes during long-term operation, enhancing the stability and reliability of the system and prolonging the service life of the display device. Through accurate compensation, the driving current can be more stable, and the light emitting device LED can perform with the expected brightness and color, significantly improving the image quality.

[0096] In some embodiments, the display panel further comprises an eighth transistor T8 and a ninth transistor T9, the eighth transistor T8 comprises a gate electrode electrically connected to the third gate line SN, one of a source electrode and a drain electrode electrically connected to the second power supply line VI2, and the other of the source electrode and the drain electrode electrically connected to the fourth node C; the ninth transistor T9 comprises a gate electrode electrically connected to the third gate line SN, one of a source electrode and a drain electrode electrically connected to the third power supply line VI3, and the other of the source electrode and the drain electrode electrically connected to the second node A; the first driving mode further comprises a second reset stage, the second reset stage is located between the data writing stage and the first light emitting stage, and the driving method further comprises:

[0097] In the second reset stage, the third gate line SN provides an on signal to the eighth transistor T8, and the third gate line SN provides an on signal to the ninth transistor T9.

[0098] The eighth transistor T8 is turned on by providing a turn-on signal to the third gate line SN, forming a conduction path to transmit the voltage of the second power supply line VI2 to the fourth node C. The ninth transistor T9 is turned on by providing a turn-on signal to the third gate line SN, forming a conduction path to transmit the voltage of the third power supply line VI3 to the second node A. The second reset stage is located between the data writing stage and the first light emitting stage. In this stage, the eighth transistor T8 is turned on by providing a turn-on signal to the third gate line SN, and the ninth transistor T9 is turned on by providing a turn-on signal to the third gate line SN. The fourth node C and the second node A are reset to ensure that their voltage states reach the expected values before entering the first light emitting stage, to ensure the accuracy of current driving and brightness control in the light emitting stage. In detail, the introduction of the second reset stage allows the fourth node C and the second node A to be reset again before entering the light emitting stage. The turn-on of the eighth transistor T8 and the ninth transistor T9 can accurately transmit the voltages of the second power supply line VI2 and the third power supply line VI3 to the fourth node C and the second node A, respectively, improving the accuracy of voltage reset. Voltage reset through the second reset stage before the light emitting stage ensures that the driving current flowing through the light emitting device LED in the light emitting stage is more stable, reducing fluctuations in the driving current caused by voltage deviation, thereby improving the stability and consistency of the display effect. In addition, accurate second reset stage operation can effectively reduce noise and distortion caused by inaccurate voltage during display, ensuring the clarity and accuracy of image display.

[0099] In some embodiments, referring to Figure 1 and Figure 3 In each frame of the display screen, the display panel 100 further includes a second driving mode. In each frame of the display screen, the number of times of the first driving mode is one, and the number of times of the second driving mode is one or more than one, and the second driving mode is always located after the first driving mode. The display panel 100 is driven in the order of one first driving mode and one or more than one second driving mode, that is, at least one second driving mode is arranged after the first driving mode, for maintaining the light emitting brightness of the light emitting device LED.

[0100] The first driving mode is mainly used for initializing and setting initial brightness data of each frame, including reset and data writing operations. It is ensured that the voltage value stored in the storage capacitor C2 is accurate to control the brightness of the light emitting device LED in the current frame. The second driving mode is used to maintain the brightness of the light emitting device LED after the first driving mode. By continuously or re-driving the light emitting device LED, it is ensured that the brightness will not decay due to long-time light emission. The reset operation is simplified, and repeated data writing is avoided when maintaining the brightness, thereby reducing the power consumption of the chip. The first driving mode is used to set the initial brightness at the beginning of each frame and ensure the accuracy of the voltage state. The second driving mode is used after the first driving mode to improve the flicker of the picture when the frequency is switched and improve the display stability by periodically resetting the anode. The superimposed use of multiple second driving modes can maintain the brightness at a low refresh frequency and reduce frequent data writing operations. At a high refresh frequency: mainly rely on the first driving mode to set the brightness, and the demand for the second driving mode is less, but generally at least one second driving mode is set after the first driving mode. At a low refresh frequency: because the time of each frame is longer, the brightness of the light emitting device LED is easy to decay, and by increasing multiple second driving modes after the first driving mode, the brightness can be effectively maintained, and the influence of brightness decay on the display effect is reduced. According to the actual display requirements, the proportion of the first driving mode and the second driving mode can be dynamically adjusted to adapt to different refresh frequencies and display requirements.

[0101] By introducing the second driving mode, the brightness stability of the light emitting device LED can be ensured at a low refresh frequency through multiple brightness maintenance operations, and the overall display effect is improved. In a frame of display picture, by reducing frequent data writing operations, the load of the driving circuit is reduced, the driving efficiency is improved, and the power consumption of the chip is reduced. By multiple brightness maintenance of the second driving mode, the non-uniformity caused by brightness decay is avoided, and the uniformity and consistency of the display are improved. When switching between different refresh frequencies, the proportion of the first driving mode and the second driving mode is adjusted to dynamically maintain the brightness, and the stability and smoothness of the display effect are ensured.

[0102] Further, compared with the first driving mode, the control timing of the second driving mode is more simplified, and the second driving mode cancels the first reset stage, the compensation stage and the data writing stage in the first driving mode. Specifically, the second driving mode includes a third reset stage and a second light emitting stage, and the driving method of the display panel in the second driving mode includes:

[0103] In the third reset stage, the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off, the seventh transistor T7 is turned off for a partial time period and turned on for a partial time period, the eighth transistor T8 and the ninth transistor T9 are turned on for a partial time period and turned off for a partial time period, and the third transistor T3 is turned on.

[0104] In the second light emitting stage, the seventh transistor T7, the sixth transistor T6, and the third transistor T3 are turned on, and the remaining transistors are all turned off, so that the light emitting device LED can maintain light emission.

[0105] Further, the third reset stage includes at least a bias stage and an initialization stage. In the bias stage, the seventh transistor T7 is turned on, and in other stages of the third reset stage, the seventh transistor T7 is turned off. In the initialization stage, the eighth transistor T8 and the ninth transistor T9 are both turned on, and in other stages of the third reset stage, the eighth transistor T8 and the ninth transistor T9 are both turned off. When the pixel emits light in the second light emitting stage of the second driving mode, the threshold voltage of the third transistor T3 can be shifted, and the voltage-current characteristic of the third transistor T3 can be changed. Since the second light emitting stage of the second driving mode becomes longer according to low frequency driving, the voltage-current characteristic of the third transistor T3 can be changed, and the brightness of the pixel can change according to the lapse of time. To prevent this, a bias voltage can be applied to the third transistor T3 in the second driving mode (or in a frame) in which the data signal is not updated. The bias voltage is periodically applied to the third transistor T3, so that the change in the voltage-current characteristic of the third transistor T3 is reduced. In addition, the brightness of the pixel does not change even as time elapses.

[0106] In the above embodiment, the first driving mode and the second driving mode are used organically to improve the display effect and prolong the service life of the light emitting device. Specifically, the first driving mode includes a reset, compensation, data writing and light emitting stage. In this mode, the pixel circuit is initialized and the brightness data is set, ensuring that the voltage state is accurate at the beginning of each frame display, thereby controlling the brightness of the light emitting device. The second driving mode simplifies the control timing, cancels the reset, compensation and data writing stages in the first driving mode, and only includes the bias and reset sub-stage and the light emitting stage. Its main role is to prevent brightness decay after the first driving mode by periodically resetting the anode and maintaining the brightness of the light emitting device. The present embodiment can increase the proportion of light emitting time to total time in a display cycle by the cooperation of the first driving mode and the second driving mode. Accordingly, since the second driving mode resets frequently and maintains the brightness, the light emitting device does not need to reach a very high brightness in a short time in each cycle, and the lower instantaneous brightness requirement reduces the current stress of the light emitting device, reduces the aging speed of the organic material, thereby prolonging the service life of the display panel. In addition, increasing the proportion of light emitting time of the light emitting device to the total time can make the light emitting time of each pixel more uniform, reduce the brightness unevenness phenomenon, and thereby improve the problem of inconsistent display picture caused by brightness unevenness.

[0107] Based on the above driving method of the display panel, the following is exemplified:

[0108] Each frame of picture, the display panel includes the first driving mode and the second driving mode, here mainly taking one first driving mode and one second driving mode per frame as an example. Of course, in other embodiments, multiple second driving modes can also be set after the first driving mode, mainly depending on the refresh frequency, the higher the refresh frequency, the more the number of second driving modes. The first driving mode and the second driving mode each include 15 time periods, specifically t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15. It should be noted that the time periods of the first driving mode and the second driving mode are represented by t1-t15, but t1-t15 of the two driving modes represent different time periods.

[0109] In the first driving mode, the first reset stage is the t2 period and the t4 period, wherein the t2 period is mainly the first reset sub-stage for the first reset of the first node Q, and the t4 period is the second reset sub-stage, in which the waveforms of the third scan line SCAN3 and the second scan line SCAN2 coincide, and in this embodiment, the t4 period, the third scan line SCAN3 and the second scan line SCAN2 are all at low level, so that the P-type transistor can be in the on state. The compensation stage is the t8 period, the data writing stage is the t11 period, the second reset stage is the t13 period, and the first light emitting stage is the t15 period.

[0110] In the second driving mode, the bias stage is the t6-t9 period, which can exist periodically in the second driving mode, i.e., the seventh transistor T7 can be controlled to be repeatedly turned on and turned off. The initialization stage is the t13 period, and the second light emitting stage is the t15 period.

[0111] For comparison, for example:

[0112] Please refer to Figure 5 , Figure 5 is the control timing diagram of the comparative example. As can be seen from the figure, in the stage of resetting the capacitor, one end of the capacitor is first reset in the first time period, and the other end of the capacitor is reset in the second time period. Since the two ends of the capacitor are not reset at the same time, the information of the previous frame of picture in the two consecutive frames of picture still exists in the current frame of picture, thereby the phenomenon of display picture trailing exists. In order to reflect the difference between the present application and the comparative example, the following example is given:

[0113] In the comparative example, it is assumed that the GI (equivalent to the second scan line in the present application) and the GC (equivalent to the third scan line in the present application) can be generated by the same driving circuit, and the GC and the GI are different levels, wherein the different levels refer to that the GC and the GI are different rows or different columns. It is assumed that the GI is the (n-x) level of the GC, the phase difference between the GI and the GC waveforms is x×h, so b+c=x×h; it is assumed that a=c=d=e=f=g=j=k=1h, then the EM2 closing time is 1+4(x-1)+3+6=4x+10.

[0114] In the embodiment of the present application, please refer to Figure 6Assuming that the third scan line SCAN3 is the second scan line SCAN2 of the (nx) level, the waveforms of the third scan line SCAN3 and the second scan line SCAN2 are exactly the same (t2=t4, t3=t5+t6, t7=t4+t5), but the phases are different. The phase difference between the waveforms of the third scan line SCAN3 and the second scan line SCAN2 is x×h, that is, t2+t3=x×h; assuming t2=t4=t6=1h, then t2+t3+t4+t5+t6+t7=3x-1, and finally the closing time of the first gate line EM1 is 3x+6.

[0115] It can be seen that t7>0, 3x+6<4x+10. The first gate line EM1 in the present application has a shorter off time and a longer luminous time. Moreover, if the second mode is inserted multiple times in a frame, the advantages of the present application are even more obvious. The off time of the first gate line EM1 is shorter than that of EM2 in the comparative example, and the pixel luminous time is longer.

[0116] An embodiment of the present application further provides a display panel. The display panel includes k pixel rows, each pixel row includes a plurality of pixels; the pixels include:

[0117] The display panel as described in any of the above embodiments, and / or

[0118] The driving method of the display panel of the pixel is the driving method of the display panel as described in any of the above embodiments;

[0119] And, k is a positive integer greater than 1.

[0120] At the same time, this application uses specific terms to describe the embodiments of this application. For example, "one embodiment," "an embodiment," and / or "some embodiments" refer to a certain feature, structure, or characteristic related to at least one embodiment of this application. Therefore, it should be emphasized and noted that "one embodiment," "an embodiment," or "an alternative embodiment" mentioned twice or multiple times in different locations in this specification does not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of this application may be appropriately combined.

[0121] Similarly, it should be noted that, in order to simplify the description of the present disclosure and thus facilitate understanding of one or more embodiments of the present disclosure, the foregoing description of the embodiments of the present disclosure sometimes combines multiple features into a single embodiment, figure, or description thereof. However, this disclosure method does not mean that the present disclosure requires more features than those recited in the claims. In fact, the features of the embodiments may be fewer than the total features of the individual embodiments disclosed above.

Claims

1. A display panel, characterized by, comprises a gate electrode electrically connected to the first node, one of a source electrode and a drain electrode electrically connected to the second node, and the other of the source electrode and the drain electrode electrically connected to the third node; the seventh transistor comprises a gate electrode electrically connected to the second gate line, one of a source electrode and a drain electrode electrically connected to the fifth power supply line, and the other of the source electrode and the drain electrode electrically connected to the second node; the sixth transistor comprises a gate electrode electrically connected to the first gate line, one of a source electrode and a drain electrode electrically connected to the third node, and the other of the source electrode and the drain electrode electrically connected to the fourth node; the light emitting device is electrically connected between the fourth node and the sixth power supply line; the storage capacitor is electrically connected between the first node and the fifth node; the first transistor comprises a gate electrode electrically connected to the second scan line, one of a source electrode and a drain electrode electrically connected to the fourth power supply line, and the other of the source electrode and the drain electrode electrically connected to the fifth node; the second transistor comprises a gate electrode electrically connected to the first scan line, one of a source electrode and a drain electrode electrically connected to the data line, and the other of the source electrode and the drain electrode electrically connected to the fifth node; the fifth transistor comprises a gate electrode electrically connected to the third scan line, one of a source electrode and a drain electrode electrically connected to the first power supply line, and the other of the source electrode and the drain electrode electrically connected to the first node; wherein the second scan line and the third scan line are connected to the same driving circuit, in each frame of display picture, the display panel comprises a first reset stage, the fifth transistor is used for resetting the first node, the first transistor is used for resetting the fifth node, and the first node and the fifth node are synchronously reset; the first reset stage comprises a first reset sub-stage and a second reset sub-stage, in the first reset sub-stage, the fifth transistor is turned on, in the second reset sub-stage, the fifth transistor and the first transistor are both turned on, and the seventh transistor is turned off. the scan signal of the second scan line has the same waveform as the scan signal of the third scan line, the phase of the scan signal of the second scan line is behind the phase of the scan signal of the third scan line, the phase of the scan signal of the second scan line and the phase of the scan signal of the third scan line partially overlap, and in the overlapping phase, at least a part of the scan signal of the second scan line and at least a part of the scan signal of the third scan line are at the same level.

2. The display panel of claim 1, wherein, the display panel further comprises a fourth transistor, the fourth transistor comprises a gate electrode electrically connected to the second scan line, one of a source electrode and a drain electrode electrically connected to the first node, and the other of the source electrode and the drain electrode electrically connected to the third node; 3. The display panel of claim 1, wherein, in each frame of display picture, the display panel comprises a compensation stage, in the compensation stage, the third transistor, the fourth transistor and the seventh transistor are all turned on, and the fifth transistor is turned off, for charging the first node. ​ 4. The display panel of claim 1, wherein, In each frame of display picture, the display panel comprises a data writing stage, in which the second transistor is turned on, and the first transistor and the seventh transistor are both turned off.

5. The display panel of claim 1, wherein, The display panel further comprises an eighth transistor and a ninth transistor, the eighth transistor comprises a gate electrode electrically connected to a third gate line, one of a source electrode and a drain electrode electrically connected to a second power supply line, and the other of the source electrode and the drain electrode electrically connected to the fourth node; the ninth transistor comprises a gate electrode electrically connected to the third gate line, one of a source electrode and a drain electrode electrically connected to a third power supply line, and the other of the source electrode and the drain electrode electrically connected to the second node; In each frame of display picture, the display panel comprises a second reset stage, in which the eighth transistor is turned on to reset the anode of the light emitting device, and the ninth transistor is turned on to charge the second node, and the seventh transistor is turned off.

6. A driving method of a display panel, characterized by, The display panel comprises a first transistor, a second transistor, a third transistor, a fifth transistor, a sixth transistor, a seventh transistor, a light emitting device, and a storage capacitor, in each frame of display picture, the display panel comprises a first driving mode, the first driving mode comprises a first reset stage, a data writing stage, and a first light emitting stage; In the first driving mode, the driving method comprises: In the first reset stage, a second scan line provides a turn-on signal to the first transistor, a third scan line provides a turn-on signal to the fifth transistor, a first node electrically connected to the storage capacitor is reset through the fifth transistor, and a fifth node electrically connected to the storage capacitor is reset through the first transistor, and the second scan line and the third scan line are connected to the same driving circuit; In the data writing stage, a first scan line provides a turn-on signal to the second transistor, and a data line writes a data signal into the storage capacitor through the second transistor; In the first light emitting stage, a first gate line provides a turn-on signal to the sixth transistor, a second gate line provides a turn-on signal to the seventh transistor, and the third transistor is controlled to be turned on to make the current of a fifth power supply line flow into the light emitting device through the seventh transistor, the third transistor, and the sixth transistor; The first reset stage comprises a first reset sub-stage and a second reset sub-stage, and the step of, in the first reset stage, the second scan line providing a turn-on signal to the first transistor, the third scan line providing a turn-on signal to the fifth transistor, the first node electrically connected to the storage capacitor being reset through the fifth transistor, and the fifth node electrically connected to the storage capacitor being reset through the first transistor, comprises: In the first reset sub-stage, the third scan line provides a turn-on signal to the fifth transistor; In the second reset sub-stage, the third scan line provides a conductive signal to the fifth transistor, the first node electrically connected to the storage capacitor is reset through the fifth transistor, the second scan line provides a conductive signal to the first transistor, the fifth node electrically connected to the storage capacitor is reset through the first transistor, and the second gate line provides a cutoff signal to the seventh transistor.

7. The driving method according to claim 6, wherein The display panel further comprises a fourth transistor, the fourth transistor comprising a gate electrode electrically connected to the second scan line, one of a source electrode and a drain electrode electrically connected to the first node, and the other of the source electrode and the drain electrode electrically connected to a third node; The first driving mode further comprises a compensation stage, the compensation stage being located between the first reset stage and the data writing stage, and the driving method further comprises: In the compensation stage, the second scan line provides a conductive signal to both the first transistor and the fourth transistor, the second gate line provides a conductive signal to the seventh transistor, and the first node provides a conductive signal to the third transistor.

8. The driving method of claim 6, wherein, The display panel further comprises an eighth transistor and a ninth transistor, the eighth transistor comprising a gate electrode electrically connected to a third gate line, one of a source electrode and a drain electrode electrically connected to a second power supply line, and the other of the source electrode and the drain electrode electrically connected to a fourth node; the ninth transistor comprising a gate electrode electrically connected to the third gate line, one of a source electrode and a drain electrode electrically connected to a third power supply line, and the other of the source electrode and the drain electrode electrically connected to a second node; the first driving mode further comprises a second reset stage, the second reset stage being located between the data writing stage and the first light emitting stage, and the driving method further comprises: In the second reset stage, the third gate line provides a conductive signal to the eighth transistor, and the third gate line provides a conductive signal to the ninth transistor.

9. The driving method according to any one of claims 6 to 8, wherein In each frame of the display picture, the display panel further comprises a second driving mode, the second driving mode being arranged at least once after the first driving mode, for maintaining the light emitting brightness of the light emitting device.

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