Semiconductor structure and method of manufacturing the same

Abstract

Embodiments of the present application relate to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises: a substrate; a device region on the substrate; an edge region on the substrate and located at the periphery of the device region; a first material layer on the device region; and a support structure on the device region and located between the first material layer and the edge region and insulated therefrom. The support structure increases the number of intervals between the first material layer and the edge region. After a protective layer is formed between the first material layer and the edge region, the thickness difference between the protective layers at different positions between the first material layer and the edge region is reduced. When the protective layer is formed by coating, the support structure reduces the flow rate of the coating material with fluidity between the first material layer and the edge region, and a semiconductor structure with smaller surface roughness is obtained.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] In order to solve the cracking problem when cutting extremely thin wafers, the SDBG (Stealth Dicing Before Grinding) process is widely used in the field of chip cutting. The core material used in the SDBG process is DAF (dieattach film). The thickness difference of the material on the wafer surface is required to be less than 2um. Figure 1 The schematic cross-sectional view of a typical semiconductor structure after forming a protective layer shows that the thickness difference (H1-H2) between the initial protective layer 30 formed on the adjacent areas of the typical chip 10 and the scribe line 20 is greater than 2 μm, which does not meet the DAF material requirements for the surface roughness of the wafer 40. In addition, in order to better protect the semiconductor devices formed on the wafer 40, it is necessary to cover the semiconductor devices with an initial protective layer 30 having a thickness greater than 4 μm. Therefore, it is not possible to reduce the thickness difference between the initial protective layer 30 in the adjacent areas of the chip 10 and the scribe line 20 on the wafer 40 by reducing the thickness of the initial protective layer 30 on the semiconductor devices. How to obtain a wafer 30 with lower roughness without affecting the performance of the semiconductor devices has become an urgent problem to be solved. Summary of the Invention

[0003] The embodiments of the present application provide a semiconductor structure and a preparation method thereof, which can reduce the height difference between the chip formed on the wafer and the PI segment on the adjacent area of ​​the dicing road, reduce the roughness of the wafer surface, optimize the wafer surface, and meet the SDBG process requirements for the substrate surface roughness.

[0004] The present application provides a semiconductor structure, comprising:

[0005] substrate;

[0006] a device region located on the substrate;

[0007] An edge region, located on the substrate and outside the device region, surrounding the device region;

[0008] A first material layer located in the device region;

[0009] The support structure is located in the device area, between the first material layer and the edge area, and is insulated from the first material layer.

[0010] In one embodiment, the support structure is flush with the topmost surface of the first material layer.

[0011] In one embodiment, there are multiple supporting structures, and the supporting structures are arranged at intervals along the extension direction of the edge area.

[0012] In one embodiment, along the extension direction of the edge region, the support structures are evenly spaced and arranged between the first material layer and the edge region.

[0013] In one embodiment, the support structure is made of the same material as the first material layer.

[0014] In one embodiment, the material of the support structure includes at least one of aluminum, copper, titanium, nickel, tungsten, silver, gold and / or alloys thereof.

[0015] In one embodiment, in the direction perpendicular to the edge region, the distance between the support structure and the first material layer is a first preset value, and the distance between the support structure and the edge region is a second preset value;

[0016] The first preset value is equal to the second preset value.

[0017] In one embodiment, the first material layer includes a redistribution layer, the device region is provided with a pad, and the pad is electrically connected to the redistribution layer.

[0018] In one embodiment, the semiconductor structure further comprises:

[0019] The protective layer is located on the substrate and covers the first material layer and the supporting structure. The protective layer has an opening therein, and the opening exposes the upper surface of the first material layer.

[0020] In one embodiment, the difference in thickness of the protection layer between the support structure and the edge region is less than 2 μm.

[0021] The above-mentioned semiconductor structure includes an edge region located outside the device region and arranged around the device region, and a support structure located in the device region, wherein the support structure is located between the first material layer and the edge region and is insulated from the first material layer; by setting the support structure, the number of intervals between the first material layer and the edge region is increased, and after a protective layer is subsequently formed between the first material layer and the edge region, the thickness difference between the protective layers at different positions between the first material layer and the edge region becomes smaller, and when the protective layer is formed by coating, the support structure reduces the flow rate of the fluid coating material between the first material layer and the edge region, thereby obtaining a semiconductor structure with smaller surface roughness.

[0022] This application also protects a method for preparing a semiconductor structure, comprising:

[0023] providing a substrate;

[0024] forming device regions and scribe lines on a substrate, wherein the scribe lines are located between adjacent device regions;

[0025] forming a first material layer and a support structure on the device region respectively;

[0026] The support structure is located between the first material layer and the dicing street, and is insulated from the first material layer.

[0027] In one embodiment, forming the first material layer and the support structure on the device region respectively includes:

[0028] forming an initial first material layer on a substrate;

[0029] The initial first material layer is patterned to obtain the first material layer and the support structure.

[0030] In one embodiment, there are multiple support structures, and the support structures are arranged at intervals along the extending direction of the dicing street. Forming the first material layer and the support structures on the device area includes:

[0031] A support structure is formed on the device area. Along the extension direction of the dicing road, the support structure is evenly spaced and arranged between the first material layer and the cutting road.

[0032] In one embodiment, the preparation method further comprises:

[0033] A protection layer is formed on the substrate, the protection layer covers the first material layer and the support structure; the protection layer has an opening, and the opening exposes the upper surface of the first material layer.

[0034] In one embodiment, the first material layer includes a redistribution layer, the device region is provided with a pad, and the pad is electrically connected to the redistribution layer;

[0035] The difference in thickness of the protective layer between the support structure and the dicing street is less than 2 μm, and the width of the dicing street is less than or equal to 60 nanometers.

[0036] The preparation method of the above-mentioned semiconductor structure first forms a device area and a scribe line between adjacent device areas on a substrate, and then forms a first material layer and a support structure on the device area, wherein the support structure is located between the first material layer and the scribe line and is insulated from the first material layer; by forming the support structure located between the first material layer and the scribe line in the device area, the number of intervals between the first material layer and the edge area is increased, and after a protective layer is subsequently formed between the first material layer and the scribe line, the thickness difference between the protective layer at different positions between the first material layer and the scribe line becomes smaller, and when the protective layer is formed by coating, the support structure reduces the flow rate of the fluid coating material between the first material layer and the scribe line, thereby obtaining a semiconductor structure with smaller surface roughness, thereby meeting the SDBG process requirements for the surface roughness of the wafer where the semiconductor structure is located. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0038] Figure 1 Schematic cross-sectional view of a typical semiconductor structure after forming a protective layer;

[0039] Figure 2 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0040] Figure 3 is a schematic diagram of a process for forming a first material layer and a support structure on a device region, respectively, in one embodiment;

[0041] Figure 4 is a schematic cross-sectional view of a semiconductor structure after an initial first material layer is formed in one embodiment;

[0042] Figure 5 is a schematic cross-sectional view of a semiconductor structure after forming a first material layer and a support structure in one embodiment;

[0043] Figure 6 is a schematic diagram of the process of forming a first material layer and a support structure on the device region respectively in another embodiment;

[0044] Figure 7 is a schematic top view of a semiconductor structure after forming a first material layer and a support structure in one embodiment;

[0045] Figure 8 for Figure 7 A partial enlarged schematic diagram of the middle C area;

[0046] Figure 9 is a partial top view of a semiconductor structure after forming a first material layer and a support structure in another embodiment;

[0047] Figure 10 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming a protective layer in one embodiment.

[0048] Description of reference numerals:

[0049] 10. Chip; 20. Scribe street; 30. Initial protective layer; 40. Wafer; 102. Substrate; 104. Conductive layer; 106. Filling layer; 108. First material layer; 110. Support structure; 112. Protective layer; 202. Through hole; 204. Initial first material layer; 206. Opening. DETAILED DESCRIPTION

[0050] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present application. The terms used herein in the description of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" as used herein includes any and all combinations of one or more of the relevant listed items.

[0052] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0053] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0054] Figure 2 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in one embodiment. Figure 2 As shown, in this embodiment, the present application claims protection for a method for preparing a semiconductor structure, comprising:

[0055] S102, providing a substrate.

[0056] A substrate is provided. The substrate can be made of undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), germanium on insulator (GeOI), etc. As an example, in this embodiment, the substrate is made of single crystal silicon.

[0057] S104 , forming a device region and dicing streets on the substrate.

[0058] Specifically, a device area and a scribe line are formed on the substrate, and the scribe line is located between adjacent device areas. The device area here is an area on the substrate for forming a semiconductor structure (chip structure). A number of semiconductor structures are distributed on the substrate, and the semiconductor structures are separated and arranged on the substrate. A scribe line is formed between adjacent semiconductor structures, that is, the scribe line is located between adjacent device areas; by cutting the substrate with the scribe line, the semiconductor structure on the substrate can be separated into independent chip structures. It is clear that the semiconductor structure here includes at least one of a transistor, a diode, a resistor structure, a capacitor structure, an inductor structure or a storage structure (dynamic random access memory (DRAM) structure, static random access memory (SRAM) structure, magnetoresistive random access memory (MRAM) structure, etc.).

[0059] S106 , forming a first material layer and a support structure on the device region respectively.

[0060] Specifically, a first material layer and a support structure are formed on the device area respectively; wherein the support structure is located between the first material layer and the dicing lane, and is insulated from the first material layer. It is understood that the semiconductor structure formed in the device area includes a functional area and a peripheral area. The first material layer is a device layer with certain functions on the device area, such as a signal lead-out layer. In actual process flow, the first material layer can be located in the functional area or in the peripheral area. The support structure is located in the area between the first material layer and the dicing lane and has a supporting function. It is clear that when the support structure and the first material layer have different properties, the support structure can be isolated from the first material layer or in contact with the first material layer. When the support structure and the first material layer have the same properties, the support structure and the first material layer are isolated. For example, when the support structure and the first material layer are respectively a conductor and an insulator, the two have different properties. When the support structure and the first material layer are both a conductor or an insulator, the two have the same properties.

[0061] The preparation method of the above-mentioned semiconductor structure first forms a device area and a scribe line between adjacent device areas on a substrate, and then forms a first material layer and a support structure on the device area, wherein the support structure is located between the first material layer and the scribe line and is insulated from the first material layer; by forming the support structure located between the first material layer and the scribe line in the device area, the number of intervals between the first material layer and the edge area is increased, and after a protective layer is subsequently formed between the first material layer and the scribe line, the thickness difference between the protective layer at different positions between the first material layer and the scribe line becomes smaller, and when the protective layer is formed by coating, the support structure reduces the flow rate of the fluid coating material between the first material layer and the scribe line, thereby obtaining a semiconductor structure with smaller surface roughness, thereby meeting the SDBG process requirements for the surface roughness of the wafer where the semiconductor structure is located.

[0062] Figure 3 1 is a schematic diagram of a process for forming a first material layer and a support structure on a device region, Figure 4 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming an initial first material layer in one embodiment. Figure 3 、 Figure 4 As shown, in one embodiment, the support structure 110 and the first material layer 108 are made of the same material and are formed in the same patterning step, respectively forming the first material layer and the support structure on the device region, including:

[0063] S202, forming an initial first material layer on the substrate.

[0064] An initial first material layer 202 is formed on the substrate 102, wherein a device area A and a scribe line B are formed on the substrate. It is understood that the initial first material layer 202 may be located on the upper surface of the substrate 102 or may not be in contact with the upper surface of the substrate 102. In this case, other device structure layers with different functions are formed between the substrate 102 and the initial first material layer 202. This application exemplifies the presence of other device structure layers between the initial first material layer 202 and the substrate 102.

[0065] In one embodiment, a conductive layer 104 is formed on the substrate 102 and located in the device region A. The conductive layer 104 is used to lead the device structure formed on the substrate 102 to the surface of the substrate 102. Exemplarily, the material constituting the conductive layer 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. The metal may be tungsten (W), nickel (Ni), copper (Cu), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0066] In one embodiment, the conductive layer 104 includes one or more of a metal interconnect layer, a pad, or a contact structure located on the device region A.

[0067] In one embodiment, a filling layer 106 covering the device area A and the scribe line B is formed on the substrate 102. A through hole 202 is formed in the filling layer 106, and the through hole 202 exposes the upper surface of the conductive layer 104. An initial first material layer 204 is located in the through hole 202 and extends along the sidewalls of the through hole 202 to cover the upper surface of the filling layer 106. It is understood that the initial first material layer 204 may or may not fill the through hole 202. When the initial first material layer 204 fills the through hole 202, the upper surface of the initial first material layer 204 is higher than the upper surface of the filling layer 106. Exemplarily, the filling layer 106 is located on the upper surface of the conductive layer 104 and extends along the sidewalls of the conductive layer 104 to cover the scribe line B. The filling layer 106 also extends along the sidewalls of the conductive layer 104 to cover the inner wall of the gap between adjacent conductive layers 104. It can be understood that the filling layer 106 fills the gaps between adjacent conductive layers 104, and the top surface of the filling layer 106 is higher than the top surface of the conductive layer 104. The steps of forming the filling layer 106 include: first, forming a filling material layer on the substrate 102 using various suitable process technologies familiar to those skilled in the art; second, forming a first patterned mask layer on the filling material layer, wherein the first patterned mask layer defines the shape and position of the filling layer 106, and the constituent material of the first patterned mask layer includes one or more of silicon nitride, anti-reflective material, photoresist or amorphous carbon; third, etching and removing the filling material layer exposed by the first patterned mask layer to obtain a gap exposing a portion of the surface of the conductive layer 104 and the filling layer 106 composed of the remaining filling material layer. Exemplarily, the constituent material of the filling layer 106 includes at least one of a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride) or an oxide (e.g., silicon dioxide).

[0068] S204 , performing patterning on the initial first material layer to obtain the first material layer and the support structure.

[0069] Figure 5 FIG. 1 is a cross-sectional view of a semiconductor structure after forming a first material layer and a support structure in one embodiment. Specifically, Figure 5As shown, first, a second patterned mask layer is formed on the initial first material layer 204 using various suitable process techniques familiar to those skilled in the art. The second patterned mask layer defines the shape and position of the first material layer 108 and the support structure 110. The material constituting the second patterned mask layer includes one or more of silicon nitride, an anti-reflective material, a photoresist, or amorphous carbon. The initial first material layer 204 exposed by the second patterned mask layer is then etched away to obtain the first material layer 108 and the support structure 110 located on the device area A, which are comprised of the remaining initial first material layer 204. At this point, the first material layer 108 and the support structure 110 are isolated from each other. The second patterned mask layer is then removed. It will be appreciated that, while forming the first material layer 108 and the support structure 110, the initial first material layer 204 on the scribe line B is also etched away. It is clear that when a conductive layer 104 located in device area A and a filling layer 106 located on substrate 102 are formed on substrate 102, wherein filling layer 106 covers device area A and scribe line B, and a through hole 202 is formed in filling layer 106 to expose the upper surface of conductive layer 104, first material layer 108 fills through hole 202 and is electrically connected to conductive layer 104, and support structure 110 is located in the area between first material layer 108 and scribe line A. It is understandable that in the X direction, there is a predetermined distance between support structure 110 and scribe line A. The predetermined distance is required to ensure that when semiconductor structures are cut and separated at scribe line B, there will be no edge or corner collapse caused by support structure 110. Here, the X direction is on the same horizontal plane as the upper surface of substrate 102. In this embodiment, support structure 110 is formed simultaneously with first material layer 108, without adding new process steps, thereby reducing production costs.

[0070] In one embodiment, the constituent material of the first material layer 108 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), copper (Cu) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0071] In another embodiment, the constituent material of the first material layer 108 includes an insulating material. Exemplarily, the insulating material includes one or more of oxide (eg, silicon dioxide), nitride (eg, silicon nitride), or oxynitride (eg, silicon oxynitride).

[0072] Continue to refer Figure 5In one embodiment, the support structure 110 is flush with the topmost surface of the first material layer 108. The topmost surface here refers to the top surface with the greatest distance from the substrate 102. In other embodiments, the topmost surface of the support structure 110 is lower than the topmost surface of the first material layer 108. This is sufficient as long as the height difference between the topmost surface of the support structure 110 and the topmost surface of the first material layer 108 satisfies the requirement that the support structure 110 reduces the flow rate of the fluid coating material between the first material 108 and the scribe line B when forming the protective layer by coating, resulting in a surface roughness that meets the substrate surface roughness requirements of the SDBG process.

[0073] Optionally, after the first material layer 108 is prepared, a support structure material layer is prepared, and the support structure material layer is patterned to obtain the support structure 110 . Figure 6 FIG. 1 is a schematic diagram of a process for forming a first material layer and a support structure on the device region, respectively, in another embodiment. Figure 5 、 Figure 6 As shown, in this embodiment, a first material layer and a support structure are formed on the device region, respectively, including:

[0074] S302, forming a first material layer on the substrate.

[0075] Specifically, first, a second material layer is formed on a substrate 102, wherein a device region A and a scribe line B are formed on the substrate. It is understandable that the second material layer can be located on the upper surface of the substrate 102 or can be out of contact with the upper surface of the substrate 102. In this case, other device structure layers with different functions are also formed between the substrate 102 and the second material layer. This application is exemplified by the presence of other device structure layers between the second material layer and the substrate 102. In this embodiment, a conductive layer 104 located in the device region A is formed on the substrate 102, and the conductive layer 104 is used to lead the device structure formed on the substrate 102 to the surface of the substrate 102; a filling layer 106 covering the device region A and the scribe line B is formed on the substrate 102, and a through hole 202 is opened in the filling layer 106, and the through hole 202 exposes the upper surface of the conductive layer 104 for exemplified description. The second material layer is located in the through hole 202 and extends along the sidewall of the through hole 202 to cover the upper surface of the filling layer 106. It is understood that the second material layer completely fills the through-hole 202, and the upper surface of the second material layer is higher than the upper surface of the filling layer 106. Next, a third patterned mask layer is formed on the second material layer using various suitable process techniques familiar to those skilled in the art. The third patterned mask layer defines the shape and position of the first material layer 108. The third patterned mask layer is composed of one or more materials selected from silicon nitride, an anti-reflective material, a photoresist, or amorphous carbon. Finally, the second material layer exposed by the third patterned mask layer is etched away, resulting in the first material layer 108 located on the device area A, which is composed of the remaining second material layer. Finally, the third patterned mask layer is removed.

[0076] S304 , forming a support structure between the first material layer and the dicing street on the substrate.

[0077] Specifically, first, a support material layer is formed on substrate 102, where the support material layer covers the upper surface of filler layer 106. Next, a fourth patterned mask layer is formed on the support material layer using various suitable process techniques familiar to those skilled in the art. The fourth patterned mask layer defines the shape and position of support structure 110, and the fourth patterned mask layer is formed of one or more materials selected from silicon nitride, antireflective material, photoresist, or amorphous carbon. Third, the support material layer exposed by the fourth patterned mask layer is etched away to obtain support structure 110 located on device area A between the first material layer and the scribe line. The fourth patterned mask layer is then removed. It will be understood that after forming first material layer 108 and support structure 110, scribe line B is not covered with the second material layer. To facilitate subsequent cutting along scribe line B to separate the semiconductor structures on substrate 102, the support material layer on scribe line B is etched away simultaneously with the formation of support structure 110. The order of step S302 and step S304 can be interchanged.

[0078] In one embodiment, the support structure 110 is made of the same material as the first material layer 108 .

[0079] In one embodiment, the support structure 110 is formed of one or more materials selected from the group consisting of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. The metal may be tungsten (W), nickel (Ni), copper (Cu), or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); the conductive metal oxide may include iridium oxide (IrO2); and the metal silicide may include titanium silicide (TiSi). Exemplarily, the support structure is formed of at least one material selected from the group consisting of aluminum, copper, titanium, nickel, tungsten, silver, gold, and / or alloys thereof.

[0080] In one embodiment, the support structure 110 is formed of a material different from the first material layer 108 .

[0081] In one embodiment, the constituent material of the support structure 110 includes an insulating material. Exemplarily, the insulating material includes one or more of an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), or a nitride oxide (e.g., silicon oxynitride). When the constituent material of the support structure 110 is an insulating material, it is beneficial to improve the electrical isolation effect between the chip structure formed in the device area A and the external area, thereby improving the reliability of the semiconductor structure. In addition, the wettability of the surface of the support structure 110 is greater than that of the first material layer 108. When a liquid material is further applied, such as polyimide, the higher wettability of the surface of the support structure 110 makes the liquid material on the edge area (the area of ​​the device area A close to the dicing lane B) more uniform.

[0082] Figure 7 FIG. 1 is a schematic top view of a semiconductor structure after forming a first material layer and a support structure in one embodiment. Figure 8 for Figure 7 The enlarged schematic diagram of the C area is shown in Figure 2. Figure 7 、 Figure 8 As shown in FIG. 1 , in one embodiment, there are multiple support structures 110 , and the support structures 110 are arranged at intervals along the extending direction of the dicing street B. Specifically, as Figure 7 、 Figure 8 As shown, there are multiple support structures located in the area C between the first material layer 108 and the cutting street B, and the support structures 110 are arranged at intervals along the extension direction X of the dicing street B. It can be understood that the X direction in the figure is only an exemplary illustration of the extension direction of the dicing street B. The dicing street B is arranged around the device area forming the semiconductor structure. Therefore, the extension direction of the dicing street B includes other directions intersecting with the X direction, such as the Y direction, which are not specifically described here.

[0083] like Figure 7 、 Figure 8 As shown, in one embodiment, forming the first material layer 108 and the support structure 110 on the device area A includes: forming the support structure 110 on the device area A, and arranging the support structures 110 uniformly and spaced apart between the first material layer 108 and the dicing street B along the extension direction of the dicing street B, exemplarily along the X direction. Specifically, among the support structures 110 arranged between the first material layer 108 and the dicing street B, the distance D between any two adjacent support structures 110 is the same.

[0084] In one embodiment, in a direction perpendicular to the scribe line B, exemplarily in the Y direction, the distance between the support structure 110 and the first material layer 108 is a first preset value L1, and the distance between the support structure 110 and the scribe line B is a second preset value L2; wherein the first preset value L1 is equal to the second preset value L2. Exemplarily, the distance between the first material layer 108 and the scribe line B (the sum of L1 and L2) is 20 μm to 40 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 37 μm, 40 μm, etc.

[0085] Figure 9 FIG. 1 is a partial top view of a semiconductor structure after forming a first material layer and a support structure in another embodiment. Figure 9 As shown, in this embodiment, the number of the support structure 110 is one, and along the extension direction of the dicing street B, the support structure 110 is arranged around the first material layer 108 .

[0086] like Figure 9As shown, in one embodiment, the first material layer 108 is made of a conductive material (such as metal tungsten), the support structure 110 is made of an insulating material (such as silicon dioxide), and the support structure 110 is in contact with the first material layer 108 .

[0087] Figure 10 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming a protective layer in one embodiment. Figure 10 As shown, in one embodiment, the preparation method further includes:

[0088] A protection layer 112 is formed on the substrate 102 , and the protection layer 112 covers the first material layer 108 and the support structure 110 . The protection layer 112 has an opening 206 therein, and the opening 206 exposes the upper surface of the first material layer 108 .

[0089] In one embodiment, the protective layer 112 is formed of a photosensitive polymer material layer made of a positive photosensitive polymer material. For example, the polymer material may include polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer material. In other embodiments, the protective layer 112 is formed of a spin-on coating liquid, such as spin-on glass.

[0090] In one embodiment, the first material layer 108 includes a redistribution layer, and the device region A is provided with a pad electrically connected to the redistribution layer.

[0091] In one embodiment, the thickness difference of the protection layer 112 between the support structure 108 and the scribe line B is less than 2 μm.

[0092] In one embodiment, the width of the scribe line B is less than or equal to 60 nanometers. It is understood that the width of the scribe line B is the distance between adjacent device regions A.

[0093] It should be understood that although Figure 2 、 Figure 3 、 Figure 6 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 2 、 Figure 3 、 Figure 6At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0094] like Figure 5 As shown, the present application provides a semiconductor structure comprising: a substrate 102, a device region A, an edge region B0, a first material layer 108, and a support structure 110. The substrate 102 can be made of undoped single crystal silicon, doped single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI). As an example, in this embodiment, the substrate 102 is made of single crystal silicon. The device region A is located on the substrate 102. The device region A is the region on the substrate 102 where the semiconductor structure (chip structure) is located. It is clear that the semiconductor structure here includes at least one of a transistor, a diode, a resistor structure, a capacitor structure, an inductor structure, or a memory structure (dynamic random access memory (DRAM) structure, static random access memory (SRAM) structure, magnetoresistive random access memory (MRAM) structure, etc.). Edge region B0 is located on substrate 102, peripheral to device region A, and surrounds device region A. Edge region B0 is the scribe line B remaining after several device regions A formed on substrate 102 are separated by scribe lines B. First material layer 108 is located in device region A. Support structure 110 is located in device region A, between first material layer 108 and edge region B0, and insulated from first material layer 108. It will be understood that the semiconductor structure formed in device region B includes a functional region and a peripheral region. First material layer 108 is a device layer in device region B with certain functions, such as a signal lead-out layer. In actual manufacturing processes, first material layer 108 can be located in either the functional region or the peripheral region. Support structure 110 is located between first material layer 108 and edge region B0, providing support. It is understood that when support structure 110 and first material layer 108 have different properties, support structure 110 can be isolated from or in contact with first material layer 108. When the support structure 110 and the first material layer 108 have the same properties, the support structure 110 and the first material layer 108 are isolated. For example, when the support structure 110 and the first material layer 108 are respectively a conductor and an insulator, the two have different properties; when the support structure 110 and the first material layer 108 are both a conductor or an insulator, the two have the same properties.

[0095] The above-mentioned semiconductor structure includes an edge region located outside the device region and arranged around the device region, and a support structure located in the device region, wherein the support structure is located between the first material layer and the edge region and is insulated from the first material layer; by setting the support structure, the number of intervals between the first material layer and the edge region is increased, and after a protective layer is subsequently formed between the first material layer and the edge region, the thickness difference between the protective layers at different positions between the first material layer and the edge region becomes smaller, and when the protective layer is formed by coating, the support structure reduces the flow rate of the fluid coating material between the first material layer and the edge region, thereby obtaining a semiconductor structure with smaller surface roughness.

[0096] Continue to refer Figure 5 In one embodiment, the semiconductor structure further includes: a conductive layer 104 located in the device region A, and the conductive layer 104 is used to lead the device structure formed on the substrate 102 to the surface of the substrate 102. Exemplarily, the constituent material of the conductive layer 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), copper (Cu), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0097] In one embodiment, the conductive layer 104 includes one or more of a metal interconnect layer, a pad, or a contact structure located on the device region A.

[0098] Continue to refer Figure 5 In one embodiment, the semiconductor structure further includes: a filling layer 106, located on the substrate 102 and covering the device area A and the edge area B0, wherein a through hole 202 is defined in the filling layer 106, and the through hole 202 exposes the upper surface of the conductive layer 104, and a first material layer 108 is located in the through hole 202 and extends along the sidewall of the through hole 202 to cover a portion of the upper surface of the filling layer 106. Exemplarily, the filling layer 106 fills the gap between adjacent conductive layers 104, and the top surface of the filling layer 106 is higher than the top surface of the conductive layer 104. The constituent material of the filling layer 106 includes at least one of a nitride (e.g., silicon nitride), an oxynitride (e.g., silicon oxynitride), or an oxide (e.g., silicon dioxide). It is understandable that in the X direction, there is a preset distance between the support structure 110 and the edge area B0. The preset distance is required to ensure that when the semiconductor structure is cut and separated in the dicing lane B, problems such as edge collapse and corner collapse will not occur due to the support structure 110. Here, the X direction is on the same horizontal plane as the upper surface of the substrate 102.

[0099] In one embodiment, the constituent material of the first material layer 108 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal can be tungsten (W), nickel (Ni), copper (Cu) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0100] In another embodiment, the constituent material of the first material layer 108 includes an insulating material. Exemplarily, the insulating material includes one or more of oxide (eg, silicon dioxide), nitride (eg, silicon nitride), or oxynitride (eg, silicon oxynitride).

[0101] Continue to refer Figure 5 In one embodiment, the top surface of the support structure 110 is flush with the top surface of the first material layer 108. The top surface here refers to the top surface with the greatest distance from the substrate 102. In other embodiments, the top surface of the support structure 110 is lower than the top surface of the first material layer 108. This is sufficient as long as the height difference between the top surface of the support structure 110 and the top surface of the first material layer 108 satisfies the requirement that the support structure 110 reduces the flow rate of the fluid coating material between the first material 108 and the scribe line B when forming the protective layer by coating, resulting in a surface roughness that meets the substrate surface roughness requirements of the SDBG process.

[0102] In one embodiment, the support structure 110 is made of the same material as the first material layer 108 .

[0103] In one embodiment, the support structure 110 is formed of one or more materials selected from the group consisting of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. The metal may be tungsten (W), nickel (Ni), copper (Cu), or titanium (Ti); the conductive metal nitride may include titanium nitride (TiN); the conductive metal oxide may include iridium oxide (IrO 2); and the metal silicide may include titanium silicide (TiSi). Exemplarily, the support structure 110 is formed of at least one of aluminum, copper, titanium, nickel, tungsten, silver, gold, and / or alloys thereof.

[0104] In one embodiment, the support structure 110 is formed of a material different from the first material layer 108 .

[0105] In one embodiment, the constituent material of the support structure 110 includes an insulating material. Exemplarily, the insulating material includes one or more of an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), or a nitride oxide (e.g., silicon oxynitride). When the constituent material of the support structure 110 is an insulating material, it is beneficial to improve the electrical isolation effect between the chip structure formed in the device area A and the external area, thereby improving the reliability of the semiconductor structure. In addition, the wettability of the surface of the support structure 110 is greater than that of the first material layer 108. When a liquid material is further applied, such as polyimide, the higher wettability of the surface of the support structure 110 makes the liquid material on the edge area (the area of ​​the device area A close to the dicing lane B) more uniform.

[0106] like Figure 7 、 Figure 8 As shown in FIG. 1 , in one embodiment, there are multiple support structures 110 , and the support structures 110 are arranged at intervals along the extension direction of the edge area B0 . Specifically, as shown in FIG. Figure 7 、 Figure 8 As shown, there are multiple support structures located in the area C between the first material layer 108 and the edge area B0, and the support structures 110 are arranged at intervals along the extension direction X of the edge area B0. It can be understood that the X direction in the figure is only an exemplary illustration of the extension direction of the edge area B0. The edge area B0 is arranged around the device area forming the semiconductor structure. Therefore, the extension direction of the edge area B0 includes other directions intersecting with the X direction, such as the Y direction, which are not specifically described here.

[0107] like Figure 7 、 Figure 8 As shown, in one embodiment, along the extension direction of the edge region B0, exemplarily along the X direction, the support structures 110 are evenly spaced between the first material layer 108 and the edge region B0. Specifically, among the support structures 110 spaced between the first material layer 108 and the edge region B0, the distance D between any two adjacent support structures 110 is the same.

[0108] See also Figure 8 In one embodiment, in the direction perpendicular to the edge region B0, exemplarily in the Y direction, the distance between the support structure 110 and the first material layer 108 is a first preset value L1, and the distance between the support structure 110 and the edge region B0 is a second preset value L2; wherein the first preset value L1 is equal to the second preset value L2. Exemplarily, the distance between the first material layer 108 and the edge region B0 (the sum of L1 and L2) is 20 μm to 40 μm, for example, 20 μm, 25 μm, 30 μm, 35 μm, 37 μm, 40 μm, etc.

[0109] like Figure 9As shown, in this embodiment, the number of the supporting structure 110 is one, and along the extension direction of the edge area B0 , the supporting structure 110 is disposed around the first material layer 108 .

[0110] like Figure 9 As shown, in one embodiment, the first material layer 108 is made of a conductive material (such as metal tungsten), the support structure 110 is made of an insulating material (such as silicon dioxide), and the support structure 110 is in contact with the first material layer 108 .

[0111] like Figure 10 As shown, in one embodiment, the semiconductor structure further includes: a protection layer 112 located on the substrate 102 and covering the first material layer 108 and the support structure 110 ; an opening 206 is defined in the protection layer 112 , and the opening 206 exposes the upper surface of the first material layer 108 .

[0112] In one embodiment, the protective layer 112 is formed of a photosensitive polymer material layer made of a positive photosensitive polymer material. For example, the polymer material may include polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or any other suitable polymer material. In other embodiments, the protective layer 112 is formed of a spin-on coating liquid, such as spin-on glass.

[0113] In one embodiment, the first material layer 108 includes a redistribution layer, and the device region A is provided with a pad electrically connected to the redistribution layer.

[0114] In one embodiment, the thickness difference of the protection layer 112 between the support structure 110 and the edge region B0 is less than 2 μm.

[0115] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. The descriptions thereof are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the patent of the embodiments of the present application shall be based on the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; a device region, located on the substrate; an edge region, located on the substrate and at the periphery of the device region, and arranged around the device region; A first material layer is located in the device area; a support structure located in the device region and between the first material layer and the edge region, wherein the support structure and a portion of the first material layer are coplanar in a direction parallel to the substrate surface, and the support structures are multiple and arranged at intervals along an extension direction of the edge region; When the supporting structure and the first material layer have different properties, the supporting structure is isolated from or in contact with the first material layer; when the supporting structure and the first material layer have the same properties, the supporting structure and the first material layer are isolated from each other.

2. The semiconductor structure according to claim 1, wherein: The support structure is flush with the topmost surface of the first material layer.

3. The semiconductor structure according to claim 1, wherein: The topmost surface of the support structure is lower than the topmost surface of the first material layer.

4. The semiconductor structure according to claim 1, wherein: Along the extension direction of the edge region, the support structures are evenly spaced and arranged between the first material layer and the edge region.

5. The semiconductor structure according to claim 1, wherein: The supporting structure is made of the same material as the first material layer. The semiconductor structure according to claim 1 , wherein: In a direction parallel to the substrate surface and perpendicular to the extending direction of the scribing street, the distance between the support structure and the first material layer is a first preset value, and the distance between the support structure and the edge area is a second preset value; The first preset value is equal to the second preset value.

7. The semiconductor structure according to claim 1, wherein: The first material layer includes a redistribution layer, the device area is provided with a pad, and the pad is electrically connected to the redistribution layer.

8. The semiconductor structure according to claim 1, wherein: Also includes: a protective layer, located on the substrate and covering the first material layer and the supporting structure; The protective layer has an opening therein, and the opening exposes the upper surface of the first material layer; Wherein, a thickness difference of the protective layer between the support structure and the edge region is less than 2 μm.

9. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming device regions and scribing lanes on the substrate, wherein the scribing lanes are located between adjacent device regions; forming a first material layer and a support structure on the device area respectively; The support structure is located between the first material layer and the scribe line, and is coplanar with a portion of the first material layer in a direction parallel to the substrate surface. There are multiple support structures, and the support structures are arranged at intervals along the extension direction of the scribe line. When the supporting structure and the first material layer have different properties, the supporting structure is isolated from or in contact with the first material layer; when the supporting structure and the first material layer have the same properties, the supporting structure and the first material layer are isolated from each other.

10. The preparation method according to claim 9, characterized in that The forming of a first material layer and a support structure on the device region respectively includes: forming a support structure on the device region, wherein the support structure is evenly spaced and arranged between the first material layer and the dicing street along an extension direction of the dicing street; The first material layer includes a redistribution layer, the device area is provided with a pad, and the pad is electrically connected to the redistribution layer; the width of the dicing street is less than or equal to 60 nanometers.

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