Semiconductor devices, integrated circuits and electronic equipment

Abstract

The present disclosure provides a semiconductor device, an integrated circuit and an electronic device, which relate to the field of semiconductor chip technology and are used to achieve effective modulation of an electric field and improve the withstand voltage and stability of a semiconductor device; the semiconductor device comprises: a substrate, a channel layer, a barrier layer, a P-type III-group nitride layer, a first electrode, a second electrode and a control electrode; wherein, along a second direction, in the P-type III-group nitride layer, a portion of the P-type III-group nitride layer closest to the second electrode has a minimum hole concentration; the second direction is parallel to the substrate; the semiconductor device is applied to a power device.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor device, an integrated circuit and an electronic device. Background Art

[0002] The third generation of semiconductor materials represented by gallium nitride (GaN) have good properties such as large bandgap, high critical breakdown electric field, high electron saturation rate, and strong radiation resistance. They are widely used in optoelectronics, radio frequency, and power electronics, and are the most preferred material system for preparing high-power radio frequency electronic devices and high-efficiency power electronic devices. At the same time, the AlGaN / GaN heterostructure formed based on its unique polarization effect can form a high-concentration, high-mobility two-dimensional electron gas (2DEG). Using this feature and the material advantages of GaN, high electron mobility transistors (HEMT) with lower on-resistance, higher withstand voltage, and greater power density can be prepared.

[0003] However, when the HEMT is under reverse bias, a large number of electric field lines from the drain will gather at the edge of the control electrode close to the drain, resulting in a peak electric field at the edge of the control electrode, which ultimately leads to premature breakdown of the HEMT and poor device stability. Summary of the invention

[0004] Embodiments of the present disclosure provide a semiconductor device, an integrated circuit, and an electronic device for realizing effective modulation of an electric field and improving the withstand voltage level and stability of the semiconductor device.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a semiconductor device is provided. The semiconductor device comprises: a substrate, a channel layer and a barrier layer stacked on one side of the substrate, a P-type III-nitride layer, a first electrode, a second electrode and a control electrode, wherein the P-type III-nitride layer is located on a side of the barrier layer away from the substrate; the control electrode is located on a side of the P-type III-nitride layer away from the substrate, the first electrode and the second electrode are located on a side of the channel layer away from the substrate, and the control electrode is located between the first electrode and the second electrode; wherein, along the second direction, in the P-type III-nitride layer, the hole concentration of the portion of the P-type III-nitride layer closest to the second electrode is the smallest; and the second direction is parallel to the substrate.

[0007] The semiconductor device provided by the above-mentioned embodiments of the present disclosure is configured such that the hole concentration of the portion of the P-type III-nitride layer closest to the second electrode is minimized. Thus, when the semiconductor device is in reverse bias (also referred to as reverse bias), as the second electrode bias increases, the peak electric field originally concentrated at the control electrode and the edge of the P-type III-nitride layer is modulated by the portion of the P-type III-nitride layer closest to the second electrode. By utilizing the effect of a small amount of 2DEG in the heterojunction below the P-type III-nitride layer where the hole concentration is relatively small, the peak electric field cannot be concentrated at the control electrode and the edge of the P-type III-nitride layer, thereby achieving effective modulation of the electric field and improving the voltage resistance level and stability of the semiconductor device.

[0008] In some embodiments, a virtual line extending along the first direction is constructed on the P-type III-nitride layer, and the P-type III-nitride layer includes: a first portion and a second portion located on both sides of the virtual line along the second direction, a size of the first portion in the second direction and a size of the second portion in the second direction are approximately equal, the first portion is closer to the second pole than the second portion, and the second direction is parallel to the substrate; wherein, along the second direction, in the first portion, a portion of the first portion closest to the virtual line has a maximum hole concentration.

[0009] In some embodiments, along the second direction, in the second portion, a portion of the second portion away from the virtual line has a minimum hole concentration.

[0010] In some embodiments, along the second direction, in the second portion, a portion close to the virtual line has a maximum hole concentration.

[0011] In some embodiments, the first portion and the second portion each include: a first sub-portion; along the second direction, a hole concentration of a portion of the first sub-portion relatively close to the virtual line is greater than a hole concentration of a portion of the first sub-portion relatively far from the virtual line.

[0012] In some embodiments, the first portion and / or the second portion further includes: a second sub-portion; the first sub-portion and the second sub-portion are arranged along the second direction; and along the second direction, the hole concentration of the second sub-portion is consistent.

[0013] In some embodiments, the first portion and / or the second portion further includes: a third sub-portion; the first sub-portion and the third sub-portion are arranged along the second direction; along the second direction, the hole concentration of a portion of the third sub-portion relatively close to the virtual line is less than the hole concentration of a portion of the third sub-portion relatively far from the virtual line.

[0014] In some embodiments, the hole concentration in the second portion is unchanged.

[0015] In some embodiments, the hole concentration of the P-type group III nitride layer is in the range of 10 13 cm 3 ~10 20 cm 3 .

[0016] In some embodiments, the doping elements in the P-type Group III nitride layer include at least one of magnesium, iron and zinc, and the P-type Group III nitride layer also includes a modulation element, which can reduce the hole concentration in the P-type Group III nitride layer.

[0017] In some embodiments, the modulation element includes at least one of hydrogen, oxygen, nitrogen, carbon, chlorine, silicon and fluorine.

[0018] On the other hand, an integrated circuit is provided. The integrated circuit includes the semiconductor device as described in any one of the above embodiments.

[0019] On the other hand, an electronic device is provided, the electronic device comprising the integrated circuit as described in any of the above embodiments; the electronic device further comprises: a circuit board, the integrated circuit is arranged on the circuit board.

[0020] It can be understood that the beneficial effects that can be achieved by the integrated circuit and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor device mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0022] Figure 1 is a schematic structural diagram of a HEMT according to some embodiments;

[0023] Figure 2 is a schematic structural diagram of a semiconductor device according to some embodiments of the present disclosure;

[0024] Figure 3 According to this disclosure Figure 2 The structure of the semiconductor device provided along the cross-sectional line AA is schematically shown Figure 1 ;

[0025] Figure 4is a schematic structural diagram of a P-type group III nitride layer according to some embodiments of the present disclosure;

[0026] Figure 5 According to this disclosure Figure 2 The structure of the semiconductor device provided along the cross-sectional line AA is schematically shown Figure 2 ;

[0027] Figure 6 A reverse bias electric field distribution diagram near a control electrode based on TCAD simulation of a semiconductor device with a P-type III-group nitride layer having a constant hole concentration according to some embodiments of the present disclosure;

[0028] Figure 7 A reverse bias electric field distribution diagram near a control electrode of a semiconductor device having a P-type III-group nitride layer with a variable hole concentration based on TCAD simulation according to some embodiments of the present disclosure;

[0029] Figure 8 is a graph showing the electric field intensity distribution of a semiconductor device according to some embodiments of the present disclosure;

[0030] Fig. 9 is a flow chart of a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0031] Fig.10 and Fig.11 It is a structural schematic diagram corresponding to each step of a method for preparing a semiconductor device according to some embodiments of the present disclosure;

[0032] Fig.12 It is a schematic diagram of the structure of an electronic device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0034] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0035] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0036] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0037] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0038] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0039] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0040] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0041] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0042] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include single crystal semiconductor materials such as silicon, silicon carbide, sapphire, group III nitrides, and diamond. Alternatively, the substrate may also include other materials such as polycrystalline diamond, ceramics, etc.

[0043] Semiconductor: A semiconductor is a material whose electrical conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities and defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an extrinsic semiconductor.

[0044] In some embodiments, Figure 1 As shown, when the control electrode 23 of a high electron mobility transistor (HEMT) is in a reverse bias state, a large number of electric field lines from the second electrode 22 will gather at the edge M of the control electrode 23 on the side close to the second electrode 22, so that a peak electric field exists at the edge M.

[0045] The structure of a HEMT is exemplarily introduced below.

[0046] In some examples, such as Figure 1 As shown, the HEMT includes a substrate 11 and a channel layer 14 and a barrier layer 16 stacked on one side of the substrate 11 .

[0047] Exemplarily, the material of the channel layer 14 includes GaN, and the material of the barrier layer 16 includes at least one of AlN and AlGaN. The following description is made by taking the example that the material of the channel layer 14 is GaN and the material of the barrier layer 16 is AlGaN.

[0048] AlGaN / GaN can form a heterojunction. The AlGaN / GaN heterojunction forms a high-density two-dimensional electron gas (2DEG) at the heterojunction interface through spontaneous polarization and piezoelectric polarization effects. This two-dimensional electron gas is spatially separated from ionized impurities, so it has a very high mobility, which makes the AlGaN / GaN HEMT have a very low on-resistance.

[0049] For example, Figure 1 As shown, the HEMT further includes: a P-type III-nitride layer 24, a control electrode 23 located on the side of the P-type III-nitride layer 24 away from the substrate 11, and a first electrode 21 and a second electrode 22. The first electrode 21 and the second electrode 22 are located on the side of the channel layer 14 away from the substrate 11, and the control electrode 23 is located between the first electrode 21 and the second electrode 22.

[0050] For example, the control electrode 23 is the gate of the HEMT, the first electrode 21 is one of the source and drain of the HEMT, and the second electrode 22 is the other of the source and drain of the HEMT. The following description is made by taking the first electrode 21 as the source of the HEMT and the second electrode 22 as the drain of the HEMT as an example. It can be understood that in other embodiments, the first electrode 21 can be the drain of the HEMT, and the second electrode 22 can be the source of the HEMT, and the embodiments of the present disclosure are not limited to this.

[0051] Exemplarily, the material of the P-type group III nitride layer 24 includes at least one of P-type GaN, P-type AlN and P-type InN. For example, the P-type group III nitride layer 24 is further doped with at least one of magnesium, iron and zinc.

[0052] like Figure 1 As shown, the AlGaN / GaN heterojunction composed of the barrier layer 16 and the channel layer 14 forms a 2DEG at its interface, and the P-type III-group nitride layer 24 can deplete the 2DEG below it to form a depletion region S1, so that the HEMT is in a normally closed state. The channel layer 14 is located in the area between the control electrode 23 and the first electrode 21 and the area between the control electrode 23 and the second electrode 22. 2DEG is still maintained. When a certain voltage is applied to the control electrode 23, the 2DEG below the control electrode 23 can be re-established, so that the HEMT is turned on.

[0053] However, when the HEMT control electrode 23 is in a reverse bias state, the HEMT needs to withstand a higher voltage of the second electrode 22. Since the HEMT inevitably has structural defects, the electric field is unevenly distributed in the AlGaN / GaN heterojunction, which will cause a concentrated electric field, i.e., a peak electric field, to exist at the edge M of the control electrode 23 and the P-type III-nitride layer 24 close to the second electrode 22. The peak electric field magnitude of the edge M of the control electrode 23 and the P-type III-nitride layer 24 close to the second electrode 22 can determine the breakdown voltage of the entire HEMT. Therefore, the presence of the peak electric field will cause the withstand voltage level of the HEMT to decrease, and ultimately lead to the problem of premature breakdown of the HEMT. Moreover, the presence of the peak electric field will cause leakage of the control electrode 23 of the HEMT, resulting in poor stability of the HEMT.

[0054] Based on this, Figure 2 and Figure 3 As shown, an embodiment of the present disclosure provides a semiconductor device 100 , which includes: a substrate 11 , a channel layer 14 , a barrier layer 16 , a P-type group III nitride layer 24 , a control electrode 23 , a first electrode 21 and a second electrode 22 .

[0055] Exemplarily, the semiconductor device 100 is a high electron mobility transistor (HEMT).

[0056] Exemplarily, the substrate 11 includes at least one of Si, SiC, GaN, sapphire and diamond. The introduction of the channel layer 14, the barrier layer 16 and the P-type group III nitride layer 24 can refer to the above content and will not be repeated here.

[0057] Exemplarily, the control electrode 23 is located between the first electrode 21 and the second electrode 22 , and the first electrode 21 , the control electrode 23 and the second electrode 22 are arranged in sequence and spaced apart from each other.

[0058] For example, Figure 2 and Figure 3 As shown, the first electrode 21 and the second electrode 22 are located on both sides of the extension direction Z of the control electrode 23 .

[0059] For example, Figure 2 As shown, the control electrode 23 is arranged in an annular shape, and the control electrode 23 surrounds the first electrode 21; the second electrode 22 is arranged in an annular shape, and the second electrode 22 surrounds the control electrode 23. Among them, the first electrode 21 can be circular, and when the first electrode 21 is circular, the control electrode 23 and the second electrode 22 can be circular ring-shaped. The first electrode 21 can be square, and when the first electrode 21 is square, the control electrode 23 and the second electrode 22 can be square ring-shaped.

[0060] Exemplarily, the first pole 21 and the second pole 22 are both connected to the heterojunction formed by the channel layer 14 and the barrier layer 16, that is, the first pole 21 and the second pole 22 are connected to the 2DEG, so that the first pole 21 and the second pole 22 form an ohmic contact with the 2DEG to reduce the on-resistance of the semiconductor device 100.

[0061] It should be noted that Figure 3 And in the subsequent content Figure 5 are cross-sectional views obtained along a cross-sectional line of the semiconductor device 100 of the two structures respectively, Figure 3 and Figure 5 The position of the corresponding cross-section line in the semiconductor device 100 is Figure 2 The position of the cross-section line AA in the semiconductor device 100 shown is the same.

[0062] In some examples, such as Figure 3 As shown, along the second direction X, in the P-type group III nitride layer 24 , the hole concentration of the portion of the P-type group III nitride layer 24 closest to the second electrode 22 is the smallest; the second direction X is perpendicular to the substrate 11 .

[0063] That is to say, the hole concentration in the P-type III-nitride layer 24 is not constant, but varies. Along the second direction, the hole concentration is the smallest at the portion of the P-type III-nitride layer 24 closest to the second electrode 22. It can also be understood that the hole concentration N1 is the smallest at the edge of the P-type III-nitride layer 24 close to the second electrode 22.

[0064] It should be noted that there are three methods for characterizing the change in hole concentration in the P-type III-nitride layer 24. (1) Characterizing the contrast of the P-type III-nitride layer 24 by scanning electron microscopy, where contrast refers to the difference in brightness between different regions on the image. Regions with higher hole concentrations have higher contrast, and vice versa; (2) Characterizing the potential of the P-type III-nitride layer 24 by Kelvin electromechanical microscopy, where different hole concentrations correspond to different potential distributions, with regions with higher hole concentrations corresponding to higher potentials and regions with lower hole concentrations corresponding to lower potentials; (3) Characterizing the hole concentration of the P-type III-nitride layer 24 by electroluminescence, where regions with higher hole concentrations have greater luminescence intensity, and vice versa.

[0065] There is a small amount of 2DEG in the heterojunction below the P-type group III nitride layer 24 with a lower hole concentration, and the concentration of 2DEG therein is lower than the concentration of 2DEG in the heterojunction not covered by the P-type group III nitride layer 24 .

[0066] By arranging the hole concentration of the portion of the P-type III-nitride layer 24 closest to the second electrode 22 in the P-type III-nitride layer 24 along the second direction X to be the smallest, when the semiconductor device 100 is in reverse bias (also called reverse bias), as the bias voltage of the second electrode 22 increases, the holes originally gathered at the control electrode 23 and the edge M of the P-type III-nitride layer 24 (such as Figure 1 The peak electric field of the P-type III-nitride layer 24 (as shown) is modulated by the portion of the P-type III-nitride layer 24 closest to the second electrode 22, and the effect of a small amount of 2DEG in the heterojunction below the P-type III-nitride layer 24 where the hole concentration is relatively small is utilized, so that the peak electric field cannot be concentrated on the control electrode 23 and the edge M of the P-type III-nitride layer 24, thereby achieving effective modulation of the electric field and improving the withstand voltage level of the semiconductor device 100 and the stability of the semiconductor device 100.

[0067] In some embodiments, Figure 3 and Figure 4 As shown, a virtual line N2 extending along the first direction Y is constructed on the P-type III-group nitride layer 24, and the P-type III-group nitride layer 24 includes: a first portion 24a and a second portion 24b located on both sides of the virtual line N2 along the second direction X, a dimension d2 of the first portion 24a in the second direction X and a dimension d3 of the second portion 24b in the second direction X are substantially equal, that is, d2≈d3, the first portion 24a is closer to the second pole 22 than the second portion 24b, and the second direction X is parallel to the substrate 11; wherein, along the second direction X, in the first portion 24a, the hole concentration of the portion of the first portion 24a closest to the virtual line N2 is the largest.

[0068] For example, Figure 3 and Figure 4 As shown, the hole concentration of the portion of the first portion 24 a closest to the virtual line N2 is the highest, and the hole concentration of the portion of the first portion 24 a farthest from the virtual line N2 is the lowest.

[0069] This can ensure that the 2DEG in the heterojunction near the virtual line N2 is depleted, and a small amount of 2DEG exists in the heterojunction below the portion of the first part 24a farthest from the virtual line N2. The change in the concentration of 2DEG can achieve the purpose of modulating the 2DEG concentration in the heterojunction below the P-type III-nitride layer 24, so as to achieve electric field modulation and improve the voltage resistance level of the semiconductor device 100 and the stability of the semiconductor device 100.

[0070] In some embodiments, Figure 4 and Figure 5 As shown, along the second direction X, in the second portion 24 b , the hole concentration is smallest at a portion of the second portion 24 b farthest from the virtual line N2 .

[0071] For example, Figure 4 and Figure 5As shown, the portion of the second portion 24b farthest from the virtual line N2 can be understood as the portion of the second portion 24b farthest from the edge N3 of the virtual line N2. The hole concentration in the portion of the second portion 24b farthest from the edge N3 of the virtual line N2 is the smallest, so as to achieve modulation of the electric field of the P-type III-nitride layer 24 close to the first pole 21.

[0072] Exemplarily, the hole concentration of the portion of the second portion 24b farthest from the virtual line N2 is greater than or equal to the hole concentration of the portion of the first portion 24a farthest from the virtual line N2. This can ensure that the electric field close to the second electrode 22 with a relatively high voltage is effectively modulated, thereby improving the withstand voltage level of the semiconductor device 100.

[0073] In some embodiments, Figure 4 and Figure 5 As shown, along the second direction X, in the second portion 24 b , the hole concentration is highest in a portion close to the virtual line N2 .

[0074] For example, Figure 4 and Figure 5 As shown, this can ensure that the 2DEG in the heterojunction near the virtual line N2 is depleted, and a small amount of 2DEG exists in the heterojunction below the portion of the second part 24b farthest from the virtual line N2. The change in the concentration of 2DEG can achieve the purpose of modulating the 2DEG concentration in the heterojunction below the P-type III-nitride layer 24, so as to achieve the modulation of the electric field of the P-type III-nitride layer 24 close to the first pole 21, thereby improving the withstand voltage level of the semiconductor device 100 and the stability of the semiconductor device 100.

[0075] In some embodiments, Figure 4 and Figure 5 As shown, the first portion 24a and the second portion 24b each include a first sub-portion 241; along the second direction X, the hole concentration of the first sub-portion 241 relatively close to the virtual line N2 is greater than the hole concentration of the first sub-portion 241 relatively far from the virtual line N2.

[0076] That is, by setting the first part 24a and the second part 24b both including the first sub-part 241, it is achieved that in the second direction X away from the virtual line N2, there is a tendency for the hole concentration in the P-type III-nitride layer 24 to decrease, so that the purpose of 2DEG modulation in the heterojunction below the P-type III-nitride layer 24 can be achieved, so that the electric field is distributed in the P-type III-nitride layer 24, so that the peak electric field cannot be concentrated on the control electrode 23 and the edge M of the P-type III-nitride layer 24, so as to achieve effective modulation of the electric field and improve the voltage resistance level of the semiconductor device 100 and the stability of the semiconductor device 100.

[0077] For example, in the second direction X away from the virtual line N2 , the hole concentrations of the first sub-portion 241 of the first portion 24 a and the first sub-portion 241 of the second portion 24 b may have the same or different decreasing trends.

[0078] Exemplarily, the number of first sub-portions 241 included in the first portion 24 a and the number of first sub-portions 241 included in the second portion 24 b may be the same or different, and the number is not limited thereto.

[0079] In some embodiments, Figure 4 and Figure 5 As shown, the first portion 24a and / or the second portion 24b further includes: a second sub-portion 242; the first sub-portion 241 and the second sub-portion 242 are arranged along the second direction X; along the second direction X, the hole concentration of the second sub-portion 242 is consistent.

[0080] For example, Figure 4 and Figure 5 As shown, the first portion 24 a and the second portion 24 b each include a second sub-portion 242 .

[0081] In some other examples, the first portion 24 a does not include the second sub-portion 242 , or the second portion 24 b does not include the second sub-portion 242 , which is not limited herein.

[0082] That is to say, along the second direction X away from the virtual line N2, the hole concentration of the P-type III-nitride layer 24 tends to decrease, but there may also be a part of the P-type III-nitride layer 24 where the hole concentration remains unchanged, which does not affect the modulation effect on the electric field.

[0083] In some embodiments, Figure 4 and Figure 5 As shown, the first portion 24a and / or the second portion 24b further includes: a third sub-portion 243; the first sub-portion 241 and the third sub-portion 243 are arranged along the second direction X; along the second direction X, the hole concentration of the portion of the third sub-portion 243 relatively close to the virtual line N2 is less than the hole concentration of the portion of the third sub-portion 243 relatively far from the virtual line N2.

[0084] For example, Figure 4 and Figure 5 As shown, the first portion 24 a and the second portion 24 b each include a third sub-portion 243 .

[0085] In some other examples, the first portion 24 a does not include the third sub-portion 243 , or the second portion 24 b does not include the third sub-portion 243 , which is not limited herein.

[0086] That is to say, along the second direction X away from the virtual line N2, the hole concentration of the P-type III-nitride layer 24 tends to decrease, but there may also be a part where the hole concentration of the P-type III-nitride layer 24 gradually increases, which does not affect the modulation effect on the electric field.

[0087] In some embodiments, Figure 2 As shown, the hole concentration in the second portion 24b remains unchanged.

[0088] In some embodiments, Figure 3 As shown, the hole concentration range of the P-type III-group nitride layer 24 is 10 13 cm 3 ~10 20 cm 3 .

[0089] For example, the hole concentration of the P-type group III nitride layer 24 is 10 13 cm 3 , 10 14 cm 3 , 10 15 cm 3 , 10 16 cm 3 , 10 17 cm 3 , 10 18 cm 3 , 10 19 cm 3 or 10 20 cm 3 Etc., there is no limitation here.

[0090] The hole concentration through the P-type group III nitride layer 24 is in the range of 10 13 cm 3 ~10 20 cm 3 is set to achieve the purpose of modulating the electric field of the semiconductor device 100.

[0091] In some embodiments, Figure 3 As shown, the P-type group III nitride layer 24 further includes a modulation element, and the modulation element can reduce the hole concentration in the P-type group III nitride layer 24 .

[0092] For example, the modulation element may provide electrons to reduce the hole concentration in the P-type group III nitride layer 24 .

[0093] By further doping modulation elements in the P-type III-nitride layer 24 doped with at least one of magnesium, iron and zinc, the purpose of further adjusting the hole concentration in the P-type III-nitride layer 24 is achieved, so that the hole concentration in the part of the P-type III-nitride layer 24 closest to the second electrode 22 is minimized, thereby achieving the purpose of electric field modulation.

[0094] Exemplarily, the modulating element includes at least one of hydrogen, oxygen, nitrogen, carbon, chlorine, silicon and fluorine.

[0095] Regarding the steps for preparing the P-type III-group nitride layer 24 containing the modulation element, refer to the contents of the method for preparing the semiconductor device, and will not be described in detail here.

[0096] In order to prove that the arrangement of the P-type III-group nitride layer 24 with the smallest hole concentration in the portion closest to the second electrode 22 can modulate the control electrode 23 and the edge M of the P-type III-group nitride layer 24 toward the second electrode 22 (such as Figure 1 The peak electric field is shown in Figure 2, providing the following data.

[0097] like Figure 6 to Figure 8 As shown, Figure 6 FIG. 1 is a reverse bias electric field distribution diagram near the control electrode 23 of a semiconductor device 100 having a constant hole concentration in the P-type group III nitride layer 24 according to some embodiments of the present disclosure based on TCAD simulation. The semiconductor device 100 is, for example, a HEMT, and the structure of the HEMT is as follows: Figure 1 As shown, it is represented as Example 1. Figure 7 FIG. 1 is a reverse bias electric field distribution diagram near the control electrode 23 of a semiconductor device 100 having a variable hole concentration in a P-type group III nitride layer 24 based on TCAD simulation according to some embodiments of the present disclosure. The structure of the semiconductor device 100 is as follows: Figure 3 As shown, it is represented as Example 2. Figure 8 is a graph of electric field intensity distribution curves of the semiconductor device 100 according to some embodiments of the present disclosure, wherein the electric field extraction position of the electric field intensity distribution curve of “Example 1” is located at Figure 1 The electric field extraction position of the electric field intensity distribution curve of "Example 2" is located at the dashed line L1 of the HEMT shown in FIG. Figure 3 At the dotted line L2 of the semiconductor device shown, the reverse bias voltage is 100V, that is, the voltage of the second electrode 22 is 100V.

[0098] from Figure 6 and Figure 8 It can be seen that the electric field peak value at the edge M of the control electrode 23 and the P-type III-group nitride layer 24 close to the second electrode 22 can reach about 2.6 MV / cm. Figure 7 and Figure 8It can be seen that the electric field peak value at the control electrode 23 and the P-type III-nitride layer 24 close to the second electrode 22 is about 1.6 MV / cm, and the electric field peak value deviates from the edge M of the control electrode 23 and the P-type III-nitride layer 24 close to the second electrode 22 .

[0099] Therefore, by setting up the P-type III-nitride layer 24 with the smallest hole concentration in the part closest to the second electrode 22, effective modulation of the electric field can be achieved, the peak voltage of the peak electric field can be reduced, and the withstand voltage level and stability of the semiconductor device 100 can be improved.

[0100] In some embodiments, Figure 3 As shown, the semiconductor device 100 further includes: a nucleation layer 12 and a buffer layer 13 , and the substrate 11 , the nucleation layer 12 , the buffer layer 13 and the channel layer 14 are arranged in sequence.

[0101] Exemplarily, the material of the nucleation layer 12 includes at least one of AlN, GaN and AlGaN.

[0102] Exemplarily, the material of the buffer layer 13 includes at least one of AlN, AlGaN and GaN.

[0103] Since the buffer layer 13 and the substrate 11 are made of different materials and usually have different lattice constants and thermal expansion coefficients, if the buffer layer 13 is directly disposed on the substrate 11, cracks may be generated in the buffer layer 13 due to lattice mismatch and thermal mismatch, resulting in a decrease in crystal quality. Therefore, the nucleation layer 12 is disposed to effectively avoid the generation of cracks in the buffer layer 13.

[0104] In some embodiments, Figure 3 As shown, the semiconductor device 100 further includes an insertion layer 15 , where the insertion layer 15 is located between the channel layer 14 and the barrier layer 16 .

[0105] Exemplarily, the material of the insertion layer 15 includes AlN, and the potential barrier of the insertion layer 15 may be greater than the potential barrier of the barrier layer 16 .

[0106] The provision of the insertion layer 15 can promote the polarization effect between the channel layer 14 and the barrier layer 16 , and increase the 2DEG concentration of the heterojunction between the channel layer 14 and the barrier layer 16 .

[0107] The present disclosure also provides a method for preparing a semiconductor device. Fig. 9 As shown, the steps of the method for preparing a semiconductor device include: R1 to R8.

[0108] R1, such as Fig.10 As shown, a channel layer 14 and a barrier layer 16 are sequentially formed on one side of a substrate 11 .

[0109] Exemplarily, a nucleation layer 12 and a buffer layer 13 are further disposed between the substrate 11 and the channel layer 14 .

[0110] Exemplarily, the nucleation layer 12 , the buffer layer 13 , the channel layer 14 and the barrier layer 16 are formed by an epitaxial growth method.

[0111] Exemplarily, the material of the substrate 11 includes: at least one of Si, SiC, GaN, sapphire and diamond; the material of the nucleation layer 12 includes: at least one of AlN, GaN and AlGaN; the material of the buffer layer 13 includes: at least one of AlN, AlGaN and GaN; the material of the channel layer 14 includes: unintentionally doped GaN; the material of the barrier layer 16 includes: at least one of AlN and AlGaN.

[0112] R2, such as Fig.10 As shown, an initial P-type III-nitride layer 201 is formed on the side of the barrier layer 16 away from the substrate 11 , and along the second direction X, the hole concentration of the initial P-type III-nitride layer 201 is equal.

[0113] Exemplarily, a whole first initial P-type group III nitride layer is formed by an epitaxial growth method, and then the first initial P-type group III nitride layer is etched by an etching process to form the initial P-type group III nitride layer 201 .

[0114] R3, such as Fig.10 As shown, a first pole 21 and a second pole 22 are formed on a side of the channel layer 14 away from the substrate 11 ; the first pole 21 and the second pole 22 are located on both sides of the initial P-type group III nitride layer 201 , and the first pole 21 and the second pole 22 are spaced apart from the initial P-type group III nitride layer 201 .

[0115] Exemplarily, the first electrode 21 and the second electrode 22 are both connected to the heterojunction formed by the channel layer 14 and the barrier layer 16. The second electrode 22 serves as a drain of the semiconductor device 100 and is used to access a forward high voltage.

[0116] R4, such as Fig.10 As shown, a mask layer 30 is formed, and the mask layer 30 only exposes a region T1 of the initial P-type group III nitride layer 201 where hole concentration adjustment is performed in advance.

[0117] Exemplarily, the material of the mask layer 30 includes: photoresist, oxide, nitride, oxynitride or metal, etc., which is not limited here.

[0118] R5, such as Fig.11 As shown, the initial modulation layer 50 is formed by ion implantation or thermal diffusion treatment of the region T1 of the initial P-type group III nitride layer 201 where the hole concentration is pre-adjusted.

[0119] Exemplarily, the modulation element includes at least one of hydrogen, oxygen, nitrogen, carbon, chlorine, silicon and fluorine. The modulation element can provide electrons to reduce the hole concentration in the P-type group III nitride layer 24.

[0120] Through the steps of ion implantation or thermal diffusion treatment, the modulation elements are gathered on the surface of the region T1 of the initial P-type group III nitride layer 201 to form the initial modulation layer 50 .

[0121] R6, such as Fig.11 As shown, the mask layer 30 is removed.

[0122] R7, such as Fig.11 As shown, a thermal annealing treatment is performed under the condition of 0°C to 1200°C to diffuse the modulation element of the initial modulation layer 50 into the initial P-type group III nitride layer 201 to form a P-type group III nitride layer 24 including the modulation element.

[0123] Exemplarily, during the thermal annealing process, the modulation element diffuses into the initial P-type group III nitride layer 201 along the first direction Y and the second direction X. The modulation element located on the surface of the initial P-type group III nitride layer 201 away from the substrate 11 diffuses into the initial P-type group III nitride layer 201 along the first direction Y. Generally, the size of the initial P-type group III nitride layer 201 along the first direction Y is small. Therefore, the modulation element located on the surface of the initial P-type group III nitride layer 201 away from the substrate 11 is easier to diffuse into the entire size range of the initial P-type group III nitride layer 201 along the first direction Y. Therefore, the concentration difference of the modulation element inside the initial P-type group III nitride layer 201 caused by the modulation element located on the surface of the initial P-type group III nitride layer 201 away from the substrate 11 is small.

[0124] However, the modulation element located on the surface of the initial P-type III-nitride layer 201 close to the second pole 22 diffuses into the initial P-type III-nitride layer 201 along the second direction X. Since the size of the initial P-type III-nitride layer 201 along the second direction X is relatively large, the diffusion of the modulation element located on the surface of the initial P-type III-nitride layer 201 close to the second pole 22 along the second direction X will be different. The closer to the second pole 22, the greater the concentration of the modulation element in the initial P-type III-nitride layer 201. Therefore, the portion of the initial modulation layer 50 located on the surface of the initial P-type III-nitride layer 201 close to the second pole 22 has a greater influence on the difference in the concentration of the modulation element inside the initial P-type III-nitride layer 201.

[0125] Since the modulating element concentration increases as it approaches the second electrode 22, and the modulating element provides electrons, the hole concentration of the P-type III-nitride layer 24 gradually decreases in the direction approaching the second electrode 22. The hole concentration of the portion of the P-type III-nitride layer 24 closest to the second electrode 22 is the smallest.

[0126] R8, such as Figure 3 As shown, a control electrode 23 is formed on a side of the P-type group III nitride layer 24 away from the substrate 11 , thereby obtaining a semiconductor device 100 .

[0127] Exemplarily, the control electrode 23 is formed by a deposition process.

[0128] Through the above steps R1 to R8, a semiconductor device 100 having a P-type group III nitride layer 24 with the smallest hole concentration in the portion closest to the second electrode 22 is prepared to achieve effective modulation of the electric field, reduce the peak value of the peak electric field, and improve the withstand voltage level and stability of the semiconductor device 100.

[0129] An embodiment of the present disclosure further provides an integrated circuit, which includes the semiconductor device 100 as described in any of the above embodiments.

[0130] An integrated circuit is a miniature electronic device or component. Using a certain process, the semiconductor devices 100, resistors, capacitors, inductors and other components and wiring required in a circuit are interconnected together, made on a small piece or several small pieces of semiconductor wafers or dielectric substrates, and then packaged in a tube shell to become a miniature structure with the required circuit function.

[0131] The integrated circuit includes the semiconductor device 100 provided in any of the above embodiments. Therefore, the integrated circuit provided in the embodiments of the present disclosure has all the beneficial effects of the semiconductor device 100 provided in any of the above embodiments, which will not be described in detail here.

[0132] like Fig.12 As shown, an embodiment of the present disclosure further provides an electronic device 1000, which includes an integrated circuit as provided in any of the above embodiments. The electronic device 1000 also includes a circuit board 200, on which the integrated circuit is disposed.

[0133] Exemplarily, the electronic device 1000 further includes an antenna, and the semiconductor device 100 on the integrated circuit is used to amplify the radio frequency signal and output it to the antenna for outward radiation.

[0134] like Fig.12 As shown, the electronic device 1000 includes the integrated circuit provided in any of the above embodiments. Therefore, the electronic device 1000 provided in the embodiment of the present disclosure has all the beneficial effects of the integrated circuit provided in any of the above embodiments, which will not be described in detail here.

[0135] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate and a channel layer and a barrier layer stacked on one side of the substrate; as well as, A P-type group III nitride layer is located on a side of the barrier layer away from the substrate; A first electrode, a second electrode and a control electrode, wherein the control electrode is located at a side of the P-type group III nitride layer away from the substrate, the first electrode and the second electrode are located at a side of the channel layer away from the substrate, and the control electrode is located between the first electrode and the second electrode; Among them, the P-type group III nitride layer also includes: a modulation element, which can reduce the hole concentration in the P-type group III nitride layer; the modulation element includes: at least one of hydrogen, oxygen, nitrogen, carbon, chlorine, silicon and fluorine; along the second direction, in the P-type group III nitride layer, the hole concentration of the part of the P-type group III nitride layer closest to the second pole is the smallest; the second direction is parallel to the substrate.

2. The semiconductor device according to claim 1, wherein: Constructing a virtual line extending in a direction perpendicular to the substrate on the P-type III-group nitride layer, the P-type III-group nitride layer comprising: a first portion and a second portion located on both sides of the virtual line along a second direction, the size of the first portion in the second direction is substantially equal to the size of the second portion in the second direction, the first portion is closer to the second pole than the second portion, and the second direction is parallel to the substrate; Here, along the second direction, in the first portion, a portion of the first portion closest to the virtual line has the highest hole concentration.

3. The semiconductor device according to claim 2, characterized in that Along the second direction, in the second portion, a portion of the second portion away from the virtual line has the smallest hole concentration.

4. The semiconductor device according to claim 3, characterized in that Along the second direction, in the second portion, a portion close to the virtual line has the highest hole concentration.

5. The semiconductor device according to claim 4, characterized in that The first part and the second part each include: a first sub-part; Along the second direction, a hole concentration of a portion of the first sub-portion relatively close to the virtual line is greater than a hole concentration of a portion of the first sub-portion relatively far from the virtual line.

6. The semiconductor device according to claim 5, characterized in that The first portion and / or the second portion further comprises: a second sub-portion; the first sub-portion and the second sub-portion are arranged along the second direction; The hole concentration of the second sub-section is uniform along the second direction.

7. The semiconductor device according to claim 5, characterized in that The first portion and / or the second portion further includes: a third sub-portion; the first sub-portion and the third sub-portion are arranged along the second direction; Along the second direction, a hole concentration of a portion of the third sub-portion relatively close to the virtual line is smaller than a hole concentration of a portion of the third sub-portion relatively far from the virtual line.

8. The semiconductor device according to claim 2, wherein: The hole concentration in the second portion remains unchanged.

9. The semiconductor device according to claim 1, wherein: The hole concentration of the P-type III-group nitride layer is in the range of 10 13 cm 3 ~10 20 cm 3 .

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The doping element in the P-type group III nitride layer includes at least one of magnesium, iron and zinc.

11. An integrated circuit, characterized in that: The invention comprises the semiconductor device according to any one of claims 1 to 10.

12. An electronic device, characterized in that: include: The integrated circuit as claimed in claim 11; A circuit board, wherein the integrated circuit is arranged on the circuit board.

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