Fin field effect transistor and preparation method thereof

Abstract

The present disclosure relates to a fin field effect transistor and a method for preparing the same, and relates to the field of semiconductor technology. The fin field effect transistor includes an active region and a gate. The active region includes a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction. The semiconductor fins extend along a second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. The first direction and the second direction intersect. The gate extends along the first direction to cover the top and side walls of the semiconductor fins in the non-interconnected area, and fills the gaps between adjacent semiconductor fins in the first direction. The present disclosure can increase the operating current of the fin field effect transistor, thereby improving the device performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a fin field effect transistor and a preparation method thereof. Background Art

[0002] With the miniaturization of semiconductor devices, the short channel effect has become more and more serious, and the impact of leakage current on devices has become more and more serious. FinFETs use a three-sided ring gate design to increase the contact area between the gate and the channel, enhance the gate's control over the channel, and thus reduce leakage current and increase operating current. However, as the size of FinFETs continues to shrink, the operating current is still difficult to meet actual needs.

[0003] Therefore, how to further increase the operating current of the FinFET and thus improve device performance is an urgent problem to be solved. Summary of the invention

[0004] Based on this, it is necessary to provide a FinFET and a preparation method thereof to increase the operating current of the FinFET and thereby improve device performance.

[0005] On the one hand, an embodiment of the present disclosure provides a fin field effect transistor, including an active region and a gate. The active region includes a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction. The semiconductor fins extend along a second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. The first direction intersects with the second direction. The gate extends along the first direction to cover the top and sidewalls of the semiconductor fins in the non-interconnected area, and fills the gaps between adjacent semiconductor fins in the first direction.

[0006] In the embodiment of the present disclosure, the semiconductor fins extend along the second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. In this way, the fin field effect transistor connects the two ends of multiple semiconductor fins, and the gate extends along the first direction to cover the top and side walls of each semiconductor fin in the non-interconnected area, and fills the gap between adjacent semiconductor fins. In this way, the embodiment of the present disclosure can reduce the resistance of the fin field effect transistor by connecting the two ends of multiple semiconductor fins without increasing the leakage current, thereby increasing the operating current of the fin field effect transistor and further improving the device performance.

[0007] In some embodiments of the present disclosure, the active region includes a source terminal and a drain terminal. The source terminal includes the first terminal of each semiconductor fin and its interconnection portion. The drain terminal includes the second terminal of each semiconductor fin and its interconnection portion. The orthographic projections of the source terminal and the drain terminal along the third direction are located on both sides of the orthographic projection of the gate along the third direction, and the third direction is perpendicular to the intersection plane of the first direction and the second direction.

[0008] In some embodiments of the present disclosure, the fin field effect transistor further includes a gate dielectric layer. The gate dielectric layer at least fills the gap between adjacent semiconductor fins and is located between the gate and each semiconductor fin. The gate dielectric layer has an opening area, and the source terminal and the drain terminal are exposed in the opening area.

[0009] In some embodiments of the present disclosure, the semiconductor fin includes a base and a functional part distributed up and down along a third direction. The third direction is perpendicular to the intersection plane of the first direction and the second direction. The gate extends along the first direction to cover the top and sidewalls of each functional part located in the non-interconnected area, and fills the interval between adjacent functional parts in the first direction.

[0010] In some embodiments of the present disclosure, the fin field effect transistor further includes: a gate dielectric layer, located between the gate and each semiconductor fin. The gate dielectric layer includes: a first dielectric layer and a second dielectric layer. The first dielectric layer covers the side walls of each base and its interconnected portion, and fills the gap between adjacent bases. The second dielectric layer is located on the first dielectric layer, extending along the first direction to cover the top and side walls of each functional portion located in the non-interconnected area. Among them, the gate is located on the second dielectric layer.

[0011] On the other hand, an embodiment of the present disclosure provides a method for preparing a fin field effect transistor, comprising the following steps.

[0012] A substrate is provided, and an active region is formed in the substrate. The active region includes a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction. The semiconductor fins extend along a second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. The first direction and the second direction intersect.

[0013] A gate is formed on the top and sidewall of each semiconductor fin located in the non-interconnection region; the gate extends along a first direction and fills the space between adjacent semiconductor fins in the first direction.

[0014] In the disclosed embodiment, the method for preparing the FinFET is as described above. The technical effect that can be achieved by the method for preparing the FinFET is the same as the technical effect that can be achieved by the FinFET in the aforementioned embodiment, and will not be described in detail here.

[0015] In some embodiments of the present disclosure, the semiconductor fin includes: a base and a functional portion distributed up and down along a third direction; and an intersecting plane of the third direction perpendicular to the first direction and the second direction. Before forming a gate on the top and sidewalls of each semiconductor fin located in a non-interconnected region, the method for preparing a fin field effect transistor further includes the following steps.

[0016] A first dielectric layer is formed to cover the substrate and the side walls of each base and the interconnection parts thereof, and the first dielectric layer fills up the spaces between adjacent bases.

[0017] A second dielectric layer is formed on the first dielectric layer, the second dielectric layer extending along the first direction and covering the top and side walls of each functional part located in the non-interconnected area. The gate is formed on the second dielectric layer.

[0018] In some embodiments of the present disclosure, an active region is formed in a substrate, including the following steps.

[0019] An etch stop layer and a hard mask auxiliary layer are stacked on the substrate.

[0020] The hard mask auxiliary layer is etched to form a plurality of auxiliary patterns arranged in parallel and spaced apart in a first direction; the auxiliary patterns are used to define the intervals between adjacent semiconductor fins.

[0021] A hard mask layer covering the auxiliary patterns and the etch stop layer is formed.

[0022] The hard mask layer is etched and the auxiliary patterns are removed, so that the remaining hard mask layer forms a dummy active region.

[0023] Using the virtual active area as a mask pattern, the etching stop layer and the substrate are etched to form an active area.

[0024] In some embodiments of the present disclosure, after forming an active region in a substrate and before forming a gate on the top and sidewalls of each semiconductor fin in a non-interconnected region, the method for preparing a fin field effect transistor further includes the following steps.

[0025] A first dielectric material layer is formed on the exposed surface of the substrate and the remaining etching stop layer.

[0026] The first dielectric material layer is etched, and the remaining etching stop layer is removed simultaneously to form a first dielectric layer. The first dielectric layer covers the substrate and the bases of each semiconductor fin and the sidewalls of the interconnected parts thereof, and fills the spaces between adjacent bases.

[0027] A second dielectric material layer and a gate material layer are sequentially formed on the first dielectric layer and the exposed surface of the active region.

[0028] The gate material layer and the second dielectric material layer are patterned and etched to form a gate and a second dielectric layer; wherein the second dielectric layer and the first dielectric layer together constitute a gate dielectric layer; the second dielectric layer has an opening area, and the portion of the active area exposed in the opening area constitutes a source terminal and a drain terminal respectively.

[0029] In some embodiments of the present disclosure, the first dielectric material layer and the second dielectric material layer are both formed by a deposition process. The deposition thickness of the first dielectric material layer is greater than the deposition thickness of the second dielectric material layer.

[0030] As described above, in the disclosed embodiment, the semiconductor fins extend along the second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. The unexpected technical effect is that the fin field effect transistor connects the two ends of multiple semiconductor fins, and the gate extends along the first direction to cover the top and sidewalls of each semiconductor fin in the non-interconnected area, and fills the gap between adjacent semiconductor fins, so that the resistance of the fin field effect transistor can be reduced by connecting the two ends of multiple semiconductor fins without increasing the leakage current, thereby increasing the operating current of the fin field effect transistor, and thus improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] FIG1(a) is a schematic diagram of a top view of a fin field effect transistor provided in an embodiment of the present disclosure; FIG1(b) is a schematic diagram of a cross-sectional structure of the structure shown in FIG1(a) along the aa' direction; FIG1(c) is a schematic diagram of a cross-sectional structure of the structure shown in FIG1(a) along the bb' direction;

[0033] Figure 2 A schematic diagram of a process for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0034] Figure 3 A schematic diagram of a process for forming an active region in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0035] Figure 4 A schematic diagram of a process of forming a gate dielectric layer in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0036] Figure 5 It is a schematic diagram of another process of forming a gate dielectric layer in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0037] Figure 6 A schematic cross-sectional view of a structure obtained in step S101 of a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0038] Figure 7 A schematic cross-sectional view of a structure obtained in step S102 of a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure;

[0039] FIG8(a) is a schematic diagram of a top view of a structure obtained in step S103 in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG8(b) is a schematic diagram of a cross-sectional structure of the structure shown in FIG8(a) along the aa' direction;

[0040] FIG9(a) is a schematic diagram of a top view of a structure obtained in step S104 in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG9(b) is a schematic diagram of a cross-sectional structure of the structure shown in FIG9(a) along the aa' direction;

[0041] FIG. 10 (a) is a schematic diagram of a top view of a structure obtained in step S105 in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG. 10 (b) is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 10 (a) along the aa' direction;

[0042] FIG. 11( a ) is a schematic diagram of a top view of a structure obtained in step S151 in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG. 11( b ) is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 11( a ) along the aa′ direction;

[0043] FIG. 12( a ) is a schematic diagram of a top view of a structure obtained in step S151 ′ in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG. 12( b ) is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 12( a ) along the aa′ direction;

[0044] FIG. 13( a ) is a schematic diagram of a top view of a structure obtained in step S152 ′ in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG. 13( b ) is a schematic diagram of a cross-sectional structure of the structure shown in FIG. 13( a ) along the aa′ direction;

[0045] FIG14( a ) is a schematic top view of a structure obtained in step S153 ′ in a method for preparing a fin field effect transistor provided in an embodiment of the present disclosure; FIG14( b ) is a schematic cross-sectional view of the structure shown in FIG14( a ) along the aa′ direction.

[0046] Description of reference numerals:

[0047] 1-active area; 10-semiconductor fin; 101-base; 102-functional part; 11-source terminal; 12-drain terminal; 2-gate; 20-gate material layer; 3-gate dielectric layer; 31-first dielectric layer; 310-32-second dielectric layer; 4-substrate; 50-silicon dioxide layer; 500-residual silicon dioxide layer; 51-etching stop layer; 510-residual etch stop layer; 52-hard mask auxiliary layer; 520-auxiliary pattern; 53-hard mask layer; 530-virtual active area. DETAILED DESCRIPTION

[0048] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0049] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0050] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0051] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0052] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0053] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0054] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0055] With the miniaturization of semiconductor devices, the short channel effect has become more and more serious, and the impact of leakage current on devices has become more and more serious. FinFETs use a three-sided ring gate design to increase the contact area between the gate and the channel, enhance the gate's control over the channel, and thus reduce leakage current and increase operating current. However, as the size of FinFETs continues to shrink, the operating current is still difficult to meet actual needs.

[0056] Based on this, it is necessary to provide a FinFET and a preparation method thereof to increase the operating current of the FinFET and thereby improve device performance.

[0057] Referring to FIG. 1 (a), FIG. 1 (b) and FIG. 1 (c), an embodiment of the present disclosure provides a fin field effect transistor, including an active region 1 and a gate 2. The active region 1 includes a plurality of semiconductor fins 10 arranged in parallel and spaced apart in a first direction (e.g., an X direction). The semiconductor fins 10 extend along a second direction (e.g., a Y direction), and the first ends of the semiconductor fins 10 in the second direction (e.g., the Y direction) are interconnected, and the second ends of the semiconductor fins 10 in the second direction (e.g., the Y direction) are interconnected. The first direction (e.g., the X direction) and the second direction (e.g., the Y direction) intersect. The gate 2 extends along the first direction (e.g., the X direction) to cover the top and sidewalls of each semiconductor fin 10 in the non-interconnected area, and fills the gaps between adjacent semiconductor fins 10 in the first direction (e.g., the X direction).

[0058] In the embodiment of the present disclosure, the semiconductor fin 10 extends along the second direction (e.g., the Y direction), and the first ends of each semiconductor fin 10 in the second direction (e.g., the Y direction) are interconnected, and the second ends of each semiconductor fin 10 in the second direction (e.g., the Y direction) are interconnected. In this way, the fin field effect transistor connects the two ends of multiple semiconductor fins 10, and the gate 2 extends along the first direction (e.g., the X direction) to cover the top and sidewalls of each semiconductor fin 10 in the non-interconnected area, and fills the gap between adjacent semiconductor fins 10. In this way, the embodiment of the present disclosure can reduce the resistance of the fin field effect transistor by connecting the two ends of multiple semiconductor fins 10 without increasing the leakage current, thereby increasing the operating current of the fin field effect transistor and further improving the device performance.

[0059] In some embodiments, please continue to refer to FIG. 1 (a), the active region 1 includes a source terminal 11 and a drain terminal 12. The source terminal 11 includes the first end of each semiconductor fin 10 and its interconnection portion. The drain terminal 12 includes the second end of each semiconductor fin 10 and its interconnection portion. The positive projections of the source terminal 11 and the drain terminal 12 along the third direction (e.g., Z direction) are located on both sides of the positive projection of the gate 2 along the third direction (e.g., Z direction), and the third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., Y direction).

[0060] In some embodiments of the present disclosure, please continue to refer to FIG. 1 (b) and FIG. 1 (c), the semiconductor fin 10 includes a base 101 and a functional portion 102 distributed up and down along a third direction (e.g., Z direction). The third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., Y direction). The gate 2 extends along the first direction (e.g., X direction) to cover the top and sidewalls of each functional portion 102 located in the non-interconnected area, and fills the interval between adjacent functional portions 102 in the first direction (e.g., X direction).

[0061] In some examples, the material of gate 2 includes polysilicon.

[0062] In some embodiments, the fin field effect transistor further includes a gate dielectric layer 3. The gate dielectric layer 3 at least fills the space between adjacent semiconductor fins 10 and is located between the gate 2 and each semiconductor fin 10. The gate dielectric layer 3 has an opening area, and the source terminal 11 and the drain terminal 12 are exposed in the opening area.

[0063] In some other embodiments, please continue to refer to FIG. 1 (a), FIG. 1 (b) and FIG. 1 (c), the gate dielectric layer 3 is located between the gate 2 and each semiconductor fin 10. The gate dielectric layer 3 includes: a first dielectric layer 31 and a second dielectric layer 32. The first dielectric layer 31 covers the sidewalls of each base 101 and its interconnected portion, and fills the gap between adjacent bases 101. The second dielectric layer 32 is located on the first dielectric layer 31, and extends along a first direction (e.g., X direction) to cover the top and sidewalls of each functional portion 102 located in the non-interconnected area. Among them, the gate 2 is located on the second dielectric layer 32.

[0064] By way of example, the material of the first dielectric layer 31 includes silicon dioxide. The material of the second dielectric layer 32 includes silicon dioxide.

[0065] See also Figure 2 The present disclosure also provides a method for preparing a fin field effect transistor. The method can achieve the same technical effect as the fin field effect transistor in the above embodiment, which will not be described in detail here. The method for preparing a fin field effect transistor includes steps S100 to S200.

[0066] S100, providing a substrate, and forming an active region in the substrate. The active region includes a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction. The semiconductor fins extend along a second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected. The first direction and the second direction intersect.

[0067] S200, forming a gate on the top and sidewall of each semiconductor fin located in the non-interconnected region. The gate extends along a first direction and fills the space between adjacent semiconductor fins in the first direction.

[0068] In some embodiments of the present disclosure, please refer to Figure 3 , step S100 forms an active area in the substrate, including steps S101~S105.

[0069] S101, forming an etch stop layer and a hard mask auxiliary layer on a substrate by stacking.

[0070] S102, etching the hard mask auxiliary layer to form a plurality of auxiliary patterns arranged in parallel and spaced apart in a first direction; the auxiliary patterns are used to define the intervals between adjacent semiconductor fins.

[0071] S103, forming a hard mask layer covering the auxiliary patterns and the etch stop layer.

[0072] S104, etching the hard mask layer and removing the auxiliary patterns, so that the remaining hard mask layer forms a virtual active area.

[0073] S105 , using the virtual active area as a mask pattern, etching the virtual active area, the etching stop layer and the substrate to form an active area.

[0074] In some embodiments of the present disclosure, the semiconductor fin includes: a base portion and a functional portion distributed up and down along a third direction. The third direction is perpendicular to the intersection plane of the first direction and the second direction. Figure 4 Before forming gates on the top and sidewalls of each semiconductor fin in the non-interconnected region, the method for preparing the fin field effect transistor further includes steps S151 to S152.

[0075] S151, forming a first dielectric layer covering the substrate and the side walls of each base and the interconnected parts thereof, wherein the first dielectric layer fills the space between adjacent bases.

[0076] S152, forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer extends along the first direction and covers the top and side walls of each functional part located in the non-interconnected area, wherein the gate is formed on the second dielectric layer.

[0077] In some embodiments, see Figure 5 After the active region is formed in the substrate and before the gate is formed on the top and sidewalls of each semiconductor fin in the non-interconnected region, the method for preparing the fin field effect transistor further includes steps S151'-S154'.

[0078] S151 ′, forming a first dielectric material layer on the exposed surfaces of the substrate and the remaining etch stop layer.

[0079] S152', etching the first dielectric material layer, and simultaneously removing the remaining etching stop layer, to form a first dielectric layer. The first dielectric layer covers the substrate and the bases of each semiconductor fin and the sidewalls of the interconnected parts thereof, and fills the spaces between adjacent bases.

[0080] S153 ′, forming a second dielectric material layer and a gate material layer in sequence on the first dielectric layer and the exposed surface of the active region.

[0081] S154', pattern-etching the gate material layer and the second dielectric material layer to form a gate and a second dielectric layer. The second dielectric layer and the first dielectric layer together constitute a gate dielectric layer. The second dielectric layer has an opening area, and the portion of the active area exposed in the opening area constitutes a source terminal and a drain terminal respectively.

[0082] In some embodiments, the first dielectric material layer and the second dielectric material layer are both formed by a deposition process, and the deposition thickness of the first dielectric material layer is greater than the deposition thickness of the second dielectric material layer.

[0083] It can be understood that in some of the above embodiments, although Figure 2~Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2~Figure 5 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0084] In order to more clearly illustrate the method for preparing the FinFET provided by the embodiment of the present disclosure, some possible implementation methods of the method for preparing the FinFET are described in detail below in conjunction with FIG. 1( a ) to FIG. 14( b ).

[0085] In step S101, refer to Figure 6 , an etch stop layer 51 and a hard mask auxiliary layer 52 are stacked on the substrate 4.

[0086] In some examples, substrate 4 may include, but is not limited to, a silicon substrate.

[0087] In some examples, before forming the etch stop layer 51 and the hard mask auxiliary layer 52, the method for preparing the fin field effect transistor further includes: forming a silicon dioxide layer 50 on the substrate. The silicon dioxide layer 50 and the etch stop layer 51 together constitute an etching protection layer.

[0088] In some examples, hard mask auxiliary layer 52 includes a polysilicon layer.

[0089] In step S102, refer to Figure 7 , the hard mask auxiliary layer 52 is etched to form a plurality of auxiliary patterns 520 arranged in parallel and spaced apart in a first direction (eg, X direction). The auxiliary patterns 520 are used to define the intervals between adjacent semiconductor fins 10 .

[0090] In step S103 , referring to FIG. 8( a ) and FIG. 8 ( b ), a hard mask layer 53 covering the auxiliary patterns 520 and the etch stop layer 51 is formed.

[0091] In some examples, hard mask layer 53 may be formed using a deposition process.

[0092] In some examples, the material of hard mask layer 53 includes, but is not limited to, silicon oxide.

[0093] Here, it should be noted that the deposition thickness of the hard mask layer 53 is determined according to the thickness of the field effect transistor to be formed. The thickness of the subsequent virtual active area 530 can be defined by controlling the deposition time of silicon oxide by comprehensively weighing factors such as etching selectivity, etching method and etching rate.

[0094] In step S104 , referring to FIG. 9 ( a ) and FIG. 9 ( b ), the hard mask layer 53 is etched and the auxiliary patterns 520 are removed, so that the remaining hard mask layer 53 forms a dummy active region 530 .

[0095] In some examples, the hard mask layer 53 is etched back using an etch-back process to form the dummy active region 530 .

[0096] In step S105, referring to FIG. 10 (a) and FIG. 10 (b), the dummy active region 530 is used as a mask pattern to etch the etch stop layer 51 and the substrate 4 to form an active region 1. The active region 1 includes a plurality of semiconductor fins 10 arranged in parallel and spaced apart in a first direction (e.g., X direction). The semiconductor fins 10 extend along a second direction (e.g., Y direction), and the first ends of the semiconductor fins 10 in the second direction (e.g., X direction) are interconnected, and the second ends of the semiconductor fins 10 in the second direction (e.g., Y direction) are interconnected. The first direction (e.g., X direction) and the second direction (e.g., Y direction) intersect.

[0097] In some examples, using the virtual active area 530 as a mask pattern to etch the etch stop layer 51 and the substrate 4 to form the active area 1 further includes: using the virtual active area 530 as a mask pattern to etch the etch stop layer 51, the silicon dioxide layer 50 and the substrate 4 to form the active area 1.

[0098] In step S151, referring to FIG. 11(a) and FIG. 11(b), the semiconductor fin 10 includes: a base 101 and a functional portion 102 distributed up and down along a third direction (e.g., Z direction). The third direction (e.g., Z direction) is perpendicular to the intersection plane of the first direction (e.g., X direction) and the second direction (e.g., Y direction). A first dielectric layer 31 is formed to cover the substrate 4 and the side walls of each base 101 and its interconnected parts, and the first dielectric layer 31 fills the gaps between adjacent bases 101.

[0099] In some examples, before forming the first dielectric layer 31 , the process further includes: removing the dummy active region 530 , the remaining etch stop layer 510 , and the remaining silicon dioxide layer 500 .

[0100] By way of example, the material of the first dielectric layer 31 includes silicon dioxide.

[0101] By way of example, the first dielectric layer 31 may be formed by a deposition process.

[0102] In step S152, referring to FIG. 1 (a) and FIG. 1 (b), a second dielectric layer 32 is formed on the first dielectric layer 31, and the second dielectric layer 32 extends along a first direction (e.g., X direction) and covers the top and sidewalls of each functional portion 102 located in the non-interconnected region. The gate 2 is formed on the second dielectric layer 32. The gate dielectric layer 3 includes the first dielectric layer 31 and the second dielectric layer 32.

[0103] In some examples, the material of second dielectric layer 32 includes silicon dioxide.

[0104] In some examples, the second dielectric layer 32 may be formed using a deposition process.

[0105] In some other embodiments, in step S151 ′, referring to FIG. 12 ( a ) and FIG. 12 ( b ), a first dielectric material layer 310 is formed on the exposed surfaces of the substrate 4 and the remaining etch stop layer 510 .

[0106] In some examples, the material of first dielectric material layer 310 includes silicon dioxide.

[0107] In some examples, the first dielectric material layer 310 may be formed using a deposition process.

[0108] In step S152', referring to FIG. 13(a) and FIG. 13(b), the first dielectric material layer 310 is etched, and the remaining etching stop layer 510 is removed simultaneously to form a first dielectric layer 31. The first dielectric layer 31 covers the substrate 4 and the sidewalls of the bases 101 of each semiconductor fin 10 and the interconnected parts thereof, and fills the spaces between adjacent bases 101.

[0109] In some examples, removing the remaining etch stop layer 510 also includes removing the remaining silicon dioxide layer 500 .

[0110] In step S153 ′, referring to FIG. 14 ( a ) and FIG. 14 ( b ), a second dielectric material layer 320 and a gate material layer 20 are sequentially formed on the exposed surfaces of the first dielectric layer 31 and the active region 1 .

[0111] In some examples, the material of the second dielectric material layer 320 includes silicon dioxide. The material of the gate material layer 20 includes polysilicon.

[0112] In some examples, the second dielectric material layer 320 and the gate material layer 20 may be formed by a deposition process.

[0113] In step S154', referring to FIG. 1 (a) and FIG. 1 (b), the gate material layer 20 and the second dielectric material layer 320 are patterned and etched to form a gate 2 and a second dielectric layer 32. The second dielectric layer 32 and the first dielectric layer 31 together constitute a gate dielectric layer 3. The second dielectric layer 32 has an opening area, and the portion of the active area 1 exposed in the opening area constitutes a source terminal 11 and a drain terminal 12, respectively.

[0114] As described above, in the embodiment of the present disclosure, the semiconductor fins 10 extend along the second direction (e.g., the Y direction), and the first ends of the semiconductor fins 10 in the second direction (e.g., the Y direction) are interconnected, and the second ends of the semiconductor fins 10 in the second direction (e.g., the Y direction) are interconnected. The unexpected technical effect is that the fin field effect transistor connects the two ends of multiple semiconductor fins 10, and the gate 2 extends along the first direction (e.g., the X direction) to cover the top and sidewalls of each semiconductor fin 10 in the non-interconnected area, and fills the gaps between adjacent semiconductor fins 10, so that the embodiment of the present disclosure can reduce the resistance of the fin field effect transistor by connecting the two ends of multiple semiconductor fins 10 without increasing the leakage current, thereby increasing the operating current of the fin field effect transistor, and thereby improving the device performance.

[0115] In the description of this specification, the technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A fin field effect transistor, characterized in that: include: An active region, comprising a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction; wherein the semiconductor fins extend along a second direction, and the first ends of the semiconductor fins in the second direction are interconnected, and the second ends of the semiconductor fins in the second direction are interconnected; the first direction intersects with the second direction; the semiconductor fins comprise: a base portion and a functional portion distributed up and down along a third direction; the third direction is perpendicular to the intersection plane of the first direction and the second direction; A gate extending along the first direction to cover the top and sidewalls of each semiconductor fin located in the non-interconnected region and fill the space between adjacent semiconductor fins in the first direction; The gate dielectric layer is located between the gate and each of the semiconductor fins, and includes: A first dielectric layer, covering the side walls of each of the bases and their interconnected parts, and filling the spaces between adjacent bases; The second dielectric layer is located on the first dielectric layer and extends along the first direction to cover the top and side walls of each of the functional parts located in the non-interconnected area; wherein the gate is located on the second dielectric layer.

2. The fin field effect transistor according to claim 1, wherein: The active region comprises: A source end, including the first end of each of the semiconductor fins and an interconnection portion thereof; a drain terminal, including the second terminal of each of the semiconductor fins and interconnected portions thereof; The orthographic projections of the source terminal and the drain terminal along the third direction are located on both sides of the orthographic projection of the gate along the third direction, and the third direction is perpendicular to the intersection plane of the first direction and the second direction.

3. The fin field effect transistor according to claim 2, wherein: The gate dielectric layer has an opening area, and the source terminal and the drain terminal are exposed in the opening area.

4. The fin field effect transistor according to any one of claims 1 to 3, characterized in that: The gate extends along the first direction to cover the top and sidewalls of each of the functional parts located in the non-interconnection region, and fills the spaces between adjacent functional parts in the first direction.

5. A method for preparing a fin field effect transistor, characterized in that: include: providing a substrate, forming an active region in the substrate; The active area includes a plurality of semiconductor fins arranged in parallel and spaced apart in a first direction; The semiconductor fins extend along a second direction, and first ends of the semiconductor fins in the second direction are interconnected, and second ends of the semiconductor fins in the second direction are interconnected; The first direction and the second direction intersect; The semiconductor fin comprises: a base portion and a functional portion distributed up and down along a third direction; the third direction is perpendicular to an intersection plane of the first direction and the second direction; forming a first dielectric layer covering the substrate and the side walls of each of the bases and their interconnected parts, wherein the first dielectric layer fills the spaces between adjacent bases; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer extends along the first direction and covers the top and side walls of each of the functional parts located in the non-interconnected area; A gate is formed on the top and sidewall of each semiconductor fin located in the non-interconnected region; the gate extends along the first direction and fills the space between adjacent semiconductor fins in the first direction; Wherein, the gate is formed on the second dielectric layer.

6. The method for preparing a fin field effect transistor according to claim 5, characterized in that: The forming of an active region in the substrate comprises: forming an etch stop layer and a hard mask auxiliary layer in a stacked manner on the substrate; Etching the hard mask auxiliary layer to form a plurality of auxiliary patterns arranged in parallel and spaced apart in a first direction; the auxiliary patterns are used to define the intervals between adjacent semiconductor fins; forming a hard mask layer covering each of the auxiliary patterns and the etch stop layer; Etching the hard mask layer and removing the auxiliary patterns, so that the remaining hard mask layer forms a virtual active area; The dummy active area is used as a mask pattern to etch the etch stop layer and the substrate to form the active area.

7. The method for preparing a fin field effect transistor according to claim 6, characterized in that: After forming the active area in the substrate and before forming gates on the top and sidewalls of each semiconductor fin in the non-interconnected area, the method for preparing the fin field effect transistor further includes: forming a first dielectric material layer on the exposed surface of the substrate and the remaining etch stop layer; Etching the first dielectric material layer and simultaneously removing the remaining etching stop layer to form a first dielectric layer; the first dielectric layer covers the substrate and the bases of each semiconductor fin and the sidewalls of the interconnected parts thereof, and fills the spaces between adjacent bases; Sequentially forming a second dielectric material layer and a gate material layer on the first dielectric layer and the exposed surface of the active region; The gate material layer and the second dielectric material layer are pattern-etched to form the gate and the second dielectric layer; wherein the second dielectric layer and the first dielectric layer together constitute a gate dielectric layer; the second dielectric layer has an opening area, and the portion of the active area exposed to the opening area constitutes a source terminal and a drain terminal respectively.

8. The method for preparing a fin field effect transistor according to claim 7, characterized in that: The first dielectric material layer and the second dielectric material layer are both formed by a deposition process; The deposition thickness of the first dielectric material layer is greater than the deposition thickness of the second dielectric material layer.

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