Back contact solar cell and preparation method thereof, and battery assembly

Abstract

The invention relates to the technical field of solar cells, and in particular to a back-contact solar cell and a preparation method thereof, and a battery assembly, wherein a porous graphene composite film is used to replace an original transparent conductive film; the graphene conductive film has good conductivity, is beneficial to improving the conductivity of N and P regions, reducing contact resistance, and improving FF and battery performance; because the graphene composite film is porous, long-wavelength light enters the porous film layer, and after multiple reflections by the pore structure, is beneficial to the absorption of the long-wavelength light by the back film layer, thereby improving the anti-reflection effect of the back; the graphene porous conductive layer contains zinc oxide, which can further enhance the anti-reflection effect and improve the current density; a porous graphene conductive film is formed on the back of a silicon wafer by screen printing, the screen printing screen pattern has an isolation region between an N region and a P region, and isolation insulation between the N region and the P region is naturally formed when the graphene conductive film is printed, thereby eliminating the process of etching an opening for the third time on the back.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a back-contact solar cell and a preparation method thereof, and a cell assembly. Background Art

[0002] At present, in the existing back-contact heterojunction solar cell process, a transparent conductive film layer is generally deposited on the back of the silicon wafer. The transparent conductive film layer is generally an indium oxide-based film doped with tin / tungsten / titanium / zinc. The target material of this film layer is generally expensive and there are problems of metal pollution such as tin and indium. Moreover, the preparation of the transparent conductive film layer in the back-contact heterojunction solar cell requires multiple openings, and the process is relatively cumbersome.

[0003] It should be noted that this part of the present invention only provides background technology related to the present invention and does not necessarily constitute prior art or known technology. Summary of the invention

[0004] The purpose of the present invention is to overcome the technical problems of relatively high cost and complicated preparation process of the transparent conductive film layer of the existing back contact solar cell.

[0005] In order to achieve the above objectives, in a first aspect, an embodiment of the present invention provides a method for preparing a back-contact solar cell, comprising the following steps:

[0006] S1. Provide a silicon wafer with a single-side textured and single-side polished structure;

[0007] S2, forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer;

[0008] S3, etching an opening for the first time on the back side of the silicon wafer to form a second semiconductor opening region;

[0009] S4, performing texturing and cleaning on the second semiconductor opening area on the back side and the front side of the silicon wafer;

[0010] S5, forming a second semiconductor layer on the back side of the silicon wafer;

[0011] S6, performing high temperature annealing on the silicon wafer;

[0012] S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0013] S8, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region;

[0014] S9, depositing a porous graphene conductive film layer on the back of the silicon wafer; the raw material of the graphene conductive film layer is graphene slurry, the graphene slurry contains 5%-20% by mass of graphene, the graphene slurry contains 3%-6% by mass of zinc carbonate powder additive, the mass percentage of N-methylpyrrolidone solvent is 70%-90%, and the mass percentage of dispersant is 2%-5%, the diameter of the graphene microsheets in the slurry is 1-6μm, and the thickness of the graphene conductive film layer formed by printing the graphene slurry is 2-10μm;

[0015] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0016] In a possible implementation, in step S9, depositing a porous graphene conductive film layer on the back side of the silicon wafer includes:

[0017] S901, printing graphene slurry on the back of the silicon wafer by screen printing;

[0018] S902, placing the printed silicon wafer in a constant temperature tunnel furnace for drying to form a porous graphene conductive film layer.

[0019] In a possible implementation, the mesh size of the wire mesh is 350-500 meshes, the drying temperature of the constant temperature tunnel furnace is 300-500° C., and the drying time is 30-40 minutes.

[0020] In a possible implementation, in step S901, printing the graphene slurry on the back of the silicon wafer by screen printing includes:

[0021] A screen printing screen having an isolation region for separating the N region and the P region is provided in advance;

[0022] The graphene slurry is printed on the back of the silicon wafer using the screen printing screen.

[0023] In a possible implementation, in step S2, forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer includes:

[0024] The first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, the isolation layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the N-type doped polysilicon layer is 70-120 nm, and the thickness of the isolation layer is 40-90 nm;

[0025] The tunneling silicon oxide layer, the N-type doped polysilicon layer, and the isolation layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500° C. When depositing the tunneling oxide layer, the mass flow rate of laughing gas is 8000-1200sccm, the pressure is 100-200Pa, the power supply is 3-20KW, and the time is 20-100s; when depositing the N-type doped polysilicon layer, the mass flow rate of silane is 1000-3000sccm, and the mass flow rate of phosphine is The flow rate is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 400-500Pa, the power is 5-20KW, and the time is 800-1300s; when depositing the isolation layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of nitrogen is 2000-5000sccm, the pressure is 200-300Pa, the power is 3-20KW, and the time is 300-800s.

[0026] In a possible implementation, in step S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region includes:

[0027] The first etching opening is obtained by laser or mask etching. If laser is used, the laser is ultraviolet or green laser, the pulse width is less than 10ns, and the width of the second semiconductor opening area is 200-400μm.

[0028] In a possible implementation, in step S4, texturing and cleaning the second semiconductor opening region on the back side and the front side of the silicon wafer includes:

[0029] The texturing liquid used for texturing cleaning is a mixture of potassium hydroxide or sodium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of texturing additives is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75℃-85℃;

[0030] During the front texturing process, the silicon nitride mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the silicon nitride mask layer is HF acid solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20℃-30℃, and the removal time is 60-300s.

[0031] In a possible implementation, in step S05, forming a second semiconductor layer on the back side of the silicon wafer includes:

[0032] The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, or a stack of a tunneling silicon oxide layer and a P-type doped polycrystalline silicon layer;

[0033] The second semiconductor layer comprises a tunneling silicon oxide layer and a P-type doped polysilicon layer, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the P-type doped polysilicon layer is 60-100 nm, the tunneling silicon oxide layer is sequentially deposited in a tubular polysilicon deposition furnace, the deposition temperature is 400-500° C., the mass flow rate of laughing gas during the deposition of the tunneling oxide layer is 8000-12000 sccm, the pressure is 100-200 Pa, the power is 3-20 KW, and the time is 20-100 s;

[0034] When a low-doped P-type amorphous silicon layer is formed by coating in a tubular polysilicon deposition furnace, the mass flow rate of silane is 1000-3000sccm, the mass flow rate of diborane or trimethylborane is 500-2000sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 200-800Pa, the power is 2-15KW, the time is 800-1300s, and the effective doping amount is 1e18-9e19cm -3 .

[0035] In a second aspect, an embodiment of the present invention further provides a back-contact solar cell, which is obtained by the preparation method described in the first aspect, and the back-contact solar cell comprises:

[0036] A silicon wafer having a front side and a back side;

[0037] A first semiconductor layer and an isolation layer are sequentially stacked on the back of the silicon wafer, the first semiconductor layer and the isolation layer are separated by a plurality of second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer;

[0038] A first semiconductor opening region is provided between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer, and the first semiconductor opening region and the surface of the second semiconductor layer around the first semiconductor opening region are covered with a porous graphene conductive film layer; the porosity of the graphene conductive film layer is 10%-40%;

[0039] The metal electrode is arranged on the graphene conductive film layer located in the first semiconductor opening area; a passivation layer and an anti-reflection layer are arranged in sequence on the front side of the silicon wafer.

[0040] In a third aspect, an embodiment of the present invention further provides a battery assembly, which includes the back-contact solar cell as described in the second aspect.

[0041] The embodiments of the present invention have at least the following technical effects:

[0042] The present invention uses the above technical scheme to replace the original transparent conductive film such as ITO film with a porous graphene composite film; the graphene conductive film has good conductivity and is applied in the field of batteries, which is beneficial to improving the conductivity of N and P regions, reducing contact resistance, and improving FF and battery performance; because the graphene composite film is porous, long-wavelength light enters the porous film layer and is reflected multiple times by the pore structure, which is beneficial to the absorption of the long-wavelength light by the back film layer, thereby improving the anti-reflection effect of the back; in addition, the graphene porous conductive layer contains zinc oxide, which can further enhance the anti-reflection effect and increase the current density; in addition, a porous graphene conductive film is formed on the back of a silicon wafer by screen printing, and the screen printing screen pattern has an isolation region between the N region and the P region. When the graphene conductive film is printed, isolation and insulation between the N region and the P region are naturally formed, thereby eliminating the process of etching an opening for the third time on the back. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 A schematic structural diagram of a back-contact solar cell provided by an embodiment of the present invention;

[0045] Figure 2 A schematic flow chart of a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0046] Figure 3 A schematic diagram of a specific process of step S9 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0047] Figure 4 A process structure diagram corresponding to step S1 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0048] Figure 5 A process structure diagram corresponding to step S2 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0049] Figure 6 A process structure diagram corresponding to step S3 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0050] Figure 7 A process structure diagram corresponding to step S4 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0051] Figure 8 A process structure diagram corresponding to step S5 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0052] Fig. 9 A process structure diagram corresponding to step S7 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0053] Fig.10 A process structure diagram corresponding to step S8 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0054] Fig.11 A process structure diagram corresponding to step S9 in a method for preparing a back-contact solar cell provided by an embodiment of the present invention;

[0055] Fig.12 A process structure diagram corresponding to step S10 in a method for preparing a back-contact solar cell provided in an embodiment of the present invention.

[0056] Description of Figure Numbers.

[0057] 1-substrate; 2-first tunneling silicon oxide layer; 3-N-type doped polysilicon layer; 4-isolation layer; 5-second tunneling silicon oxide layer; 6-N-type doped polysilicon layer; 7-passivation layer; 8-anti-reflection layer; 9-graphene conductive film layer; 10-metal electrode. DETAILED DESCRIPTION

[0058] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] Those skilled in the art will understand that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art in the field to which the present invention belongs. It should also be understood that terms such as those defined in common dictionaries should be understood to have meanings consistent with the meanings in the context of the prior art, and will not be interpreted with idealized or overly formal meanings unless specifically defined as here.

[0060] Those skilled in the art will appreciate that, unless otherwise stated, the singular forms "a", "an", "" and "the" used herein may also include plural forms. It should be further understood that the term "comprising" used in the specification of the present invention refers to the presence of features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The term "and / or" used herein includes all or any unit and all combinations of one or more associated listed items.

[0061] The first aspect is combining Figure 1 and Figure 2 The present invention provides a method for preparing a back-contact solar cell, comprising the following steps:

[0062] S1. Provide a silicon wafer with a single-side textured and single-side polished structure, such as Figure 4 shown.

[0063] S2. Forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer.

[0064] Specifically, Figure 5 As shown, the first semiconductor layer includes a tunneling silicon oxide layer and an N-type doped polysilicon layer, the isolation layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, the thickness of the tunneling silicon oxide layer is 1-2nm, the thickness of the N-type doped polysilicon layer is 70-120nm, and the thickness of the isolation layer is 40-90nm. The above-mentioned suitable thicknesses of silicon oxide, polysilicon and isolation layer are conducive to taking into account both passivation and conductive properties, and are conducive to improving the conversion efficiency of the battery.

[0065] The tunneling silicon oxide layer 2, the N-type doped polysilicon layer 3, and the isolation layer 4 are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500°C; when depositing the tunneling oxide layer, the mass flow rate of laughing gas is 8000-1200sccm, the pressure is 100-200Pa, the power supply is 3-20KW, and the time is 20-100s; when depositing the N-type doped polysilicon layer 3, the mass flow rate of silane is 1000-3000sccm, and the mass flow rate of phosphine is The flow rate is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 400-500Pa, the power is 5-20KW, and the time is 800-1300s; when depositing the isolation layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of nitrogen is 2000-5000sccm, the pressure is 200-300Pa, the power is 3-20KW, and the time is 300-800s.

[0066] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region.

[0067] Specifically, Figure 6 As shown, the first etching opening is obtained by laser or mask etching. If laser is used, the laser is ultraviolet or green laser, the pulse width is less than 10ns, and the width of the second semiconductor opening area W2 is 200-400μm.

[0068] S4, performing texturing and cleaning on the second semiconductor opening area on the back side and the front side of the silicon wafer.

[0069] Alternatively, if Figure 7 As shown, in step S4, the second semiconductor opening area on the back side of the silicon wafer and the front side are subjected to texturing and cleaning, including:

[0070] The texturing liquid used for texturing cleaning is a mixture of potassium hydroxide or sodium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of texturing additives is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75℃-85℃.

[0071] During the front texturing process, the silicon nitride mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the silicon nitride mask layer is HF acid solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20℃-30℃, and the removal time is 60-300s.

[0072] S5. Forming a second semiconductor layer on the back side of the silicon wafer.

[0073] Specifically, Figure 8 As shown, the second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, or a stack of a tunneling silicon oxide layer and a P-type doped polycrystalline silicon layer.

[0074] The second semiconductor layer comprises a tunneling silicon oxide layer and a P-type doped polysilicon layer, the thickness of the tunneling silicon oxide layer is 1-2nm, the thickness of the P-type doped polysilicon layer is 60-100nm, the tunneling silicon oxide layer is sequentially deposited in a tubular polysilicon deposition furnace, the deposition temperature is 400-500°C, the mass flow rate of nitrous oxide when depositing the tunneling oxide layer is 8000-12000sccm, the pressure is 100-200Pa, the power supply is 3-20KW, and the time is 20-100s. By setting appropriate parameters, the passivation performance is better, the conductivity is better, and it is more conducive to improving the conversion efficiency of the battery.

[0075] When a low-doped P-type amorphous silicon layer is formed by coating in a tubular polysilicon deposition furnace, the mass flow rate of silane is 1000-3000sccm, the mass flow rate of diborane or trimethylborane is 500-2000sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 200-800Pa, the power is 2-15KW, the time is 800-1300s, and the effective doping amount is 1e18-9e19cm -3 .

[0076] S6. Performing high temperature annealing on the silicon wafer.

[0077] Optionally, high temperature annealing requires the introduction of nitrogen and oxygen, the mass flow rate of nitrogen is 5000-15000sccm, the mass flow rate of oxygen is 3000-10000sccm, the annealing temperature is 850-950°C, the pressure is 1000-10000Pa, and the time is 40-60 minutes. After high temperature annealing, the P-type amorphous silicon layer forms a P-type polycrystalline silicon layer.

[0078] S7. Form a passivation layer and an anti-reflection layer on the front side of the silicon wafer.

[0079] Alternatively, if Fig. 9 As shown, the passivation layer 7 can be one or a combination of an amorphous silicon passivation layer, a silicon oxide passivation layer and an aluminum oxide passivation layer. Preferably, the passivation layer 7 is a combination of a silicon oxide and an aluminum oxide passivation layer, the thickness of the silicon oxide is 1-2nm, and the aluminum oxide is 3-4nm. The above setting of appropriate silicon oxide and aluminum oxide thickness is conducive to ensuring the front passivation effect while improving the optical performance.

[0080] The anti-reflection layer can be one or a combination of silicon nitride, aluminum oxide and silicon oxide, preferably a combination of silicon nitride and silicon oxide, the thickness of silicon nitride is 50-100 nm, and the thickness of silicon oxide is 80-150 nm.

[0081] S8. Etch an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region.

[0082] Alternatively, if Fig.10 As shown, the second etching opening is performed by laser, the laser may be ultraviolet or green laser, the pulse width is less than 10ns, and the width of the formed first semiconductor opening region W1 is 100-250μm.

[0083] S9. A porous graphene conductive film layer is deposited on the back of a silicon wafer; the raw material of the graphene conductive film layer is graphene slurry, the graphene slurry contains 5%-20% by mass of graphene microflakes, 3%-6% by mass of zinc carbonate powder additive, 70%-90% by mass of N-methylpyrrolidone solvent, and 2%-5% by mass of dispersant, the diameter of the graphene microflakes in the slurry is 1-6μm, and the thickness of the graphene conductive film layer formed by printing the graphite slurry is 2-10μm.

[0084] In this embodiment, adding suitable graphene microsheets and zinc carbonate powder to the graphene slurry is beneficial to improving the conductivity of the graphene conductive layer and the metal electrode. At the same time, during the baking process of the graphene slurry, zinc carbonate is decomposed by heat to release carbon dioxide gas, thereby forming a porous graphene composite film in the film layer. The porous composite film is beneficial to improving the reflection of the long-wave band on the back side. At the same time, the zinc oxide powder decomposed and retained in the composite film has a wide bandgap, high exciton binding energy, and less parasitic absorption, which is beneficial to further improve the anti-reflection effect on the back side.

[0085] Alternatively, if Fig.11 and Figure 3 As shown, a porous graphene conductive film layer is deposited on the back of the silicon wafer, including:

[0086] S901, printing graphene slurry on the back of the silicon wafer by screen printing.

[0087] Specifically, in step S901, the graphene slurry is screen-printed on the back of the silicon wafer, including:

[0088] A screen printing screen having an isolation region for separating the N region and the P region is provided in advance;

[0089] The graphene slurry is printed on the back of the silicon wafer using a screen printing screen.

[0090] In this embodiment, the silk screen printing screen pattern used has an isolation area between the N area and the P area. When printing the graphene conductive film, an isolation insulation W3 between the N area and the P area is naturally formed, thereby eliminating the process of etching an opening for the third time on the back of the silicon wafer. Compared with the existing sputtering process of the ITO conductive film, it is beneficial to save production costs.

[0091] S902, placing the printed silicon wafer in a constant temperature tunnel furnace for drying to form a porous graphene conductive film layer.

[0092] Optionally, the mesh size of the wire mesh is 350-500 meshes, the drying temperature of the constant temperature tunnel furnace is 300-500° C., and the drying time is 30-40 minutes.

[0093] The selection of a suitable screen mesh number during the above printing, and the appropriate drying temperature and time are conducive to the graphene slurry forming a uniform film layer on the surface of the silicon wafer, thereby improving the overall conductive performance.

[0094] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0095] Alternatively, if Fig.12 As shown, metal electrodes are formed on the surfaces of the first semiconductor opening region W1 and the second semiconductor opening region W2 on the back side of the silicon wafer 1 by using screen printing technology.

[0096] In the second aspect, an embodiment of the present invention provides a back-contact solar cell, which is obtained using the preparation method in the aforementioned embodiment. The back-contact solar cell includes: a silicon wafer, a first semiconductor layer, an isolation layer, a second semiconductor layer, a graphene conductive film layer, a metal electrode, a passivation layer and an anti-reflection layer.

[0097] Specifically, the silicon wafer has a front side and a back side, a first semiconductor layer and an isolation layer are sequentially stacked on the back side of the silicon wafer, the first semiconductor layer and the isolation layer are separated by a plurality of second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer.

[0098] A first semiconductor opening area is provided between adjacent second semiconductor opening areas, the first semiconductor opening area separates the second semiconductor layer, and the first semiconductor opening area and the surface of the second semiconductor layer around the first semiconductor opening area are covered with a porous graphene conductive film layer; the porosity of the graphene conductive film layer is 10%-40%, and the graphene conductive film layer contains a zinc carbonate powder additive.

[0099] The metal electrode is arranged on the graphene conductive film layer located in the first semiconductor opening area; the front side of the silicon wafer is sequentially provided with a passivation layer and an anti-reflection layer.

[0100] In a third aspect, an embodiment of the present invention provides a battery assembly, including the back-contact solar cell in the aforementioned embodiments.

[0101] The embodiments of the present invention are described in detail below, which are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0102] Example 1

[0103] A back contact solar cell having a structure as Figure 1 As shown, it includes: a silicon wafer, a first semiconductor layer, an isolation layer, a second semiconductor layer, a graphene conductive film layer, a metal electrode, a passivation layer and an anti-reflection layer. The porosity of the graphene conductive film layer is 25%.

[0104] A method for preparing a back contact solar cell, the process diagram of which is shown in FIG. Figure 2 As shown, the following steps are included:

[0105] S1. Provide a silicon wafer with a single-side textured and single-side polished structure;

[0106] S2, forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer;

[0107] S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region;

[0108] S4, performing texturing and cleaning on the second semiconductor opening area on the back side and the front side of the silicon wafer;

[0109] S5, forming a second semiconductor layer on the back side of the silicon wafer;

[0110] S6, performing high temperature annealing on the silicon wafer;

[0111] S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer;

[0112] S8, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region;

[0113] S9. A porous graphene conductive film layer is deposited on the back of the silicon wafer. The raw material of the graphene conductive film layer is graphene slurry. The graphene slurry contains 15% graphene microflakes, 4% zinc carbonate powder additive, 78.5% NMP (N-methylpyrrolidone) solvent, and 2.5% dispersant. The diameter of the graphene microflakes in the slurry is 1-3μm. The thickness of the graphene conductive film layer formed by printing the graphite slurry is 6μm.

[0114] S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively.

[0115] Example 2

[0116] Referring to the back contact solar cell structure of Example 1, the difference is that the graphene slurry contains 10% graphene and the graphene slurry contains 5% zinc carbonate powder additive.

[0117] Example 3

[0118] Refer to the back contact solar cell structure of Example 1, except that the thickness of the graphene conductive film layer is 4 μm.

[0119] Example 4

[0120] Refer to the back contact solar cell structure of Example 1, except that the porosity of the graphene conductive film layer is 20%.

[0121] Comparative Example 1

[0122] Refer to the back contact solar cell of Example 1, except that an ITO film layer is used instead of a graphene conductive film layer.

[0123] Comparative Example 2

[0124] The method for preparing a back-contact solar cell is described with reference to Example 1, except that the content of graphene in the graphene slurry is 3%.

[0125] Comparative Example 3

[0126] The method for preparing a back-contact solar cell is described with reference to Example 1, except that the graphene slurry does not contain zinc carbonate powder additive.

[0127] Comparative Example 4

[0128] The method for preparing a back-contact solar cell is described with reference to Example 1, except that the content of the zinc carbonate powder additive in the graphene slurry is 10%.

[0129] Comparative Example 5

[0130] Refer to the back contact solar cell of Example 1, except that the thickness of the graphene conductive film layer is 0.5 μm.

[0131] Comparative Example 6

[0132] Refer to the back contact solar cell structure of Example 1, except that the porosity of the graphene conductive film layer is 7%.

[0133] The performance data of the back contact solar cell obtained in the above examples and comparative examples are shown in the following table:

[0134] Table 1 Comparison of performance data of back contact solar cells in different embodiments

[0135]

[0136] It can be seen from the above results that, compared with the comparative example, the embodiment scheme of the present invention can effectively ensure the battery conversion efficiency and help reduce the production cost of the battery. Further, according to Example 1 and Examples 2-4, it can be seen that the preferred preparation scheme of the graphene conductive film layer of the present invention can further maintain the conversion efficiency of the battery at a high level, which is more conducive to further improving efficiency and reducing costs, and improving the market competitiveness of the product. It should be noted that the specific values ​​in the above table are relative values ​​after normalization, and do not represent the actual parameter values, so they are without units.

[0137] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a back-contact solar cell, characterized in that: The following steps are involved: S1. Provide a silicon wafer with a single-side textured and single-side polished structure; S2, forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer; S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region; S4, performing texturing and cleaning on the second semiconductor opening area on the back side and the front side of the silicon wafer; S5, forming a second semiconductor layer on the back side of the silicon wafer; S6, performing high temperature annealing on the silicon wafer; S7, forming a passivation layer and an anti-reflection layer on the front side of the silicon wafer; S8, etching an opening on the back side of the silicon wafer for the second time to form a first semiconductor opening region; S9, depositing a porous graphene conductive film layer on the back of the silicon wafer; the raw material of the graphene conductive film layer is graphene slurry, the graphene slurry contains 5%-20% by mass of graphene, the graphene slurry contains 3%-6% by mass of zinc carbonate powder additive, the mass percentage of N-methylpyrrolidone solvent is 70%-90%, and the mass percentage of dispersant is 2%-5%, the diameter of the graphene microsheets in the slurry is 1-6μm, and the thickness of the graphene conductive film layer formed by printing the graphene slurry is 2-10μm; In step S9, depositing a porous graphene conductive film layer on the back side of the silicon wafer includes: S901, printing graphene slurry on the back of the silicon wafer by screen printing; In step S901, the graphene slurry is screen-printed on the back of the silicon wafer, including: A screen printing screen having an isolation region for separating the N region and the P region is provided in advance; Printing graphene slurry on the back of the silicon wafer using the screen printing screen; S902, placing the printed silicon wafer in a constant temperature tunnel furnace for drying to form a porous graphene conductive film layer; S10, forming metal electrodes at the first semiconductor opening and the second semiconductor opening on the back side of the silicon wafer respectively; During the baking process of the graphene slurry, zinc carbonate is decomposed by heat to release carbon dioxide gas, thereby forming a porous graphene composite film in the film layer. The porous graphene composite film is beneficial to improving the reflection of the long-wave band on the back side, and at the same time, the zinc oxide powder generated by the thermal decomposition of zinc carbonate is retained in the graphene composite film.

2. The method for preparing a back-contact solar cell according to claim 1, characterized in that: The mesh number of the wire mesh is 350-500 meshes, the drying temperature of the constant temperature tunnel furnace is 300-500° C., and the drying time is 30-40 minutes.

3. The method for preparing a back-contact solar cell according to claim 1, characterized in that: In step S2, forming a first semiconductor layer and an isolation layer on the back side of the silicon wafer includes: The first semiconductor layer comprises a tunneling silicon oxide layer and an N-type doped polysilicon layer, the isolation layer is at least one of silicon nitride, silicon oxide, silicon oxynitride or nitrogen-containing polysilicon, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the N-type doped polysilicon layer is 70-120 nm, and the thickness of the isolation layer is 40-90 nm; The tunneling silicon oxide layer, the N-type doped polysilicon layer, and the isolation layer are sequentially deposited and annealed at high temperature using a tubular polysilicon deposition furnace, and the deposition temperature is 400-500° C. When depositing the tunneling oxide layer, the mass flow rate of laughing gas is 8000-1200sccm, the pressure is 100-200Pa, the power supply is 3-20KW, and the time is 20-100s; when depositing the N-type doped polysilicon layer, the mass flow rate of silane is 1000-3000sccm, and the mass flow rate of phosphine is The flow rate is 1000-2500sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 400-500Pa, the power is 5-20KW, and the time is 800-1300s; when depositing the isolation layer, the mass flow rate of silane is 1000-2000sccm, the mass flow rate of nitrogen is 2000-5000sccm, the pressure is 200-300Pa, the power is 3-20KW, and the time is 300-800s.

4. The method for preparing a back-contact solar cell according to claim 1, characterized in that: In step S3, etching an opening on the back side of the silicon wafer for the first time to form a second semiconductor opening region comprises: The first etching opening is obtained by laser or mask etching. If laser is used, the laser is ultraviolet or green laser, the pulse width is less than 10ns, and the width of the second semiconductor opening area is 200-400μm.

5. The method for preparing a back-contact solar cell according to claim 1, characterized in that: In step S4, the texturing and cleaning of the second semiconductor opening area on the back side and the front side of the silicon wafer includes: The texturing liquid used for texturing cleaning is a mixture of potassium hydroxide or sodium hydroxide, texturing additives and water, wherein the mass percentage of potassium hydroxide or sodium hydroxide is 1%-5%, the mass percentage of texturing additives is 0.5%-1%, the texturing time is 8-30 minutes, and the texturing temperature is 75℃-85℃; During the front texturing process, the silicon nitride mask layer on the back of the silicon wafer is also removed through the final cleaning solution. The solution used to remove the silicon nitride mask layer is HF acid solution, the mass percentage of HF acid is 0.5%-5%, the mass percentage of deionized water is 95%-99.5%, the processing temperature is 20℃-30℃, and the removal time is 60-300s.

6. The method for preparing a back-contact solar cell according to claim 1, characterized in that: In step S05, forming a second semiconductor layer on the back side of the silicon wafer includes: The second semiconductor layer is a stack of an intrinsic hydrogenated amorphous silicon layer and a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer, or a stack of a tunneling silicon oxide layer and a P-type doped polycrystalline silicon layer; The second semiconductor layer comprises a tunneling silicon oxide layer and a P-type doped polysilicon layer, the thickness of the tunneling silicon oxide layer is 1-2 nm, the thickness of the P-type doped polysilicon layer is 60-100 nm, the tunneling silicon oxide layer is sequentially deposited in a tubular polysilicon deposition furnace, the deposition temperature is 400-500° C., the mass flow rate of laughing gas during the deposition of the tunneling oxide layer is 8000-12000 sccm, the pressure is 100-200 Pa, the power is 3-20 KW, and the time is 20-100 s; When a low-doped P-type amorphous silicon layer is formed by coating in a tubular polysilicon deposition furnace, the mass flow rate of silane is 1000-3000sccm, the mass flow rate of diborane or trimethylborane is 500-2000sccm, the mass flow rate of hydrogen is 7000-9000sccm, the pressure is 200-800Pa, the power is 2-15KW, the time is 800-1300s, and the effective doping amount is 1e18-9e19cm -3 .

7. A back contact solar cell, characterized in that: The back contact solar cell is obtained by the preparation method according to any one of claims 1 to 6, comprising: A silicon wafer having a front side and a back side; A first semiconductor layer and an isolation layer are sequentially stacked on the back of the silicon wafer, the first semiconductor layer and the isolation layer are separated by a plurality of second semiconductor opening regions, and the second semiconductor opening regions and the surface of the first semiconductor layer around the second semiconductor opening regions are covered with the second semiconductor layer; A first semiconductor opening region is provided between adjacent second semiconductor opening regions, the first semiconductor opening region separates the second semiconductor layer, and the first semiconductor opening region and the surface of the second semiconductor layer around the first semiconductor opening region are covered with a porous graphene conductive film layer; the porosity of the graphene conductive film layer is 10%-40%; The metal electrode is arranged on the graphene conductive film layer located in the first semiconductor opening area; a passivation layer and an anti-reflection layer are arranged in sequence on the front side of the silicon wafer.

8. A battery assembly, characterized in that: It comprises the back contact solar cell as claimed in claim 7.

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