Delay measurement circuit structure and measurement method

Abstract

Provided are a delay measurement circuit structure and a measurement method. The circuit comprises: a delay circuit, a first signal at an input end, which is delayed by at least two groups of delay circuit units and finally outputs a second signal through a first AND gate; a delay output signal detection circuit, which combines an enable signal consistent with the input end of the delay circuit with the first signal to control the on-off of an N-type transistor and obtain at least one output signal detection current, and obtains a third signal according to the enable signal and the output of the delay circuit unit, wherein at least a plurality of output signal detection currents and the delay time are obtained by adjusting the gate voltage of the N-type transistor in the delay circuit unit and / or the voltage of the capacitor of the P-type transistor, and finally the internal delay time of the chip is obtained by measuring the current value, so that after the chip is plated, the internal delay of the chip can be adjusted without repeatedly re-plate-making to change the number of redundant delays.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip testing, and in particular to a delay measurement circuit structure and a delay measurement method for a semiconductor chip delay unit. Background Art

[0002] A large number of delay units are used in chip standard parts. These delay units and delay devices are used to achieve a preset time delay between various devices and components in the integrated circuit. According to the different requirements for the length of the delay, the delay units used in the chip can be roughly divided into long delay units and short delay units. The delay of long and short delay units is usually measured in nanoseconds.

[0003] In some known chip layout design schemes, in addition to the long and short delay units and delay devices required for design, some redundant delay units will also be designed. Similarly, the redundant delay units also include redundant long delay devices and redundant short delay devices. Part of the purpose of designing these redundant delay units is that the components that make up the integrated circuit are inconsistent due to different production batches and / or are affected by process drift, which will cause a deviation between the actual delay time of the prepared chip and the preset delay time. To overcome this problem, the existing practice is to obtain the chip delay by deduction and speculation based on the actual output of the chip after power-on, and then redesign the chip based on the delay. This redesign is carried out by increasing or reducing the number of redundant delay units and delay devices, in order to make the actual delay of the chip closer to the designed delay. In other words, the redundant delay units and delay devices designed in the existing scheme are complementary solutions for adjusting the delay of the chip after it is manufactured. However, the actual delay of the chip cannot be directly measured and obtained, and the limitations of the existing chip production process are important reasons why redundant delay units and delay devices must be included in the existing design.

[0004] In order to arrange enough delay units, a larger layout area is usually required to meet the needs of chip delay adjustment. The redundant long delay unit is complex to design and will occupy a larger layout area than the short delay unit. Between the two, the redundant long delay unit is more affected by process drift.

[0005] It should be further pointed out that an issue that is equally important as the limited chip design area is that this chip design method of first preparing, then measuring and finally adjusting is also restricted by the accuracy of the delay measurement itself. The existing measurement method is an indirect deduction and speculation method as mentioned above. Therefore, the delay deviation determined by this deduction and adjustment may also have errors. This does not take into account the redundant delay units and the delay device itself, which may also be affected by production batches and process drifts, resulting in differences in delay time from the design value.

[0006] The above reasons make it difficult to improve chip performance. This post-production measurement and adjustment process also increases the process production cost because the chip design layout needs to be repeatedly adjusted and redesigned.

[0007] In view of this, an improvement direction that is easier to think of is that since re-plate making is still required for measurement after preparation, it is reasonable to consider completing the delay measurement step before chip plate making. However, the reason why this cannot be done is that the chip delays before plate making are all preset theoretical values, and the actual delay values ​​between devices can only be derived after the chip is prepared. In other words, the delay deviation is generated after preparation and cannot be obtained before chip preparation. Then the expected reasonable improvement method is to try to adjust the delay after the chip is prepared, which is an adjustment method that does not require re-plate making and measurement. Summary of the invention

[0008] In view of this, the present invention provides a delay measurement circuit structure and a measurement method to solve at least one of the above problems.

[0009] In order to solve the above technical problems, the first aspect of the present invention is to provide a delay measurement circuit structure, which is used to measure the delay time of the delay device inside the chip after the chip plate making is completed, wherein the delay measurement circuit structure includes: a delay device circuit, which is configured to output a first signal at the input end through a delay of at least two groups of delay circuit units, and finally output a second signal through a first AND gate, wherein the delay circuit unit is a delay adjustment circuit composed of a plurality of first N-type transistors connected in parallel, or a P-type transistor capacitor connected in parallel; a delay device output signal detection circuit, which is a detection circuit. The detection circuit is configured to control the on and off of a second N-type transistor by combining an enable signal consistent with the input end of the delay circuit and the first signal, and obtain at least one output signal detection current, and obtain a third signal according to the enable signal and the output of the delay circuit unit, and obtain the delay time of the delay circuit according to the rising edges of the first signal and the third signal, wherein at least a plurality of the output signal detection currents and the delay times are obtained by adjusting the gate voltage of the N-type transistor in the delay circuit unit and / or the voltage of the capacitor of the P-type transistor.

[0010] As a preferred scheme of a preferred embodiment of the first aspect of the present invention, the delay circuit unit includes: a first delay circuit unit formed by connecting a plurality of first N-type transistors in parallel, and the gate of each of the N-type transistors is connected to a delay time control bias voltage; a second delay circuit unit formed by connecting a plurality of P-type transistor capacitors in parallel, and each of the P-type transistor capacitors is connected to a delay time control voltage, and the delay circuit outputs a first comparison signal after being delayed by the first delay circuit unit, and the first comparison signal outputs a second comparison signal after being delayed by the second delay circuit unit, wherein the delay output signal detection circuit obtains a fourth signal based on the comparison of the first comparison signal and the second comparison signal, and the third signal is the comparison result of the fourth signal and the enable signal.

[0011] As a further preferred embodiment of this aspect of the present invention, the input end of the delay circuit also includes a multiplexer and a P-type transistor, the multiplexer is configured to be enabled by the enable signal and select from at least two input signals to turn on the P-type transistor, the P-type transistor is configured to be turned on by the output drive of the multiplexer, take the delay circuit drive power supply as input, and output the first signal.

[0012] As a further embodiment of the present invention, the delay device output signal detection circuit includes: a first NAND gate, which compares and outputs the fourth signal based on the first comparison signal and the second comparison signal; a second NAND gate, which compares and outputs the third signal based on the fourth signal and the enable signal; and a second AND gate, which compares and outputs the fifth signal based on the enable signal and at least one input signal of the multiplexer, and the signal turns on the second N-type transistor to obtain the output signal detection current.

[0013] As a further preferred embodiment of this aspect of the present invention, the gate of the second N-type transistor is connected to the output of the second AND gate, and the drain thereof is connected to the second comparison signal, and when the second N-type transistor is turned on under the drive of the fifth signal, its source outputs the output signal detection current.

[0014] The second aspect of the present invention is to provide a delay measurement method, which is used to measure the delay time of a delay device inside a chip after chip plate making is completed, wherein the method includes the following steps: a step of configuring a delay measurement circuit structure as described in the first aspect of the present invention; a step of adjusting the first delay circuit unit and / or the second delay circuit unit to obtain multiple groups of output signal detection currents and delay times; a step of obtaining a current-time ratio of at least one output signal detection current and delay time based on the multiple groups of output signal detection currents and delay times; a step of obtaining an expected output current based on a preset fixed delay time and the current-time ratio; a step of adjusting the first delay circuit unit and / or the second delay circuit unit, and measuring the value of the output signal detection current until the output signal detection current reaches the expected output current.

[0015] As a more preferred embodiment of the second invention of the present invention, the step of adjusting the first delay circuit unit and / or the second delay circuit unit is specifically: changing the size of at least one delay time control bias voltage in the first delay circuit unit, and / or changing the size of at least one delay time control voltage in the second delay circuit unit.

[0016] Compared with the prior art, the preferred embodiment of the present invention measures the current value to obtain the internal delay time of the chip, so that after the chip is plated, the internal delay of the chip can be adjusted without repeatedly re-plate-making to change the number of redundant delay devices. While significantly simplifying the chip delay measurement process, it greatly reduces the measurement cost and improves the configuration accuracy of the delay time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram schematically showing an equivalent circuit structure of a long-delay delay unit;

[0018] Figure 2 is a waveform diagram, schematically showing Figure 1 The waveforms of the input and output signals of the delay device in the structure shown;

[0019] Figure 3 FIG. 2 is a schematic diagram showing the states corresponding to different delay times when different RC time constants are combined.

[0020] Figure 4 is a schematic diagram schematically showing an equivalent structure of a delay detection circuit in a preferred embodiment of the present invention;

[0021] Figure 5 is a waveform diagram, schematically showing Figure 4 The waveforms of the input signal and output signal of the delay device in the preferred embodiment are shown. DETAILED DESCRIPTION

[0022] See also Figure 1 , Figure 1 A long-time delay unit is shown. The long-time delay unit 100 shown includes a delay circuit array, which is composed of two groups of delay circuit units, which are defined as a first delay circuit unit 101 and a second delay circuit unit 102 for convenience of description. The long-time delay unit 100 is driven by a delay input signal and a delay power supply, and finally outputs a delay output signal through a first AND gate 103 through the adjustment of the first delay circuit unit 101 and the second delay circuit unit 102. For example, Figure 1 For the long delay unit 100 shown in FIG. 1 , the time difference between the delay input signal and the delay output signal is the delay that the delay unit can achieve. Figure 1 The delay unit structure shown realizes the delay between two devices.

[0023] The first delay circuit unit 101 is composed of n N-type transistors connected in parallel, wherein the gate of each N-type transistor is connected to a delay time control bias voltage, and the drains of the N-type transistors in the first delay circuit unit 101 are connected in parallel to each other and are connected in series to a first load resistor R1. Under this structure, the bias current output by the first delay circuit unit can be adjusted by turning on and / or off at least one delay time control bias voltage and adjusting the resistance value of the load resistor R1.

[0024] Let's look at the second delay circuit unit 102. In the second delay circuit unit 102 composed of n P-type transistor capacitors connected in parallel, each P-type transistor capacitor is connected to a delay time control voltage, and the load capacitance of the P-type transistor capacitor can be changed by controlling at least one delay time control voltage.

[0025] In the first delay circuit unit 101, controlling the size of the redirected bias circuit can also be considered as equivalent to controlling the current value flowing through the load circuit R1. In the second delay circuit unit 102, adjusting the number of startup particles (capacitor quantity) of the load capacitor, that is, controlling the numerical value of the load capacitor. Obviously, the size of each N-type transistor in the first delay circuit unit 101 and the size of each P-type transistor capacitor in the second delay circuit unit 102 can be the same or different, because any such arrangement does not affect the adjustment method of the delay circuit unit. On the basis of the first delay circuit unit 101 and the second delay circuit unit 102, the delay time of the long delay unit is derived from the RC time constant (T=RC), that is, the time constant is the product of capacitance and resistance. Therefore, as mentioned above, in the long delay unit, the resistance value in the first delay circuit unit is adjusted, and / or the capacitance value in the second delay circuit unit is adjusted, so that the output of the first AND gate 103 can be changed, thereby generating a delay time corresponding to the RC time constant value in the delay unit. According to the above conclusion, adjusting the resistance value in the first delay circuit unit is to adjust the bias current in the first delay circuit unit, and adjusting the capacitance value in the second delay circuit unit is to adjust the number of startup particles of the load capacitor therein. Continue to refer to Figure 1 , the first delay circuit unit 101 is connected to one input of the first AND gate 103, and the other input of the first AND gate 103 is connected to the second delay circuit unit 102. Let's look at the input and output of the delay circuit array. The input of the circuit array is connected to the aforementioned load resistor R1, and specifically includes a P-type transistor 104 and a driving power supply 105 of the long-time delay unit 100. The delay input signal is connected to the gate of the P-type transistor 104. In this way, the switch device function is realized through the delay input signal, and the P-type transistor 104 is turned on and off. At the output of the circuit array, the first delay circuit unit 101 and the second delay circuit unit 102 are compared through the first AND gate 103. The influence of the first delay circuit unit 101 and the second delay circuit unit 102 on the circuit can be regarded as changing the current size of each branch. Therefore, when the two inputs of the first AND gate 103 are both high level, the output signal of the delay device is also high level.

[0026] As mentioned above, in Figure 1Based on the structure shown, the delay time control bias and delay time control voltage in the two delay circuit units are independently controlled, and different bias currents, load resistor values, and load capacitors are combined to provide delay units with different delay times. That is, through the aforementioned control and adjustment methods, the output signal of the delay device output by the first AND gate can be changed. It should be understood that due to the time difference between the delay device input signal and the delay device output signal, that is, the delay that can be achieved by the delay unit, then, by changing the delay device output signal output by the first AND gate, the delay time of the delay unit can be changed without changing the input signal. Figure 2 is a schematic diagram, schematically showing the input signal and output signal of the delay device, Figure 2 The double-headed arrow in the figure defines the time interval from a high level of the delay device input signal to a high level of the delay device output signal, and this time interval is also the fixed delay that can be achieved by the delay unit shown. Figure 3 The schematic diagram shows the states of different delay times when different RC time constants are combined. The double-headed arrows in the figure are Figure 2 The two ends of the arrow respectively define the delay time corresponding to different RC time constants (combinations 1 to N). In other words, when the RC time constant changes (the load resistance or capacitance changes), the delay time will also change accordingly.

[0027] Due to the limitations of the time detection method itself, it is difficult to obtain accurate delay time by adjusting the chip after plate making. In addition, the delay device itself will be affected by process drift, resulting in inconsistency between actual delay and calibrated delay. Therefore, the iterative process of improving chip device delay not only consumes a lot of time and re-plate making costs, but more importantly, it is impossible to accurately measure and define the actual delay of the chip.

[0028] The purpose of the improvement of the preferred embodiment of the present invention is to provide a method for obtaining the actual delay time data of the long delay unit in the chip without repeated re-plating, and to adjust the chip timing and improve the chip performance by adjusting the long delay unit. However, after the plate is made, since the direct measurement or derivation measurement method cannot be accurate due to the limitation of the detection means, if the length of the interval time is converted into other quantities that are easier to obtain and have higher detection accuracy (for example, not affected by process drift), the technical purpose of obtaining the actual delay without re-plating can be achieved.

[0029] Embodiments of the present invention will be described below with reference to the accompanying drawings. It will be appreciated by those skilled in the art that the described embodiments may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the drawings and description are illustrative in nature and are not intended to limit the scope of protection of the claims. In addition, in this specification, the drawings are not drawn to scale and the same reference numerals represent the same parts.

[0030] It should be noted that the expressions “first” and “second” used in the embodiments of the present invention are intended to distinguish two non-identical entities with the same name or non-identical parameters. It can be seen that “first” and “second” are only for the convenience of expression and should not be understood as limitations on the embodiments of the invention. The subsequent embodiments will not explain this one by one.

[0031] exist Figure 1 and Figure 2 Based on the existing topology shown, the preferred embodiment of the present invention is further improved to form the following Figure 4 The equivalent circuit structure shown in Figure 1 is shown in Figure 1. Figure 4 ,and Figure 1 The structure shown is different in that Figure 1 In the existing structure shown, at the position where the delay input signal is located (i.e., the input side), what is connected to the P-type transistor is no longer just a single delay input signal, but a multiplexer is configured at the gate of the P-type transistor. The multiplexer is a combinational circuit that uses a set of selection lines to select an input line from multiple input lines and guides the input binary signal to the output line. As shown in the figure, in this preferred embodiment, a duplexer 106 is selected, and in addition to configuring a delay input signal at its input end, it is also connected to a detection input signal and enabled by a detection circuit enable signal. Figure 1 Another difference in the structure shown is that in Figure 1 A delay device output signal detection circuit 200 is also provided at the position of the first AND gate 103 (ie, the output side) in the conventional structure shown.

[0032] Continue to view Figure 3 The delay device output signal detection circuit includes a first NAND gate 201, a second NAND gate 202 and a second AND gate 203. Figure 1Among the two inputs of the first AND gate 103, one is the current after voltage division by the first delay circuit unit 101, and the other is the current after voltage division by the first delay circuit unit 101 and the second delay circuit unit 102. For the convenience of explanation, the output after voltage division by the first delay circuit unit 101 is defined as the first comparison signal, and the output after voltage division by the first and second delay circuit units 102 is defined as the second comparison signal. The two inputs of the first NAND gate 201 are the first comparison signal and the second comparison signal, and output a delay device output signal. In order to distinguish it from the output of the first AND gate 103, the output of the first AND gate 103 is defined as the first delay device output signal, and the output of the first NAND gate 201 is defined as the second delay device output signal. In actual detection, the first delay device output signal is used for internal chip control, and the second delay device output signal is used for external chip detection. Of the two inputs of the second NAND gate 202, one is the second delay output signal, and the other is an enable signal consistent with a detection circuit enable signal on the duplexer 106. The output of the second NAND gate 202 is connected to the first detection pin 204, thereby obtaining an output detection signal.

[0033] It also includes a second AND gate 203. The detection circuit enable signal on the input of the second NAND gate 202 is also connected to the second AND gate 203. The other input of the second AND gate 203 is a detection input signal consistent with the duplexer 106. The detection input signal is output by a detection input control signal through the second detection pin 205. It also includes an N-type transistor 207. The gate of the N-type transistor is the output of the second AND gate 203, the drain is the output of the second comparison signal through a second load resistor R2, and the source outputs a comparison current. The comparison current is connected to the third detection pin 206 and finally outputs the detection output current. It should be pointed out that, in the preferred embodiment of the present invention, for example, the first, second, and third detection pins do not need to be set separately. This is because, in order to meet the needs of mass production and tape-out during chip plate making, a number of detection input pins and detection output pins have been pre-designed and reserved for detection. These pins can be led out for testing the chip. Similarly, there is no need to design an additional circuit to generate the detection circuit enable signal, because the test instructions have been pre-designed inside the chip during chip manufacturing. In the preferred embodiment of the present invention, these test instructions can be used as the detection circuit enable signal.

[0034] The working process of the circuit is as follows: when the detection circuit enable signal is at a low level, the second NAND gate 202 in the detection circuit does not work, that is, the delay output signal detection circuit does not work. At the duplexer 106, the detection circuit enable signal is at a low level, and the duplexer 106 will select the delay input signal for output. In this state, the first AND gate 103 will still output the first delay output signal according to the first comparison signal and the second comparison signal, and the first NAND gate 201 will also output the second delay output signal. At the second NAND gate 202, since the detection circuit enable signal is at a low level, the second NAND gate 202 will still maintain the output high level, so that the output detection signal output by the first detection pin 204 is also at a high level. At the same time, in this state, at the second AND gate 203, since the detection circuit enable signal is at a low level, no matter whether the detection input signal is at a high level or a low level at this time, the output of the second AND gate 203 is at a low level, and then since the gate is at a low level, the N-type transistor at this position remains in the off state, the source of the N-type transistor has no current output, and the third detection pin 206 has no current output, or in other words, the detection output current is zero at this time.

[0035] At the next moment, when the detection circuit enable signal changes from a low level to a high level, compared with the previous moment: on the one hand, at the duplexer 106, its output changes from the delay input signal to the detection input signal, so that at the second NAND gate 202, according to the comparison between the second delay output signal and the detection circuit enable signal, the output of the second NAND gate 202 outputs an output detection signal through the first detection pin 204; on the other hand, when the detection circuit enable signal is at a high level, the delay output signal detection circuit is started, and the detection input control signal changes from a low level to a high level, then when the detection input signal is also at a high level, the output of the second AND gate 203 is changed, so that the N-type transistor is turned on and generates a current at its source, and the third detection pin 206 will eventually generate a detection output current.

[0036] Figure 5 2 is a waveform diagram showing that when the detection circuit enable signal changes from a low level to a high level and the delay output signal detection circuit works, the difference between the high level rising edge of the detection input control signal and the high level rising edge of the detection output signal is the actual current delay time. Further, by measuring the magnitude of the detection output current output by the third detection pin 206, the ratio of the current to the actual delay time can be obtained.

[0037] In the delay circuit array, for the first delay circuit unit 101 and the second delay circuit unit 102, the delay time control bias voltage and / or the delay time control voltage can be adjusted, for example, the gate voltage of each N-type transistor in the first delay circuit unit 101 is controlled, and for example, the delay time control voltage on each P-type transistor capacitor in the second delay circuit unit is controlled to change the magnitude of the detection output current output through the third detection pin 206. At the same time, the above operation will also affect the detection output signal finally output by the output end of the second AND gate 203, and further affect the delay time of the current array. The ratio of these detection output currents to the delay time will also change accordingly. In this way, according to the current delay circuit array, multiple delay times and detection output currents with different ratios can be formed, which can be regarded as a process to identify multiple gears with different delay times, and each gear corresponds to a set of delay time and detection output current ratios. Therefore, the adjustment of the delay time after chip plate making can be regarded as adjusting the ratio of the delay time to the detection output current to the corresponding gear. This adjustment and setting process is not composed of a single data parameter, but rather the ratio of two parameters that are synchronously affected. Moreover, compared to directly measuring the chip delay time, measuring the output current is a better solution in terms of both measurement accuracy and difficulty. Therefore, it can not only greatly reduce the impact of process drift on chip delay, but more importantly, the greatly simplified detection process can significantly reduce the cost of chip delay testing.

[0038] Correspondingly, a preferred embodiment of another aspect of the present invention is to provide a delay detection method based on the delay detection circuit structure described in the first aspect of the present invention. This method also expects to accurately measure the delay time of the delay device inside the chip after the chip platemaking is completed, without the need to re-plate and adjust the number of redundant delay devices. Unlike the prior art, in order to avoid the measurement error caused by the existing direct or indirect derivation of device delay, in the preferred embodiment of the present invention, a detection current is drawn and the magnitude of the current is detected. Since the accuracy of current detection is significantly better than the measurement of delay time, the preferred embodiment of the present invention first attempts to convert the original detection method of delay time into current detection. However, the problem that still needs to be solved is how to establish the relationship between the current size and the amount of delay time, so as to ultimately achieve the improvement of the length of the delay time by adjusting the current.

[0039] Since the current value and delay time used for detection will change when the circuit is adjusted, the relationship between the current and the delay time can be established numerically, for example, the ratio between the two. With a specific ratio between the current and the delay time in a specific circuit, the delay time of the device can be adjusted and determined by simply adjusting and observing the change in the current value.

[0040] Under this technical idea, the delay detection method provided by the preferred embodiment of this aspect of the present invention includes the following steps: First, according to the guidance of the preferred embodiment of the first aspect of the present invention, the following is configured: Figure 4 The equivalent circuit structure shown. As mentioned above, Figure 4 The equivalent circuit structure shown includes a first delay circuit unit and a second delay circuit unit. By adjusting these delay circuit units, the output detection signal and the output detection current can be changed synchronously. Then, based on this adjustment method, multiple groups of output signal detection currents and delay times are obtained. Based on the multiple groups of output signal detection currents and delay times, a current-time ratio of at least one output signal detection current and delay time is obtained, and the expected output current is obtained according to the preset fixed delay time and the current-time ratio; finally, the first delay circuit unit and / or the second delay circuit unit are adjusted, and the value of the output signal detection current is measured until the output signal detection current reaches the expected output current. Review Figure 3 , multiple groups of delay times corresponding to different RC time constants can be configured in advance according to needs, and each RC time constant corresponds to a configuration scheme of a first delay circuit unit and / or a second delay circuit unit. This mapping relationship can quickly adjust the chip delay time through the RC time constant (similar to a gear).

[0041] The adjustment of the first delay circuit unit and the second delay circuit unit is specifically to change the bias voltage or control voltage in the delay circuit unit. Changing the value of the voltage can also be to make the voltage of a certain transistor or transistor capacitor zero, that is, to make a certain transistor not participate in the delay adjustment of the input signal. In this way, the first delay circuit unit and the second delay circuit unit are modified in a synchronous or asynchronous manner, thereby changing the first and second comparison signals output by them for use in the detection circuit.

[0042] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A delay measurement circuit structure, which is used to measure the delay time of a delay device inside a chip after chip plate making is completed, wherein: The delay measurement circuit structure includes: A delay circuit, wherein the delay circuit is configured such that a first signal at an input end is delayed by at least two groups of delay circuit units and finally outputs a second signal through a first AND gate, wherein the delay circuit unit is a delay adjustment circuit composed of a plurality of first N-type transistors connected in parallel or a plurality of P-type transistors and capacitors connected in parallel; A delay output signal detection circuit, the detection circuit is configured to control the on and off of a second N-type transistor by combining an enable signal consistent with the input end of the delay circuit with the first signal, and obtain at least one output signal detection current, And, according to the enable signal and the output of the delay circuit unit, a third signal is obtained, and according to the rising edges of the first signal and the third signal, the delay time of the delay circuit is obtained, wherein, The delay circuit outputs a first comparison signal after being delayed by a first delay circuit unit, and the first comparison signal outputs a second comparison signal after being delayed by a second delay circuit unit, and the delay output signal detection circuit obtains a fourth signal according to the comparison between the first comparison signal and the second comparison signal, and the third signal is a comparison result between the fourth signal and the enable signal; By adjusting the gate voltage of the N-type transistor in the delay circuit unit and / or the voltage of the P-type transistor capacitor, at least multiple output signal detection currents and the delay time are obtained, and by adjusting the delay adjustment circuit to change the output signal detection current, the delay time is adjusted.

2. The delay measurement circuit structure according to claim 1, wherein: The delay circuit unit comprises: A first delay circuit unit is formed by connecting a plurality of first N-type transistors in parallel, wherein the gate of each of the N-type transistors is connected to a delay time control bias voltage; The second delay circuit unit is formed by connecting a plurality of P-type transistor capacitors in parallel, and each of the P-type transistor capacitors is connected to a delay time control voltage.

3. The delay measurement circuit structure according to claim 2, wherein: The input end of the delay circuit also includes a multiplexer and a P-type transistor, wherein the multiplexer is configured to be enabled by the enable signal and to select from at least two input signals to turn on the P-type transistor. The P-type transistor is configured to be turned on by being driven by the output of the multiplexer, to take the delay circuit driving power supply as input, and to output the first signal.

4. The delay measurement circuit structure according to claim 3, wherein: The delay device output signal detection circuit comprises: a first NAND gate, wherein the first NAND gate compares and outputs the fourth signal according to the first comparison signal and the second comparison signal; a second NAND gate, wherein the second NAND gate compares and outputs the third signal according to the fourth signal and the enable signal; A second AND gate is configured to compare and output a fifth signal according to the enable signal and at least one input signal of the multiplexer, wherein the fifth signal turns on the second N-type transistor to obtain the output signal detection current.

5. The delay measurement circuit structure according to claim 4, wherein: The gate of the second N-type transistor is connected to the output of the second AND gate, and the drain of the second N-type transistor is connected to the second comparison signal. When the second N-type transistor is turned on by the fifth signal, the source of the second N-type transistor outputs the output signal detection current.

6. A delay measurement method, which is used to measure the delay time of a delay device inside a chip after chip plate making is completed, wherein: The method comprises the following steps: The step of configuring the delay measurement circuit structure as claimed in any one of claims 1 to 5; A step of adjusting the first delay circuit unit and / or the second delay circuit unit to obtain multiple sets of output signal detection currents and delay times; A step of obtaining a current-to-time ratio of at least one output signal detection current and delay time according to a plurality of groups of output signal detection currents and delay times; A step of obtaining a desired output current according to a preset fixed delay time and the current-time ratio; The step of adjusting the first delay circuit unit and / or the second delay circuit unit, adjusting the load resistance, and measuring the value of the output signal detection current until the output signal detection current reaches the expected output current.

7. The delay measurement method according to claim 6, wherein: The steps of adjusting the first delay circuit unit and / or the second delay circuit unit are specifically: changing the magnitude of at least one delay time control bias voltage in the first delay circuit unit, and / or changing the magnitude of at least one delay time control voltage in the second delay circuit unit.

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