An FPGA-based optical fiber communication protocol frame conversion method and device

Abstract

The present invention relates to a method and device for fiber optic communication protocol frame conversion based on FPGA. The method includes: generating a corresponding configuration file through upper computer configuration; according to the fiber optic mode configuration file by program module RT, selecting the FPGA bitstream of single fiber mode or multi-fiber mode and loading it into the FPGA, and sending the frame structure configuration file to the FPGA; parsing the frame structure configuration file in the FPGA, configuring the frame structure lookup table, and switching to the running mode; in the running mode, the FPGA receives the fiber optic data of the emulator or controller and deframes it, accesses the frame structure lookup table according to the deframing result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing; after framing is completed, the FPGA sends the framed fiber optic data through the corresponding fiber optic communication protocol according to the receiving optical port rate of the controller or emulator to be sent. Compared with the prior art, the present invention realizes high-speed and low-latency massive data transmission between the emulator and different controllers in a multilevel system.

Description

Technical Field

[0001] The present invention relates to the technical field of simulation communication, and particularly to a fiber optic communication protocol frame conversion method and device based on FPGA. Background Art

[0002] With the rapid economic development and the continuous expansion of industrial production scale, the demand for energy by people is also increasing continuously. The traditional two-level voltage source inverter can no longer meet the demand for high voltage and high power by people. Therefore, more and more researchers conduct in-depth research and application on multilevel converter technologies (chain reactive power compensation devices, high-voltage direct-connected energy storage, modular multilevel converters). The traditional electrical communication method has problems such as insufficient real-time simulator interface quantity, complex signal docking, and large floor area during the interaction process of a large amount of electrical data, and can no longer meet the application test requirements of multilevel systems. In the current application of new energy hardware-in-the-loop testing in the power industry, fiber optic communication is usually used for communication between a real-time simulator and a controller to achieve high-speed and low-latency data interaction of a large amount of electrical quantity data. This interaction method has become the mainstream solution in the current application of multilevel system hardware-in-the-loop testing.

[0003] However, there may be a problem of inconsistent optical port rates between the simulator and the controller, and different controller manufacturers may use different communication protocols. This requires a fiber optic communication protocol frame conversion device to achieve seamless conversion between different protocols. Therefore, in order to make multilevel application testing more convenient, a protocol conversion device is needed to convert the fiber optic data frame structure output by the simulator into the fiber optic data frame structure used on the controller side. Summary of the Invention

[0004] The purpose of the present invention is to overcome the defects that there are inconsistent optical port rates between the existing real-time simulator and the multilevel system controller and inconsistent frame structures of communication protocols of each manufacturer in the above-mentioned existing technologies, and to provide a fiber optic communication protocol frame conversion method and device based on FPGA.

[0005] The purpose of the present invention can be achieved by the following technical solutions:

[0006] A fiber optic communication protocol frame conversion method based on FPGA, used for data communication between a controller and a simulator, includes the following steps:

[0007] Generate a corresponding configuration file through upper computer configuration and send it to the program module RT. The configuration file includes a frame structure configuration file and a fiber optic mode configuration file;

[0008] The program module RT selects the FPGA bitstream of the single-fiber mode or multi-fiber mode according to the fiber mode configuration file, and loads it into the FPGA, and issues the frame structure configuration file to the FPGA;

[0009] Parse the frame structure configuration file in the FPGA, configure the frame structure lookup table, and after the configuration is completed, switch to the running mode;

[0010] In the running mode, the FPGA receives the fiber data from the emulator or controller and deframes it, accesses the frame structure lookup table according to the deframing result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing;

[0011] After the framing is completed, the FPGA sends the framed fiber data through the corresponding fiber communication protocol according to the receiving optical port rate of the controller or emulator to be sent.

[0012] Further, the process of generating the corresponding configuration file through the host computer configuration is specifically as follows:

[0013] Configure the frame structure in the front end of the host computer. The configuration information of the frame structure includes the number of downlink data, data type, physical quantity, fiber module data endianness, fiber module transmission time interval, uplink data length, whether the enable bit is pulled high, and frame synchronization packet header;

[0014] Generate the frame structure configuration file according to the configuration information of the frame structure in the back end of the host computer, and generate the configuration file according to the fiber communication structure to configure the fiber mode configuration file.

[0015] Further, during the process of the FPGA receiving the frame structure configuration file, check whether the configuration start control word of the frame structure configuration file is correct. If it is correct, start configuring the frame structure lookup table. After the configuration is completed, create and feedback the configuration completion flag to the program module RT; After receiving the configuration completion flag, the program module RT ends the sending of the frame structure configuration file.

[0016] Further, the process of the FPGA deframing the received fiber data is specifically as follows:

[0017] Check whether the deframing IP interface enable signal of the FPGA is in a usable state. If it is, judge whether the received fiber data frame header is correct. If it is correct, obtain the fiber data and store the output in the BRAM in the FPGA;

[0018] For the single-fiber mode, store the fiber data in the BRAM in the FPGA;

[0019] For the multi-fiber mode, store the fiber data transmitted by different fibers in different BRAMs in the FPGA respectively.

[0020] Furthermore, after the FPGA deframes the received optical fiber data, it also includes error code detection for the optical fiber data output by the controller. The specific process of this error code detection is as follows:

[0021] Read the lower four bits of the pulse width modulation information from the BRAM in the FPGA and determine whether the code pattern is correct. If it is correct, refresh the optical fiber data and resend it. If it is incorrect, keep sending the optical fiber data of the previous frame.

[0022] Furthermore, the specific process of the FPGA performing data recombination according to the frame structure lookup table is as follows:

[0023] In single optical fiber mode, enable all ports of the data processing IP in the FPGA, and perform data recombination on the obtained deframing result according to the frame structure lookup table;

[0024] In multi-optical fiber mode, for the deframing results of different optical fiber transmissions obtained, enable one port of the data processing IP in the FPGA respectively, and perform data recombination according to the frame structure lookup table;

[0025] The recombination process for the data transmitted from the emulator to the controller includes the following steps:

[0026] 11): Obtain the frame structure length of the frame data from the deframing result;

[0027] 12): According to the frame structure length and the written frame data, judge whether the frame data configuration is completed. If it is completed, end. If it is not completed, execute step 13);

[0028] 13): Check whether the obtained frame data is constant filling. If it is, obtain the corresponding constant filling value and register it as a frame data, generate the required controller-side frame data and store it in the BRAM; if not, according to the frame data, obtain the configuration data type, endianness, data initial data type and data position through the frame structure lookup table, generate a mapping address according to the data position, access the mapping address, complete the data type conversion, and register it as a frame data, generate the required controller-side frame data and store it in the BRAM;

[0029] The recombination process for the data transmitted from the controller to the emulator includes the following steps:

[0030] 21): Obtain the frame structure length of the frame data from the deframing result;

[0031] 22): According to the frame structure length and the written frame data, judge whether the frame data configuration is completed. If it is completed, end. If it is not completed, execute step 23);

[0032] (23): Check whether the acquired frame data is constant padding. If so, generate the required emulator-side frame data and store it in the corresponding BRAM. If not, based on the frame data, obtain the configuration data endianness, configuration enable bit high flag, configuration data target optical fiber, and configuration data position through the frame structure lookup table. Combine the frame data sent by the controller, obtain the target data according to the configuration data endianness and configuration enable bit high flag, refresh the corresponding position data, generate the required emulator-side frame data, and store it in the corresponding BRAM.

[0033] Further, the frame forming process includes the following steps:

[0034] Check through the FPGA whether the corresponding frame forming enable signal is in an available state at this time. If so, start frame forming;

[0035] During the frame forming process, control the time interval of data transmission by controlling the frequency of the frame forming enable signal.

[0036] Further, during the transmission of optical fiber data, according to the receiving optical port rate of the controller or emulator on the receiving side, and use the corresponding optical fiber communication protocol for data transmission.

[0037] Further, during the data processing process in the FPGA, the method further includes:

[0038] For the data transmitted from the controller to the emulator, after checking whether the low four-bit pattern of the pulse width modulation signal sent by the controller is correct, read the frame structure configuration file, complete the enable bit operation of the pulse width modulation signal, and report the obtained data to the program module RT; during the reporting process, for the single optical fiber mode, complete data reporting through one address; for the multi-optical fiber mode, perform data reporting through multiple reporting addresses corresponding to each optical fiber respectively;

[0039] For the data transmitted from the emulator to the controller, after generating the controller frame structure according to the frame structure configuration file, report the generated controller frame structure; during the reporting process, for the single optical fiber mode, report the configured controller frame structure data; for the multi-optical fiber mode, on the basis of the controller frame structure data, add and report the unconfigured data.

[0040] The present invention also provides a fiber optic communication protocol frame conversion device based on FPGA, including:

[0041] A host computer, used to generate a configuration file and send it to the program module RT. The configuration file includes a frame structure configuration file and an optical fiber mode configuration file;

[0042] The program module RT is used to select the FPGA bitstream in single-fiber mode or multi-fiber mode according to the fiber mode configuration file and send the frame structure configuration file to the FPGA;

[0043] The FPGA is used to parse the frame structure configuration file, configure the frame structure lookup table, and after the configuration is completed, switch to the running mode; in the running mode, the FPGA receives the fiber data from the emulator and the controller, deframes it, accesses the frame structure lookup table according to the deframing result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing; after the framing is completed, the FPGA sends the framed fiber data through the corresponding fiber communication protocol according to the receiving optical port rates of the controller and the emulator to be sent;

[0044] The fiber interface is used for sending and receiving data of different fiber communication protocols to communicate between the FPGA and the emulator and the controller.

[0045] Compared with the prior art, the present invention has the following advantages:

[0046] (1) The present invention sets the frame structure configuration file and the fiber mode configuration file based on the host computer, the program module RT and the FPGA. The FPGA sets the optimal BRAM data storage method, data reorganization method and data reporting method according to the characteristics of single-fiber mode and multi-fiber mode; for the data transmission of upstream data and downstream data, the corresponding optimal method is selected for data reorganization, and the output is sent according to the data protocols and receiving optical port rates of the controller and the emulator side, realizing the conversion of multi-optical port different fiber communication frame protocols. And through the setting of the configuration file by the host computer, it supports flexible customization of modifying the protocol and modifying the data sending time interval, enabling the hosts using different high-level protocols and different optical port rates on the communication network to cooperate with each other and adapt to three multi-level applications of the chain type reactive power compensation device, high-voltage direct-connected energy storage, and modular multi-level converter.

[0047] (2) The present invention can also observe the data information in real time on the host computer, realizing high-speed and low-latency massive data transmission between the emulator and different controllers in the multi-level system. Description of the Drawings

[0048] Figure 1 It is a schematic flow chart of a fiber communication protocol frame conversion method based on FPGA provided in an embodiment of the present invention;

[0049] Figure 2 It is a schematic diagram of the processing steps of the downstream data in the single-fiber mode provided in an embodiment of the present invention;

[0050] Figure 3 It is a block diagram of the deframing process of the FPGA provided in an embodiment of the present invention;

[0051] Figure 4 Schematic diagram of a single - fiber - mode uplink data processing step provided in an embodiment of the present invention;

[0052] Figure 5 Schematic diagram of an FPGA error - code detection process provided in an embodiment of the present invention;

[0053] Figure 6 Logic block diagram of traversing a frame - structure configuration table provided in an embodiment of the present invention;

[0054] Figure 7 Block diagram of an FPGA frame - forming process provided in an embodiment of the present invention;

[0055] Figure 8 Block diagram of a multi - fiber - mode downlink data step provided in an embodiment of the present invention;

[0056] Figure 9 Block diagram of a multi - fiber - mode uplink data step provided in an embodiment of the present invention;

[0057] Figure 10 Schematic diagram of an FPGA data - reporting process provided in an embodiment of the present invention. Detailed implementation manners

[0058] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. Usually, the components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the protection scope of the present invention.

[0060] It should be noted that: Similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0061] Embodiment 1

[0062] As Figure 1 shown, this embodiment provides a fiber - optic communication protocol frame conversion method based on FPGA for data communication between a controller and an emulator, including the following steps:

[0063] S1: Generate the corresponding configuration file through the host computer configuration and send it to the program module RT. The configuration file includes a frame structure configuration file and an optical fiber mode configuration file.

[0064] S2: Through the program module RT, according to the optical fiber mode configuration file, select the FPGA bitstream of the single optical fiber mode or the multi - optical fiber mode and load it into the FPGA, and send the frame structure configuration file to the FPGA.

[0065] S3: Parse the frame structure configuration file in the FPGA, configure the frame structure lookup table, and after the configuration is completed, switch to the running mode.

[0066] S4: In the running mode, the FPGA receives the optical fiber data of the emulator or the controller and decodes the frame. According to the frame decoding result, access the frame structure lookup table, reorganize the sampled data according to the table, generate the required frame structure data, and perform frame assembly.

[0067] S5: After the frame assembly is completed, the FPGA sends the framed optical fiber data through the corresponding optical fiber communication protocol according to the receiving optical port rate of the controller or the emulator to be sent.

[0068] In this embodiment, the data from the real - time emulator to the multi - level controller is defined as downlink data; the data from the multi - level controller to the real - time emulator is defined as uplink data. Among them, the downlink data includes data such as the voltage, current, power unit capacitor voltage and status, and power unit DC - side current of each phase, and the uplink data includes data such as the pulse - width modulation signal and the start - stop command.

[0069] In step S1, the process of the host computer performing file configuration from the front - end and the back - end specifically includes the following steps:

[0070] S101: Connect to the device through the device IP in the front - end of the host computer and configure the frame structure. The configuration information of this frame structure includes the number of downlink data, data type, physical quantity, big - endian or little - endian of the optical fiber module data, the sending time interval of the optical fiber module, the data length of the uplink data, whether the enable bit is pulled high, the frame synchronization packet header, and the packet header, etc.

[0071] S102: Read the front - end configuration information in the back - end of the host computer, generate the configuration file, establish a TCP communication with the program module RT and send the device RT configuration file, including the frame structure file and the optical fiber mode configuration file.

[0072] Step S2 mainly reads the optical fiber mode configuration file through the program module RT, selects the corresponding FPGA bitstream and loads it into the FPGA. There are two sets of FPGA bitstreams: the single optical fiber mode and the multi - optical fiber mode, which respectively correspond to the application scenarios where the controller has only one optical fiber and the controller has multiple optical fibers.

[0073] It also reads the fiber optic communication protocol frame structure configuration file from the host computer and downloads it to the FPGA;

[0074] The process of the program module RT reading the configuration file also includes the following steps:

[0075] S201: The program module RT reads the configuration file generated by the host computer, checks whether the data flag bit is correct. If the check is correct, it executes step S202; otherwise, it feeds back an error alarm.

[0076] S202: The program module RT serially sends the configuration file, uses a 32-bit interface, controls the FPGA operating mode to the configuration mode, and downloads the protocol frame structure configuration file to the FPGA.

[0077] The process of configuring the frame structure lookup table in step S3 is specifically as follows:

[0078] S301: The FPGA starts to configure the frame structure lookup table and checks the configuration start control word. If the check of the configuration start control word is correct, it starts the configuration. After the configuration is completed, it creates and transmits a feedback configuration completion flag to the RT.

[0079] S302: The program module RT checks the configuration completion flag, ends the sending of the configuration file, controls the operating mode to the running mode, and the entry into the running mode is indicated by: the RUN light is on.

[0080] The process of the FPGA receiving and deframing the fiber optic data from the emulator or controller in step S4 specifically includes the following steps:

[0081] S401: The FPGA receives and deframes the fiber optic data from the emulator and the controller:

[0082] Check whether the deframing IP interface enable signal of the FPGA is in an available state. If it is, then judge whether the received fiber optic data frame header is correct. If it is correct, obtain the fiber optic data and store the output in the BRAM in the FPGA;

[0083] For the single fiber mode, the fiber optic data is stored in the BRAM in the FPGA;

[0084] For the multi-fiber mode, the fiber optic data transmitted by different fibers is stored in different BRAMs in the FPGA respectively.

[0085] In this embodiment, the corresponding process is specifically divided into:

[0086] The FPGA receives the optical fiber data from the emulator and deframes it: The FPGA enables a port of the deframing IP, checks whether the enabling signal of the deframing IP interface is equal to 1 at this time. If it is equal to 1, deframing starts, the AXI bus data is obtained and written into the BRAM. The optical fiber data of multiple fibers is stored in different BRAMs in the FPGA respectively;

[0087] The FPGA receives the optical fiber data from the controller and deframes it: If the single optical fiber mode is executed, that is, there is only 1 optical fiber in the controller at this time; the FPGA enables the deframing IP, checks whether the enabling signal of the deframing IP interface is equal to 1 at this time. If it is equal to 1, deframing starts, the AXI bus data is obtained and written into the BRAM. The optical fiber data is stored in one BRAM in the FPGA.

[0088] If the multi - optical fiber mode is executed, that is, there are multiple optical fibers in the controller at this time; the FPGA enables the deframing IP, and the deframing process is as Figure 3 shown. Check whether the enabling signal of the deframing IP interface is equal to 1 at this time. If it is equal to 1, deframing starts. The FPGA obtains the AXI bus data and writes the data into the corresponding BRAM. The optical fiber data of multiple fibers is stored in different BRAMs in the FPGA respectively.

[0089] Preferably, step S4 further includes performing error code detection on the optical fiber data output by the controller, as Figure 5 shown. The process of this error code detection is specifically as follows:

[0090] Read the lower four - bit data of the pulse - width modulation information from the BRAM in the FPGA, that is, the code pattern of PWM 0 - 4 Bits, and judge whether the code pattern is correct. If it is correct, refresh the optical fiber data and resend it. If it is incorrect, keep sending the optical fiber data of the previous frame.

[0091] In step S4, accessing the frame structure lookup table, reorganizing the sampled data according to the table, generating the required frame structure data, and the process of framing specifically is:

[0092] S402: In the single - optical fiber mode, enable all ports of the data - processing IP in the FPGA, and reorganize the deframing result obtained according to the frame structure lookup table;

[0093] In the multi - optical fiber mode, for the deframing results transmitted by different optical fibers obtained, enable one port of the data - processing IP in the FPGA respectively, and reorganize the data according to the frame structure lookup table;

[0094] The process of reorganizing the data transmitted from the emulator to the controller includes the following steps:

[0095] 11): Obtain the frame structure length of the frame data from the deframing result;

[0096] 12): Determine whether the frame data configuration is completed according to the frame structure length and the written frame data. If it is completed, end the process. If not, execute step 13).

[0097] 13): Check whether the obtained frame data is constant padding. If so, obtain the corresponding constant padding value and store it as a frame data, and generate the required frame data on the controller side and store it in the BRAM. If not, according to the frame data, obtain the configuration data type, endianness, data initial data type, and data position through the frame structure lookup table, generate a mapped address based on the data position, access the mapped address, complete the data type conversion, store it as a frame data, and generate the required frame data on the controller side and store it in the BRAM.

[0098] The recombination process for data transmitted from the controller to the emulator includes the following steps:

[0099] 21): Obtain the frame structure length of the frame data from the deframing result.

[0100] 22): Determine whether the frame data configuration is completed according to the frame structure length and the written frame data. If it is completed, end the process. If not, execute step 23).

[0101] 23): Check whether the obtained frame data is constant padding. If so, generate the required frame data on the emulator side and store it in the corresponding BRAM. If not, according to the frame data, obtain the configuration data endianness, configuration enable bit high flag, configuration data target optical fiber, and configuration data position through the frame structure lookup table, combine with the frame data sent by the controller, obtain the target data according to the configuration data endianness and configuration enable bit high flag, refresh the corresponding position data, generate the required frame data on the emulator side and store it in the corresponding BRAM.

[0102] The corresponding process in this embodiment is specifically as follows:

[0103] If the single-fiber mode is executed, that is, the controller has only 1 optical fiber at this time.

[0104] For the downlink data, as Figure 2 shown, the FPGA enables all ports of the data processing IP and traverses the frame structure lookup table. As Figure 6 shown, the FPGA first obtains the frame structure length. Check whether the frame data is constant padding at this time. If so, obtain the constant padding value and store this data as a frame data. If the frame data is not constant padding at this time, obtain the configuration data type, endianness, data initial data type, and data position. Generate a mapped address based on the data position. The FPGA accesses the mapped address, completes the data type conversion, stores this data as a frame data, generates the required frame data on the controller side and stores it in a BRAM.

[0105] For uplink data, such as Figure 4 shown, the FPGA enables all ports of the data processing IP and traverses the frame structure lookup table. As Figure 6 shown, the FPGA obtains the length of the uplink frame structure. If the frame data at this time is not constant padding, it obtains the configuration data endianness, the configuration enable bit pull-up flag, the configuration data target optical fiber, and the configuration data position. The FPGA obtains the target data according to the configuration data and the register controller data, in accordance with the endianness and the enable pull-up flag, refreshes the data at the corresponding position, generates the required emulator-side frame data, and stores it in the corresponding BRAM.

[0106] If the multi-fiber mode is executed, that is, there are multiple optical fibers in the controller at this time. For downlink data, such as Figure 8 shown, the FPGA enables one port of the data processing IP, traverses the different optical fiber frame structure lookup tables simultaneously, writes the frame data into the corresponding BRAM, generates the controller-side frame data, and stores it in the corresponding BRAM.

[0107] For uplink data, such as Figure 9 shown, the FPGA enables one port of the data processing IP, traverses the frame structure lookup table, generates the required emulator-side frame data, and stores it in the corresponding BRAM.

[0108] The framing process in step S4 is specifically as follows:

[0109] S403: The FPGA starts framing. As Figure 7 shown, the FPGA checks whether the framing IP interface enable signal at this time is equal to 1. If it is equal to 1, it starts framing.

[0110] S404: In the framing IP, the data sending time interval on the controller side is controlled by controlling the frequency of the framing enable signal, and the frequency of the framing enable signal is controlled according to the configuration file.

[0111] In step S5, the FPGA sends the corresponding optical fiber data at the receiving optical port rates of the controller and the emulator respectively through different optical fiber communication protocols;

[0112] In this embodiment, since the optical port rates of the emulator and the controller are inconsistent, the optical fiber data needs to be sent by optical fiber sending modules with different rates. For the controller side, the FPGA sends the controller-side optical fiber data at the receiving optical port rate of the controller through the Aurora 8b / 10b optical fiber communication protocol; for the emulator side, the FPGA sends the emulator-side optical fiber data at a 10G rate through the Aurora 64b / 66b optical fiber communication protocol.

[0113] Preferably, during the data processing by the FPGA, the method further includes:

[0114] S6: For the data transmitted from the controller to the emulator, after checking whether the low four-bit pattern of the pulse width modulation signal sent by the controller is correct, read the frame structure configuration file. After completing the enabling bit operation of the pulse width modulation signal, report the obtained data to the program module RT. During the reporting process, for the single fiber mode, complete the data reporting through one address; for the multi-fiber mode, complete the data reporting through multiple reporting addresses corresponding to each fiber respectively.

[0115] For the data transmitted from the emulator to the controller, after generating the controller frame structure according to the frame structure configuration file, report the generated controller frame structure. During the reporting process, for the single fiber mode, report the configured controller frame structure data; for the multi-fiber mode, on the basis of the controller frame structure data, add and report the unconfigured data.

[0116] In this embodiment, it specifically includes:

[0117] S601: As Figure 10 shown, the FPGA reports the data transmitted by the CPU according to the frame structure configuration file, the length of each packet configuration, and other information.

[0118] For the upstream data (pulse width modulation signal): Check the low 4-bit pattern of the pulse width modulation signal sent by the controller, that is, whether the pattern of PWM 0 - 4 Bits is correct, then read the configuration table. After completing the enabling bit operation of the pulse width modulation signal, report the obtained data. The single fiber mode completes the data reporting through one address, and the multi-fiber mode completes the data reporting through multiple addresses, and each fiber has one reporting address.

[0119] For the downstream data: After generating the controller frame structure according to the configuration table, report the structure data. The single fiber mode only reports the configured data, and the multi-fiber mode can add unconfigured data on the basis of the controller frame structure, such as information such as battery capacity and sub-module current.

[0120] S602: The program module RT parses the reported data according to the user frame structure, and the host computer can observe the data in real time: information such as sub-module voltage, sub-module current, battery capacity, and pulse width modulation signal.

[0121] This embodiment also provides a fiber optic communication protocol frame conversion device based on FPGA, including:

[0122] A host computer, used to generate a configuration file and send it to the program module RT. The configuration file includes a frame structure configuration file and a fiber mode configuration file;

[0123] The program module RT is used to select the FPGA bitstream of the single fiber mode or the multi-fiber mode according to the fiber mode configuration file and load it into the FPGA, and send the frame structure configuration file to the FPGA.

[0124] An FPGA is used to parse the frame structure configuration file, configure the frame structure lookup table, and after the configuration is completed, switch to the running mode. In the running mode, the FPGA receives the optical fiber data from the emulator and the controller and deframes it, accesses the frame structure lookup table according to the deframing result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing. After the framing is completed, the FPGA sends the framed optical fiber data through the corresponding optical fiber communication protocol according to the receiving optical port rates of the controller and the emulator to be sent, that is, executes the above-mentioned optical fiber communication protocol frame conversion method based on the FPGA.

[0125] An optical fiber interface is configured with 16 optical fiber interfaces for sending and receiving data of different optical fiber communication protocols to communicate between the FPGA and the emulator and the controller.

[0126] The preferred specific embodiments of the present invention have been described in detail above. It should be understood that those of ordinary skill in the art can make many modifications and variations according to the concept of the present invention without creative labor. Therefore, all technical solutions that can be obtained by those skilled in the art in the technical field of the present invention through logical analysis, reasoning or limited experiments based on the concept of the present invention on the basis of the prior art should be within the protection scope determined by the claims.

Claims

1. A method for converting optical fiber communication protocol frames based on FPGA, used for data communication between a controller and an emulator, characterized in that: The following steps are involved: Generate corresponding configuration files through host computer configuration and send them to program module RT. The configuration files include frame structure configuration files and fiber mode configuration files. Through the program module RT, according to the fiber mode configuration file, select the FPGA bit stream of the single fiber mode or the multi-fiber mode to load into the FPGA, and send the frame structure configuration file to the FPGA; Parse the frame structure configuration file in FPGA, configure the frame structure lookup table, and after the configuration is completed, switch to the running mode; In the operation mode, the FPGA receives the optical fiber data from the simulator or controller and deframes it, accesses the frame structure lookup table according to the deframe result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing; After the framing is completed, the FPGA sends the framed optical fiber data through the corresponding optical fiber communication protocol according to the receiving optical port rate of the controller or simulator to be sent; The process of the FPGA performing data reorganization according to the frame structure lookup table includes: in the single fiber mode, enabling all ports of the data processing IP in the FPGA, and performing data reorganization on the obtained de-framing result according to the frame structure lookup table; In multi-fiber mode, for the de-framing results of different optical fiber transmissions, one port of the data processing IP in the FPGA is enabled respectively, and data is reassembled according to the frame structure lookup table; The reorganization process of the data transmitted from the simulator to the controller includes: if the acquired frame data is not filled with a constant, the data position is acquired through a frame structure lookup table, a mapping address is generated, a data type conversion is completed, and the required controller side frame data is generated; The reorganization process of data transmitted from the controller to the emulator includes: if the acquired frame data is not filled with a constant, the target data is obtained by configuring the data size end and the configuration enable bit high flag through the frame structure lookup table and combining it with the frame data sent by the controller, and the corresponding position data is refreshed to generate the required emulator side frame data.

2. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: The process of generating the corresponding configuration file through the host computer configuration is specifically as follows: Configure the frame structure in the host computer front end, the configuration information of the frame structure includes the number of downlink data, data type, physical quantity, optical fiber module data size, optical fiber module transmission time interval, uplink data length, whether to enable the bit to be pulled high, and frame synchronization header; In the host computer backend, a frame structure configuration file is generated according to the configuration information of the frame structure, and a fiber mode configuration file is configured according to the fiber communication structure to generate a configuration file.

3. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: When receiving the frame structure configuration file, the FPGA checks whether the configuration start control word of the frame structure configuration file is correct. If it is correct, it starts to configure the frame structure lookup table. After the configuration is completed, it creates and feeds back a configuration completion flag to the program module RT. After receiving the configuration completion flag, the program module RT ends sending the frame structure configuration file.

4. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: The process of the FPGA de-framing the received optical fiber data is specifically as follows: Check whether the FPGA's de-framing IP interface enable signal is in a usable state. If so, determine whether the received fiber data frame header is correct. If correct, obtain the fiber data and store the output in the BRAM in the FPGA. For single fiber mode, the fiber data is stored in the BRAM in the FPGA; For the multi-fiber mode, the fiber data transmitted by different optical fibers are stored in different BRAMs in the FPGA respectively.

5. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: After the FPGA deframes the received optical fiber data, it also includes performing error detection on the optical fiber data output by the controller. The process of the error detection is specifically as follows: The lower four bits of pulse width modulation information are read from the BRAM in the FPGA, and the code type is determined to be correct. If correct, the optical fiber data is refreshed and resent. If incorrect, the previous frame of optical fiber data is kept for transmission.

6. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: The process of reassembling the data transmitted from the simulator to the controller includes the following steps: 11): Get the frame structure length of the frame data from the de-framing result; 12): According to the frame structure length and the written frame data, determine whether the frame data configuration is completed. If completed, end; if not completed, execute step 13); 13): Check whether the acquired frame data is filled with constants. If so, obtain the corresponding constant filling value and store it as a frame data, generate the required controller side frame data and store it in BRAM; if not, obtain the configuration data type, big and small end, data initial data type and data position through the frame structure lookup table according to the frame data, generate a mapping address according to the data position, access the mapping address, complete the data type conversion, and store it as a frame data, generate the required controller side frame data and store it in BRAM; The process of reassembling the data transmitted from the controller to the simulator includes the following steps: 21): Get the frame structure length of the frame data from the de-framing result; 22): According to the frame structure length and the written frame data, determine whether the frame data configuration is completed. If completed, end; if not completed, execute step 23); 23): Check whether the acquired frame data is filled with constants. If so, generate the required simulator side frame data and store it in the corresponding BRAM; if not, obtain the configuration data size end, configuration enable bit high flag, configuration data target fiber and configuration data position through the frame structure lookup table according to the frame data, and combine with the frame data sent by the controller to obtain the target data according to the configuration data size end and the configuration enable bit high flag, and refresh the corresponding position data to generate the required simulator side frame data and store it in the corresponding BRAM.

7. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: The framing process comprises the following steps: The FPGA is used to check whether the corresponding framing enable signal is in an available state. If so, framing is started. During the framing process, the time interval for data transmission is controlled by controlling the frequency of the framing enable signal.

8. The optical fiber communication protocol frame conversion method based on FPGA according to claim 1, characterized in that: During the transmission of optical fiber data, data is transmitted according to the receiving optical port rate of the controller or simulator on the receiving side and using the corresponding optical fiber communication protocol.

9. The optical fiber communication protocol frame conversion method based on FPGA according to claim 5, characterized in that: During the data processing by the FPGA, the method further includes: For the data transmitted from the controller to the simulator, after checking whether the lower four-bit code pattern of the pulse width modulation signal sent by the controller is correct, the frame structure configuration file is read, and after completing the enable bit operation of the pulse width modulation signal, the obtained data is reported to the program module RT; during the reporting process, for the single-fiber mode, the data is reported through one address; for the multi-fiber mode, the data is reported through multiple reporting addresses corresponding to each fiber; For data transmitted from the emulator to the controller, after the controller frame structure is generated according to the frame structure configuration file, the generated controller frame structure is reported; during the reporting process, for the single fiber mode, the configured controller frame structure data is reported; for the multi-fiber mode, on the basis of the controller frame structure data, additional unconfigured data is reported.

10. An optical fiber communication protocol frame conversion device based on FPGA, characterized in that: include: The host computer is used to generate a configuration file and send it to the program module RT. The configuration file includes a frame structure configuration file and a fiber mode configuration file. The program module RT is used to select the FPGA bit stream of the single fiber mode or the multi-fiber mode to load into the FPGA according to the fiber mode configuration file, and send the frame structure configuration file to the FPGA; FPGA, used for parsing the frame structure configuration file, configuring the frame structure lookup table, and switching to the running mode after the configuration is completed; in the running mode, the FPGA receives the optical fiber data from the simulator and the controller and deframes it, accesses the frame structure lookup table according to the deframe result, reorganizes the sampled data according to the table, generates the required frame structure data, and performs framing; After the framing is completed, the FPGA sends the framed optical fiber data through the corresponding optical fiber communication protocol according to the receiving optical port rate of the controller and simulator to be sent; Fiber optic interface, used for sending and receiving data of different fiber optic communication protocols to communicate between FPGA and simulator and controller; The process of the FPGA performing data reorganization according to the frame structure lookup table includes: in the single fiber mode, enabling all ports of the data processing IP in the FPGA, and performing data reorganization on the obtained de-framing result according to the frame structure lookup table; In multi-fiber mode, for the de-framing results of different optical fiber transmissions, one port of the data processing IP in the FPGA is enabled respectively, and data is reassembled according to the frame structure lookup table; The reorganization process of the data transmitted from the simulator to the controller includes: if the acquired frame data is not filled with a constant, the data position is acquired through a frame structure lookup table, a mapping address is generated, a data type conversion is completed, and the required controller side frame data is generated; The reorganization process of data transmitted from the controller to the emulator includes: if the acquired frame data is not filled with a constant, the target data is obtained by configuring the data size end and the configuration enable bit high flag through the frame structure lookup table and combining it with the frame data sent by the controller, and the corresponding position data is refreshed to generate the required emulator side frame data.

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