Semiconductor package structure

Abstract

The embodiment of the present application relates to a kind of semiconductor package structure.The semiconductor package structure includes: substrate, including the substrate pad and virtual board pad on substrate;Chip stack, including chip stacked in substrate from bottom to top, chip has transmission pad and virtual pad, wherein, transmission pad is electrically connected with substrate pad;Thermal conduction line, one end of thermal conduction line is connected with the virtual pad, the other end of thermal conduction line is connected with virtual board pad, for heat conduction from chip to substrate.By thermal conduction line, heat generated in the process of chip operation can be conducted to substrate, and then quickly dissipate to external environment, so as to achieve the purpose of reducing chip temperature, mention chip performance.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] As the capacity demand for dynamic random access devices grows, the number of chips stacked in a package increases. The central chip, in addition to its own heat generation, is also subject to heat conduction from the chips below and above it. In particular, the close spacing between chips in a stacked structure on either side results in a more concentrated thermal effect. The resin surrounding the chip and the DAF film between adjacent chips have low thermal conductivity, conducting heat slowly. This results in high surface temperatures for the chips within the package, impacting their normal operation. Reducing the surface temperature of the chips within the package has become an urgent issue. Summary of the Invention

[0003] An embodiment of the present application provides a semiconductor packaging structure, which can reduce the temperature of the chip surface in the semiconductor packaging structure and improve the overall performance of the semiconductor packaging structure.

[0004] The present application provides a semiconductor package structure, comprising:

[0005] a substrate, comprising a substrate pad and a dummy pad located on the substrate;

[0006] A chip stack, the chip stack comprising chips stacked sequentially from bottom to top on the substrate, the chips having transmission pads and dummy pads, wherein the transmission pads are electrically connected to the substrate pads;

[0007] A heat conduction line, one end of which is connected to the dummy pad, and the other end of which is connected to the dummy board pad, is used to conduct heat from the chip to the substrate.

[0008] In one embodiment, the number of the dummy pads is greater than or equal to 1, and at least one of the dummy pads is located in a middle area of ​​the chip.

[0009] In one embodiment, the number of the dummy pads is greater than 1, and the plurality of dummy pads are arranged at intervals from a middle area to a peripheral area of ​​the chip.

[0010] In one embodiment, the density of the dummy pads decreases from the middle area to the peripheral area of ​​the chip.

[0011] In one embodiment, the number of the virtual board pads is the same as the number of the virtual pads, and the positions of the virtual board pads and the virtual pads correspond one to one.

[0012] In one embodiment, the number of the dummy pads is one, the dummy pads extend along a first direction, and the width of the dummy pads in the first direction is greater than or equal to the total length of the distribution area of ​​the dummy pads on the chip;

[0013] The first direction is the arrangement direction of the dummy pads on the chip.

[0014] In one embodiment, the heat transfer line comprises a bonding wire.

[0015] In one embodiment, the substrate includes a surface layer and an intermediate layer located below the surface layer, and the semiconductor package structure further includes:

[0016] A contact plug is provided in a through hole that penetrates both the surface contact area of ​​the surface layer and the intermediate contact area of ​​the intermediate layer;

[0017] The substrate pad and the dummy pad are provided on the surface of the surface layer away from the intermediate layer.

[0018] In one embodiment, the dummy pad is disposed in a surface grounding area of ​​the surface layer.

[0019] In one embodiment, the semiconductor package structure further includes:

[0020] The adhesive layer is located between adjacent chips to bond the chips together.

[0021] The above-mentioned semiconductor packaging structure includes a substrate provided with a virtual board pad, a chip with a virtual pad; a heat conduction line with one end connected to the virtual pad and the other end connected to the virtual board pad. The heat generated during the operation of the chip can be conducted to the substrate through the heat conduction line, and then quickly dissipated to the external environment, thereby achieving the purpose of reducing the chip temperature and improving chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0023] Figure 1 is a schematic cross-sectional view of a semiconductor package structure in one embodiment;

[0024] Figure 2 is a schematic top view of a chip in one embodiment;

[0025] Figure 3 is a schematic top view of a semiconductor package structure in one embodiment;

[0026] Figure 4 is a schematic top view of a semiconductor package structure in another embodiment;

[0027] Figure 5 FIG. 4 is a flow chart of a method for preparing a semiconductor packaging structure in one embodiment.

[0028] Description of reference numerals:

[0029] 102, substrate; 104, chip stack; 106, heat conduction line; 108, contact plug; 202, substrate pad; 204, dummy board pad; 206, chip; 208, transmission pad; 210, dummy pad; 212, surface layer; 214, power layer; 215, through hole; 216, contact layer; 218, conductive plug; 220, signal transmission line; 222, solder ball; 224, adhesive layer. DETAILED DESCRIPTION

[0030] To facilitate understanding of the embodiments of the present application, a more comprehensive description of the embodiments of the present application will be provided below with reference to the accompanying drawings. The accompanying drawings provide preferred embodiments of the embodiments of the present application. However, the embodiments of the present application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive disclosure of the embodiments of the present application.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the embodiments of the present application pertain. The terms used herein in the description of the embodiments of the present application are intended only to describe specific embodiments and are not intended to limit the embodiments of the present application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0032] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the methods or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the embodiments of the present application.

[0033] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In the description of this application, the meaning of "several" is at least one, such as one, two, etc., unless otherwise clearly and specifically defined.

[0034] Figure 1 FIG. 1 is a cross-sectional view of a semiconductor package structure in one embodiment. Figure 1 As shown, in this embodiment, a semiconductor package structure is provided, including: a substrate 102, a chip stack 104 and a heat conduction line 106; the substrate 102 includes a substrate pad 202 and a dummy pad 204 located on the substrate 102, wherein the substrate pad 202 is electrically connected to the metal layer circuit in the substrate 102; the chip stack 104 includes chips 206 stacked on the substrate 102 from bottom to top, where bottom to top refers to a direction from the upper surface of the substrate 102 to a direction away from the upper surface of the substrate 102 The chip 206 has a transmission pad 208 and a dummy pad 210, wherein the transmission pad 208 is electrically connected to the substrate pad 202, and the transmission pad 208 is used to realize the transmission of signals between the chip 206 and the external circuit. The dummy pad 210 here does not have the function of signal transmission; one end of the heat conduction line 106 is connected to the dummy pad 210, and the other end of the heat conduction line 106 is connected to the dummy board pad 204, which is used to conduct heat from the chip 206 to the substrate 102.

[0035] The above-mentioned semiconductor packaging structure includes a substrate provided with a virtual board pad, a chip with a virtual pad; a heat conduction line with one end connected to the virtual pad and the other end connected to the virtual board pad. The heat generated during the operation of the chip can be conducted to the substrate through the heat conduction line, and then quickly dissipated to the external environment, thereby achieving the purpose of reducing the chip temperature and improving chip performance.

[0036] In one embodiment, the heat transfer line 106 includes a bonding wire. Using a bonding wire as the heat transfer line 106 to transfer heat from the chip 206 to the substrate 102 can reduce the difficulty of forming the heat transfer line 106.

[0037] In one embodiment, the material of the heat conducting wire 106 includes copper, gold, or aluminum. It should be noted that the material of the heat conducting wire 106 only needs to be able to conduct heat from the chip 206 to the substrate 102 .

[0038] For example, there are at least two heat conducting wires 106, one end of which is connected to different virtual pads 210, and the other end can be connected to the same virtual board pad 204 or to different virtual board pads 204. It is understood that there are at least two heat conducting wires 106, one end of which is connected to the same virtual pad 210, and the other end can be connected to the same virtual board pad 204 or to different virtual board pads 204. This setting can increase the speed of heat conduction from the virtual pad 210 to the virtual board pad 204.

[0039] Continue to refer Figure 1 In one embodiment, the substrate 102 includes a surface layer 212 and an intermediate layer 214 located below the surface layer, and the semiconductor packaging structure further includes: a through hole 215, which simultaneously penetrates the surface grounding area of ​​the surface layer 212 and the middle grounding area of ​​the intermediate layer 214, wherein the substrate pad 202 and the virtual board pad 204 are provided on the surface of the surface layer 212 away from the intermediate layer 214. Specifically, intermediate layer 214 is located on the side of surface layer 212 facing away from chip stack 104. Surface layer 212 is the upper surface layer of substrate 102 that contacts chip stack 104. Surface layer 212 is provided with surface metal wiring circuits and a surface grounding region. Substrate pads 202 are connected to the surface metal wiring circuits, and dummy pads 204 are located in the surface grounding region. Intermediate layer 214 is the portion of substrate 102 that supports intermediate power metal wiring circuits and an intermediate grounding region for providing power to substrate 102. The surface metal wiring circuits and the intermediate power metal wiring circuits are isolated from each other by insulating material (e.g., PPG) located near intermediate layer 214 in surface layer 212. It will be understood that the orthographic projection of the surface grounding region on intermediate layer 214 at least partially overlaps with the intermediate grounding region, and that vias 215 extend through the overlapping portion of the orthographic projection of the surface grounding region on intermediate layer 214 and the intermediate grounding region. By providing through-holes 215, the interior of substrate 102 is in direct contact with the external environment. Heat within substrate 102 is dissipated to the external environment through the sidewalls of through-holes 215, further reducing the overall temperature of the semiconductor package structure and preventing the impact of excessive substrate 102 temperature on the performance of the semiconductor package structure. For example, through-holes 215 expose a portion of the lower surface of dummy pad 204. Heat transferred to dummy pad 204 via heat transfer line 106 can be dissipated directly to the external environment through through-holes 215, accelerating the cooling of chip 206 and reducing the impact of temperature increases on chip performance.

[0040] In one embodiment, the dummy pad 204 is disposed on a surface grounding region of the surface layer 212 to prevent short circuits.

[0041] Exemplarily, the semiconductor package structure further includes a contact plug 108 disposed in a through-hole 215 extending through both the surface ground region of the surface layer 212 and the intermediate region of the intermediate layer 214. The substrate pad 202 and the dummy pad 204 are disposed on the surface of the surface layer 212 facing away from the intermediate layer 214. When the orthographic projection of the surface ground region on the intermediate layer 214 at least partially overlaps with the intermediate region, the lower surface of at least one contact plug 108 is at least flush with the surface of the intermediate layer 214 facing away from the intermediate layer 214. Typically, the surface ground region and the intermediate region are completely separated by an insulating material (e.g., PPG) in the surface layer 212 near the intermediate layer 214. By providing the contact plug 108, the surface ground region and the intermediate region are connected, accelerating heat dissipation from the substrate 102 to the external environment, further reducing the overall temperature of the semiconductor package structure and preventing excessive substrate temperature from affecting the performance of the semiconductor package structure.

[0042] For example, the upper surface of the contact plug 108 contacts the lower surface of the virtual board pad 204. At this time, the heat conducted to the virtual board pad 204 through the heat conduction line 106 can be dissipated to the external environment through the contact plug 108, which can accelerate the cooling speed of the chip 206 and reduce the impact of the temperature increase on the chip performance.

[0043] Exemplarily, the materials forming the contact plug 108 include one or more of copper, gold, aluminum, tungsten, titanium, and titanium nitride. It should be noted that the material of the contact plug 108 only needs to be able to conduct heat and not affect the electrical connection between the metal wiring layers provided in the substrate 102.

[0044] Continue to refer Figure 1 Exemplarily, the semiconductor package structure further includes a conductive plug 218, which is disposed in a contact hole penetrating the substrate 102 and is used to transmit a signal to the chip 206. Exemplarily, the upper surface of the conductive plug 218 contacts the lower surface of the substrate pad 202.

[0045] Exemplarily, the conductive plug 218 is made of conductive materials such as copper, gold, aluminum, tungsten, titanium, titanium nitride, and polysilicon.

[0046] Exemplarily, the semiconductor package structure further includes a signal transmission line 220, one end of the signal transmission line 220 being connected to the transmission pad 208, and the other end of the signal transmission line 220 being connected to the substrate pad 202, so that the transmission pad 208 and the substrate pad 202 are electrically connected via the signal transmission line 220. It is understood that the constituent material of the signal transmission line 220 includes one or more of copper, gold, aluminum, tungsten, titanium, or titanium nitride.

[0047] Furthermore, the substrate 102 further includes a lower surface layer 216 . The lower surface layer 216 is located on a side of the intermediate layer 214 away from the surface layer 212 . The semiconductor package structure is connected to an external circuit via the lower surface layer 216 .

[0048] It can be understood that the lower surface layer 216 is the partial thickness of the substrate 102 that supports the lower power metal wiring circuit and the lower grounding area for providing power to the substrate 102. The lower metal wiring circuit and the intermediate power metal wiring circuit are isolated by the insulating material (such as PPG) of the lower surface layer 216 close to the intermediate layer 214; when the orthographic projections of the surface grounding area and the intermediate grounding area on the lower surface layer 216 overlap with the lower grounding area, the through hole 215 where the contact plug 108 is located passes through the overlapping area in the lower surface layer 216. At this time, the lower surface of the contact plug 108 is flush with the surface of the lower surface layer 216 facing away from the intermediate layer 214. The upper surface of the contact plug 108 can be flush with the upper surface of the substrate 102 or lower than the upper surface of the substrate 102. When the upper surface of the contact plug 108 is lower than the upper surface of the substrate 102, the heat in the substrate 102 is dissipated to the external environment through the contact plug 108 and the side wall of the through hole 215.

[0049] Illustratively, the semiconductor package structure further includes solder balls 222 disposed on a side of the lower surface layer 216 away from the intermediate layer 214. Solder balls 222 contact the lower surface of the conductive plug 218 to connect the conductive plug 218 to an external circuit. Illustratively, the material constituting the solder balls 222 includes at least one of tin, gold, copper, or an alloy of tin, gold, and copper. It will be appreciated that the solder balls 222 are located directly below the conductive plug 218.

[0050] Continue to refer Figure 1 In one embodiment, the chip stack 104 includes a plurality of chips 206 stacked from bottom to top on the substrate 102, and the semiconductor package structure further includes: an adhesive layer 224, located between adjacent chips 206 to adhere the chips 206. The adhesive layer 224 is made of an insulating material. It is understandable that the adhesive layer 224 is located between the chip 206 and the substrate 102 to adhere the chip 206 to the substrate 102. An exemplary material constituting the adhesive layer 224 includes a DAF film, wherein the DAF film is composed of a first adhesive surface, a second adhesive surface, and a high thermal conductivity resin layer located between the first adhesive surface and the second adhesive surface, and the first adhesive surface is bonded to the chip 206.

[0051] Figure 2 FIG. 1 is a top view of a chip in an embodiment. Figure 2As shown, in one embodiment, the number of the dummy pads 210 is greater than or equal to 1, and at least one of the dummy pads 210 is located in the middle area of ​​the chip 206. Specifically, along the length direction of the chip 206 (two intersecting sides on the chip 206, one of which is the length direction and the other is the width direction, illustratively, the length direction of the chip 206 is the direction in which the transmission pads 208 on the chip 206 are arranged, represented by the X direction in the figure), the chip 206 is divided into a middle area A, a transition area B, and a peripheral area C from the center of the chip 206 to the edge of the chip 206. The number of the dummy pads 210 is greater than or equal to 1, and at least one of the dummy pads 210 is located in the middle area A of the chip 206.

[0052] Continue to refer Figure 2 In one embodiment, the number of the dummy pads 210 is greater than one, and the plurality of dummy pads 210 are spaced apart from the middle region A of the chip 206 toward the peripheral region C. By setting the number of the dummy pads 210 to be greater than one, when the heat transfer wire 106 is connected to the dummy pads 210 through a wire bonding process, the wire bonding process is facilitated to proceed smoothly, and the wire bonding position is identified with high accuracy, which facilitates the control of the wire bonding process.

[0053] In one embodiment, the density of the dummy pads 210 decreases from the middle region A to the peripheral region C of the chip 206. Figure 2 As shown, along the X direction, the distance L3 between adjacent dummy pads 210 in the middle region A is smaller than the distance L4 between adjacent dummy pads 210 in the transition region B, and the distance L3 is smaller than the distance L5 between adjacent dummy pads 210 in the peripheral region C.

[0054] In other embodiments, from the middle region A to the peripheral region C of the chip 206, the density of the dummy pads 210 in the middle region A is greater than the density of the dummy pads 210 in the transition region B, and the density of the dummy pads 210 in the transition region B is equal to the density of the dummy pads 210 in the peripheral region C. That is, the distance between adjacent dummy pads 210 in the middle region A of the chip 102 is less than the distance between adjacent dummy pads 210 in the transition region B, and the distance between adjacent dummy pads 210 in the transition region B is equal to the distance between adjacent dummy pads 210 in the peripheral region C. Thermal simulation technology indicates that the operating heat of the chip 206 decreases from the middle region A to the transition region B of the chip 206. By setting the density of the dummy pads 210 in the middle region A to be greater than the density of the dummy pads 210 in the transition region B, and the density of the dummy pads 210 in the transition region B to be equal to the density of the dummy pads 210 in the peripheral region C, the heat dissipation speed can be improved while the number of dummy pads 210 remains unchanged. In another embodiment, from the middle region A to the peripheral region C of the chip 206, the density of the dummy pads 210 in the middle region A is equal to the density of the dummy pads 210 in the transition region B, and the density of the dummy pads 210 in the transition region B is greater than the density of the dummy pads 210 in the peripheral region C. That is, the distance between adjacent dummy pads 210 in the middle region A of the chip 102 is equal to the distance between adjacent dummy pads 210 in the transition region B, and the distance between adjacent dummy pads 210 in the transition region B is less than the distance between adjacent dummy pads 210 in the peripheral region C. Thermal simulation technology indicates that the operating heat of the chip 206 decreases from the transition region B to the peripheral region C of the chip 206. Setting the density of the dummy pads 210 in the middle region A equal to the density of the dummy pads 210 in the transition region B, and the density of the dummy pads 210 in the transition region B greater than the density of the dummy pads 210 in the peripheral region C, can improve heat dissipation while keeping the number of dummy pads 210 unchanged.

[0055] In yet another embodiment, the density of the dummy pads 210 decreases from the middle region A to the peripheral region C of the chip 206. Thermal simulation technology indicates that the operating heat of the chip 206 decreases from the middle region A to the peripheral region C of the chip 206. This setting can improve the speed of heat dissipation while keeping the number of dummy pads 210 constant. It is understood that the density and number of dummy pads 210 are set based on the corresponding heat distribution of the middle region A, transition region B, and peripheral region C during the operation of the chip 206, thereby achieving the purpose of quickly reducing the chip temperature and improving the performance of the chip 206. For example, the number of dummy pads 210 is 1, and the shape of the dummy pad 210 is similar to the shape of the heat distribution diagram of the chip 206 during operation.

[0056] It is clear that in order to ensure the connection between the heat conducting wire 106 and the dummy pad 210, the size of the dummy pad 210 needs to meet the process requirements corresponding to the connection purpose. For example, due to the process limitations of the wire bonding process and the size of the solder ball, Figure 2 As shown, along the X direction, the distance L3 / L4 / L5 between adjacent virtual pads 210 is greater than 10um, the width of the virtual pad 210 is greater than 43um, and along the Y direction intersecting with the X direction, the length of the virtual pad 210 is greater than 50um. For example, the Y direction intersects the X direction perpendicularly.

[0057] Figure 3 FIG. 1 is a top view of a semiconductor package structure in one embodiment. Figure 3 As shown, in this embodiment, the number of the virtual board pads 204 is the same as the number of the virtual pads 210 , and the positions of the virtual board pads 204 and the virtual pads 210 correspond one to one.

[0058] In other embodiments, the number of the virtual board pads 204 is greater than the number of the virtual pads 210. This setting can increase the total area of ​​the virtual board pads 204 that receive heat and the total area of ​​the virtual board pads 204 that dissipate heat, thereby increasing the speed at which heat is transferred from the virtual pads 210 to the virtual board pads 204 and increasing the speed at which heat is dissipated from the virtual board pads 204.

[0059] Exemplarily, the size of the dummy pad 204 is equal to or larger than the size of the dummy pad 210. By setting the size of the dummy pad 204 to be larger than the size of the dummy pad 210, the heat dissipation speed of the dummy pad 204 can be increased.

[0060] It is clear that in order to ensure the connection between the heat transfer line 106 and the dummy pad 204, the size of the dummy pad 204 and the horizontal spacing between the edge of the chip stack 104 and the dummy pad 204 must meet the process requirements corresponding to the connection purpose. For example, due to the process limitations of the wire bonding process and the size of the solder balls, the distance between adjacent dummy pads 204 along the X direction is greater than 10μm; when the number of dummy pads 204 is greater than 1, the width of the dummy pad 204 is greater than 35μm; along the Y direction intersecting the X direction, the length of the dummy pad 204 is greater than 90μm, and the horizontal spacing D between the edge of the chip stack 104 and the dummy pad 204 is greater than or equal to 250μm.

[0061] Figure 4 FIG. 1 is a top view of a semiconductor package structure in another embodiment. Figure 5As shown, in one embodiment, the number of the dummy pads 204 is one, and the dummy pads 204 extend along a first direction. In the first direction, the width W1 of the dummy pads 204 is greater than or equal to the total length W2 of the area where the dummy pads 210 are distributed on the chip 206. The first direction is the arrangement direction of the dummy pads 210 on the chip 206, which is the X direction in the figure. Due to the process limitations of the wire bonding process and the size of the solder balls, in actual applications, in order to offset the left and right offset of the chip 206 when attached to the substrate 102, the width W1 of the dummy pads 204 is greater than the total length W2 of the area where the dummy pads 210 are distributed on the chip 206. Along the Y direction intersecting the X direction, the length of the dummy pads 204 is greater than 90 μm, and the horizontal spacing D between the edge of the chip stack 104 and the dummy pads 204 is greater than or equal to 250 μm. It can be understood that the speed at which heat is dissipated from the dummy pad 204 can be increased by increasing the width W1 of the dummy pad 204 and the length of the dummy pad 204 .

[0062] Figure 5 FIG. 1 is a flow chart of a method for preparing a semiconductor packaging structure in one embodiment. Figure 1 、 Figure 5 As shown, in this embodiment, a method for preparing a semiconductor package structure is provided, for preparing any of the semiconductor package structures described above, the preparation method comprising:

[0063] S102, providing a substrate provided with substrate pads.

[0064] A substrate 102 is provided, on which a substrate pad 202 is provided. The substrate pad 202 is electrically connected to a metal layer circuit in the substrate 102 .

[0065] S104, forming a dummy pad on the substrate.

[0066] A dummy pad 204 is formed on the substrate 102 by a process well known to those skilled in the art.

[0067] S106, providing a chip provided with a transmission pad.

[0068] A chip 206 is provided, and a transmission pad 208 is provided on the chip 206 , wherein the transmission pad 208 is used to realize signal transmission between the chip 206 and an external circuit.

[0069] S108 , forming a dummy pad on the chip.

[0070] A dummy pad 210 is formed on the chip 206 . The dummy pad 210 does not have a signal transmission function.

[0071] S110 , stacking chips on a substrate in sequence from bottom to top to form a chip stack.

[0072] The chips 206 are stacked on the substrate 102 in sequence from bottom to top to form a chip stack 104 . Here, from bottom to top refers to a direction from the upper surface of the substrate 102 to a direction away from the upper surface of the substrate 102 .

[0073] S112 , forming a heat conduction line with one end connected to the dummy pad and the other end connected to the dummy board pad.

[0074] A heat conduction line 106 is formed to connect the substrate 102 and the chip 206, one end of the heat conduction line 106 is connected to the dummy pad 210, and the other end of the heat conduction line 106 is connected to the dummy board pad 204, for conducting heat from the chip 206 to the substrate 102; wherein the transmission pad 208 is electrically connected to the substrate pad 202.

[0075] The preparation method of the above-mentioned semiconductor packaging structure includes forming a virtual board pad 204 on the substrate 102, forming a virtual pad 210 on the chip 106, stacking the chips 206 from bottom to top on the substrate 102 to form a chip stack 104, and forming a heat conduction line 106 with one end connected to the virtual pad 210 and the other end connected to the virtual board pad 204. The heat generated by the chip 206 during operation can be conducted to the substrate 102 through the heat conduction line 106, and then quickly dissipated to the external environment, thereby achieving the purpose of reducing the chip temperature and improving chip performance.

[0076] In one embodiment, the heat transfer line 106 includes a bonding wire. Using a bonding wire as the heat transfer line 106 to transfer heat from the chip 206 to the substrate 102 can reduce the difficulty of forming the heat transfer line 106.

[0077] In one embodiment, the material of the heat conducting wire 106 includes copper, gold, or aluminum. It should be noted that the material of the heat conducting wire 106 only needs to be able to conduct heat from the chip 206 to the substrate 102 .

[0078] In one embodiment, forming a heat transfer line having one end connected to the dummy pad and the other end connected to the dummy board pad includes forming at least two heat transfer lines 106, wherein one end of each of the heat transfer lines 106 is connected to different dummy pads 210, and the other end can be connected to the same dummy board pad 204 or to different dummy board pads 204. It is understood that forming at least two heat transfer lines 106, wherein one end of each of the heat transfer lines 106 is connected to the same dummy pad 210, and the other end can be connected to the same dummy board pad 204 or to different dummy board pads 204, can increase the speed at which heat is transferred from the dummy pad 210 to the dummy board pad 204. In one embodiment, the substrate 102 includes a surface layer 212 and an intermediate layer 214 located below the surface layer 212, and the surface of the surface layer 212 away from the intermediate layer 214 is provided with the substrate pad 202 and the dummy board pad 204, and the preparation method further includes: forming a through hole 215, the through hole 215 simultaneously penetrating the surface grounding area of ​​the surface layer 212 and the intermediate grounding area of ​​the intermediate layer 214; specifically, the intermediate layer 214 is located on the side of the surface layer 212 away from the chip stack 104, where the surface layer 212 is the substrate 1 Surface layer 212, the upper surface layer in contact with chip stack 104, is provided with a surface metal wiring circuit and a surface grounding region. Substrate pads 202 are connected to the surface metal wiring circuit, and dummy pads 204 are located in the surface grounding region. Intermediate layer 214, which is the portion of substrate 102 thick that supports intermediate power metal wiring circuits and an intermediate grounding region for supplying power to substrate 102, is isolated from the surface metal wiring circuit by an insulating material (e.g., PPG) located near intermediate layer 214 on surface layer 212. It will be understood that the orthographic projection of the surface grounding region on intermediate layer 214 at least partially overlaps with the intermediate grounding region, and that vias 215 extend through the overlapping portion of the orthographic projection of the surface grounding region on intermediate layer 214 and the intermediate grounding region. By providing through-holes 215, the interior of substrate 102 is in direct contact with the external environment. Heat within substrate 102 is dissipated to the external environment through the sidewalls of through-holes 215, further reducing the overall temperature of the semiconductor package structure and preventing the impact of excessive substrate 102 temperature on the performance of the semiconductor package structure. For example, through-holes 215 expose a portion of the lower surface of dummy pad 204. Heat transferred to dummy pad 204 via heat transfer line 106 can be dissipated directly to the external environment through through-holes 215, accelerating the cooling of chip 206 and reducing the impact of temperature increases on chip performance.

[0079] In one embodiment, the dummy pad 204 is disposed on a surface grounding region of the surface layer 212 to prevent short circuits.

[0080] In one embodiment, the preparation of the semiconductor package structure further includes forming contact plugs 108 in the through-holes 215. Providing the contact plugs 108 can accelerate the rate at which heat within the substrate 102 is dissipated to the external environment, thereby further reducing the overall temperature of the semiconductor package structure and preventing the impact of excessive substrate temperature on the performance of the semiconductor package structure.

[0081] When the orthographic projection of the surface ground region on the intermediate layer 214 at least partially overlaps with the intermediate interlayer region, the lower surface of at least one contact plug 108 is at least flush with the surface of the intermediate layer 214 facing away from the intermediate layer 214. Typically, the surface ground region and the intermediate interlayer region are completely separated by an insulating material (such as PPG) on the surface layer 212 near the intermediate layer 214. By providing contact plugs 108 to connect the surface ground region and the intermediate interlayer region, the speed at which heat within the substrate 102 is dissipated to the external environment can be accelerated, further reducing the overall temperature of the semiconductor package structure and preventing the impact of excessive substrate temperature on the performance of the semiconductor package structure.

[0082] For example, the upper surface of the contact plug 108 contacts the lower surface of the virtual board pad 204. At this time, the heat conducted to the virtual board pad 204 through the heat conduction line 106 can be dissipated to the external environment through the contact plug 108, which can accelerate the cooling speed of the chip 206 and reduce the impact of the temperature increase on the chip performance.

[0083] Exemplarily, the materials forming the contact plug 108 include one or more of copper, gold, aluminum, tungsten, titanium, and titanium nitride. It should be noted that the material of the contact plug 108 only needs to be able to conduct heat and not affect the electrical connection between the metal wiring layers provided in the substrate 102.

[0084] Continue to refer Figure 1 , exemplarily, the method for preparing a semiconductor package structure further includes:

[0085] A conductive plug 218 is formed on the substrate 102 and disposed in a contact hole penetrating the substrate 102 for transmitting a signal to the chip 206 . Exemplarily, the upper surface of the conductive plug 218 contacts the lower surface of the substrate pad 202 .

[0086] Exemplarily, the method for preparing a semiconductor package structure further includes: forming a signal transmission line 220 between the transmission pad 208 and the substrate pad 202, wherein one end of the signal transmission line 220 is connected to the transmission pad 208, and the other end of the signal transmission line 220 is connected to the substrate pad 202, so that the transmission pad 208 and the substrate pad 202 are electrically connected via the signal transmission line 220. It is understood that the constituent material of the signal transmission line 220 includes one or more of copper, gold, aluminum, tungsten, titanium, or titanium nitride.

[0087] Furthermore, the substrate 102 further includes a lower surface layer 216 . The lower surface layer 216 is located on a side of the intermediate layer 214 away from the surface layer 212 . The semiconductor package structure is connected to an external circuit via the lower surface layer 216 .

[0088] It can be understood that the lower surface layer 216 is the partial thickness of the substrate 102 that supports the lower power metal wiring circuit and the lower grounding area for providing power to the substrate 102. The lower metal wiring circuit and the intermediate power metal wiring circuit are isolated by the insulating material (such as PPG) of the lower surface layer 216 close to the intermediate layer 214; when the orthographic projections of the surface grounding area and the intermediate grounding area on the lower surface layer 216 overlap with the lower grounding area, the through hole 215 where the contact plug 108 is located passes through the overlapping area in the lower surface layer 216. At this time, the lower surface of the contact plug 108 is flush with the surface of the lower surface layer 216 facing away from the intermediate layer 214. The upper surface of the contact plug 108 can be flush with the upper surface of the substrate 102 or lower than the upper surface of the substrate 102. When the upper surface of the contact plug 108 is lower than the upper surface of the substrate 102, the heat in the substrate 102 is dissipated to the external environment through the contact plug 108 and the side wall of the through hole 215.

[0089] Exemplarily, the method for fabricating a semiconductor package structure further includes forming solder balls 222 on a side of the lower surface layer 216 facing away from the intermediate layer 214. The solder balls 222 contact the lower surface of the conductive plug 218 to connect the conductive plug 218 to an external circuit. Exemplarily, the material constituting the solder balls 222 includes at least one of tin, gold, copper, or an alloy of tin, gold, and copper. It is understood that the solder balls 222 are located directly below the conductive plug 218.

[0090] Continue to refer Figure 1In one embodiment, the chip stack 104 includes a plurality of chips 206 stacked from bottom to top on the substrate 102. The chips 206 are stacked sequentially from bottom to top on the substrate to form the chip stack, including: forming an adhesive layer 224 in a predetermined chip area on the substrate 102; placing the chip 206 on the adhesive layer 224; repeating the steps of forming the adhesive layer 224 on the chip 206; and placing the chip 206 on the adhesive layer 224 until the desired chips 206 are placed, wherein the adhesive layer 224 is located between adjacent chips 206 to bond the chips 206. Exemplarily, the adhesive layer 224 is made of an insulating material. For example, the material constituting the adhesive layer 224 includes a DAF film, wherein the DAF film is composed of a first adhesive surface, a second adhesive surface, and a high thermal conductivity resin layer located between the first adhesive surface and the second adhesive surface, and the first adhesive surface is bonded to the chip 206.

[0091] In one embodiment, before forming a dummy pad on the chip, the preparation method further includes: providing a chip stack including a chip without a dummy pad 210, a substrate without a dummy board pad 204, and a standard semiconductor packaging structure without a heat conduction line 106, and obtaining the heat distribution of the working heat of the chip on the chip surface in the standard semiconductor packaging structure through thermal simulation technology; and obtaining the pad position of the dummy pad on the chip surface based on the heat distribution.

[0092] In one embodiment, the operating heat of the chip decreases from the middle area of ​​the chip to the peripheral area of ​​the chip.

[0093] In one embodiment, forming dummy pads on a chip includes: setting the number and density of dummy pads 210 based on the heat distribution of the chip's operating heat on the chip surface, wherein the number of dummy pads 210 is greater than or equal to one, and at least one dummy pad 210 is located in a central region of the chip 206. Specifically, along the length direction of the chip 206 (two intersecting sides of the chip 206, one of which is the length direction and the other is the width direction, illustratively, the length direction of the chip 206 is the direction in which the transmission pads 208 on the chip 206 are arranged, represented by the X direction in the figure), the chip 206 is divided into a central region A, a transition region B, and a peripheral region C from the center of the chip 206 to the edge of the chip 206. The number of dummy pads 210 is greater than or equal to one, and at least one dummy pad 210 is located in the central region A of the chip 206.

[0094] In one embodiment, the number of the dummy pads 210 is greater than one, and the plurality of dummy pads 210 are spaced apart from the middle region A of the chip 206 toward the peripheral region C. By setting the number of the dummy pads 210 to be greater than one, when the heat transfer wire 106 is connected to the dummy pads 210 through a wire bonding process, the wire bonding process is facilitated to proceed smoothly, and the wire bonding position is identified with high accuracy, which facilitates the control of the wire bonding process.

[0095] In one embodiment, the working heat of the chip 206 decreases from the middle area A of the chip 206 to the peripheral area C of the chip 206. The forming of the dummy pads on the chip includes: forming dummy pads 210 on the chip 206 with a density decreasing from the middle area A to the peripheral area C of the chip 206. Figure 3 As shown, along the X direction, the distance L3 between adjacent dummy pads 210 in the middle area A is smaller than the distance L4 between adjacent dummy pads 210 in the transition area B, and the distance L3 is smaller than the distance L5 between adjacent dummy pads 210 in the peripheral area C. This setting can improve the heat dissipation speed while keeping the number of dummy pads 210 unchanged.

[0096] In other embodiments, the operating heat of the chip 206 decreases from the middle region A of the chip 206 to the transition region B of the chip 206 , and forming dummy pads on the chip includes: forming dummy pads 210 on the chip 206 with a density in the middle region A greater than that in the transition region B, and with a density in the transition region B equal to that in the peripheral region C. That is, the distance between adjacent dummy pads 210 in the middle region A of the chip 102 is smaller than the distance between adjacent dummy pads 210 in the transition region B, and the distance between adjacent dummy pads 210 in the transition region B is equal to the distance between adjacent dummy pads 210 in the peripheral region C.

[0097] In another embodiment, the operating heat of the chip 206 decreases from the transition region B of the chip 206 to the peripheral region C of the chip 206 , and forming dummy pads on the chip includes: forming dummy pads 210 on the chip 206 with a density in the middle region A equal to that in the transition region B, and a density in the transition region B greater than that in the peripheral region C. That is, the distance between adjacent dummy pads 210 in the middle region A of the chip 102 is equal to the distance between adjacent dummy pads 210 in the transition region B, and the distance between adjacent dummy pads 210 in the transition region B is less than the distance between adjacent dummy pads 210 in the peripheral region C.

[0098] It is understood that the density and number of dummy pads 210 are set based on the corresponding heat distribution of the intermediate region A, transition region B, and peripheral region C during the operation of chip 206, thereby achieving the purpose of quickly reducing the chip temperature and improving the performance of chip 206. For example, the number of dummy pads 210 is 1, and the shape of dummy pad 210 is similar to the shape of the heat distribution diagram of chip 206 during operation.

[0099] It is clear that to ensure the connection between heat transfer line 106 and dummy pad 210, the size of dummy pad 210 must meet the process requirements for achieving the connection. For example, due to the process limitations of the wire bonding process and the size of the solder ball, the distance between adjacent dummy pads 210 along the X direction is greater than 10 μm, the width of dummy pad 210 is greater than 43 μm, and the length of dummy pad 210 along the Y direction intersecting the X direction is greater than 50 μm. For example, the Y direction intersects the X direction at right angles.

[0100] like Figure 4 As shown, in this embodiment, forming virtual board pads on the substrate includes: forming virtual board pads 204 on the substrate, the number of which is the same as the number of the virtual pads 210 and the positions of which correspond one-to-one to the preset positions of the virtual pads 210 on the substrate.

[0101] In other embodiments, forming virtual board pads on the substrate includes: forming a number of virtual board pads 204 on the substrate that is greater than the number of the virtual pads 210. Through this setting, the total area of ​​the virtual board pads 204 that receive heat and the total area of ​​the virtual board pads 204 that dissipate heat can be increased, thereby increasing the speed at which heat is transferred from the virtual pads 210 to the virtual board pads 204, and at the same time increasing the speed at which heat is dissipated from the virtual board pads 204.

[0102] Exemplarily, forming a dummy pad on the substrate includes forming a dummy pad 204 on the substrate having a size equal to or larger than that of the dummy pad 210. By setting the size of the dummy pad 204 larger than that of the dummy pad 210, the heat dissipation speed of the dummy pad 204 can be increased.

[0103] It is clear that in order to ensure the connection between the heat transfer line 106 and the dummy pad 204, the size of the dummy pad 204 and the horizontal spacing between the edge of the chip stack 104 and the dummy pad 204 must meet the process requirements corresponding to the connection purpose. For example, due to the process limitations of the wire bonding process and the size of the solder balls, the distance L between adjacent dummy pads 204 along the X direction is greater than 10μm; when the number of dummy pads 204 is greater than 1, the width of the dummy pad 204 is greater than 35μm; along the Y direction intersecting the X direction, the length of the dummy pad 204 is greater than 90μm, and the horizontal spacing D between the edge of the chip stack 104 and the dummy pad 204 is greater than or equal to 250μm.

[0104] like Figure 5 As shown, in one embodiment, the number of the dummy pads 204 is one, and the dummy pads 204 extend along a first direction. In the first direction, the width W1 of the dummy pads 204 is greater than or equal to the total length W2 of the area where the dummy pads 210 are distributed on the chip 206. The first direction is the arrangement direction of the dummy pads 210 on the chip 206, which is the X direction in the figure. Due to the process limitations of the wire bonding process and the size of the solder balls, in actual applications, in order to offset the left and right offset of the chip 206 when attached to the substrate 102, the width W1 of the dummy pads 204 is greater than the total length W2 of the area where the dummy pads 210 are distributed on the chip 206. Along the Y direction intersecting the X direction, the length of the dummy pads 204 is greater than 90 μm, and the horizontal spacing D between the edge of the chip stack 104 and the dummy pads 204 is greater than or equal to 250 μm. It can be understood that the speed at which heat is dissipated from the dummy pad 204 can be increased by increasing the width W1 of the dummy pad 204 and the length of the dummy pad 204 .

[0105] It should be understood that although Figure 5 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. In addition, Figure 5 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0106] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] The above-described embodiments merely represent several implementation methods of the embodiments of the present application. The descriptions thereof are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that, for those skilled in the art, several variations and improvements can be made without departing from the concept of the embodiments of the present application, and these all fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the patent of the embodiments of the present application shall be based on the appended claims.

Claims

1. A semiconductor packaging structure, characterized in that: include: a substrate, comprising a substrate pad and a dummy pad located on the substrate; A chip stack, the chip stack comprising chips stacked sequentially from bottom to top on the substrate, the chips having transmission pads and dummy pads, wherein the transmission pads are electrically connected to the substrate pads; a heat conduction line, one end of the heat conduction line being connected to the dummy pad, and the other end of the heat conduction line being connected to the dummy board pad, for conducting heat from the chip to the substrate; The number of the dummy pads is greater than 1, and the plurality of dummy pads are spaced apart from the middle area to the peripheral area of ​​the chip; and the density of the dummy pads decreases from the middle area to the peripheral area of ​​the chip.

2. The semiconductor package structure according to claim 1, wherein: The number of the dummy pads is greater than or equal to 1, and at least one of the dummy pads is located in a middle area of ​​the chip.

3. The semiconductor package structure according to claim 1, wherein: The number of the virtual board pads is the same as the number of the virtual pads, and the positions of the virtual board pads and the virtual pads correspond one to one.

4. The semiconductor package structure according to claim 1, wherein: The number of the dummy pads is 1, the dummy pads extend along a first direction, and the width of the dummy pads in the first direction is greater than or equal to the total length of the distribution area of ​​the dummy pads on the chip; The first direction is the arrangement direction of the dummy pads on the chip.

5. The semiconductor package structure according to claim 1, wherein: The heat transfer lines include bonding wires.

6. The semiconductor package structure according to claim 1, wherein: The substrate includes a surface layer and an intermediate layer located below the surface layer, and the semiconductor package structure further includes: A contact plug is provided in a through hole that penetrates both the surface contact area of ​​the surface layer and the intermediate contact area of ​​the intermediate layer; The substrate pad and the dummy pad are provided on the surface of the surface layer away from the intermediate layer.

7. The semiconductor package structure according to claim 6, wherein: The dummy board pad is arranged on the surface grounding area of ​​the surface layer.

8. The semiconductor package structure according to claim 1, wherein: The semiconductor package structure further includes: The adhesive layer is located between adjacent chips to bond the chips together.

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