A control circuit and control method for constant working current

Abstract

The present invention relates to a control circuit of a constant working current and a control method thereof, characterized in that the circuit comprises a constant voltage source U0, a constant current source I0, a current sampling circuit, a current adjustment circuit, and a load circuit; wherein the current sampling circuit is composed of a first resistor R1, a second resistor R2, a first NMOS tube M1, a second NMOS tube M2, and a first operational amplifier OP1; wherein the current adjustment circuit is composed of a third resistor R3, a fourth resistor R4, a third NMOS tube M3, and a second operational amplifier OP2; due to the introduction of the current sampling circuit and the current adjustment circuit, the current output of the constant voltage source can be kept constant no matter how the current Iload of the load circuit changes.

Description

Technical Field

[0001] The present invention relates to the field of power supply systems requiring a constant operating current, and in particular to a control circuit and a control method for a constant operating current. Background Art

[0002] Nowadays, the integration of integrated circuits is getting higher and higher, and the number of peripheral devices is getting smaller and smaller. Especially in various sensors, even the entire chip has only two pins: the power pin and the ground pin, which makes it increasingly difficult to communicate with the chip. The chip can receive information by changing the power supply voltage, and send information by changing the power supply current. To ensure the reliability of communication, higher requirements are placed on the stability of the entire chip current. Under different power supply voltages and different temperatures, relative stability must be guaranteed. Summary of the invention

[0003] The purpose of the present invention is to provide a constant working current control circuit and a control method thereof to solve the problems raised in the above background technology.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] A control circuit for a constant working current comprises a constant voltage source U0, a constant current source I0, a current sampling circuit, a current adjustment circuit and a load circuit; wherein the current sampling circuit is composed of a first resistor R1, a second resistor R2, a first NMOS tube M1, a second NMOS tube M2 and a first operational amplifier OP1, and is used to sample the current of the load circuit and output a current component to the current adjustment circuit; the current adjustment circuit is composed of a third resistor R3, a fourth resistor R4, a third NMOS tube M3 and a second operational amplifier OP2; and the circuit comprises 6 connection nodes, namely a first node, a second node, a third node, a fourth node, a fifth node and a sixth node.

[0006] In the current sampling circuit, one end of the first resistor R1 away from the first node is connected to one end of the second resistor R2 away from the second node and the drain of the third NMOS tube and connected together to VDD of the constant voltage source, and one end of the first resistor R1 close to the first node is connected to the first node; the first node is a connection point between one end of the first resistor R1 close to the first node, the negative end of the first operational amplifier OP1, and one end of the load circuit close to the first node; the second node is a connection point between one end of the second resistor R2 close to the second node, the positive end of the first operational amplifier OP1, and the drain of the first NMOS tube M1; one end of the second resistor R2 away from the second node is connected to VDD, and one end close to the second node is connected to the second node.

[0007] The negative terminal of the first operational amplifier OP1 is connected to the first node, the positive terminal of the first operational amplifier OP1 is connected to the second node, and the O terminal of the first operational amplifier is connected to the third node; the third node is the connection point between the O terminal of the first operational amplifier and the gate of the first NMOS tube M1 and the gate of the second NMOS tube M2.

[0008] The drain of the first NMOS transistor M1 is connected to the second node, the gate of the first NMOS transistor M1 is connected to the third node, and the source of the first NMOS transistor M1 is grounded.

[0009] The drain of the second NMOS tube M2 is connected to the fifth node, the gate of the second NMOS tube M2 is connected to the third node, and the source of the second NMOS tube M2 is grounded; the fifth node is the connection point of the drain of the second NMOS tube, one end of the third resistor R3 close to the fifth node, and the positive end of the second operational amplifier OP2.

[0010] The third resistor R3 in the current regulating circuit has one end close to the fifth node connected to the fifth node, and one end away from the fifth node connected to the ground.

[0011] One end of the fourth resistor R4 close to the sixth node is connected to the sixth node, and one end away from the sixth node is grounded; the sixth node is a connection point between one end of the fourth resistor R4 close to the sixth node, the negative end of the second operational amplifier OP2, and the source of the third NMOS tube M3.

[0012] The negative terminal of the second operational amplifier OP2 is connected to the sixth node, the positive terminal of the second operational amplifier OP2 is connected to the fifth node, and the O terminal of the second operational amplifier is connected to the fourth node; the fourth node is the connection point between the O terminal of the second operational amplifier OP2 and the gate of the third NMOS; the drain of the third NMOS tube M3 is connected to VDD, the gate of the third NMOS tube M3 is connected to the fourth node, and the source of the third NMOS tube M3 is connected to the sixth node.

[0013] A control method using the control circuit comprises the following steps:

[0014] In the control circuit, when the load circuit changes due to frequency, temperature, etc., the load circuit current Iload will change, and a variable with a size of "∆Iload" will be added relative to the change. This variable is caused by the first operational amplifier OP1, the first NMOS tube M1 and the second NMOS tube M2. The current IM1 flowing through the second resistor R2 will generate a current variable:

[0015] ΔIM1= ΔIload / Nr21, formula (1)

[0016] Nr21 is the ratio of the resistance values ​​of R2 and R1;

[0017] Since the gate-source voltages of the first NMOS tube M1 and the second NMOS tube M2 are the same, that is, Vgs1=Vgs2, the current variable generated by the current IM2 flowing through the second NMOS tube M2 is:

[0018] ΔIM2= ΔIM1 / Nm12, formula (2)

[0019] Nm12 is the ratio of the width to length ratio of M1 and M2;

[0020] Substituting into formula (1):

[0021] ΔIM2= ΔIload / (Nr21*Nm12), formula (3)

[0022] The constant current source I0 in the control circuit has two components, namely IR3 flowing through the third resistor R3 and IM2 flowing through the second NMOS tube M2, so:

[0023] IR0= IR3+IM2, formula (4)

[0024] Combining formula (3) and formula (4), since the constant current source I0 remains unchanged, the variable of IR3 is:

[0025] ΔIR3= -ΔIload / (Nr21*Nm12), formula (5)

[0026] The variable flowing through the third NMOS tube M3 after the action of the current adjustment circuit is:

[0027] ΔIM3=Nr34*ΔIR3, formula (6)

[0028] Nr34 is the ratio of the resistance values ​​of R3 and R4;

[0029] Substitute formula (5) into formula (6)

[0030] ΔIM3=-Nr34*ΔIload / (Nr21*Nm12), formula (7)

[0031] The current IU0 flowing out of the constant voltage source U0 increases by ∆Iload and ∆IM1, and decreases by ∆IM3.

[0032] In order to obtain a constant IU0 in the control circuit, the increase component and the decrease component must be the same, that is:

[0033] ΔIload+ΔIM1+ΔIM3=0, formula (8)

[0034] Substituting into formula (1) and formula (7) and simplifying it, we get:

[0035] ΔIload+ΔIload / Nr21=Nr34*ΔIload / (Nr21*Nm12), formula (9)

[0036] Further simplification

[0037] Nm12*(Nr21+1)=Nr34, formula (10)

[0038] To obtain a constant IU0, it is only necessary to satisfy formula (10), where Nm12 is the ratio of M1 to M2, Nr21 is the resistance ratio of resistors R2 and R1, and Nr34 is the resistance ratio of resistors R3 and R4.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] The present invention introduces a current sampling circuit and a current adjustment circuit so that no matter how the load current changes in the entire system solution, the total current of the entire system will remain relatively stable within a certain range: that is, the constant current source I0 is multiplied by a coefficient, and this coefficient is determined by the ratio of the third resistor R3 and the fourth resistor R4. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A control circuit diagram of a constant operating current proposed by the present invention. DETAILED DESCRIPTION

[0042] In order to clarify the technical problems, technical solutions, implementation processes and performance demonstrations, the present invention is further described in detail below in conjunction with the embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. The exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] The same reference numerals indicate elements with the same or similar functions. Although various aspects of the embodiments are shown in the drawings,

[0044] Unless otherwise indicated, the drawings are not necessarily drawn to scale.

[0045] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0046] In addition, in order to better illustrate the present disclosure, numerous specific details are given in the following detailed description.

[0047] Those skilled in the art will appreciate that the present disclosure may be practiced without certain specific details.

[0048] Methods, means, components and circuits well known to those skilled in the art have not been described in detail in order to obscure the subject matter of the present disclosure.

[0049] Example 1

[0050] like Figure 1 As shown, a control circuit for a constant working current includes a constant voltage source U0, a constant current source I0, a current sampling circuit 7, a current adjustment circuit 8 and a load circuit; wherein the current sampling circuit 7 is composed of a first resistor R1, a second resistor R2, a first NMOS tube M1, a second NMOS tube M2 and a first operational amplifier OP1, and is used to sample the current of the load circuit and output a current component to the current adjustment circuit 8; the current adjustment circuit 8 is composed of a third resistor R3, a fourth resistor R4, a third NMOS tube M3 and a second operational amplifier OP2; there are 6 relatively important connection nodes in the circuit, namely a first node 1, a second node 2, a third node 3, a fourth node 4, a fifth node 5 and a sixth node 6.

[0051] In the current sampling circuit 7, an end of the first resistor R1 away from the first node 1 is connected to an end of the second resistor R2 away from the second node 2, and the drain of the third NMOS tube and are connected together to VDD of the constant voltage source, and an end of the first resistor R1 close to the first node 1 is connected to the first node 1; the first node 1 is a connection point between an end of the first resistor R1 close to the first node 1, the negative end of the first operational amplifier OP1, and an end of the load circuit close to the first node 1; the second node 2 is a connection point between an end of the second resistor R2 close to the second node 2, the positive end of the first operational amplifier OP1, and the drain of the first NMOS tube M1.

[0052] One end of the second resistor R2 away from the second node 2 is connected to VDD, and one end of the second resistor R2 close to the second node 2 is connected to the second node 2 .

[0053] The negative terminal of the first operational amplifier OP1 is connected to the first node 1, the positive terminal of the first operational amplifier OP1 is connected to the second node 2, and the O terminal of the first operational amplifier is connected to the third node 3; the third node 3 is the connection point between the O terminal of the first operational amplifier and the gate of the first NMOS tube M1 and the gate of the second NMOS tube M2.

[0054] The drain of the first NMOS transistor M1 is connected to the second node 2 , the gate of the first NMOS transistor M1 is connected to the third node 3 , and the source of the first NMOS transistor M1 is grounded.

[0055] The drain of the second NMOS tube M2 is connected to the fifth node 5, the gate of the second NMOS tube M2 is connected to the third node 3, and the source of the second NMOS tube M2 is grounded; the fifth node 5 is the connection point of the drain of the second NMOS tube, one end of the third resistor R3 close to the fifth node 5, and the positive end of the second operational amplifier OP2.

[0056] The third resistor R3 in the current regulating circuit 8 has one end close to the fifth node 5 connected to the fifth node 5 , and has one end away from the fifth node 5 connected to the ground.

[0057] One end of the fourth resistor R4 close to the sixth node 6 is connected to the sixth node 6, and the other end away from the sixth node 6 is grounded; the sixth node 6 is the connection point between one end of the fourth resistor R4 close to the sixth node 6, the negative end of the second operational amplifier OP2 and the source of the third NMOS tube M3.

[0058] The negative terminal of the second operational amplifier OP2 is connected to the sixth node 6, the positive terminal of the second operational amplifier OP2 is connected to the fifth node 5, and the O terminal of the second operational amplifier is connected to the fourth node 4; the fourth node 4 is the connection point between the O terminal of the second operational amplifier OP2 and the third NMOS gate.

[0059] The drain of the third NMOS transistor M3 is connected to VDD, the gate of the third NMOS transistor M3 is connected to the fourth node 4 , and the source of the third NMOS transistor M3 is connected to the sixth node 6 .

[0060] Example 2

[0061] A method for controlling a constant operating current. Figure 1 When the load circuit changes due to frequency, temperature, etc., the load circuit current Iload will change. For the convenience of explanation, it is assumed that a variable is added relative to the change, and the size is "∆Iload". This variable is affected by the first operational amplifier OP1, the first NMOS tube M1 and the second NMOS tube M2. The current IM1 flowing through the second resistor R2 will generate a current variable:

[0062] ΔIM1= ΔIload / Nr21, formula (1)

[0063] Nr21 is the ratio of the resistance values ​​of R2 and R1;

[0064] Since the gate-source voltages of the first NMOS tube M1 and the second NMOS tube M2 are the same, that is, Vgs1=Vgs2, the current variable generated by the current IM2 flowing through the second NMOS tube M2 is:

[0065] ΔIM2= ΔIM1 / Nm12, formula (2)

[0066] Nm12 is the ratio of the width to length ratio of M1 and M2;

[0067] Substituting into formula (1):

[0068] ΔIM2= ΔIload / (Nr21*Nm12), formula (3)

[0069] exist Figure 1 The constant current source I0 has two components, IR3 flowing through the third resistor R3 and IM2 flowing through the second NMOS tube M2, so:

[0070] IR0= IR3+IM2, formula (4)

[0071] Combining formula (3) and formula (4), since the constant current source I0 remains unchanged, the variable of IR3 is:

[0072] ΔIR3= -ΔIload / (Nr21*Nm12), formula (5)

[0073] go through Figure 1 The current adjustment circuit 8 in the embodiment described above has the following variables flowing through the third NMOS tube M3:

[0074] ΔIM3=Nr34*ΔIR3, formula (6)

[0075] Nr34 is the ratio of the resistance values ​​of R3 and R4;

[0076] Substitute formula (5) into formula (6)

[0077] ΔIM3=-Nr34*ΔIload / (Nr21*Nm12), formula (7)

[0078] According to the analysis of the above embodiment 2, the components of the current IU0 flowing out of the constant voltage source U0 that increase are ∆Iload and ∆IM1, and the component that decreases is ∆IM3;

[0079] exist Figure 1 In order to obtain a constant IU0, the increased component and the decreased component must be the same, that is:

[0080] ΔIload+ΔIM1+ΔIM3=0, formula (8)

[0081] Substituting into formula (1) and formula (7) and simplifying it, we get:

[0082] ΔIload+ΔIload / Nr21=Nr34*ΔIload / (Nr21*Nm12), formula (9)

[0083] Further simplification

[0084] Nm12*(Nr21+1)=Nr34, formula (10)

[0085] According to the above analysis, to obtain a constant IU0, it is only necessary to satisfy formula (10), where Nm12 is the ratio of M1 to M2, Nr21 is the resistance ratio of resistors R2 and R1, and Nr34 is the resistance ratio of resistors R3 and R4. Formula (10) can be easily established through reasonable circuit design and layout.

[0086] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments, and the above embodiments and descriptions are only for the present invention.

[0087] The preferred embodiments are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may also have various

[0088] The scope of the invention is defined by the invention.

[0089] The following claims and their equivalents are defined.

[0090] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A constant working current control circuit, characterized in that: The invention comprises a constant voltage source U0, a constant current source I0, a current sampling circuit (7), a current adjustment circuit (8) and a load circuit; wherein the current sampling circuit (7) is composed of a first resistor R1, a second resistor R2, a first NMOS transistor M1, a second NMOS transistor M2 and a first operational amplifier OP1, and is used to sample the current of the load circuit and output a current component to the current adjustment circuit (8); the current adjustment circuit (8) is composed of a third resistor R3, a fourth resistor R4, a third NMOS transistor M3 and a second operational amplifier OP2; the circuit comprises 6 connection nodes, namely a first node (1), a second node (2), a third node (3), a fourth node (4), a fifth node (5) and a sixth node (6); ... In the circuit (7), an end of the first resistor R1 away from the first node (1) is connected to an end of the second resistor R2 away from the second node (2), and the drain of the third NMOS transistor, and together connected to VDD of the constant voltage source; an end of the first resistor R1 close to the first node (1) is connected to the first node (1); the first node (1) is a connection point between an end of the first resistor R1 close to the first node (1), a negative end of the first operational amplifier OP1, and an end of the load circuit close to the first node (1); the second node (2) is an end of the second resistor R2 close to the second node (2), a positive end of the first operational amplifier OP1, and a drain of the first NMOS transistor M1. the second resistor R2 has one end away from the second node (2) connected to VDD, and one end close to the second node (2) connected to the second node (2); the third resistor R3 in the current adjustment circuit (8) has one end close to the fifth node (5) connected to the fifth node (5), and one end away from the fifth node (5) connected to ground; the negative end of the first operational amplifier OP1 is connected to the first node (1), the positive end of the first operational amplifier OP1 is connected to the second node (2), and the O end of the first operational amplifier is connected to the third node (3); the third node (3) is the connection point between the O end of the first operational amplifier and the gate of the first NMOS transistor M1 and the gate of the second NMOS transistor M2; The drain of the first NMOS transistor M1 is connected to the second node (2), the gate of the first NMOS transistor M1 is connected to the third node (3), and the source of the first NMOS transistor M1 is grounded; the drain of the second NMOS transistor M2 is connected to the fifth node (5), the gate of the second NMOS transistor M2 is connected to the third node (3), and the source of the second NMOS transistor M2 is grounded; the fifth node (5) is a connection point between the drain of the second NMOS transistor, an end of the third resistor R3 close to the fifth node (5), and the positive terminal of the second operational amplifier OP2; an end of the fourth resistor R4 close to the sixth node (6) is connected to the sixth node (6), and an end away from the sixth node (6) is grounded;The sixth node (6) is a connection point between one end of the fourth resistor R4 close to the sixth node (6), the negative end of the second operational amplifier OP2 and the source of the third NMOS tube M3; the negative end of the second operational amplifier OP2 is connected to the sixth node (6), the positive end of the second operational amplifier OP2 is connected to the fifth node (5), and the O end of the second operational amplifier is connected to the fourth node (4); the fourth node (4) is a connection point between the O end of the second operational amplifier OP2 and the gate of the third NMOS tube M3; the drain of the third NMOS tube M3 is connected to VDD, the gate of the third NMOS tube M3 is connected to the fourth node (4), and the source of the third NMOS tube M3 is connected to the sixth node (6). ; 2. A control method using the control circuit as claimed in claim 1, characterized in that: The following steps are involved: In the control circuit, when the load circuit changes due to frequency, temperature, etc., the load circuit current Iload will change, and a variable with a size of "∆Iload" will be added relative to the change. This variable is caused by the first operational amplifier OP1, the first NMOS tube M1 and the second NMOS tube M2. The current IM1 flowing through the second resistor R2 will generate a current variable: ΔIM1= ΔIload / Nr21, formula (1) Nr21 is the ratio of the resistance values ​​of R2 and R1; Since the gate-source voltages of the first NMOS tube M1 and the second NMOS tube M2 are the same, that is, Vgs1=Vgs2, the current variable generated by the current IM2 flowing through the second NMOS tube M2 is: ΔIM2= ΔIM1 / Nm12, formula (2) Nm12 is the ratio of the width to length ratio of M1 and M2; Substituting into formula (1): ΔIM2= ΔIload / (Nr21*Nm12), formula (3) The constant current source I0 in the control circuit has two components, namely IR3 flowing through the third resistor R3 and IM2 flowing through the second NMOS tube M2, so: IR0= IR3+IM2, formula (4) Combining formula (3) and formula (4), since the constant current source I0 remains unchanged, the variable of IR3 is: ΔIR3= -ΔIload / (Nr21*Nm12), formula (5) The variable flowing through the third NMOS tube M3 after the action of the current adjustment circuit (8) is: ΔIM3=Nr34*ΔIR3, formula (6) Nr34 is the ratio of the resistance values ​​of R3 and R4; Substitute formula (5) into formula (6) ΔIM3=-Nr34*ΔIload / (Nr21*Nm12), formula (7) The current IU0 flowing out of the constant voltage source U0 increases by ∆Iload and ∆IM1, and decreases by ∆IM3. In order to obtain a constant IU0 in the control circuit, the increase component and the decrease component must be the same, that is: ΔIload+ΔIM1+ΔIM3=0, formula (8) Substituting into formula (1) and formula (7) and simplifying it, we get: ΔIload+ΔIload / Nr21=Nr34*ΔIload / (Nr21*Nm12), formula (9) Further simplification Nm12*(Nr21+1)=Nr34, formula (10) To obtain a constant IU0, it is only necessary to satisfy formula (10), where Nm12 is the ratio of M1 to M2, Nr21 is the resistance ratio of resistors R2 and R1, and Nr34 is the resistance ratio of resistors R3 and R4.

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