A method and device for preventing and repairing digital chip noise

Abstract

The present invention provides a method and device for preventing and repairing noise in a digital chip, and relates to the field of integrated circuit technology. The method includes obtaining input parameters, and performing different noise prevention processes in the layout planning stage, layout stage, clock tree synthesis and optimization stage, and wiring stage of the early stage of the digital back-end design process according to the input parameters. It is determined whether the noise after the wiring stage converges. If not, a noise repair script is generated, and the noise is repaired until the noise converges. The present invention adopts prevention and repair methods to solve the noise problem in the early and late stages of the digital back-end design process, and forms a noise repair script and process for quickly repairing the noise under the condition of minimizing the probability and amount of noise, thereby reducing the number of iterations of the digital back-end design, improving the efficiency of noise repair, and reducing the development time cost.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to a method and device for preventing and repairing digital chip noise. Background Art

[0002] As chip scale and system complexity continue to increase, chip feature sizes gradually become smaller, and noise is generated and enhanced. Noise, also known as crosstalk, is a factor that causes the chip operating voltage or signal to deviate from the normal track or distort. The noise problem becomes increasingly obvious as the chip feature size gradually becomes smaller. It mainly refers to the increase in coupling capacitance between lines and the decrease in ground capacitance after the line width and line spacing between process metal layers and between lines on the same layer become narrower. The size of the noise is proportional to the coupling capacitance and inversely proportional to the ground capacitance, resulting in increasingly serious noise problems.

[0003] On the one hand, noise may cause chip performance problems, such as timing delays. When digital back-end engineers perform timing signoff, they will spend more energy to collect timing. On the other hand, noise may also cause chip functional problems. Once the noise signal exceeds the noise tolerance, the signal is distorted, the chip function fails, and ultimately the chip design fails. Therefore, in the digital chip back-end design and development process, repairing noise is particularly important.

[0004] Noise is one of the most important indicators for digital back-end design and development sign-off. Currently, there is no complete system process and design solution to prevent and repair it. Existing technologies mainly rely on manual repair by designers, which is carried out from process parameters or function option configuration of automated layout and routing tools. This repair method is too fragmented, and there are problems such as weak noise repair, large post-repair efforts, many iterations, and low noise repair efficiency, which is contrary to the situation where every second counts in chip design and development. In addition, the traditional manual repair method is also highly dependent on the experience of designers, with varying results and low efficiency.

[0005] In summary, how to reduce the number of iterations of digital back-end design and improve the efficiency of noise repair is a technical problem that needs to be urgently solved by technical personnel in this field. Summary of the invention

[0006] The object of the present invention is to provide a method for preventing and repairing noise in a digital chip, so as to reduce the number of iterations of digital back-end design and improve the efficiency of noise repair.

[0007] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0008] The present invention provides a method for preventing and repairing digital chip noise, the method comprising:

[0009] Acquiring input parameters, performing layout planning according to the input parameters, and performing a first noise prevention process in the layout planning stage;

[0010] Performing layout according to the input parameters and the result of the layout planning stage, and performing a second noise prevention process in the layout stage;

[0011] Perform clock tree synthesis and optimization according to the input parameters and the result of the layout stage, and perform a third noise prevention process in the clock tree synthesis and optimization stage;

[0012] Performing routing according to the input parameters and the results of the clock tree synthesis and optimization phase, and performing a fourth noise prevention process during the routing phase;

[0013] It is determined whether the noise after the wiring stage is converged. If not, a noise repair script is generated and the noise is repaired until the noise is converged.

[0014] Optionally, the input parameters include configuration parameters and the functional module's own parameters; the configuration parameters include chip process parameters, metal interconnect layer parameters, data flow direction parameters, chip packaging rule constraints, design rule constraints and blocking constraints; the functional module includes at least macro units, standard units and drive units, and the functional module's own parameters are used to characterize the type, quantity and size of the functional module.

[0015] Optionally, the method for performing the first noise prevention process in the layout planning stage includes:

[0016] Determine the size of the chip based on the chip process parameters, metal interconnection layer parameters and the functional module's own parameters, and set the power module on the high-level metal interconnection layer;

[0017] The macro units are placed based on the size of the chip, the parameters of the functional modules themselves, the parameters of the direction of the data flow, the design rule constraints, and the chip packaging rule constraints.

[0018] Optionally, the types of the macro units include input and output units, intellectual property units and storage units, the blocking constraints include hard blocking constraints, and the method for placing the macro units based on the size of the chip, the parameters of the functional modules themselves, the direction parameters of the data flow, the design rule constraints, and the chip packaging rule constraints includes:

[0019] Planning the placement order of the macro units according to the direction parameters of the data flow, and ensuring that the macro units are away from functional modules that are prone to generate high-frequency signals or noise;

[0020] When the macro unit is flipped or mirrored, the macro unit is flipped or mirrored according to the requirements corresponding to the design rule constraints;

[0021] The input and output units are placed at the border of the chip, the storage units and the intellectual property units are placed around the core area of ​​the chip, and the center of the core area is reserved for placing the standard units;

[0022] Determine the placement position of the input-output unit according to the chip packaging rule constraint, and reserve a first preset distance between the input-output unit and the core area;

[0023] A second preset distance is reserved between the IP unit and the core area, and the hard blocking constraint is applied around the IP unit; wherein the second preset distance is smaller than the first preset distance;

[0024] The plurality of storage units are placed back to back, and the winding spacing between adjacent storage units is ensured to meet the requirements of the design rule constraints.

[0025] Optionally, the blocking constraint includes a soft blocking constraint, and the method of performing a second noise prevention process in the layout stage includes:

[0026] Increasing the occupied space of the standard cell according to the size information of the standard cell, placing the standard cell in a congestion-driven or timing-driven manner, and applying the soft blocking constraint around the standard cell to limit the density of the standard cell layout;

[0027] determining whether the size of the driving unit meets a preset size according to the size information of the driving unit, and if not, marking the driving unit as an unused unit to avoid use;

[0028] The layout planning stage and the layout stage are iterated multiple times, and the congestion, density, area and timing of the layout stage are ensured to meet the requirements by optimizing the layout of the macro cells, redefining the layout size and adding physical constraints.

[0029] Optionally, the method for performing the third noise prevention process in the clock tree synthesis and optimization stage includes:

[0030] Inserting a clock gating unit into the clock line to control the transmission of the clock signal;

[0031] Divide the critical paths in the clock tree into one group, and divide the non-critical paths in the clock tree into another group, so that the automated placement and routing tool optimizes each group separately when balancing the clock tree to avoid the non-critical paths affecting the critical paths;

[0032] Setting the line width and spacing of the clock line to twice the default values;

[0033] Adding shielding lines on both sides of the clock line;

[0034] If the parallel routing lengths of the interfering line and the disturbed line exceed a preset length, a buffer is inserted into the disturbed line, or the interfering line and the disturbed line are arranged on different metal interconnection layers to reduce the parallel routing lengths on the same metal interconnection layer, or the interfering line or the disturbed line is routed in a zigzag manner to reduce the parallel routing lengths; wherein the interfering line is a signal line that generates a noise signal source, and the disturbed line is a signal line that is affected by the noise.

[0035] Optionally, the method of performing the fourth noise prevention process in the wiring stage includes:

[0036] Increase the spacing between signal lines or use staggered routing to avoid parallel routing;

[0037] Use shielding or differential pair wiring for key signals to enhance anti-interference capabilities.

[0038] Optionally, the method of determining whether the noise after the routing stage is converged, and if not, generating a noise repair script and repairing the noise until the noise converges includes:

[0039] The resistor and capacitor parameter extraction stage in the digital back-end design process generates a standard parasitic parameter extraction file based on the data output in the wiring stage;

[0040] Performing signal integrity analysis and static timing analysis on the standard parasitic parameter extraction file, and generating a noise violation report;

[0041] Determining whether the noise has converged according to the noise violation report;

[0042] If not, perform noise violation repair to obtain a noise repair script, add an engineering change instruction stage before the resistor and capacitor parameter extraction stage, import the noise repair script into the engineering change instruction stage, and repair the noise in the engineering change instruction stage until the noise converges.

[0043] Optionally, the method for repairing noise in the engineering change order stage includes:

[0044] Increase the line width and line spacing of the signal line; weaken the driving ability of the interfering line; increase the driving ability of the disturbed line; insert a buffer into the disturbed line; add shielding line protection on both sides of the disturbed line;

[0045] The interfering line is a signal line that generates a noise signal source, and the disturbed line is a signal line that is affected by the noise.

[0046] Compared with the prior art, the present invention has the following beneficial effects:

[0047] The present invention provides a method for preventing and repairing noise in a digital chip. By performing noise prevention in the layout planning stage, layout stage, clock tree synthesis and optimization stage, and wiring stage in the early stage of the digital back-end design process, the probability and amount of noise generation can be reduced. By automatically forming a noise repair script and process in the later stage of the digital back-end design process, noise violations can be repaired efficiently and quickly. The early stage noise prevention processing can minimize the probability and amount of noise occurrence, so that the number of iterations can be reduced during the later stage repair, the development time cost can be reduced, and the efficiency can be improved.

[0048] Compared with the fragmented noise repair method of the prior art, the present invention starts from prevention and repair respectively, and forms a noise repair script and process for quickly repairing noise while minimizing the probability and amount of noise occurrence. It can effectively prevent and quickly repair noise in a more complete and systematic manner, greatly improving the noise repair efficiency and reducing the number of iterations of digital back-end design. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the present invention will be briefly introduced below. It should be understood that the following drawings only show certain technical solutions of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0050] Figure 1 One of the flow charts of a digital backend design provided by the present invention.

[0051] Figure 2 The present invention provides a flowchart of a method for preventing and repairing digital chip noise.

[0052] Figure 3 The second flowchart of a digital backend design provided by the present invention.

[0053] Figure 4 A module schematic diagram of a digital chip noise prevention and repair device provided by the present invention.

[0054] Figure numerals: 100 - digital chip noise prevention and repair device; 110 - first noise prevention module; 120 - second noise prevention module; 130 - third noise prevention module; 140 - fourth noise prevention module; 150 - noise repair module. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the drawings in the present invention. Obviously, the described technical solutions are part of the technical solutions of the present invention, but not all of the technical solutions. Generally, the components of the technical solutions of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the technical solutions of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents the selected technical solutions of the present invention. Based on the technical solutions in the present invention, all other technical solutions obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0057] In the description of the present invention, terms such as "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance. It should be noted that the features of the present invention can be combined with each other without conflict.

[0058] As described in the background technology, as the chip feature size gradually becomes smaller, the complexity of circuit wiring in the digital back-end physical design process continues to increase, causing signal integrity-related issues to become more serious. When the distance between multiple signal lines is too small, the voltage change on a certain signal line will affect the adjacent signal line through electromagnetic coupling, thereby generating noise. For the convenience of description, the signal line that generates the noise signal source is called the aggressor net, and the signal line affected by the noise is called the victim net. The impact of noise on the signal can be mainly divided into two categories: delay and glitch.

[0059] The impact of noise on signal delay is called delay noise, which means that the disturbed line itself is in the process of voltage change. At this time, the voltage change of the interfering line may speed up or slow down its change (this depends on whether the voltage changes of the disturbed line and the interfering line are in the same direction or opposite direction), making the voltage conversion time of the disturbed line longer or shorter, thereby causing timing errors.

[0060] The effect of noise on glitches is called functional noise, which means that the affected line is originally in a static or stable state, but the glitches are caused on the affected line due to the change in the voltage of the interfering line. If the glitches exceed the noise tolerance, the original signal value is changed, and the changed signal value is collected by the circuit, the circuit state will change, resulting in functional errors.

[0061] At present, the repair of noise mainly relies on manual repair by designers. After analyzing the results reported by the automated layout and routing tool one by one, manual repairs are performed on the places where noise violations occur, and then the wiring iterations are repeated. With the development of advanced process nodes and the increasing scale of projects, the number and time of iterations of digital chip back-end design are getting longer and longer. Therefore, reducing the number of iterations is very important for the race against time of the project. In addition, the traditional manual repair method is highly dependent on the experience of designers, with varying results and low efficiency.

[0062] Based on the above-mentioned problems of low noise repair efficiency and many iterations of digital back-end design, the present invention provides a method for preventing and repairing noise in a digital chip. The method starts from the two stages before and after the digital back-end design process, and prevents the generation of noise in the early stage of the digital back-end design process, thereby reducing the probability and amount of noise generation. In the later stage, an automatic repair script and process are formed to repair noise violations efficiently and quickly. The method starts with two means, prevention and repair, respectively, and forms an automated script and process for quickly repairing noise under the condition of minimizing the probability and amount of noise occurrence, which greatly improves the noise repair efficiency, reduces the number of iterations of digital back-end design, and reduces the development time cost.

[0063] To better understand the principles of the present invention, please refer to Figure 1 ,The following is an introduction to the entire digital back-end design process of the chip.

[0064] First, the Register Transfer Level (RTL) code of the front-end design is converted into the gate-level netlist and Standard Design Constraint (SDC) file required for the back-end design stage through the synthesis tool, that is, the timing rule constraints. Among them, the gate-level netlist is used to represent what functions are implemented, such as storage, delay and other functions. The SDC file is used to represent the timing rule constraints that have been set during chip design, such as the conditions that the timing needs to meet when the chip implements a certain function.

[0065] Next, in the data preparation stage, the files, data, environment or processes required for the back-end design are configured. Specifically, the system mainly configures the input parts and environment required for data preparation. Among them, the input parts include the gate-level netlist and timing rule constraints after RTL code synthesis, the timing library model (Timing Lib), and the process library (including process lef files and stdlef files, etc.). In addition, the operating environment of the digital back-end design process needs to be configured and inspected to ensure that the process is correct.

[0066] Then, the data is read in using the tool to initialize the data preparation phase. Initialization includes testing whether the logic of the timing rule constraints is correct. After the initialization is completed, the layout planning phase, layout phase, clock tree synthesis and optimization phase, and wiring phase will be entered in sequence. Specifically, the layout planning phase mainly realizes the planning of chip area size, macro units and power modules. In the layout phase, tools can be used to automatically place standard units. The clock tree synthesis and optimization phase can be achieved by setting target values ​​such as offset and delay, and using tools to insert buffer units in the physical layout. The wiring phase can realize the connection of various modules and units arranged in the layout phase.

[0067] In the embodiment of the present invention, in order to improve the efficiency of noise repair, noise prevention processing can be performed in the above-mentioned layout planning stage, layout stage, clock tree synthesis and optimization stage, and wiring stage, and a noise repair script is generated after the wiring stage to automatically repair the noise until the noise converges. Finally, the chip layout information without noise violations is output, and the manufacturer can carry out tape-out production based on the chip layout information.

[0068] Based on the above introduction to the entire digital back-end design process, the digital chip noise prevention and repair method provided by the present invention will be exemplarily described below.

[0069] As an alternative implementation, see Figure 2 , the method comprising:

[0070] Step 10: Obtain input parameters, perform layout planning based on the input parameters, and perform the first noise prevention process in the layout planning stage.

[0071] Step 20: Perform layout according to the input parameters and the results of layout planning, and perform a second noise prevention process during the layout stage.

[0072] Step 30: Perform clock tree synthesis and optimization based on the input parameters and layout results, and perform a third noise prevention process in the clock tree synthesis and optimization stage.

[0073] Step 40 , routing is performed according to the input parameters and the results of clock tree synthesis and optimization, and a fourth noise prevention process is performed during the routing stage.

[0074] Step 50: determine whether the noise after the routing stage has converged. If not, generate a noise repair script and repair the noise until the noise converges.

[0075] By preventing noise in the early layout planning stage, layout stage, clock tree synthesis and optimization stage, and routing stage, the probability and amount of noise can be minimized. This can reduce the number of iterations during later repairs, reduce development time costs, and improve efficiency.

[0076] The digital chip noise prevention and repair method provided by the present invention starts with the two means of prevention and repair respectively, and forms a noise repair script and process for quickly repairing noise under the condition of minimizing the probability and amount of noise occurrence, thereby avoiding excessive number of noise repair iterations in the later stage, improving the noise repair efficiency, and being able to effectively prevent and quickly repair noise in a more complete and systematic manner.

[0077] Combine the following Figure 3 , which details the noise handling methods at each stage of the digital back-end design process.

[0078] In an embodiment of the present invention, the input parameters required in the subsequent design process are obtained through the data reading stage. The input parameters include configuration parameters and the parameters of the functional module itself. The configuration parameters and the parameters of the functional module itself can be obtained from the gate-level netlist, timing rule constraints, timing library model, process library, and operating environment configuration.

[0079] Optionally, the configuration parameters include chip process parameters, metal interconnection layer parameters, data flow direction parameters, chip packaging rule constraints, design rule constraints, and blocking constraints, etc. Among them, the design rule constraints can be used to ensure that the semiconductor chip meets the specifications of the manufacturing process during physical design.

[0080] The functional module includes at least a macro unit, a standard unit and a driving unit, and the functional module's own parameters are used to characterize the type, quantity and size of the functional module. For example, the functional module's own parameters may include information such as the number of macro units, the type of macro units, the size of standard units, and the size of driving units.

[0081] Methods for performing layout planning based on input parameters and performing the first noise prevention process at the layout planning stage include:

[0082] First, the chip size is determined based on the chip manufacturing process parameters, metal interconnect layer parameters, and the functional module's own parameters.

[0083] Among them, the parameters of the functional module itself can be the number of macro units. Reasonable chip size is not only related to the cost of the chip, but also affects the performance of the chip and is one of the factors that restrict whether the subsequent layout and routing can continue. If the chip area is planned too small, the space resources available for layout and routing are limited, resulting in excessive density and congestion. The parameters of indicators such as design rule violations (DRV) and noise will eventually lead to design failure.

[0084] Second, the power module is placed on a high-level metal interconnect layer.

[0085] Since the high-level metal is thick, the line width and the resistance are small, this is not only beneficial to the overcurrent capacity, but also to the convergence of the voltage drop (IRDrop). If the IR Drop is too large, the power consumption and timing performance of the chip will be affected. In addition, the high-level metal interconnect layer can be used as a shielding layer to block external electromagnetic interference. The power module will generate a certain amount of electromagnetic radiation when working, which may interfere with other sensitive circuits. By setting the power module on the high-level metal interconnect layer, most of the external RF interference can be reflected and the electromagnetic coupling can be reduced, thereby protecting the circuit below from noise interference.

[0086] Third, the macro units are placed based on the chip size, the functional module's own parameters, the data flow direction parameters, the design rule constraints, and the chip packaging rule constraints.

[0087] If the placement of macro cells and the spacing between macro cells are not set properly, a large number of design rule violations, congestion, increased wiring, and increased probability and quantity of noise will occur. Therefore, in order to reduce the probability and quantity of noise, it is necessary to scientifically and reasonably place the macro cells in the layout planning stage.

[0088] The following rules are followed during the placement of macro units:

[0089] Plan the placement order of macro units according to the direction of data flow information, and ensure that the macro units are away from functional modules that are prone to generate high-frequency signals or noise.

[0090] When a macro cell is flipped or mirrored, the macro cell is flipped or mirrored according to the requirements corresponding to the design rule constraints. For example, the design document of the macro cell clearly states that a certain macro cell cannot be flipped or mirrored, but the designer flips or mirrors the macro cell during the placement process, which will cause design rule violations, noise generation and other problems. Therefore, when placing macro cells, it is necessary to combine the corresponding design rule constraints, data documents, and process files.

[0091] In addition, it should be noted that the parameters of the functional module itself contain the type information of the macro unit. The types of macro units can generally be divided into input / output units (IO), intellectual property units (IP), and memory units. Among them, the input / output unit is responsible for the exchange of signals inside and outside the macro unit; the intellectual property unit refers to the module that is packaged by the supplier or foundry and is used to implement a specific functional module, such as a module for signal conversion; the memory unit refers to a module used as a storage device.

[0092] The placement rules for macro units such as input and output units, intellectual property units, and storage units are as follows:

[0093] (1) Input and output units are placed at the edge of the chip, storage units and intellectual property units are placed around the core area of ​​the chip, and the center of the core area is reserved for standard units.

[0094] Since macro cells are usually large in size, by placing macro cells at the chip boundary (i.e. around the core area), macro cells can be avoided from becoming obstacles in the layout, and the cutting of the standard cell area (i.e. the center of the core area) can be reduced, thereby making the global wiring path smoother, reducing the routing length and corners, and improving signal integrity.

[0095] (2) Determine the placement of the input-output unit according to the chip packaging rule constraints, and reserve a first preset distance between the input-output unit and the core area.

[0096] The placement of the input and output units should first comply with the requirements corresponding to the chip packaging rules and constraints, that is, to facilitate the routing of the package pins. Secondly, a first preset distance needs to be reserved between the input and output units and the core area to avoid latchup. Good planning of the input and output unit positions makes the entire chip design layout concise and clear, avoiding loop windings, thereby reducing the probability of noise generation.

[0097] (3) A second preset distance is reserved between the IP unit and the core region, and a hard blocking constraint is imposed around the IP unit.

[0098] It should be noted that blocking constraints generally include hard blocking constraints and soft blocking constraints. Among them, hard blocking constraints indicate that no unit can be placed, and soft blocking constraints indicate that units can only be moved within certain specific time periods.

[0099] In an embodiment of the present invention, the distance between the intellectual property unit and the core area can be reserved as a second preset distance according to the requirements of the IP physical integration document. The second preset distance is smaller than the first preset distance. That is, the distance between the intellectual property unit and the core area is shorter than the distance between the input and output unit and the core area.

[0100] By applying hard blocking constraints around the IP unit, the IP unit can be forced to maintain sufficient isolation from other components. Among them, hard blocking constraints include place blocking constraints and route blocking constraints. Place blocking constraints can prevent other high-noise modules or signal lines from approaching sensitive IP units, so that electromagnetic interference from surrounding circuits is physically blocked, reducing the direct impact on the signals within the IP unit. Route blocking constraints guide routing tools to avoid specific areas to ensure that signal lines are not forced to form sharp angles or unnecessary long paths, which helps reduce signal delays, reflections, and crosstalk, thereby improving signal quality and reducing noise.

[0101] (4) Place multiple storage units back to back and ensure that the winding spacing between adjacent storage units meets the design rule constraints.

[0102] When placing memory cells back to back, you need to pay attention to their pin direction and spacing, ensure that the winding spacing between adjacent memory cells meets the design rule constraints, and avoid deep wells between memory cells, which will lead to winding difficulties, noise, timing degradation, etc. Reasonable placement of memory cells can reduce the crossing and parallel length between signal lines, thereby reducing crosstalk.

[0103] After the layout planning is completed, the layout phase begins. In the layout phase, the tool automatically places the standard cells according to the timing rule constraints and the macro cells and power modules that have been placed. The tool will also adjust the position of the standard cells based on factors such as timing, area, and congestion to optimize the layout results.

[0104] The method for performing the second noise prevention treatment at the layout stage is as follows:

[0105] First, reduce the layout density of standard cells.

[0106] When laying out standard cells, it is necessary to limit the density of standard cell layout. The smaller the density, the more space there is for later wiring and the lower the probability of noise generation.

[0107] In the embodiment of the present invention, methods for reducing the density of standard cells include but are not limited to the following:

[0108] (1) Increase the occupied space of the standard cell according to the size information of the standard cell.

[0109] Assuming that the actual size of the standard cell is 0.5um, in order to reduce the density of the standard cell, a certain amount of space can be left around the standard cell and the size of the standard cell can be increased to 0.6um. In this way, when the tool is laying out the 0.5um standard cell, it will consider the size of the standard cell to be 0.6um. By increasing the space occupied by the standard cell, the layout density of the standard cell is reduced, ensuring that the standard cell has more space in the subsequent layout and routing, thereby reducing the probability of noise generation.

[0110] (2) Use congestion-driven or timing-driven methods to place standard cells.

[0111] Using congestion drive to place standard cells can evenly distribute the use of wiring resources and reduce the increase in resistance and capacitance delays and signal integrity problems caused by local over-dense wiring. By avoiding the formation of high-density areas, the coupling between signal lines can be reduced, thereby reducing the probability and amount of noise caused by coupling capacitance. Using timing drive to place standard cells can reduce timing violations. Through reasonable layout, the quality of signal propagation can be improved, the steepness of signal edges can be reduced, and the generation of transient noise can be reduced.

[0112] (3) Apply soft blocking constraints around standard cells to limit the density of standard cell layout.

[0113] Although soft blocking constraints do not prohibit routing, by increasing the routing cost, they can guide the routing tool to avoid the standard cell area, thereby reducing the standard cell layout density and avoiding signal lines being too close to the standard cell, causing routing congestion.

[0114] In addition, by applying blocking constraints around standard cells, it is also possible to avoid placing standard cells between macro cells and in some dead corners, and to keep standard cells away from modules that are prone to generate high-frequency signals or noise, thereby reducing design rule violations, congestion, noise, etc.

[0115] Second, judging whether the size of the driving unit meets the preset size according to the size information of the driving unit, if not, marking the driving unit as an unused unit to avoid use.

[0116] Since a driver unit that is too large may cause waste of area and power consumption, and a driver unit that is too small may have insufficient driving force, causing design rule violations and noise problems, in order to reduce the probability and amount of noise generation, it is necessary to avoid using a driver unit that is too large or too small.

[0117] Specifically, it is determined whether the size of the driving unit meets the preset size based on the size information of the driving unit. If not, the driving unit that does not meet the preset size can be marked as a don't use unit through a script in the digital backend design process to avoid use.

[0118] Third, iterate the layout planning stage and layout stage multiple times, optimizing the layout of macro cells, redefining the layout size, and adding physical constraints to ensure that the congestion, density, area, and timing of the layout stage meet the requirements.

[0119] After the layout phase is completed, the clock tree synthesis and optimization phase begins. The main task of this phase is to create an efficient and balanced clock distribution network to ensure that the clock signal can be transmitted to each register or timing unit simultaneously and accurately. Specifically, the synthesis tool will perform clock tree synthesis based on the content and parameters in the design constraint file and the constraints in the process to shorten the clock tree as much as possible and optimize the clock tree. After the clock tree is synthesized, further timing optimization is performed for the setup time and hold time to facilitate the next step of routing.

[0120] The method for performing the third noise prevention process in the clock tree synthesis and optimization stage is as follows:

[0121] First, a clock gating unit is inserted into the clock line to control the transmission of the clock signal.

[0122] The clock line is the guarantee for controlling the function of the entire chip or the normal operation law, and the clock line has a high frequency, high power consumption, and a high probability and amount of noise interference. In order to reduce the power consumption of the clock line and the probability of being interfered by noise, in an embodiment of the present invention, a clock gating unit (clock gate) is inserted into the clock line to control the transmission of the clock signal. The clock gating unit is equivalent to the switch of the clock. When a certain clock is not needed, the clock line can be disconnected through the clock gating unit, thereby reducing power consumption. In addition, inserting a clock gating unit in the clock line is equivalent to adding a cutting buffer, which shortens the length of the clock line, thereby reducing the probability of noise generation.

[0123] Second, divide the critical paths in the clock tree into one group, and divide the non-critical paths in the clock tree into another group, so that the automated placement and routing tool can optimize each group separately when balancing the clock tree to avoid non-critical paths affecting critical paths.

[0124] During the clock tree synthesis process, the tool will insert multiple levels of buffers into multiple clock lines to ensure that most of the clock lines are balanced. Sometimes, in order to balance a non-critical clock line, the tool will also insert a large number of buffers on these critical paths, resulting in redundant buffers. This not only wastes area and power consumption, but may also make timing difficult to converge and increase noise.

[0125] In order to solve this problem, in an embodiment of the present invention, by dividing the critical path and non-critical path in the clock tree into two groups, and allowing the tool to insert buffers separately for these two groups when balancing the clock tree, it is possible to avoid the non-critical path affecting the critical path, thereby shortening the buffer level and reducing the probability and amount of noise generation. In addition, the clock line that is too long and affects the timing can be shortened, thereby reducing the probability and amount of noise generation while obtaining good timing.

[0126] Third, set the clock line width and spacing to twice the default values.

[0127] As an optional implementation, the line width and spacing of the clock line are set to twice the default values ​​according to the double width double space (2W2S) rule, which can increase the anti-interference ability and overcurrent capability of the clock line, thereby reducing the probability of the clock line being interfered by noise.

[0128] Fourth, add shielding lines on both sides of the clock line.

[0129] As another optional implementation, in order to increase the anti-interference capability of the clock line, shielding lines (eg, ground lines) may be added on both sides of the clock line to reduce coupling capacitor noise.

[0130] Fifth, if the parallel running length of the interfering line and the disturbed line exceeds the preset length, a buffer is inserted into the disturbed line to reduce the impact of noise on the disturbed line and improve its own anti-interference ability.

[0131] Alternatively, the disturbing line and the disturbed line are arranged on different metal interconnection layers to reduce the length of parallel lines on the same metal interconnection layer.

[0132] Alternatively, the interfering line or the disturbed line is arranged in a zigzag routing manner to reduce the length of the parallel routing, wherein the interfering line is a signal line generating a noise signal source, and the disturbed line is a signal line affected by the noise.

[0133] After the clock tree synthesis and optimization stage, the routing stage begins. The tool will use metal connections to implement the physical connection and detailed routing of the devices based on the logical connection relationship of the devices defined in the gate-level netlist, under the constraints of timing and process, and select the appropriate number of metal layers and metal wire lengths for physical routing.

[0134] The fourth noise prevention process at the wiring stage is as follows:

[0135] First, increase the spacing between signal lines or use staggered wiring to avoid parallel wiring.

[0136] For areas with high noise and loose winding (i.e. low density), the spacing between signal lines can be increased to improve the anti-interference ability of signal lines. For areas with high noise and tight winding (i.e. high density), staggered wiring can be used, for example, signal lines are set on different metal interconnect layers to avoid parallel wiring. In addition, during the wiring process, looping wiring should be avoided as much as possible, and the maximum length of wiring should be limited to avoid parallel connection or a single signal line that is too long to generate noise.

[0137] Second, use shielding or differential pair wiring for key signals to enhance anti-interference capabilities.

[0138] After the wiring is completed, the digital netlist and layout can be generated after the relevant design rule violations, timing and other indicators basically meet the requirements. At this time, the automatic inspection script written by the present invention can be used to check the maximum length of the signal line (max length), the number and density of the fixed level pins (tie load), the clock line and other indicators one by one, and print out a detailed report. The designer can check the problem points according to the errors and warnings in the report, and solve them one by one, so as to prevent noise well.

[0139] By performing different noise prevention processes in the above-mentioned layout planning stage, layout stage, clock tree synthesis and optimization stage, and routing stage, the probability of noise generation can be greatly reduced. The remaining noise can be repaired through the optimization verification process of the digital back-end design.

[0140] In an embodiment of the present invention, the optimization verification process of the digital back-end design includes a resistor and capacitor parameter extraction stage, a signal integrity analysis stage, and a static timing analysis stage.

[0141] During the physical design process, the delay of the standard cell is characterized by the timing library, that is, the delay of the standard cell can be parasitic directly in the timing library through the lookup table. The delay calculation of the interconnection line between the devices is estimated by the fan-out-length pair. Therefore, after the physical design is completed (that is, after the wiring stage is completed), the resistance and capacitance parameter extraction stage can be carried out to extract the resistance and capacitance parameters.

[0142] Specifically, in the resistor and capacitor parameter extraction stage, the parasitic extraction tool is used to refine the parasitic parameters (including resistors and capacitors) on the interconnection lines of the chip circuit, generate a standard parasitic parameter extraction file (SPEF file), and obtain accurate resistance and capacitance values ​​for calculating the delay on the interconnection lines.

[0143] The standard parasitic parameter extraction file generated in the resistor and capacitor parameter extraction phase is read into the signal integrity analysis phase and the static timing analysis phase. The signal integrity analysis phase is used to perform noise checks and analyze noise based on the obtained standard parasitic parameter extraction file. In the static timing analysis phase, the timing information of the timing path is reported using the timing tool based on the standard parasitic parameter extraction file. In the process of using the timing path reported by the tool, the option of reporting crosstalk or noise can be added. Designers can also analyze the severity of crosstalk through the index and optimize the noise while optimizing the timing for the path.

[0144] After the signal integrity analysis phase and the static timing analysis phase, a noise violation report will be generated. The noise violation report is used to determine whether the noise has converged (i.e., whether there is a noise violation).

[0145] If there is a noise violation, the violation point is found in the noise violation report, and then the driver point is found according to the violation point, and the driving force of the driver point is analyzed to perform noise repair. For example, if the driving force of the driver point is large, a buffer unit can be inserted into the network that generates the noise. If the driving force of the driver point is insufficient, its driving multiple can be increased.

[0146] That is, when the noise has not converged, you only need to import the noise violation report into the physical design tool, and the automatic repair will be completed, and finally a noise repair script will be generated. Add an Engineering Change Order (ECO) stage before the resistor and capacitor parameter extraction stage, import the noise repair script into the ECO stage, and repair the noise in the ECO stage. Use the ECO stage as the repair iteration stage to automatically repair the remaining noise violations by repeatedly iterating the small process from the ECO stage to the static timing analysis stage and the signal integrity analysis stage.

[0147] As an optional implementation, the method of repairing noise during the ECO routing phase includes but is not limited to: (1) increasing the line width and line spacing of the signal line. (2) reducing the driving capability of the interfering line. (3) increasing the driving capability of the disturbed line. (4) inserting a buffer into the disturbed line. (5) adding shielding line protection on both sides of the disturbed line.

[0148] During the engineering change order phase, noise repair is performed, the winding iteration is repeated and new data is generated. The data is obtained and the resistor and capacitor parameter extraction phase, signal integrity analysis phase, and static timing analysis phase are performed to complete the resistor and capacitor parameter extraction and noise analysis, complete a repair small process, and obtain a noise violation report. Then, based on the report, continue to check whether the noise has converged. If not, repeat this part of the small process until the noise converges.

[0149] Therefore, the present invention performs noise prevention in the early stage of the digital back-end design process and noise repair in the later stage of the digital back-end design process, and forms a noise repair script and process for quickly repairing noise under the condition of minimizing the probability and amount of noise occurrence. It can effectively prevent and quickly repair noise in a more complete and systematic manner, greatly improve the noise repair efficiency, and reduce the number of iterations of the digital back-end design.

[0150] Based on the above implementation, please refer to Figure 4 The present invention also provides a digital chip noise prevention and repair device 100, the device comprising:

[0151] The first noise prevention module 110 is used to perform layout planning according to input parameters and perform a first noise prevention process in the layout planning stage.

[0152] The second noise prevention module 120 is used to perform layout according to the input parameters and the result of the layout planning stage, and perform a second noise prevention process in the layout stage.

[0153] The third noise prevention module 130 is used to perform clock tree synthesis and optimization according to the input parameters and the results of the layout stage, and perform a third noise prevention process in the clock tree synthesis and optimization stage.

[0154] The fourth noise prevention module 140 is used to perform routing according to the input parameters and the results of the clock tree synthesis and optimization stage, and perform a fourth noise prevention process in the routing stage.

[0155] The noise repair module 150 is used to determine whether the noise after the routing stage is converged. If not, a noise repair script is generated and the noise is repaired until the noise is converged.

[0156] In summary, the present invention provides a method and device for preventing and repairing noise in a digital chip. By performing noise prevention in the layout planning stage, layout stage, clock tree synthesis and optimization stage, and wiring stage in the early stage of the digital back-end design process, the probability and amount of noise generation can be reduced. By automatically forming a noise repair script and process in the later stage of the digital back-end design process, noise violations can be repaired efficiently and quickly. The probability and amount of noise occurrence can be minimized through early noise prevention processing, so that the number of iterations can be reduced during later repairs, reducing development time costs and improving efficiency.

[0157] Compared with the fragmented noise repair method of the prior art, the present invention starts from prevention and repair respectively, and forms a noise repair script and process for quickly repairing noise while minimizing the probability and amount of noise occurrence. It can effectively prevent and quickly repair noise in a more complete and systematic manner, greatly improving the noise repair efficiency and reducing the number of iterations of digital back-end design.

[0158] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

[0159] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for preventing and repairing digital chip noise, characterized in that: The digital chip noise prevention and repair method comprises: Acquiring input parameters, performing layout planning according to the input parameters, and performing a first noise prevention process in the layout planning stage; Performing layout according to the input parameters and the result of the layout planning stage, and performing a second noise prevention process in the layout stage; Perform clock tree synthesis and optimization according to the input parameters and the result of the layout stage, and perform a third noise prevention process in the clock tree synthesis and optimization stage; Performing routing according to the input parameters and the results of the clock tree synthesis and optimization phase, and performing a fourth noise prevention process during the routing phase; Determine whether the noise after the wiring stage is converged, if not, generate a noise repair script, and repair the noise until the noise converges; The methods for performing the third noise prevention process in the clock tree synthesis and optimization stage include: Inserting a clock gating unit into the clock line to control the transmission of the clock signal; Divide the critical paths in the clock tree into one group, and divide the non-critical paths in the clock tree into another group, so that the automated placement and routing tool optimizes each group separately when balancing the clock tree to avoid the non-critical paths affecting the critical paths; Setting the line width and spacing of the clock line to twice the default values; Adding shielding lines on both sides of the clock line; If the parallel routing length of the interfering line and the disturbed line exceeds a preset length, a buffer is inserted into the disturbed line, or the interfering line and the disturbed line are arranged on different metal interconnection layers to reduce the length of the parallel routing on the same metal interconnection layer, or the interfering line or the disturbed line is arranged in a zigzag routing manner to reduce the length of the parallel routing; wherein the interfering line is a signal line generating a noise signal source, and the disturbed line is a signal line affected by the noise; The method of determining whether the noise after the routing stage has converged, and if not, generating a noise repair script and repairing the noise until the noise converges includes: The resistor and capacitor parameter extraction stage in the digital back-end design process generates a standard parasitic parameter extraction file based on the data output after the fourth noise prevention process in the wiring stage; Performing signal integrity analysis and static timing analysis on the standard parasitic parameter extraction file, and generating a noise violation report; Determining whether the noise has converged according to the noise violation report; If not, perform noise violation repair to obtain a noise repair script, add an engineering change instruction stage before the resistor and capacitor parameter extraction stage, import the noise repair script into the engineering change instruction stage, and repair the noise in the engineering change instruction stage until the noise converges.

2. The method for preventing and repairing digital chip noise according to claim 1, characterized in that: The input parameters include configuration parameters and the function module's own parameters; The configuration parameters include chip process parameters, metal interconnect layer parameters, data flow direction parameters, chip packaging rule constraints, design rule constraints and blocking constraints; The functional modules at least include macro cells, standard cells and driving cells, and the parameters of the functional modules themselves are used to characterize the type, quantity and size of the functional modules.

3. The method for preventing and repairing digital chip noise according to claim 2, characterized in that: The method for performing the first noise prevention process in the layout planning stage includes: Determine the size of the chip based on the chip process parameters, metal interconnection layer parameters and the functional module's own parameters, and set the power module on the high-level metal interconnection layer; The macro units are placed based on the size of the chip, the parameters of the functional modules themselves, the parameters of the direction of the data flow, the design rule constraints, and the chip packaging rule constraints.

4. The method for preventing and repairing digital chip noise according to claim 3, characterized in that: The types of the macro units include input and output units, intellectual property units and storage units. The blocking constraints include hard blocking constraints. The method for placing the macro units based on the size of the chip, the parameters of the functional modules themselves, the direction parameters of the data flow, the design rule constraints, and the chip packaging rule constraints includes: Planning the placement order of the macro units according to the direction parameters of the data flow, and ensuring that the macro units are away from functional modules that are prone to generate high-frequency signals or noise; When the macro unit is flipped or mirrored, the macro unit is flipped or mirrored according to the requirements corresponding to the design rule constraints; The input and output units are placed at the border of the chip, the storage units and the intellectual property units are placed around the core area of ​​the chip, and the center of the core area is reserved for placing the standard units; Determine the placement position of the input-output unit according to the chip packaging rule constraint, and reserve a first preset distance between the input-output unit and the core area; A second preset distance is reserved between the IP unit and the core area, and the hard blocking constraint is applied around the IP unit; wherein the second preset distance is smaller than the first preset distance; The plurality of storage units are placed back to back, and the winding spacing between adjacent storage units is ensured to meet the requirements of the design rule constraints.

5. The method for preventing and repairing digital chip noise according to claim 2, characterized in that: The blocking constraint includes a soft blocking constraint, and the method for performing a second noise prevention process in the layout stage includes: Increasing the occupied space of the standard cell according to the size information of the standard cell, placing the standard cell in a congestion-driven or timing-driven manner, and applying the soft blocking constraint around the standard cell to limit the density of the standard cell layout; determining whether the size of the driving unit meets a preset size according to the size information of the driving unit, and if not, marking the driving unit as an unused unit to avoid use; The layout planning stage and the layout stage are iterated multiple times, and the congestion, density, area and timing of the layout stage are ensured to meet the requirements by optimizing the layout of the macro cells, redefining the layout size and adding physical constraints.

6. The method for preventing and repairing digital chip noise according to claim 1, characterized in that: Methods for performing the fourth noise prevention process at the wiring stage include: Increase the spacing between signal lines or use staggered routing to avoid parallel routing; Use shielding or differential pair wiring for key signals to enhance anti-interference capabilities.

7. The method for preventing and repairing digital chip noise according to claim 1, characterized in that: The method for repairing noise during the engineering change order stage includes: Increase the line width and line spacing of signal lines; Weaken the driving ability of the interference line; Increase the driving capability of the disturbed line; inserting a buffer in the disturbed line; Adding shielding wire protection on both sides of the disturbed wire; The interfering line is a signal line that generates a noise signal source, and the disturbed line is a signal line that is affected by the noise.

8. A digital chip noise prevention and repair device, characterized in that: Used to execute the digital chip noise prevention and repair method according to any one of claims 1 to 7, the digital chip noise prevention and repair device comprises: A first noise prevention module, used to obtain input parameters, perform layout planning according to the input parameters, and perform a first noise prevention process in the layout planning stage; A second noise prevention module, used for performing layout according to the input parameters and the result of the layout planning stage, and performing a second noise prevention process in the layout stage; A third noise prevention module, configured to perform clock tree synthesis and optimization according to the input parameters and the result of the layout phase, and perform a third noise prevention process in the clock tree synthesis and optimization phase; a fourth noise prevention module, configured to perform routing according to the input parameters and the results of the clock tree synthesis and optimization phase, and perform a fourth noise prevention process in the routing phase; The noise repair module is used to determine whether the noise after the routing stage is converged. If not, a noise repair script is generated and the noise is repaired until the noise converges.

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