Gate drive circuit and driving method

Abstract

The present invention provides a gate drive circuit and drive method, wherein a control signal input module is connected to a signal processing module, which is in turn connected to a drive signal output module; the control signal input module transmits a control signal to a first branch node and / or a second branch node under the control of an enable signal; the signal processing module receives the control signal and processes the control signal under the control of a first clock signal to generate an intermediate signal; and the drive signal output module controls and outputs the control signal based on the intermediate signal to generate a drive signal. In this way, a gate drive circuit with a simple structure can be formed, simplifying the manufacturing process and enabling implementation based on LTPO technology; the control signal is processed and converted by the clock signal, so that the waveform of the drive signal outputted is normal and stable, thus resolving the problem that the existing drive circuit structure and process based on LTPO technology are complex and thus limited in display screen application.

Description

Technical Field

[0001] This invention relates to the field of display panel technology, and in particular to a gate driving circuit and driving method. Background Technology

[0002] Current gate drive circuits are quite complex and cannot meet user needs, so a new gate drive circuit is urgently needed. Summary of the Invention

[0003] The purpose of this invention is to provide a gate driving circuit and driving method to solve the problem that the existing gate driving circuit has a complex structure and process, which limits its application in display screens.

[0004] To address the aforementioned technical problems, this invention provides a gate driving circuit, comprising a control signal input module, a signal processing module, and a drive signal output module. The control signal input module is connected to the signal processing module via a first branch node and a second branch node, and the signal processing module is connected to the drive signal output module via a first connection node and a second connection node. The control signal input module transmits a control signal to the first branch node and / or the second branch node under the control of an enable signal. The signal processing module receives the control signal and processes it under the control of a first clock signal to generate an intermediate signal. The drive signal output module outputs a control signal based on the intermediate signal to generate a drive signal.

[0005] Optionally, in the gate driving circuit, the control signal includes a first control signal and a second control signal, and the control signal input module includes a first input unit and a second input unit; the first input unit is used to transmit the first control signal to a first branch node under the control of an enable signal; the second input unit is used to transmit the first control signal or the second control signal to a second branch node under the control of an enable signal; wherein, the voltage of the first control signal is less than the voltage of the second control signal.

[0006] Optionally, in the gate driving circuit, the first input unit includes a first transistor; the gate of the first transistor is connected to the enable signal, the first electrode of the first transistor is connected to the first control signal, and the second electrode of the first transistor is connected to the first branch node.

[0007] Optionally, in the gate driving circuit, the first input unit further includes a second transistor; the gate of the second transistor is connected to the enable signal, the first terminal of the second transistor is connected to the second control signal, and the second terminal of the second transistor is connected to the first branch node.

[0008] Optionally, in the gate driving circuit, the second input unit includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the enable signal, the first terminal of the third transistor is connected to the second control signal, and the second terminal of the third transistor is connected to the second branch node; the gate of the fourth transistor is connected to the enable signal, the first terminal of the fourth transistor is connected to the first control signal, and the second terminal of the fourth transistor is connected to the second branch node.

[0009] Optionally, in the gate driving circuit, the control signal further includes a third control signal, wherein the first terminal of the third transistor is connected to the third control signal to replace the second control signal, and the voltage of the third control signal is greater than the voltage of the second control signal.

[0010] Optionally, in the gate driving circuit, the signal processing module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the gate of the fifth transistor is connected to the first clock signal, the first terminal of the fifth transistor is connected to the first branch node, and the second terminal of the fifth transistor and the second terminal of the sixth transistor are connected to the first connection node; the first terminal of the sixth transistor is connected to the second control signal, and the gate of the sixth transistor is connected to the intermediate node; the gate of the seventh transistor is connected to the first clock signal, the first terminal of the seventh transistor is connected to the second branch node, and the second terminal of the seventh transistor is connected to the intermediate node; the gate of the eighth transistor is connected to the first control signal, the first terminal of the eighth transistor is connected to the intermediate node, and the second terminal of the eighth transistor is connected to the second connection node.

[0011] The intermediate signal includes a first intermediate signal and a second intermediate signal. The first connection node is used to transmit the first intermediate signal, and the second connection node is used to transmit the second intermediate signal. The first intermediate signal and the second intermediate signal control the generation of the drive signal by the drive signal output module.

[0012] Optionally, in the gate driving circuit, the driving signal output module includes a first output unit and a second output unit; the first output unit is used to output the second control signal as the driving signal in response to the first intermediate signal; the second output unit is used to output the first control signal as the driving signal in response to the second intermediate signal.

[0013] Optionally, in the gate driving circuit, the first output unit includes a ninth transistor and a first capacitor; the gate of the ninth transistor is connected to the first connection node, the first terminal of the ninth transistor is connected to the second control signal, and the second terminal of the ninth transistor is connected to the output terminal of the gate driving circuit; the two ends of the first capacitor are respectively connected to the gate and the first terminal of the ninth transistor.

[0014] Optionally, in the gate driving circuit, the second output unit includes a tenth transistor and a second capacitor; the gate of the tenth transistor is connected to the second connection node, the first terminal of the tenth transistor is connected to the first control signal, and the second terminal of the tenth transistor is connected to the output terminal of the gate driving circuit; one end of the second capacitor is connected to the second connection node, and the other end is input with a second clock signal.

[0015] Optionally, in the gate driving circuit, the period of the first clock signal is the same as the period of the second clock signal, and the duty cycle of the first clock signal is greater than the duty cycle of the second clock signal.

[0016] To solve the above technical problems, the present invention also provides a driving method applied to the gate driving circuit as described in any of the preceding claims, characterized in that the driving method includes:

[0017] When the enable signal is high and the first clock signal is high, the first branch node is low, the second branch node is high, the first connection node is high, the second connection node is low, and the drive signal is low.

[0018] When the enable signal is high and the first clock signal goes low, the first branch node goes low, the second branch node goes high, the first connection node goes low, the second connection node goes high, and the drive signal goes high.

[0019] When the enable signal goes low and the first clock signal goes high, the first branch node goes low, the second branch node goes low, the first connection node goes low, the second connection node goes high, and the drive signal goes high.

[0020] When the enable signal is low and the first clock signal goes low, the first branch node goes high, the second branch node goes low, the first connection node goes high, and the second connection node goes low. When the second clock signal goes low, the level of the second connection node drops again, and the drive signal goes low.

[0021] The gate driving circuit and driving method provided by this invention include a control signal input module, a signal processing module, and a driving signal output module. The control signal input module is connected to the signal processing module through a first branch node and a second branch node, and the signal processing module is connected to the driving signal output module through a first connection node and a second connection node. The control signal input module is used to transmit a control signal to the first branch node and / or the second branch node under the control of an enable signal. The signal processing module receives the control signal and processes it under the control of a first clock signal to generate an intermediate signal. The driving signal output module controls the output of the control signal according to the intermediate signal to generate a driving signal. Through circuit design, a simple gate driving circuit can be formed, thereby simplifying the manufacturing process. Furthermore, this gate driving circuit can be implemented based on LTPO technology. By processing and converting the input control signal using a clock signal, the waveform of the final output driving signal is normal and stable, solving the problem that existing LTPO-based driving circuits are complex in structure and process, limiting their application in displays. Attached Figure Description

[0022] Figure 1 This is a block diagram of the gate drive circuit provided in this embodiment;

[0023] Figure 2 The circuit schematic of the first gate drive circuit provided in this embodiment;

[0024] Figure 3 The circuit schematic of the second gate drive circuit provided in this embodiment;

[0025] Figure 4 The circuit schematic diagram of the third gate drive circuit provided in this embodiment;

[0026] Figure 5 The circuit timing control diagram of the first gate drive circuit provided in this embodiment;

[0027] Figure 6 The circuit timing control diagram of the cascaded gate drive circuit provided in this embodiment is shown. Detailed Implementation

[0028] The gate driving circuit and driving method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only used to facilitate and clarify the illustration of the embodiments of this invention. Furthermore, the structures shown in the drawings are often part of the actual structure. In particular, different figures may emphasize different aspects and sometimes use different scales.

[0029] It should be noted that the terms "first," "second," etc., used in the specification, claims, and drawings of this invention are used to distinguish similar objects in order to describe embodiments of the invention, and are not used to describe a specific order or sequence. It should be understood that such uses of terminology are interchangeable where appropriate. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] With the development of display technology, narrow bezel displays have become the main trend in the development of high-quality displays due to their advantages such as simplicity, aesthetics, and large viewable area for the same size. In order to reduce the area occupied by circuits in narrow bezel displays, GIP (gate driver in panel) technology is usually used. This technology uses the array process of the liquid crystal display panel to directly fabricate the gate driving circuit on the array substrate, thereby realizing a line-by-line scanning driving method for the gate.

[0031] Based on this, this embodiment provides a gate driving circuit, such as... Figure 1 As shown, the system includes a control signal input module, a signal processing module, and a drive signal output module. The control signal input module is connected to the signal processing module via a first branch node and a second branch node. The signal processing module is connected to the drive signal output module via a first connection node and a second connection node. The control signal input module transmits a control signal to the first branch node and / or the second branch node under the control of an enable signal. The signal processing module receives the control signal and processes it under the control of a first clock signal to generate an intermediate signal. The drive signal output module outputs a control signal based on the intermediate signal to generate a drive signal.

[0032] The gate drive circuit provided in this embodiment can be designed to form a simple gate drive circuit, thereby simplifying the manufacturing process. Moreover, the gate drive circuit can be implemented based on LTPO technology. By processing and converting the input control signal through a clock signal, the waveform of the final output drive signal is normal and stable, which solves the problem that the existing LTPO-based drive circuits are complex in structure and process and thus limited in display applications.

[0033] In practical applications, when there are multiple gate drive circuits, each gate drive circuit can be connected in a cascade manner. The specific connection method is consistent with the prior art, and this application will not elaborate on it further.

[0034] Furthermore, in this embodiment, the control signal includes a first control signal and a second control signal, and the control signal input module includes a first input unit and a second input unit; the first input unit is used to transmit the first control signal to a first branch node under the control of an enable signal; the second input unit is used to transmit either the first control signal or the second control signal to a second branch node under the control of an enable signal; wherein, the voltage of the first control signal is less than the voltage of the second control signal. In this way, the entire gate drive circuit is divided into two branches, thereby facilitating the signal processing module to compare and process the two control signals with different voltages input from the two input units.

[0035] Specifically, in this embodiment, such as Figure 2 As shown, in one possible embodiment, the first input unit includes a first transistor T1; the gate of the first transistor T1 is connected to the enable signal EIN, the first terminal of the first transistor T1 is connected to the first control signal VGL, and the second terminal of the first transistor T1 is connected to the first branch node n1.

[0036] Furthermore, in this embodiment, the second input unit includes a third transistor T3 and a fourth transistor T4; the gate of the third transistor T3 is connected to the enable signal EIN, the first terminal of the third transistor T3 is connected to the second control signal VGH, and the second terminal of the third transistor T3 is connected to the second branch node n2; the gate of the fourth transistor T4 is connected to the enable signal EIN, the first terminal of the fourth transistor T4 is connected to the first control signal VGL, and the second terminal of the fourth transistor T4 is connected to the second branch node n2.

[0037] In practical applications, the first transistor T1 is an NMOS TFT (N-type metal-oxide-semiconductor thin-film transistor), which can be an oxide TFT or an LTPS TFT. Similarly, the third transistor T3 is an NMOS TFT, which can be an oxide TFT or an LTPS TFT; and the fourth transistor T4 is a PMOS TFT (P-type metal-oxide-semiconductor thin-film transistor). Thus, when the enable signal is active (high level), the first transistor T1 and the third transistor T3 are turned on, resulting in the first control signal VGL (low level) being received at the first branch node n1, and the second control signal VGH (high level) being received at the second branch node n2.

[0038] In another embodiment, the first input unit can also be modified, specifically, as follows: Figure 3As shown, the first input unit further includes a second transistor T2; the gate of the second transistor T2 is connected to the enable signal EIN, the first terminal of the second transistor T2 is connected to the second control signal VGH, and the second terminal of the second transistor T2 is connected to the first branch node n1.

[0039] In practical applications, the second transistor is a PMOS TFT.

[0040] At this point, the first input unit and the second input unit have the same structure, except that the input control signals are swapped. In the first input unit, the NMOS TFT (first transistor T1) inputs the first control signal VGL, and the PMOS TFT (second transistor T2) inputs the second control signal VGH. In the second input unit, the NMOS TFT (third transistor T3) inputs the second control signal VGH, and the PMOS TFT (fourth transistor T4) inputs the first control signal VGL. In this way, not only is the first branch node n1 at a low level and the second branch node n2 at a high level when the enable signal EIN is valid, but the addition of the second transistor T2 also ensures that the voltage at the first branch node n1 is more stable.

[0041] In another embodiment, the control signal input to the second input unit can also be changed, specifically, as follows: Figure 4 As shown, the control signal also includes a third control signal. The first terminal of the third transistor T3 is connected to the third control signal VGH2 to replace the second control signal VGH. The voltage of the third control signal VGH2 is greater than the voltage of the second control signal VGH. This ensures that the third transistor T3 is in the off state, avoids the possibility of leakage between the third transistor T3 and the fourth transistor T4, and improves the stability of the circuit.

[0042] Furthermore, in this embodiment, as Figure 2As shown, the signal processing module includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. The gate of the fifth transistor T5 is connected to the first clock signal CK1, the first terminal of the fifth transistor is connected to the first branch node n1, and the second terminal of the fifth transistor and the second terminal of the sixth transistor T6 are connected to the first connection node n4. The first terminal of the sixth transistor T6 is connected to the second control signal VGH, and the gate of the sixth transistor T6 is connected to the intermediate node n3. The gate of the seventh transistor T7 is connected to the first clock signal CK1, the first terminal of the seventh transistor T7 is connected to the second branch node n2, and the second terminal of the seventh transistor T7 is connected to the intermediate node n3. The gate of the eighth transistor T8 is connected to the first control signal VGL, the first terminal of the eighth transistor T8 is connected to the intermediate node n3, and the second terminal of the eighth transistor T8 is connected to the second connection node n5.

[0043] In this embodiment, the intermediate signal includes a first intermediate signal and a second intermediate signal. The first connection node n4 is used to transmit the first intermediate signal, and the second connection node n5 is used to transmit the second intermediate signal. The first intermediate signal and the second intermediate signal control the generation of the drive signal by the drive signal output module.

[0044] In practical applications, the fifth, sixth, seventh, and eighth transistors are all PMOS TFTs. Since the signal processing module includes only four transistors of the same type and specifications, the circuit structure is simplified, effectively reducing the overall circuit footprint and power consumption, thus lowering the overall cost. Furthermore, by changing the signal voltage connected to the gate of each transistor and the voltage at its first electrode, the switching on and off of the transistors can be controlled, thereby changing the voltage at the output of the transistor's second electrode, and thus controlling the generation of the drive signal by the drive signal output module.

[0045] Furthermore, in this embodiment, the drive signal output module includes a first output unit and a second output unit; the first output unit is used to output the second control signal as the drive signal in response to the first intermediate signal; the second output unit is used to output the first control signal as the drive signal in response to the second intermediate signal.

[0046] Specifically, in this embodiment, such as Figure 2As shown, the first output unit includes a ninth transistor T9 and a first capacitor C1; the gate of the ninth transistor T9 is connected to the first connection node n4, the first terminal of the ninth transistor T9 is connected to the second control signal VGH, and the second terminal of the ninth transistor T9 is connected to the output terminal of the gate drive circuit; the two ends of the first capacitor C1 are connected to the gate and the first terminal of the ninth transistor T9, respectively.

[0047] In practical applications, the ninth transistor T9 is a PMOS TFT; the value of the first capacitor C1 can be 200fF. Of course, in different application scenarios, such as when the specifications of the transistor are different, the value of the first capacitor C1 may be different. The optimal value of the first capacitor C1 can be obtained through simulation.

[0048] In this embodiment, the second output unit includes a tenth transistor T10 and a second capacitor C2; the gate of the tenth transistor T10 is connected to the second connection node n5, the first terminal of the tenth transistor T10 is connected to the first control signal VGL, and the second terminal of the tenth transistor T10 is connected to the output terminal of the gate drive circuit; one end of the second capacitor C2 is connected to the second connection node n5, and the other end is input to the second clock signal CK2.

[0049] In practical applications, the tenth transistor T10 is a PMOS TFT; the value of the second capacitor C2 can be 100fF. Similarly, in different application scenarios, such as when the transistor specifications are different, the value of the second capacitor C2 may be different. The optimal value of the second capacitor C2 can be obtained through simulation.

[0050] In this way, by utilizing the electrical characteristics of capacitors and combining them with the changes in the gate and first electrode voltages of each transistor in the drive signal output module, the high and low levels of the final output drive signal can be controlled accordingly.

[0051] In practical applications, the first terminal of each transistor can be the source, and the second terminal can be the drain.

[0052] Preferably, in this embodiment, the period of the first clock signal CK1 is the same as the period of the second clock signal CK2, and the duty cycle of the first clock signal CK1 is greater than the duty cycle of the second clock signal CK2.

[0053] In this embodiment, the falling edges (level change from high to low) of the first clock signal CK1 and the second clock signal CK2 affect the level changes at the first connection node n4 and the second connection node n5. Therefore, in order to generate a bootstrap effect at the second connection node n5 and ensure the stability of the drive signal output, the falling edge of the second clock signal CK2 needs to be slightly delayed compared to the falling edge of the first clock signal CK1. Specifically, depending on the actual situation, a reasonable delay of 0.2 to 1 μs can be made to ensure that there is no significant delay when the drive signal changes from high to low. In practical applications, the clock signals are usually set symmetrically, that is, the low-level range of the second clock signal CK2 is located in the middle of the low-level range of the first clock signal CK1, so that the duty cycle of the first clock signal CK1 is greater than the duty cycle of the second clock signal CK2.

[0054] See below. Figure 2 , Figure 5 and Figure 6 The driving method (working process) of the gate driving circuit provided in this embodiment will be described in detail.

[0055] In this embodiment, as Figure 2 and Figure 5 As shown, the driving method of the gate driving circuit includes:

[0056] When the enable signal EIN is high and the first clock signal CK1 is high, the first transistor T1 and the third transistor T3 are turned on, so the first branch node n1 is low and the second branch node n2 is high. At the same time, the intermediate node n3 remains low, so the first connection node n4 is high and the second connection node n5 is low. At this time, the tenth transistor T10 is turned on and the drive signal EM is low.

[0057] When the enable signal EIN is high and the first clock signal CK1 goes low, the first branch node n1 is still low and the second branch node n2 is still high. However, at this time, the seventh transistor T7 turns on, making the intermediate node n3 go high. At the same time, the ninth transistor T9 turns on, making the first connection node n4 go low and the second connection node n5 go high. The tenth transistor T10 turns off, and the drive signal EM goes high.

[0058] During the period when the enable signal EIN is high, regardless of how the first clock signal CK1 changes, each node maintains the state of the previous moment, that is, the first connection node n4 maintains a low level, the second connection node n5 maintains a high level, and the drive signal EM maintains a high level.

[0059] When the enable signal EIN goes low and the first clock signal CK1 goes high, the first transistor T1 and the third transistor T3 are turned off and the fourth transistor T4 is turned on. As a result, the first branch node n1 is low and the second branch node n2 is low. At the same time, since the first clock signal CK1 is high, the first connection node n4 remains low, the intermediate node n3 and the second connection node n5 remain high, and the drive signal EM is high.

[0060] When the enable signal EIN is low and the first clock signal CK1 goes low, the first branch node n1 is reset to high, the second branch node n2 and the intermediate node n3 are low, the fifth transistor T5 and the sixth transistor T6 are turned on, the first connection node n4 is reset to high, the tenth transistor T10 is turned on and the ninth transistor T9 is turned off, and the second connection node n5 goes low. When the second clock signal CK2 goes low after a short period of time (e.g., 1μs), the level of the second connection node n5 is reduced again due to the bootstrap effect (the second capacitor C2 couples the voltage at the second connection node n5 from VGL-Vth to a lower level than VGL, where Vth is the turn-off voltage of the tenth transistor T10), causing the tenth transistor T10 to be fully turned on, and the drive signal EM is low, specifically the first control signal VGL. When the second clock signal CK2 goes high, the second connection node n5 is coupled back to VGL-Vth, at which point the tenth transistor T10 is in a near-off state, and the drive signal EM remains at the low level VGL.

[0061] When the enable signal EIN is low, the first branch node n1 becomes low, the second branch node n2 becomes high, while the intermediate node n3, the first connection node n4, and the second connection node n5 maintain the state of the previous moment, that is, the first connection node n4 remains high, the second connection node n5 remains low, and the drive signal EM remains low at VGL.

[0062] In practical applications, when multiple cascaded gate drive circuits exist, their timing diagrams are as follows: Figure 6 As shown, the gate drive circuit structures of each stage are identical. When the first clock signal of the even-numbered gate drive circuit is CK1 and the second clock signal is CK2, the first clock signal of the odd-numbered gate drive circuit is CK3 and the second clock signal is CK4. Figure 6 It can be seen that the first clock signal CK3 and the second clock signal CK4 of the odd-numbered levels are ahead of the first clock signal CK1 and the second clock signal CK2 of the even-numbered levels, respectively. Moreover, the periods of each clock signal are the same. Regardless of whether it is an odd-numbered or even-numbered level, the duty cycle of the first clock signal is the same, and the duty cycle of the second clock signal is also the same, thereby ensuring that the driving signal output of each level is controlled in a consistent manner.

[0063] It should be noted that, Figure 6 The timing diagram shown focuses on illustrating the relationship between the clock signals of the odd-level gate drive circuit and the even-level gate drive circuit. The timing of the first connection node n4, the second connection node n5, and the drive signal EM corresponds to the clock signals CK1 and CK2 of the even-level gate drive circuit. The timing of the first connection node n4, the second connection node n5, and the drive signal EM corresponding to the odd-level gate drive circuit can be obtained from the timing diagram of the even-level gate drive circuit, and will not be elaborated further in this application.

[0064] The gate driving circuit provided in this embodiment uses a total of 9 transistors (TFTs) and 2 capacitors. The circuit structure is simple and occupies a small area, making it suitable for narrow bezel displays. In addition, two N-type transistors (NMOS TFTs) are used in the control signal input module. The two NMOS TFTs can be manufactured using LTPO technology, which provides a driving circuit with a simple structure and process under LTPO technology. This allows LTPO technology to be applied to narrow bezel scenarios, thus broadening the application scope of LTPO technology.

[0065] Furthermore, this embodiment also provides a display device including the gate driving circuit described above. In practical applications, those skilled in the art can obtain a display device having the gate driving circuit provided in this application and the corresponding manufacturing process based on the prior art and the gate driving circuit provided in this application, which will not be elaborated further in this application.

[0066] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to mutually. In addition, the different parts between embodiments can also be combined with each other, and this invention does not limit this.

[0067] The gate driving circuit and driving method provided in this embodiment include a control signal input module, a signal processing module, and a driving signal output module. The control signal input module is connected to the signal processing module through a first branch node and a second branch node, and the signal processing module is connected to the driving signal output module through a first connection node and a second connection node. The control signal input module is used to transmit a control signal to the first branch node and / or the second branch node under the control of an enable signal. The signal processing module receives the control signal and processes it under the control of a first clock signal to generate an intermediate signal. The driving signal output module controls the output of the control signal according to the intermediate signal to generate a driving signal. Through circuit design, a simple gate driving circuit can be formed, thereby simplifying the manufacturing process. Furthermore, this gate driving circuit can be implemented based on LTPO technology. By processing and converting the input control signal using a clock signal, the final output driving signal waveform is normal and stable, solving the problem that existing LTPO-based driving circuits are complex in structure and process, limiting their application in displays.

[0068] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A gate driving circuit, characterized in that, The system includes a control signal input module, a signal processing module, and a drive signal output module. The control signal input module is connected to the signal processing module via a first branch node and a second branch node. The signal processing module is connected to the drive signal output module via a first connection node and a second connection node. The control signal input module transmits a control signal to the first branch node and / or the second branch node under the control of an enable signal. The signal processing module receives the control signal and processes it under the control of a first clock signal to generate an intermediate signal. The drive signal output module outputs a control signal based on the intermediate signal to generate a drive signal. The control signal includes a first control signal and a second control signal, and the control signal input module includes a first input unit and a second input unit; the first input unit is used to transmit the first control signal to a first branch node under the control of an enable signal; the second input unit is used to transmit either the first control signal or the second control signal to a second branch node under the control of an enable signal; wherein, the voltage of the first control signal is less than the voltage of the second control signal; The signal processing module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The gate of the fifth transistor is connected to the first clock signal, the first terminal of the fifth transistor is connected to the first branch node, and the second terminal of the fifth transistor and the second terminal of the sixth transistor are connected to the first connection node. The first terminal of the sixth transistor is connected to the second control signal, and the gate of the sixth transistor is connected to the intermediate node. The gate of the seventh transistor is connected to the first clock signal, the first terminal of the seventh transistor is connected to the second branch node, and the second terminal of the seventh transistor is connected to the intermediate node. The gate of the eighth transistor is connected to the first control signal, the first terminal of the eighth transistor is connected to the intermediate node, and the second terminal of the eighth transistor is connected to the second connection node. The intermediate signal includes a first intermediate signal and a second intermediate signal. The first connection node is used to transmit the first intermediate signal, and the second connection node is used to transmit the second intermediate signal. The first intermediate signal and the second intermediate signal control the generation of the drive signal by the drive signal output module.

2. The gate driving circuit according to claim 1, characterized in that, The first input unit includes a first transistor; the gate of the first transistor is connected to the enable signal, the first terminal of the first transistor is connected to the first control signal, and the second terminal of the first transistor is connected to the first branch node.

3. The gate driving circuit according to claim 2, characterized in that, The first input unit further includes a second transistor; the gate of the second transistor is connected to the enable signal, the first terminal of the second transistor is connected to the second control signal, and the second terminal of the second transistor is connected to the first branch node.

4. The gate driving circuit according to claim 1, characterized in that, The second input unit includes a third transistor and a fourth transistor; the gate of the third transistor is connected to the enable signal, the first terminal of the third transistor is connected to the second control signal, and the second terminal of the third transistor is connected to the second branch node; the gate of the fourth transistor is connected to the enable signal, the first terminal of the fourth transistor is connected to the first control signal, and the second terminal of the fourth transistor is connected to the second branch node.

5. The gate driving circuit according to claim 4, characterized in that, The control signal also includes a third control signal, wherein the first terminal of the third transistor is connected to the third control signal to replace the second control signal, and the voltage of the third control signal is greater than the voltage of the second control signal.

6. The gate driving circuit according to claim 1, characterized in that, The drive signal output module includes a first output unit and a second output unit; the first output unit is used to output the second control signal as the drive signal in response to the first intermediate signal; the second output unit is used to output the first control signal as the drive signal in response to the second intermediate signal.

7. The gate driving circuit according to claim 6, characterized in that, The first output unit includes a ninth transistor and a first capacitor; the gate of the ninth transistor is connected to the first connection node, the first terminal of the ninth transistor is connected to the second control signal, and the second terminal of the ninth transistor is connected to the output terminal of the gate driving circuit. The two ends of the first capacitor are respectively connected to the gate and the first electrode of the ninth transistor.

8. The gate driving circuit according to claim 6, characterized in that, The second output unit includes a tenth transistor and a second capacitor; the gate of the tenth transistor is connected to the second connection node, the first terminal of the tenth transistor is connected to the first control signal, and the second terminal of the tenth transistor is connected to the output terminal of the gate drive circuit. One end of the second capacitor is connected to the second connection node, and the other end is input with a second clock signal.

9. The gate driving circuit according to claim 8, characterized in that, The period of the first clock signal is the same as the period of the second clock signal, and the duty cycle of the first clock signal is greater than the duty cycle of the second clock signal.

10. A driving method applied to the gate driving circuit as described in any one of claims 1 to 9, characterized in that, The driving method includes: When the enable signal is high and the first clock signal is high, the first branch node is low, the second branch node is high, the first connection node is high, the second connection node is low, and the drive signal is low. When the enable signal is high and the first clock signal goes low, the first branch node goes low, the second branch node goes high, the first connection node goes low, the second connection node goes high, and the drive signal goes high. When the enable signal goes low and the first clock signal goes high, the first branch node goes low, the second branch node goes low, the first connection node goes low, the second connection node goes high, and the drive signal goes high. When the enable signal is low and the first clock signal goes low, the first branch node goes high, the second branch node goes low, the first connection node goes high, and the second connection node goes low. When the second clock signal goes low, the level of the second connection node drops again, and the drive signal goes low.

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