A semiconductor device and a method of fabricating the same

Abstract

The embodiment of the present application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate; an epitaxial structure located on one side of the substrate and comprising a first two-dimensional electron gas located on an active region; a deposition connecting structure located on a side of the epitaxial structure away from the substrate, and the deposition connecting structure is electrically connected with the first two-dimensional electron gas; a conductive structure located on a passive region and electrically connected with the first two-dimensional electron gas, the conductive connecting structure is used for electrical connection with a cathode in a deposition slot; a deposition structure located on a side of the deposition connecting structure away from the substrate, and the deposition structure is in contact with the deposition connecting structure for electrical connection. By adopting the above technical scheme, the process flow of the deposition structure can be simplified and the geometry of the deposition structure can be improved by adding the conductive structure in the passive region and taking the first two-dimensional electron gas as a connecting bridge between the conductive structure and the deposition connecting structure, so as to reduce the production cost and improve the device reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor device and a preparation method thereof. BACKGROUND

[0002] Gallium nitride semiconductor material has become a research hotspot due to its large band gap, high electron saturation drift velocity, high breakdown field strength, good heat conduction performance and other characteristics.

[0003] At present, in order to meet the requirements of large current and high reliability, a thick metal is generally electrodeposited in the drain, source and wire bonding area of the chip. Before electrodeposition, a seed metal layer is evaporated or sputtered. After the seed metal process is completed, the seed metal layer at the position not subjected to electrodeposition needs to be covered with photoresist, and then metal electrodeposition is performed. After the electrodeposition of the metal is completed, a stripping process is generally used to strip the two photoresist layers and the seed metal layer, and then a passivation layer is formed on the upper surface for protection.

[0004] However, the electrodeposition process in the prior art requires at least two masks, and the preparation process is complex and the cost is high. Moreover, the electrodeposition using two masks results in a T-shaped metal structure, which reduces the growth quality of the subsequent passivation layer, and thus failure may occur under certain environmental conditions (such as high humidity). SUMMARY

[0005] Embodiments of the present application provide a semiconductor device and a preparation method thereof. By providing a conductive structure in the passive region and using the two-dimensional electron gas as a connecting bridge between the conductive structure and the deposition connecting structure, the process flow of the deposition structure is simplified and the geometry of the deposition structure is improved, thereby reducing the production cost and improving the reliability of the device.

[0006] In a first aspect, embodiments of the present application provide a semiconductor device, comprising an active region and a passive region surrounding the active region.

[0007] The semiconductor device further comprises:

[0008] a substrate;

[0009] an epitaxial structure located on one side of the substrate, and the epitaxial structure comprises a two-dimensional electron gas located in the active region;

[0010] a deposition connecting structure located on a side of the epitaxial structure away from the substrate, and the deposition connecting structure is electrically connected to the first two-dimensional electron gas;

[0011] a conductive structure at least partially located in the passive region and electrically connected to the first two-dimensional electron gas, and the conductive connecting structure is used to electrically connect with a cathode in a deposition tank;

[0012] A deposition structure is located on a side of the deposition connecting structure away from the substrate, and the deposition structure is in electrical contact with the deposition connecting structure.

[0013] Optionally, the semiconductor device comprises at least two chip structures, the first two-dimensional electron gas in any two adjacent chip structures is electrically connected through the conductive structure, and the deposition connecting structures in the at least two chip structures form an equipotential structure through the conductive structure.

[0014] Optionally, the conductive structure comprises a second two-dimensional electron gas located in the passive region and in the epitaxial structure.

[0015] Optionally, the conductive structure comprises a connection trace at least partially located in the passive region.

[0016] Optionally, the at least two chip structures are arranged in a first direction and a second direction; the first direction and the second direction intersect and are both parallel to the plane in which the substrate is located.

[0017] The connection trace comprises a first connection trace and a second connection trace, the first connection trace extends in the first direction, and the second connection trace extends in the second direction.

[0018] Two chip structures arranged adjacent in the first direction are electrically connected through the second two-dimensional electron gas, and / or two chip structures arranged adjacent in the first direction are electrically connected through the first connection trace.

[0019] Two chip structures arranged adjacent in the second direction are electrically connected through the second two-dimensional electron gas and the second connection trace, and / or two chip structures arranged adjacent in the second direction are electrically connected through the first connection trace and the second connection trace.

[0020] Optionally, the deposition structure comprises a first surface close to the substrate and a second surface away from the substrate.

[0021] The vertical projection of the first surface on the plane in which the substrate is located covers the vertical projection of the second surface on the plane in which the substrate is located.

[0022] Optionally, the deposition connecting structure comprises at least one of a source electrode located in the active region, a drain electrode, a first pad connected to the drain electrode and located in the passive region, and a second pad electrically connected to the gate electrode and located in the passive region; the source electrode and the drain electrode are electrically connected to the first two-dimensional electron gas through an ohmic contact, and the gate electrode forms an electrical contact with the first two-dimensional electron gas through a Schottky junction.

[0023] The deposition structure includes at least one of a first deposition structure located in the active region and in contact with the source electrode and the drain electrode, a second deposition structure located in the passive region and in contact with the first pad, and a third deposition structure located in the passive region and in contact with the second pad.

[0024] In a second aspect, the embodiments of the present application further provide a method for manufacturing a semiconductor device, comprising:

[0025] providing a substrate and manufacturing an epitaxial structure on one side of the substrate, the epitaxial structure including a first two-dimensional electron gas in an active region;

[0026] manufacturing a deposition connection structure on a side of the epitaxial structure away from the substrate, the deposition connection structure being in contact with the first two-dimensional electron gas;

[0027] manufacturing a conductive structure in at least a passive region, the conductive structure being in electrical connection with the first two-dimensional electron gas, and the deposition connection structure forming an equipotential structure through the conductive structure;

[0028] arranging the semiconductor device in a deposition tank and electrically connecting the conductive structure with a cathode in the deposition tank;

[0029] manufacturing a deposition structure on a side of the deposition connection structure away from the substrate, the deposition structure being in electrical connection with the deposition connection structure.

[0030] Optionally, manufacturing a deposition structure on a side of the deposition connection structure away from the substrate, comprises:

[0031] manufacturing a negative photoresist on a side of the deposition connection structure away from the substrate;

[0032] exposing and developing the negative photoresist to form a photoresist opening in the negative photoresist, the photoresist opening exposing part of the deposition connection structure; an opening area of the photoresist opening on a side close to the substrate is greater than an opening area of the photoresist opening on a side away from the substrate;

[0033] manufacturing a deposition structure in the photoresist opening, the deposition structure including a first surface on a side close to the substrate and a second surface on a side away from the substrate, a vertical projection of the first surface on a plane where the substrate is located covering a vertical projection of the second surface on the plane where the substrate is located.

[0034] Optionally, manufacturing a deposition structure in the photoresist opening, comprises:

[0035] controlling a thickness of the deposition structure to be less than a thickness of the negative photoresist;

[0036] The preparation method further comprises:

[0037] The negative photoresist is removed.

[0038] Optionally, a deposition structure is prepared on the side of the deposition connection structure away from the substrate, comprising:

[0039] A first mask structure is used to prepare a deposition structure on the side of the deposition connection structure away from the substrate;

[0040] The preparation method further comprises:

[0041] The first mask structure is used to prepare an adhesion layer on the side of the deposition structure away from the substrate;

[0042] A passivation layer is prepared on the side of the adhesion layer away from the substrate.

[0043] The semiconductor device provided by the embodiment of the present application can simplify the process flow of the deposition structure and improve the geometry of the deposition structure by arranging the conductive structure in the passive region and taking the first two-dimensional electron gas as a connecting bridge between the conductive structure and the deposition connection structure, thereby reducing the production cost and improving the device reliability. In the embodiment of the present application, the first two-dimensional electron gas in the epitaxial structure can be used as a carrier, and the conductive structure and the deposition connection structure are both electrically connected to the first two-dimensional electron gas. In this way, the deposition connection structure forms an equipotential structure through the first two-dimensional electron gas and can be used as a "deposition seed layer" of the deposition structure. The deposition connection structure can be directly used for the deposition of the deposition structure, and a seed metal layer does not need to be prepared separately, thereby simplifying the process flow of the deposition structure and reducing the production cost of the deposition structure. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 A top view structural schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0045] Figure 2 A sectional view structural schematic diagram of a semiconductor device provided by the embodiment of the present application;

[0046] Figure 3 A top view structural schematic diagram of another semiconductor device provided by the embodiment of the present application;

[0047] Figure 4 A sectional view structural schematic diagram of another semiconductor device provided by the embodiment of the present application;

[0048] Figure 5 A flowchart of a preparation method of a semiconductor device provided by the embodiment of the present application;

[0049] Figure 6Another flow chart of a method for manufacturing a semiconductor device is provided in the embodiments of the present application.

[0050] Figure 7 A structure diagram for forming a photoresist opening in a negative photoresist is provided in the embodiments of the present application.

[0051] Figure 8 A structure diagram for manufacturing a deposition structure in the photoresist opening is provided in the embodiments of the present application.

[0052] Figure 9 Another flow chart of a method for manufacturing a semiconductor device is provided in the embodiments of the present application. DETAILED DESCRIPTION

[0053] The present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application. In addition, it should be noted that only the parts related to the present application are shown in the drawings for the convenience of description.

[0054] Before introducing the semiconductor device provided in the embodiments of the present application, the working principle of electro-deposition and the process of manufacturing a deposition structure in the prior art are briefly described.

[0055] In the prior art, a deposition metal is generally formed in a specific area of a semiconductor device by the principle of electro-deposition. Since the position where the deposition metal is formed must be conductive, and there is no equipotential structure in the prior semiconductor device, a seed metal layer is evaporated or sputtered before electro-deposition as an equipotential structure in the electro-deposition process. The manufacturing process of the seed metal layer is complex and high in cost, and increases the film thickness of the semiconductor device.

[0056] In view of the defects in the prior art, the embodiments of the present application provide a semiconductor device to simplify the process flow of the deposition structure and reduce the production cost of the deposition structure. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts fall within the scope of the present application.

[0057] Specifically, Figure 1 A top view structure diagram of a semiconductor device provided in the embodiments of the present application is shown in FIG. 1, Figure 2 is a sectional structure diagram of a semiconductor device provided in the embodiments of the present application, as shown in FIG. 2, Figure 1 and Figure 2As shown, the semiconductor device includes an active region aa and a passive region bb surrounding the active region aa; the semiconductor device further includes a substrate 110; an epitaxial structure 120 located on one side of the substrate 110 and the epitaxial structure 120 includes a first two-dimensional electron gas; a deposition connecting structure 210 located on a side of the epitaxial structure 120 away from the substrate 110, and the deposition connecting structure 210 is electrically connected with the first two-dimensional electron gas; a conductive structure 10 at least partially located in the passive region bb and electrically connected with the first two-dimensional electron gas, the conductive structure 10 is used to be electrically connected with a cathode in a deposition slot; a deposition structure 220 located on a side of the deposition connecting structure 210 away from the substrate 110, and the deposition structure 220 is in contact with the deposition connecting structure 210 and electrically connected.

[0058] For example, the substrate 110 can be formed by one of silicon, sapphire, silicon carbide, gallium arsenide. The epitaxial structure 120 located on one side of the substrate 110 can be formed by one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum nitride or indium aluminum gallium nitride, etc. Specifically, the two-dimensional electron gas is formed in the epitaxial structure 120.

[0059] Further, with reference to Figure 1 and Figure 2 As shown, the deposition connecting structure 210 is electrically connected with the first two-dimensional electron gas, for example, the deposition connecting structure 210 can be electrically connected with the first two-dimensional electron gas through an ohmic contact or a Schottky contact. On this basis, the semiconductor device provided by the embodiment of the present application further includes a conductive structure 10 at least partially located in the passive region bb, Figure 1The conductive structure 10 is partially located in the passive region bb and partially located in the active region aa. The conductive structure located at least partially in the passive region bb is electrically connected with the first two-dimensional electron gas, and the conductive structure 10 can be used to be electrically connected with the cathode in the deposition tank (not shown in the figure), thus forming a conduction loop of the cathode-conductive structure-two-dimensional electron gas-deposition connection structure. Therefore, when the semiconductor device is arranged in the deposition tank and the conductive structure 10 is electrically connected with the cathode in the deposition tank, the signal on the cathode can be transmitted to the deposition connection structure 210 through the loop of the conductive structure-two-dimensional electron gas-deposition connection structure, so that the metal ions in the electrolyte in the deposition tank can be deposited on the surface of the deposition connection structure 210 to obtain the deposition structure 220. That is, by arranging the conductive structure at least in the passive region, and further arranging the conductive structure to be electrically connected with the cathode in the deposition tank and the first two-dimensional electron gas respectively, and since the deposition connection structure is electrically connected with the first two-dimensional electron gas, the first two-dimensional electron gas in the active region of the semiconductor device becomes a conduction bridge between the conductive structure and the deposition connection structure, so that multiple deposition connection structures 210 can form an equipotential structure, that is, the deposition connection structure 210 can form an equivalent “deposition seed layer” through the conductive structure 10 and the first two-dimensional electron gas, so as to realize the electrodeposition on the deposition connection structure 210, that is, to form the deposition structure 220. In this way, on the one hand, by incorporating the two-dimensional electron gas into the deposition process, the process flow of the deposition structure can be simplified and the geometry of the deposition structure can be improved, thereby reducing the production cost and improving the reliability of the device; on the other hand, compared with the prior art, there is no need to separately prepare a seed metal layer, which reduces the process difficulty of the deposition structure; and only one photoresist layer is needed to define the deposition position of the deposition structure, compared with the process of two photoresist layers and two mask plates in the prior art, the number of photoresist and mask plates is reduced, the process difficulty and cost demand of the deposition structure are reduced, and the preparation efficiency of the deposition structure is improved.

[0060] It should be noted that the deposition connection structure in the embodiment of the present application can be a structure inherent to the semiconductor device, and the electrical connection between the deposition connection structure and the two-dimensional electron gas can be achieved by forming an ohmic contact between the deposition connection structure and the two-dimensional electron gas, or other structures electrically connected with the deposition connection structure and the two-dimensional electron gas form an ohmic contact to achieve the electrical connection between the deposition connection structure and the two-dimensional electron gas, which is not limited in the embodiment of the present application. The setting mode of the deposition connection structure is described in detail in the following embodiment. As long as the electrical connection between the conductive structure and the deposition connection structure is achieved through the two-dimensional electron gas, and the equipotential setting mode between the deposition connection structures is ensured, it belongs to the protection scope of the embodiment of the present application.

[0061] It should be further explained that the semiconductor device provided by the embodiments of the present application can be a single-cell structure including one chip structure, or a multi-cell structure including at least two chip structures, each of which includes the first two-dimensional electron gas, the deposition connection structure and the deposition structure as described in the above embodiments. For the semiconductor device including one chip structure, the conductive structure forms an electrical connection relationship between the deposition connection structure in the chip structure and the cathode in the deposition groove; for the semiconductor device including at least two chip structures, the conductive structure forms an equipotential structure between the deposition connection structures in the at least two chip structures, and the deposition connection structure in each chip structure forms an electrical connection relationship with the cathode in the deposition groove, so as to facilitate the electrodeposition on the deposition connection structure, i.e., the scheme of forming the deposition structure.

[0062] The semiconductor device provided by the embodiments of the present application can simplify the process flow of the deposition structure and improve the geometric shape of the deposition structure by arranging the conductive structure in the passive region and taking the first two-dimensional electron gas as a connecting bridge between the conductive structure and the deposition connection structure, thereby reducing the production cost and improving the device reliability. In the embodiments of the present application, the first two-dimensional electron gas in the epitaxial structure can be used as a carrier, and the deposition connection structure and the conductive structure are both electrically connected to the first two-dimensional electron gas, so that the deposition connection structure forms an equipotential structure through the first two-dimensional electron gas and can be used as a "deposition seed layer" of the deposition structure. The deposition of the deposition structure can be directly performed through the deposition connection structure, without separately preparing a seed metal layer, so as to simplify the process flow of the deposition structure and reduce the production cost of the deposition structure.

[0063] Optionally, Figure 3 is a top view structural schematic diagram of another semiconductor device provided by the embodiments of the present application, as shown in Figure 3 The semiconductor device includes at least two chip structures, the first two-dimensional electron gas in any two adjacent chip structures is electrically connected through the conductive structure 10, and the deposition connection structures 210 in the at least two chip structures form an equipotential structure through the conductive structure 10.

[0064] Specifically, the semiconductor includes at least two chip structures, wherein the at least two chip structures can be arranged in an array. The first two-dimensional electron gas in any two adjacent chip structures is electrically connected through the conductive structure 10, so that the first two-dimensional electron gas in the active area aa of the semiconductor device can become a conductive bridge between the conductive structure 10 and the deposition connection structure 210. The deposition connection structure 210 can form an equipotential structure through the conductive structure 10, that is, the deposition connection structure 210 can form an equivalent "deposition seed layer" through the conductive structure 10 and the first two-dimensional electron gas, so as to realize electrodeposition on the deposition connection structure 210, that is, to form a deposition structure 220, so as to ensure that each chip structure in the entire semiconductor device can form a deposition structure 220 on the surface of the deposition connection structure 210. In this way, by incorporating the two-dimensional electron gas into the deposition process, the process flow of the deposition structure can be simplified and the geometry of the deposition structure can be improved, thereby reducing production costs and improving device reliability.

[0065] Optionally, with reference back to Figure 1 As shown, the conductive structure 10 includes a second two-dimensional electron gas (not shown in the figure) located in the passive area bb and located in the epitaxial structure; and / or, the conductive structure 10 includes a connection trace (as shown in the figure) at least partially located in the passive area bb. Figure 1

[0066] For example, at least part of the conductive structure is located in the passive area and is electrically connected with the first two-dimensional electron gas located in the active area, so that the conductive structure can be arranged to include a second two-dimensional electron gas located in the passive area and located in the epitaxial structure, that is, the second two-dimensional electron gas and the first two-dimensional electron gas can be an integrated structure, so as to form a loop of cathode-second two-dimensional electron gas-first two-dimensional electron gas-deposition connection structure, based on which a deposition structure can be obtained by metal deposition on the deposition structure connection surface. It should be noted that in the preparation process of the semiconductor device, a heterojunction structure is formed in the epitaxial structure in the passive area and the active area, so that a two-dimensional electron gas can be formed in the passive area and the active area. However, because the active area is the working area of the semiconductor device, the electrodes forming ohmic structure or Schottky contact with the two-dimensional electron gas are located in the active area, so that the two-dimensional electron gas in the passive area can be neutralized by an ion implantation process. In the embodiment of the present application, the two-dimensional electron gas in the passive area can be used as a conductive structure electrically connected with the cathode in the deposition tank, so that the conductive structure can utilize the two-dimensional electron gas in the passive area which already exists in the semiconductor device, so as to reduce the process of neutralizing the two-dimensional electron gas in the passive area, simplify the arrangement of the conductive structure, and simplify the preparation process of the semiconductor device.

[0067] Alternatively, with reference back to Figure 1 ​As shown, the conductive structure 10 includes a connection trace 101 located at least partially in the passive region bb, the connection trace 101 includes a partial trace part located in the active region aa and a partial trace part located in the passive region bb, the partial trace part located in the active region aa can be electrically connected with the deposited connection structure 210 (for example, the source electrode) located in the active region aa and located at the edge region of the active region aa, and the partial trace part located in the passive region bb can be electrically connected with the cathode in the deposition slot, so as to form a loop of the cathode-conductive structure-active region edge-deposited connection structure-first two-dimensional electron gas-deposited connection structure at the rest position of the active region aa, and based on this, the deposition structure can be obtained by metal deposition on the deposition structure connection surface.

[0068] Alternatively, the conductive structure can simultaneously include a connection trace located in the passive region and a second two-dimensional electron gas (not shown in the figure), the connection trace and the second two-dimensional electron gas form an ohmic structure in the passive region, and the connection trace is electrically connected with the cathode in the deposition slot, the second two-dimensional electron gas is integrally arranged with the first two-dimensional electron gas, and the deposited connection structure forms an ohmic structure with the first two-dimensional electron gas in the active region, so as to form a loop of the cathode-connection trace-second two-dimensional electron gas-first two-dimensional electron gas-deposited connection structure, and based on this, the deposition structure can be obtained by metal deposition on the deposition structure connection surface.

[0069] In summary, by arranging the conductive structure to include a second two-dimensional electron gas located in the passive region and located in the epitaxial structure, and / or the conductive structure includes a connection trace located at least partially in the passive region, so as to form a loop of the cathode-conductive structure-first two-dimensional electron gas-deposited connection structure, and based on this, the deposition structure can be obtained by metal deposition on the deposition structure connection surface, which facilitates thickening of the electrode structure or the pad structure in the active region, reduces the signal transmission impedance, and improves the performance of the semiconductor device.

[0070] It should be noted that the above embodiments are only described by taking a semiconductor device including one chip structure as an example, and it can be understood that the semiconductor device can also include at least two chip structures, and next, taking a semiconductor device including at least two chip structures as an example, the specific arrangement mode of the conductive structure is described.

[0071] Optionally, continuing to refer to Figure 3The at least two chip structures are arranged in a first direction (X direction as shown in the figure) and a second direction (Y direction as shown in the figure); the first direction and the second direction are perpendicular to each other and both are parallel to the plane of the substrate; the connecting wire 101 includes a first connecting wire 1011 extending in the first direction and a second connecting wire 1012 extending in the second direction; two chip structures arranged adjacent in the first direction are electrically connected by a second two-dimensional electron gas, and / or two chip structures arranged adjacent in the first direction are electrically connected by the first connecting wire 1011; two chip structures arranged adjacent in the second direction are electrically connected by the second two-dimensional electron gas and the second connecting wire 1012, and / or two chip structures arranged adjacent in the second direction are electrically connected by the first connecting wire 1011 and the second connecting wire 1012.

[0072] For example, the semiconductor device can include at least two chip structures arranged in an array and each chip structure includes an active region and a passive region, the different chip structures can be electrically connected by a conductive structure, and the conductive structure located at the edge of the semiconductor device is also electrically connected to the cathode in the deposition tank, so that the at least two chip structures can form equipotential structures with the cathode in the deposition tank through the conductive structure and the first two-dimensional electron gas, facilitating the deposition of metal ions on the surface of the deposition connection structure in each chip structure to form a deposition structure.

[0073] Specifically, the connecting wire 101 can include a first connecting wire 1011 extending in the first direction and a second connecting wire 1012 extending in the second direction, two chip structures arranged adjacent in the first direction are electrically connected by a second two-dimensional electron gas (not shown in the figure), and / or two chip structures arranged adjacent in the first direction are electrically connected by the first connecting wire 101 (as shown in Figure 3 two chip structures arranged adjacent in the second direction are electrically connected by the second two-dimensional electron gas and the second connecting wire 1012 (not shown in the figure), and / or two chip structures arranged adjacent in the second direction are electrically connected by the first connecting wire 1011 and the second connecting wire 1012 (as shown in Figure 3 two chip structures arranged adjacent in the second direction are electrically connected by the second two-dimensional electron gas and the second connecting wire 1012 (not shown in the figure), and / or two chip structures arranged adjacent in the second direction are electrically connected by the first connecting wire 1011 and the second connecting wire 1012 (as shown in

[0074] Optionally, based on the above-mentioned embodiments, continuing to refer to Figure 2 , the deposition structure 220 comprises a first surface 2201 close to one side of the substrate 110 and a second surface 2202 away from the one side of the substrate 110; the vertical projection of the first surface 2201 on the plane where the substrate 110 is located covers the vertical projection of the second surface 2202 on the plane where the substrate 110 is located.

[0075] For example, continuing to refer to Figure 2 , the first surface 2201 can be understood as the lower surface of the deposition structure 220, the second surface 2202 can be understood as the upper surface of the deposition structure 220, and the vertical projection of the first surface 2201 on the plane where the substrate 110 is located covering the vertical projection of the second surface 2202 on the plane where the substrate 110 is located can be understood as the first surface 2201 covering the second surface 2202 along the thickness direction of the semiconductor device, that is, the included angle between the sidewall of the deposition structure 220 and the first surface 2201 is an acute angle. In this way, the growth quality of the subsequent passivation layer can be ensured, and the passivation layer can better cover the deposition structure 220. The problem of metal protruding at both ends of the "T"-shaped deposition structure 220 in the prior art is avoided, thereby improving the reliability of the semiconductor device.

[0076] It should be noted that the deposition structure 220 is defined by photoresist to determine the deposition position of the deposition structure 220. By reasonably setting the type of photoresist, for example, the "small on top and large on bottom" structure of the deposition structure 220 can be realized by using negative photoresist. Specifically, the part of the negative photoresist covered by the mask will be removed by the developing solution. Therefore, when the negative photoresist is exposed, the photoresist outside the exposure range will be denatured, and the photoresist below the exposure range will also be denatured to a certain extent due to the small amount of exposure. That is, the negative photoresist can form an opening with a "small on top and large on bottom" shape, and then the deposition structure 220 with a "small on top and large on bottom" shape can be formed on the deposition connection structure 210, that is, the vertical projection of the first surface 2201 on the plane where the substrate 110 is located covers the vertical projection of the second surface 2202 on the plane where the substrate 110 is located, which is beneficial to the better coverage of the passivation layer on the deposition structure 220.

[0077] Optionally, Figure 4 Another cross-sectional structure of a semiconductor device is provided in an embodiment of the present application. As shown in Figure 4 , the semiconductor device further comprises an adhesion layer 230 and a passivation layer 240; the adhesion layer 230 is located away from one side of the substrate 110, and the passivation layer 240 is located away from one side of the adhesion layer 230.

[0078] Exemplarily, the material of the adhesion layer 230 can be Ti or TiN. Specifically, the adhesion layer 230 ensures good adhesion between the deposition structure 220 and the passivation layer 240, i.e. can avoid delamination. In addition, the adhesion layer 230 can increase adhesion, facilitate the formation of the passivation layer 240, can increase the compactness of the semiconductor device structure, and make the device firm and not easy to delaminate. The passivation layer 240 is used to passivate and protect the deposition structure 220, to prevent the deposition structure 220 from being eroded by impurities or water and oxygen, and to ensure the stability of the performance of the semiconductor device.

[0079] Optionally, continuing to refer to Figure 1 and Figure 3 As shown, the semiconductor device includes an active area aa and a passive area bb surrounding the active area aa; the deposition connection structure 210 includes at least one of a source electrode 140 in the active area aa, a drain electrode 150, a first pad 160 electrically connected to the drain electrode 150 and located in the passive area bb, and a second pad 170 electrically connected to the gate electrode 130 and located in the passive area bb; the source electrode 140 and the drain electrode 150 are electrically connected to the first two-dimensional electron gas through an ohmic contact, and the gate electrode 130 is electrically connected to the first two-dimensional electron gas through a Schottky junction; the deposition structure 220 includes at least one of a first deposition structure in the active area aa and in contact with the source electrode 140 and the drain electrode 150, a second deposition structure in the passive area and in contact with the first pad 160, and a third deposition structure in the passive area bb and in contact with the second pad 170.

[0080] Specifically, referring to Figure 1 and 3 The active area aa can be understood as an area where a two-dimensional electron gas, an electron or a hole exists below it, and its working state and characteristics are affected by external circuits, which is the active working area of the semiconductor device. The passive area bb participates in the work of the semiconductor device, but its working state is not affected by external circuits, for example, an electrode lead-out structure in the active area aa can be provided in the passive area bb, and the passive area bb can be arranged around the active area aa. Further, the first pad 160 can be a drain pad, and the second pad 170 can be a gate pad. Specifically, the drain electrode 150 in the active area aa can be connected to the drain pad in the passive area bb through a drain interconnection metal, i.e. the drain electrode 150 can receive a drain voltage signal through the drain pad, to ensure the normal work of the semiconductor device. The gate electrode 130 in the active area aa can be connected to the gate pad in the passive area bb through a gate interconnection metal, and the gate electrode 130 can receive a gate voltage signal through the gate pad, to ensure the normal work of the semiconductor device.

[0081] As an example, the source 140 and the drain 150 are electrically connected to the first two-dimensional electron gas through ohmic contact, and thus the deposition connection structure 210 can be deposited on the source 140 and the drain 150 in the active area aa, i.e., the source 140 and the drain 150 are electrically connected to the conductive structure 10 through the first two-dimensional electron gas, so that the deposition connection structure 210 can receive the cathode signal, and then the deposition structure 220 can be formed on the source 140 and the drain 150, so that the seed metal layer does not need to be prepared in the active area, the process flow of the deposition structure is simplified and the geometry of the deposition structure is improved, thereby reducing the production cost and improving the device reliability.

[0082] As another example, the deposition connection structure 210 can further include the first pad 160 electrically connected to the drain 140 and located in the passive area bb, and specifically, since the drain 150 is electrically connected to the first two-dimensional electron gas and the conductive structure 10 is electrically connected to the first two-dimensional electron gas, the drain 150 is electrically connected to the first pad 160, i.e., the conductive structure 10 can be electrically connected to the first pad 160 in the passive area bb, and then the deposition structure 220 can be formed on the first pad 160, so that the seed metal layer does not need to be prepared in the passive area, the process flow of the deposition structure is simplified and the geometry of the deposition structure is improved, thereby reducing the production cost and improving the device reliability.

[0083] As another example, the deposition connection structure 210 can further include the second pad 170 electrically connected to the gate 130 and located in the passive area bb, and specifically, since the gate 130 is electrically connected to the first two-dimensional electron gas through the Schottky junction and the conductive structure 10 is electrically connected to the first two-dimensional electron gas, the gate 130 is electrically connected to the second pad 170, i.e., the conductive structure 10 can be electrically connected to the second pad 170 in the passive area bb, and then the deposition structure 220 can be formed on the second pad 170, so that the seed metal layer does not need to be prepared in the passive area, the process flow of the deposition structure is simplified and the geometry of the deposition structure is improved, thereby reducing the production cost and improving the device reliability.

[0084] In summary, the deposition structure 220 can be formed on at least one of the source 140, the drain 150, the first pad 160 and the second pad 170, so that on the one hand, the deposition structure formation process is diversified, and on the other hand, the production cost is reduced and the device reliability is improved.

[0085] Optionally, continuing to refer to Figure 2 The epitaxial structure 120 includes a channel layer 1201 and a barrier layer 1202 located on a side of the channel layer 1201 away from the substrate 110; a heterojunction structure is formed between the barrier layer 1202 and the channel layer 1201, and the two-dimensional electron gas is arranged in the heterojunction structure.

[0086] The channel layer 1201 is illustratively a Group III nitride, such as Al x Ga 1－x N, where 0≤x<1, x=0 indicating that the channel layer 1201 is GaN. The channel layer 1201 can also be other Group III nitrides, such as InGaN or AlInGaN. The channel layer 1201 can be un-doped or unintentionally doped. The channel layer 1201 can also be a multi-layer structure, such as a superlattice, a combination of GaN or AlGaN.

[0087] The barrier layer 1202 is illustratively AlN, AlInN, AlGaN or AlInGaN. The barrier layer 1202 has a sufficient thickness and a sufficiently high Al composition to cause a significant carrier concentration at the interface between the channel layer 1201 and the barrier layer 1202. Due to the bandgap difference between the barrier layer 1202 and the channel layer 1201 and the piezoelectric effect at the interface between the barrier layer 1202 and the channel layer 1201, a hetero-junction structure is formed between the channel layer 1201 and the barrier layer 1202, i.e. a two-dimensional electron gas is formed. The deposition connection in the deposition connection structure can be electrically connected with the two-dimensional electron gas, the multiple independently arranged deposition connections are ensured to form an equipotential structure through the two-dimensional electron gas, can serve as a "deposition seed layer" of the deposition structure, can directly deposit the deposition structure through the deposition connection structure, do not need to separately prepare a seed metal layer, can simplify the process flow of the deposition structure, and reduce the production cost of the deposition structure.

[0088] It should be understood that the embodiments of the present application are from the perspective of semiconductor device design, by adding a conductive structure in the passive region, and further setting the conductive structure and the deposition connection structure are both electrically connected with the first two-dimensional electron gas, that is, the first two-dimensional electron gas as a conductive structure and the deposition connection structure between the connecting bridge. Since the conductive structure is used for electrical connection with the cathode in the deposition groove, the deposition connection structure can achieve the purpose of electrical connection with the cathode in the deposition groove, so that the deposition structure can be directly formed on the surface of the deposition connection structure, which can simplify the process flow of the deposition structure and improve the geometry of the deposition structure, thereby reducing the production cost and improving the device reliability. The semiconductor device includes but is not limited to: high-power high electron mobility transistor (High Electron Mobility Transistor, HEMT) working in high-voltage and large-current environment, transistor of silicon-on-insulator (Silicon-On-Insulator, SOI) structure, transistor of gallium arsenide (GaAs) base and metal oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), metal semiconductor field effect transistor (Metal-Semiconductor Field-Effect Transistor, MISFET), double heterojunction field effect transistor (Double Heterojunction Field-Effect Transistor, DHFET), junction field effect transistor (Junction Field-Effect Transistor, JFET), metal semiconductor field effect transistor (Metal-Semiconductor Field-Effect Transistor, MESFET), metal insulating layer semiconductor heterojunction field effect transistor (Metal-Semiconductor Heterojunction Field-Effect Transistor, MISHFET) or other field effect transistors. The deposition connection structure and the deposition structure provided in the semiconductor device of the embodiments of the present application can be widely used in the fields of semiconductor device manufacturing such as radio frequency microwave and power electronics. Especially for gallium nitride electronic devices with large band gap, high electron mobility, high breakdown field strength and good heat conduction performance, the advantages are more obvious, and the high performance requirements of the rapidly developing electronic communication field can be better met.

[0089] Based on the same inventive concept, the embodiments of the present application also provide a preparation method of a semiconductor device, Figure 5 A flowchart of a preparation method of a semiconductor device provided by the embodiments of the present application is shown in FIG. 2. As shown in FIG. 2, the preparation method of the semiconductor device includes the following steps. Figure 5As shown, the method for manufacturing the semiconductor device provided by the embodiments of the present application can include:

[0090] S101, providing a substrate and manufacturing an epitaxial structure on one side of the substrate, the epitaxial structure including a first two-dimensional electron gas in an active region.

[0091] For example, the method for manufacturing the substrate can be atmospheric pressure chemical vapor deposition, sub-atmospheric pressure chemical vapor deposition, metal organic chemical vapor deposition, low pressure chemical vapor deposition, high density plasma chemical vapor deposition, ultra-high vacuum chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, hybrid physical-chemical vapor deposition, rapid thermal chemical vapor deposition, vapor phase epitaxy, pulsed laser deposition, atomic layer epitaxy, molecular beam epitaxy, sputtering or evaporation.

[0092] For example, the method for growing the epitaxial structure can include metal organic chemical vapor deposition, hydride vapor phase epitaxy, molecular beam epitaxy and liquid phase epitaxy, and the embodiments of the present application are not limited thereto. Specifically, the two-dimensional electron gas is formed in the epitaxial structure.

[0093] S102, manufacturing a deposition connection structure on the side of the epitaxial structure away from the substrate, the deposition connection structure being electrically connected to the first two-dimensional electron gas.

[0094] Specifically, with reference to Figure 1 and Figure 2 , the deposition connection structure 210 is electrically connected to the first two-dimensional electron gas, for example, the deposition connection structure 210 can be electrically connected to the first two-dimensional electron gas in the form of ohmic contact or Schottky contact. When the deposition connection structure 210 includes at least two independently arranged deposition connection portions 2101, any deposition connection portion 2101 is electrically connected to the two-dimensional electron gas. That is, the two-dimensional electron gas in the epitaxial structure 120 of the semiconductor device is used as a wire, and the plurality of independently arranged deposition connection structures are connected through the first two-dimensional electron gas, so that the plurality of independently arranged deposition connection portions 2101 can form an equipotential structure, that is, the plurality of independently arranged deposition connection portions 2101 can form an equivalent "deposition seed layer" through the first two-dimensional electron gas.

[0095] S103, manufacturing a conductive structure in at least the passive region, the conductive structure being electrically connected to the first two-dimensional electron gas, and the deposition connection structure forming an equipotential structure through the conductive structure.

[0096] With reference to Figure 1As shown, since the conductive structure 10 is electrically connected with the first two-dimensional electron gas, and meanwhile the conductive structure 10 can be used to electrically connect with the cathode in the deposition tank (not shown in the figure), thus a conductive loop of cathode-conductive structure-first two-dimensional electron gas-deposition connection structure is formed. Therefore, when the semiconductor device is arranged in the deposition tank, and the conductive structure 10 is electrically connected with the cathode in the deposition tank, the signal on the cathode can be transmitted to the deposition connection structure 210 through the loop of conductive structure-first two-dimensional electron gas-deposition connection structure. The deposition connection structure 210 forms an equipotential structure through the conductive structure 10, thus by incorporating the two-dimensional electron gas into the deposition process, the process flow of the deposition structure can be simplified and the geometry of the deposition structure can be improved, thereby reducing the production cost and improving the device reliability.

[0097] S104, arranging the semiconductor device in the deposition tank and electrically connecting the conductive structure with the cathode in the deposition tank.

[0098] Specifically, the deposition tank is provided with an electroplating solution, an anode and a cathode immersed in the electroplating solution, and the electroplating solution contains metal cations. By arranging the semiconductor device in the deposition tank and electrically connecting the conductive structure with the cathode in the deposition tank, when a voltage is applied between the anode and the cathode in the deposition tank, the signal on the cathode can be transmitted to the deposition connection structure through the conductive structure and the first two-dimensional electron gas, and the deposition connection structure forms an equipotential structure with the cathode, which facilitates the subsequent deposition of metal cations on the surface of the deposition connection structure.

[0099] S105, preparing a deposition structure on the side of the deposition connection structure away from the substrate, and the deposition structure is in contact with the deposition connection structure.

[0100] Specifically, continuing to refer to Figure 1 As described above, since the signal on the cathode can be transmitted to the deposition connection structure 210 through the loop of conductive structure-first two-dimensional electron gas-deposition connection structure, the cathode signal can be received on the deposition connection structure, and thus the metal ions in the electrolyte in the deposition tank can be deposited on the surface of the deposition connection structure 210 to obtain a deposition structure 220. On the one hand, by transmitting the cathode signal to the deposition connection structure through the conductive structure and the first two-dimensional electron gas, the process flow of the deposition structure 220 can be simplified and the geometry of the deposition structure 220 can be improved, thereby reducing the production cost and improving the device reliability; on the other hand, compared with the prior art, a seed metal layer does not need to be prepared separately, which reduces the process difficulty of the deposition structure; and only one photoresist layer is needed to define the deposition position of the deposition structure 220, which reduces the number of photoresists and mask plates compared with the prior art which needs two photoresists and two mask plates, thereby reducing the process difficulty and cost demand of the deposition structure and improving the preparation efficiency of the deposition structure.

[0101] The preparation method of the semiconductor device provided by the embodiment of the present application adds the conductive structure in the passive region, and further sets the conductive structure and the deposition connection structure to be electrically connected with the first two-dimensional electron gas, that is, the first two-dimensional electron gas serves as a connecting bridge between the conductive structure and the deposition connection structure. Since the conductive structure is used for electrical connection with the cathode in the deposition groove, the deposition connection structure can achieve the purpose of electrical connection with the cathode in the deposition groove, so that the deposition structure can be directly formed on the surface of the deposition connection structure, thereby simplifying the process flow of the deposition structure and improving the geometry of the deposition structure, so as to reduce the production cost and improve the reliability of the device. In the embodiment of the present application, the first two-dimensional electron gas in the epitaxial structure can be used as a carrier, and the deposition connection structure is electrically connected with the first two-dimensional electron gas, so that the deposition connection structure forms an equipotential structure with the first two-dimensional electron gas and the conductive structure, and can serve as a "deposition seed layer" of the deposition structure. The deposition connection structure can be directly used for deposition of the deposition structure, without separately preparing a seed metal layer, so as to simplify the process flow of the deposition structure and reduce the production cost of the deposition structure.

[0102] On the basis of the above-mentioned embodiment, the embodiment of the present application further provides another preparation method of a semiconductor device, Figure 6 The flowchart of the another preparation method of a semiconductor device provided by the embodiment of the present application is shown in FIG. 2. As shown in FIG. 2, the preparation method of the semiconductor device provided by the embodiment of the present application can include the following steps. Figure 6

[0103] S201, providing a substrate and preparing an epitaxial structure on one side of the substrate, wherein the epitaxial structure includes a first two-dimensional electron gas located in an active region.

[0104] S202, preparing a deposition connection structure on the side of the epitaxial structure away from the substrate, wherein the deposition connection structure is electrically connected with the first two-dimensional electron gas.

[0105] S203, preparing a conductive structure at least in the passive region, wherein the conductive structure is electrically connected with the first two-dimensional electron gas, and the deposition connection structure forms an equipotential structure through the conductive structure.

[0106] S204, setting the semiconductor device in a deposition groove and electrically connecting the conductive structure with a cathode in the deposition groove.

[0107] S205, preparing a negative photoresist on the side of the deposition connection structure away from the substrate.

[0108] S206, exposing and developing the negative photoresist to form a photoresist opening in the negative photoresist, wherein the photoresist opening exposes part of the deposition connection structure; and the opening area of the photoresist opening on the side close to the substrate is greater than the opening area of the photoresist opening on the side away from the substrate.

[0109] Specifically,​Figure 7 A structure diagram for forming a photoresist opening in a negative photoresist is provided for an embodiment of the present application, as shown in Figure 7 As shown, the part of the negative photoresist 82 covered by the mask is removed by the developing solution, thus when the negative photoresist is exposed, the photoresist outside the exposure range can be ensured to be denatured, and the photoresist below the exposure range can also be denatured to different degrees due to the small exposure amount, that is, the negative photoresist can form an opening with a shape of "small on top and large on bottom", that is, the opening area of the photoresist opening near the substrate side is larger than the opening area of the photoresist opening far from the substrate side.

[0110] S207, a deposition structure is prepared in the photoresist opening, the deposition structure includes a first surface near the substrate side and a second surface far from the substrate side, the vertical projection of the first surface on the substrate plane covers the vertical projection of the second surface on the substrate plane; the deposition structure is in contact with the deposition connection structure and is electrically connected.

[0111] Specifically, Figure 8 A structure diagram for preparing a deposition structure in a photoresist opening is provided for an embodiment of the present application, as shown in Figure 8 As shown, by preparing the deposition structure 220 in the photoresist opening, the deposition structure 220 with a shape of "small on top and large on bottom" can be formed on the deposition connection structure 210, that is, the vertical projection of the first surface 2201 of the deposition structure 220 on the substrate 110 plane covers the vertical projection of the second surface 2202 on the substrate 110 plane, thus the growth quality of the passivation layer can be ensured, and the passivation layer can better cover the deposition structure. The problem of metal protruding at both ends of the "T" shaped deposition structure in the prior art can be avoided, thus the reliability of the semiconductor device can be improved.

[0112] Optionally, continuing to refer to Figure 8 Preparation of the deposition structure in the photoresist opening can include controlling the thickness of the deposition structure 220 to be less than the thickness of the negative photoresist 82, thus it is beneficial to remove the negative photoresist 82, that is, the peeling of the photoresist is realized.

[0113] S208, the photoresist is removed.

[0114] The preparation method of the semiconductor device provided by the embodiment of the present application can form a photoresist opening with a small upper part and a large lower part when the negative photoresist is exposed and developed, and then electrodepositing can be performed on the part of the deposition connecting structure exposed by the photoresist opening, that is, a deposition structure with a small upper part and a large lower part is formed, so that the growth quality of the subsequent passivation layer can be ensured, thereby improving the reliability of the semiconductor device. In addition, the thickness of the deposition structure is smaller than that of the negative photoresist, which is beneficial to the removal of the negative photoresist, and then the passivation layer can be formed on the deposition structure to protect the deposition structure.

[0115] On the basis of the above-mentioned embodiment, the embodiment of the present application further provides another preparation method of a semiconductor device, Figure 9 The flowchart of the preparation method of the semiconductor device provided by the embodiment of the present application is shown in FIG. 1. Figure 9 As shown in FIG. 1, the preparation method of the semiconductor device provided by the embodiment of the present application can include the following steps.

[0116] S301, providing a substrate and preparing an epitaxial structure on one side of the substrate, the epitaxial structure including a two-dimensional electron gas located in an active region.

[0117] S302, preparing a deposition connecting structure on the side of the epitaxial structure away from the substrate, the deposition connecting structure being electrically connected with the first two-dimensional electron gas.

[0118] S303, preparing a conductive structure at least in the passive region, the conductive structure being electrically connected with the first two-dimensional electron gas, and the deposition connecting structure forming an equipotential structure through the conductive structure.

[0119] S304, placing the semiconductor device in a deposition tank and electrically connecting the conductive structure with a cathode in the deposition tank.

[0120] S305, preparing a deposition structure on the side of the deposition connecting structure away from the substrate, the deposition structure being in contact with the deposition connecting structure.

[0121] Optionally, the first mask structure is used to prepare the deposition structure on the side of the deposition connecting structure away from the substrate.

[0122] For example, the first mask structure can be a photomask, that is, the photomask is used to prepare the deposition structure on the side of the deposition connecting structure away from the substrate, and then by setting the conductive structure in the passive region and taking the first two-dimensional electron gas as a connecting bridge between the conductive structure and the deposition connecting structure, the process flow of the deposition structure can be simplified and the geometry of the deposition structure can be improved, thereby reducing the production cost and improving the reliability of the device.

[0123] S306, using the first mask structure to prepare an adhesion layer on the side of the deposition structure away from the substrate.

[0124] Exemplarily, the material of the adhesion layer can be Ti or TiN. Specifically, the adhesion layer can play a role of lattice matching, i.e. on the one hand, the adhesion layer can match the lattice of the metal in the deposition structure, and on the other hand, the adhesion layer can match the lattice of the passivation layer, so as to ensure that the adhesion effect between the deposition structure and the passivation layer is good, i.e. the delamination can be avoided.

[0125] Optionally, the adhesion layer is prepared on the side of the deposition structure away from the substrate by using the first mask structure.

[0126] Specifically, since the deposition structure is "small on top and large on bottom", the growth of the adhesion layer can be directly performed on the deposition structure, and the growth of the adhesion layer can use the same mask structure as the deposition structure, thereby reducing the preparation cost of the semiconductor device.

[0127] S307, a passivation layer is prepared on the side of the adhesion layer away from the substrate.

[0128] Specifically, the passivation layer is prepared on the side of the adhesion layer away from the substrate, and the passivation layer can cover the deposition structure, thereby playing a role of protecting the deposition structure.

[0129] The preparation method of the semiconductor device provided by the embodiment of the present application can sequentially prepare the deposition structure and the adhesion layer by using the first mask structure, thereby saving the process flow and production cost, and in addition, the preparation of the adhesion layer is beneficial to the coverage of the passivation layer, so that the semiconductor device structure is compact and firm, and is not easy to delaminate, thereby avoiding warping.

[0130] Note that the above is only the preferred embodiment of the present application and the applied technical principle. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and those skilled in the art can make various obvious changes, re-adjustments and substitutions without departing from the protection scope of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments, and can include more other equivalent embodiments without departing from the concept of the present application, and the scope of the present application is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized by, The semiconductor device comprises: The semiconductor device further comprises: a substrate; an epitaxial structure located on one side of the substrate and comprising a first two-dimensional electron gas located in the active region; a deposition connection structure located on a side of the epitaxial structure away from the substrate and in electrical connection with the first two-dimensional electron gas; a conductive structure at least partially located in the passive region and in electrical connection with the first two-dimensional electron gas, the conductive structure being used for electrical connection with a cathode in a deposition slot; a deposition structure located on a side of the deposition connection structure away from the substrate and in electrical connection with the deposition connection structure.

2. The semiconductor device according to claim 1, wherein The semiconductor device comprises at least two chip structures, the first two-dimensional electron gas in any two adjacent chip structures being electrically connected through the conductive structure, and the deposition connection structures in at least two chip structures forming an equipotential structure through the conductive structure.

3. The semiconductor device of claim 2, wherein, The conductive structure comprises a second two-dimensional electron gas located in the passive region and in the epitaxial structure; and / or, the conductive structure comprises a connection trace at least partially located in the passive region.

4. The semiconductor device according to claim 3, wherein The at least two chip structures are arranged in a first direction and a second direction; the first direction and the second direction intersect and are both parallel to the plane in which the substrate lies; The connection trace comprises a first connection trace and a second connection trace, the first connection trace extending in the first direction, and the second connection trace extending in the second direction; Two chip structures arranged adjacent in the first direction are electrically connected through the second two-dimensional electron gas, and / or two chip structures arranged adjacent in the first direction are electrically connected through the first connection trace; Two chip structures arranged adjacent in the second direction are electrically connected through the second two-dimensional electron gas and the second connection trace, and / or two chip structures arranged adjacent in the second direction are electrically connected through the first connection trace and the second connection trace.

5. The semiconductor device of claim 1, wherein The deposition structure comprises a first surface close to the substrate and a second surface away from the substrate; The vertical projection of the first surface on the plane in which the substrate lies covers the vertical projection of the second surface on the plane in which the substrate lies.

6. The semiconductor device of claim 1, wherein The deposition connection structure comprises at least one of a source electrode located in the active region, a drain electrode, a first pad in electrical connection with the drain electrode and located in the passive region, and a second pad in electrical connection with a gate electrode and located in the passive region; the source electrode and the drain electrode are in electrical connection with the first two-dimensional electron gas through an ohmic contact, and the gate electrode forms an electrical contact with the first two-dimensional electron gas through a Schottky junction; The deposition structure comprises at least one of a first deposition structure located in the active region and in electrical connection with the source electrode and the drain electrode, a second deposition structure located in the passive region and in electrical connection with the first pad, and a third deposition structure located in the passive region and in electrical connection with the second pad.

7. A method of manufacturing a semiconductor device, characterized by The semiconductor device comprises: A substrate is provided and an epitaxial structure is prepared on one side of the substrate, the epitaxial structure comprising a first two-dimensional electron gas in an active region; A deposition connection structure is prepared on a side of the epitaxial structure away from the substrate, the deposition connection structure being electrically connected to the first two-dimensional electron gas; At least in a passive region, a conductive structure is prepared, the conductive structure being electrically connected to the first two-dimensional electron gas, and the deposition connection structure forms an equipotential structure through the conductive structure; The semiconductor device is disposed in a deposition slot and the conductive structure is electrically connected to a cathode in the deposition slot; A deposition structure is prepared on a side of the deposition connection structure away from the substrate, the deposition structure being in contact with the deposition connection structure.

8. The production method according to claim 7, characterized by, A deposition structure is prepared on a side of the deposition connection structure away from the substrate, comprising: A negative photoresist is prepared on a side of the deposition connection structure away from the substrate; The negative photoresist is exposed and developed to form a photoresist opening in the negative photoresist, the photoresist opening exposing part of the deposition connection structure; the opening area of the photoresist opening on the side close to the substrate is greater than the opening area of the photoresist opening on the side away from the substrate; A deposition structure is prepared in the photoresist opening, the deposition structure comprising a first surface on the side close to the substrate and a second surface on the side away from the substrate, the vertical projection of the first surface on the plane of the substrate covering the vertical projection of the second surface on the plane of the substrate.

9. The production method according to claim 8, characterized by, A deposition structure is prepared in the photoresist opening, comprising: The thickness of the deposition structure is controlled to be less than the thickness of the negative photoresist; The preparation method further comprises: The negative photoresist is removed.

10. The preparation method according to claim 7, characterized in that, A deposition structure is prepared on a side of the deposition connection structure away from the substrate, comprising: A first mask structure is used to prepare a deposition structure on a side of the deposition connection structure away from the substrate; The preparation method further comprises: An adhesion layer is prepared on a side of the deposition structure away from the substrate using the first mask structure; A passivation layer is prepared on a side of the adhesion layer away from the substrate.

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