Improved SAR Analog-to-Digital Converter and Its Control Method, Successive Approximation Logic Circuit

Abstract

The present invention discloses an improved SAR analog-to-digital converter, its control method, and a successive approximation logic circuit. The successive approximation logic circuit includes n first flip-flops D1 i and n second flip-flops D2 i ; the D terminal of the first flip-flop D10 is grounded, and the Set terminal receives the set signal sent by the controller; the CLK terminal of the first flip-flop D1 i receives the clock signal sent by the controller; the Q terminal of the first flip-flop D1 i is connected to the D terminal of the first flip-flop D1 i+1 ; the Q terminal of the first flip-flop D1 i is connected to the Set terminal of the second flip-flop D2 i ; the D terminal of the second flip-flop D2 j receives the comparison signal sent by the comparator; the CLK terminal of the second flip-flop D2 j is connected to the Q terminal of the adjacent second flip-flop D2 z ; the CLK terminal and the D terminal of the second flip-flop D2 n are grounded; the Q terminal of the second flip-flop D21 is connected to the controller through a unidirectional device; an edge-triggered short-term hold circuit is connected between the outputs of the unidirectional devices of the second flip-flop D20 and the second flip-flop D21. The input end of the edge-triggered short-term hold circuit makes the output end maintain a high potential within a delay period according to a pulse, and returns to a low potential after the end of the delay period.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more particularly, to an improved SAR analog-to-digital converter and its control method. Background Art

[0002] With the development of communication systems and the application of embedded systems, the research on analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for converting between analog and digital signals has received increasing attention. Among various analog-to-digital converters (ADCs), the successive approximation analog-to-digital conversion technology is a key technology application for medium and high resolutions in the market. The SAR analog-to-digital converter, that is, the successive approximation analog-to-digital converter, has advantages such as low power consumption, medium and high sampling rates and resolutions, and is convenient for integration.

[0003] The SAR analog-to-digital converter generally consists of a sample-and-hold circuit, a comparator, a DAC, a successive approximation logic circuit, and a controller. The sample-and-hold circuit is used to sample the input voltage. The comparator is used to compare the input voltage with the output voltage of the DAC and transmit the comparison signal to the successive approximation logic circuit. The successive approximation logic circuit controls the conversion switch of the DAC according to the clock signal from the controller, the drive signal, and the comparison signal from the DAC.

[0004] The successive approximation logic circuit is a key component of the SAR analog-to-digital converter. The successive approximation logic circuit uses two rows of D flip-flops to implement logic control. The first row of D flip-flops forms a shift register, and the shift register realizes successive shifting according to the clock signal and the drive signal, and the Q terminals of each D flip-flop are successively set. The second row of D flip-flops respectively realizes successive approximation logic according to the Q-terminal output of the D flip-flop arranged in front in the queue, the set output of the corresponding D flip-flop in the shift register, and the comparison signal.

[0005] In the prior art, for the successive approximation logic of the second row of D flip-flops in the successive approximation logic circuit, generally, the Q terminal of the first D flip-flop is set to 1, and the Q terminals of other D flip-flops are set to 0 as the initial bit of the successive approximation logic. This initial bit generates a comparison voltage near the median of the maximum comparison voltage through the control of the conversion switch of the DAC. For example, the maximum comparison value that a 4-bit SAR analog-to-digital converter can generate is 15, and the corresponding Q-terminal output of the second row of D flip-flops is [1, 1, 1, 1]. The initial output of the Q terminals of each D flip-flop in the second row is [1, 0, 0, 0], and the corresponding input voltage is 8. Then, for an input voltage outside the valid range, the SAR analog-to-digital converter cannot first judge the out-of-range of the input voltage and still starts successive approximation from the median of the maximum comparison voltage. Summary of the Invention

[0006] Based on this, in the first aspect of the embodiments of the present invention, an improved SAR analog-to-digital converter is disclosed, which includes a sample-and-hold circuit, a comparator, a DAC, a successive approximation logic circuit, and a controller.

[0007] The successive approximation logic circuit includes n first flip-flops D1 i and n second flip-flops D2 i ;

[0008] The D terminal of the first flip-flop D10 is grounded, and the Set terminal receives the set signal sent by the controller;

[0009] The CLK terminal of the first flip-flop D1 i receives the clock signal sent by the controller;

[0010] The Q terminal of the first flip-flop D1 i is connected to the D terminal of the first flip-flop D1 i+1 ;

[0011] The Q terminal of the first flip-flop D1 i is connected to the Set terminal of the second flip-flop D2 i ;

[0012] The D terminal of the second flip-flop D2 j receives the comparison signal sent by the comparator;

[0013] The CLK terminal of the second flip-flop D2 j is connected to the Q terminal of the adjacent second flip-flop D2 z ;

[0014] The CLK terminal and the D terminal of the second flip-flop D2 n are grounded;

[0015] The Q terminal of the second flip-flop D21 is connected to the controller through a unidirectional device;

[0016] An edge-triggered short-term hold circuit is connected between the outputs of the second flip-flop D20 and the unidirectional device of the second flip-flop D21. The input terminal of the edge-triggered short-term hold circuit makes the output terminal remain at a high potential within a delay period according to a pulse, and returns to a low potential after the end of the delay period;

[0017] 0 ≤ i ≤ 2, 0 ≤ j < z ≤ n - 1, where i, j, z, and n are positive integers.

[0018] In some embodiments disclosed in the present invention,

[0019] The Q terminals of the second flip-flops D2 i are respectively connected to the controller through unidirectional devices;

[0020] The second flip-flop D2x Connect the edge-triggered short-term hold circuit K between the output of the unidirectional device and the adjacent second flip-flop D2 y ; x ;

[0021] 0 ≤ x < y ≤ n - 1, where x and y are positive integers.

[0022] In some embodiments disclosed in the present invention,

[0023] The Q terminals of the second flip-flop D2 i are respectively connected to the controller through unidirectional devices;

[0024] The output of the unidirectional device of the second flip-flop D20 is connected to the output of the unidirectional device of each second flip-flop D2 m through the edge-triggered short-term hold circuit respectively;

[0025] 1 ≤ m ≤ n - 1.

[0026] In some embodiments disclosed in the present invention,

[0027] The edge-triggered short-term hold circuit is configured as a monostable trigger circuit.

[0028] In some embodiments disclosed in the present invention,

[0029] The monostable trigger circuit includes a third flip-flop D3, a capacitor C, and a resistor R;

[0030] The D terminal of the third flip-flop D3 is connected to the power supply, the Set terminal is grounded, the CLK terminal is connected to the input, the Q terminal is connected to the output, the Q terminal is connected to the R terminal through the resistor R, and is grounded through the capacitor C.

[0031] In some embodiments disclosed in the present invention,

[0032] The sample and hold circuit and the DAC are integrated in a capacitive DAC with an inherent sample and hold function.

[0033] In some embodiments disclosed in the present invention,

[0034] The capacitive DAC includes an array composed of n - 1 capacitors arranged in binary weighted order.

[0035] Moreover, a successive approximation logic circuit is disclosed in the second aspect of the embodiments of the present invention.

[0036] The successive approximation logic circuit includes n first flip-flops D1 i and n second flip-flops D2 i ;

[0037] The D terminal of the first flip - flop D10 is grounded, and the Set terminal receives the set signal sent by the controller;

[0038] The CLK terminal of the first flip - flop D1 i receives the clock signal sent by the controller;

[0039] The Q terminal of the first flip - flop D1 i is connected to the D terminal of the first flip - flop D1 i+1 ;

[0040] The Q terminal of the first flip - flop D1 i is connected to the Set terminal of the second flip - flop D2 i ;

[0041] The D terminal of the second flip - flop D2 j receives the comparison signal sent by the comparator;

[0042] The CLK terminal of the second flip - flop D2 j is connected to the Q terminal of the adjacent second flip - flop D2 z ;

[0043] The CLK terminal of the second flip - flop D2 n and the D terminal are grounded;

[0044] The Q terminal of the second flip - flop D21 is connected to the controller through a unidirectional device;

[0045] An edge - triggered short - term hold circuit is connected between the outputs of the unidirectional devices of the second flip - flop D20 and the second flip - flop D21. The input terminal of the edge - triggered short - term hold circuit keeps the output terminal at a high potential within a delay period according to a pulse and returns to a low potential after the end of the delay period;

[0046] 0 ≤ i ≤ 2, 0 ≤ j < z ≤ n - 1, where i, j, z, and n are positive integers.

[0047] Moreover, a control method for an improved SAR analog - to - digital converter is disclosed in the third aspect of the embodiments of the present invention. The control method is applied to the improved SAR analog - to - digital converter,

[0048] The control method includes,

[0049] The controller sends a high - level set signal to the Set terminal of the first flip - flop D10;

[0050] When the Set terminal of the first flip - flop D10 is set to high level, the Q terminal of the first flip - flop D10 is set to high level;

[0051] When the Q terminal of the first flip - flop D10 is set to high level, the Set terminal of the second flip - flop D20 is set to high level;

[0052] When the Set terminal of the second flip - flop D20 is set high, the Q terminal of the second flip - flop D20 is set high;

[0053] When the Q terminal of the second flip - flop D20 is set high, the input terminal of the edge - triggered short - term hold circuit K0 receives a pulse signal, and the output terminal of the edge - triggered short - term hold circuit K0 is set high and then set low after a delay time;

[0054] When the output terminal of the edge - triggered short - term hold circuit K0 is set high, the controller controls the conversion switch of the DAC according to the current outputs of all the second flip - flops D2 i to make the comparator output a comparison signal;

[0055] The controller determines whether the input voltage is over - limit according to the comparison signal;

[0056] When the input voltage is over - limit, the controller feeds back voltage over - limit to the outside and / or stops the operation of the devices of the improved SAR analog - to - digital converter;

[0057] When the input voltage is not over - limit, after the end of the delay period, the controller sends a number of clock signals to the first flip - flop D1 i in sequence, and the successive approximation logic circuit performs successive approximation according to the clock signals and the comparison signal;

[0058] After all the clock signals are sent, the controller generates a digital signal corresponding to the input voltage according to the Q terminals of all the second flip - flops D2 i ;

[0059] In addition, a third aspect of the embodiments of the present invention discloses a control method for an improved SAR analog - to - digital converter, and the control method is applied to the improved SAR analog - to - digital converter,

[0060] The control method includes,

[0061] The controller sends a high - level setting signal to the Set terminal of the first flip - flop D10;

[0062] When the Set terminal of the first flip - flop D10 is set high, the Q terminal of the first flip - flop D10 is set high;

[0063] When the Q terminal of the first flip - flop D10 is set high, the Set terminal of the second flip - flop D21 is set high;

[0064] When the Set terminal of the second flip - flop D21 is set high, the Q terminal of the second flip - flop D21 is set high;

[0065] When the Q terminal of the second flip - flop D21 is set high, the input terminal of the edge - triggered short - term hold circuit K0 receives a pulse signal, and the edge - triggered short - term hold circuit Ki The output terminals are sequentially set to high level and then to low level after a delay period;

[0066] When all the output terminals of the edge-triggered short-term hold circuit K i are set to high level, the controller controls the conversion switch of the DAC according to the current outputs of all the second flip-flops D2 i to make the comparator output a comparison signal;

[0067] The controller determines whether the potential of the input voltage exceeds the limit according to the comparison signal;

[0068] When the input voltage exceeds the limit, the controller feeds back voltage overlimit to the outside and / or stops the operation of the devices of the improved SAR analog-to-digital converter;

[0069] When the input voltage does not exceed the limit, after the end of the delay period, the controller sequentially sends a plurality of clock signals to the first flip-flop D1 i The successive approximation logic circuit performs successive approximation according to the clock signals and the comparison signal;

[0070] After all the clock signals are sent, the controller generates a digital signal corresponding to the input voltage according to the Q terminals of each second flip-flop D2 i

[0071] Compared with the prior art, in the embodiment of the present invention, the successive approximation logic circuit is improved, and based on the control logic of successive approximation, extreme value checking is realized, the application scenario of the successive approximation logic circuit is expanded, so that the improved SAR analog-to-digital converter can be used in technical scenarios that are more sensitive to the threshold of the input voltage, and the traditional SAR analog-to-digital conversion technology is renewed.

[0072] For the above solution, the present invention will be described in detail with reference to the accompanying drawings for the disclosed exemplary embodiments, so as to make the other features and advantages of the embodiments of the present invention clear. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0074] Figure 1 It is the circuit schematic diagram of the improved SAR analog-to-digital converter for this embodiment;

[0075] Figure 2 ​This is the circuit schematic diagram of the successive approximation logic circuit in this embodiment;

[0076] Figure 3 This is the circuit schematic diagram of the monostable trigger circuit in this embodiment. Specific implementation manner

[0077] To facilitate the understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0078] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0079] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" or "having" etc. specify the presence of the stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0080] This embodiment discloses an improved SAR analog-to-digital converter. The improved SAR analog-to-digital converter includes a sample-and-hold circuit (S / H), a comparator (comp), a DAC, a successive approximation logic circuit (SAR) and a controller.

[0081] Among them, the sample-and-hold circuit is used to sample and hold the input voltage.

[0082] Among them, the DAC is used to generate a reference voltage according to the reference voltage and the control of the conversion switch by the controller;

[0083] Among them, the comparator is used to compare the held input voltage with the reference voltage generated by the DAC and transmit the generated comparison signal to the successive approximation logic circuit.

[0084] Among them, the successive approximation logic circuit generates a control signal for the conversion switch of the DAC in a successive approximation manner according to the set signal from the controller, the clock signal, and the comparison signal from the comparator.

[0085] Among them, the controller determines whether the potential of the current input voltage meets the requirements or exceeds the range according to the control signal during the successive approximation process of the successive approximation logic circuit and the comparison signal of the comparator, and records the digital signal corresponding to the input voltage according to the control signal after the successive approximation ends.

[0086] Figure 2 Fig. 4 shows a circuit schematic diagram of the successive approximation logic circuit of this embodiment.

[0087] This embodiment takes an 8-bit improved SAR analog-to-digital converter as an example, that is, n = 9.

[0088] Among them, the successive approximation logic circuit includes nine first flip-flops D1 i and nine second flip-flops D2 i , where i ∈ [1, 2,.., 8], eight monostable trigger circuits and nine diodes.

[0089] The first flip-flop D1 i and the second flip-flop D2 i are D flip-flops. The D flip-flop includes a Set terminal, a D terminal, a Q terminal and a CLK terminal. The Set terminal is used to receive the set signal of the pulse. The CLK is used to receive the clock signal of the pulse. The Q terminal is used to set the high level after the Set terminal receives the set signal, or to maintain the same potential as the D terminal after the CLK terminal receives the clock signal. Preferably, the D flip-flop is triggered by the rising edge.

[0090] The monostable trigger circuit is a unit circuit with two working states: a stable state and a transient state. When there is no input signal to trigger, the output of the monostable trigger circuit is in the stable state. When there is an input signal to trigger, the output of the monostable trigger circuit flips from the stable state to the transient state and automatically returns to the stable state after a period of time. The length of the transient time of the monostable trigger circuit depends on the circuit parameters of the monostable trigger circuit itself and has nothing to do with the length of the action time of the input signal. Preferably, the monostable trigger circuit is triggered by the rising edge.

[0091] The D terminal of the first flip-flop D10 is grounded, and the Set terminal is connected to the sending end of the set signal of the controller to receive the set signal.

[0092] The CLK terminal of each first flip-flop D1 i is synchronously connected to the sending end of the clock signal of the controller to receive the clock signal, 0 ≤ i ≤ 9.

[0093] The Q terminal of each first flip-flop D1 i is respectively connected to the D terminal of the corresponding first flip-flop D1 i+1 to keep the potential of the Q terminal of the first flip-flop D1 i the same as the potential of the D terminal of the first flip-flop D1 i+1 .

[0094] Each first flip-flop D1 i has its Q terminal connected to the Set terminal of the second flip-flop D2 i so that the Set terminal of the second flip-flop D2 i can receive a pulse when the Q terminal of each first flip-flop D1 i flips from low to high.

[0095] Each second flip-flop D2 j has its D terminal connected to the output terminal of the comparator to receive a comparison signal output by the comparator according to the input voltage and the current DAC output, where 0 ≤ j < z ≤ 8.

[0096] Each second flip-flop D2 j has its CLK terminal connected to the Q terminal of an adjacent second flip-flop D2 z so that the CLK terminal of the second flip-flop D2 j can receive a pulse when the Q terminal of the corresponding second flip-flop D2 z flips from low to high, where 0 ≤ j < z ≤ 8.

[0097] The CLK terminal and the D terminal of the second flip-flop D28 are grounded.

[0098] The Q terminal of the second flip-flop D2 i is respectively connected to each input terminal of the controller through the corresponding diode D5 i so that the controller can receive the current setting of the Q terminal of each second flip-flop D2 i The controller realizes the switching of each switching switch in the DAC according to the setting of the Q terminal of each second flip-flop D2 i .

[0099] The output terminal of the diode D5 x is connected to the output terminal of the diode D5 y with a monostable trigger circuit. The input terminals of each monostable trigger circuit are connected to the output terminal of the corresponding diode D5 x and the output terminals are connected to the output terminal of the corresponding diode D5 y , where 0 ≤ x < y ≤ 9.

[0100] Based on this, in this embodiment, during the successive approximation process of the successive approximation logic circuit, through the combination of the monostable trigger circuit, the diode, the first flip-flop D1 i and the second flip-flop D2 i , it can be realized that when the Q terminal of the second flip-flop D2 corresponding to the previous bit flips from low to high, all the low-bit second flip-flops D2 in the subsequent bit i i ​The Q terminal of remains high within a total delay period and returns to low after the end of the delay period. During the delay period, the controller controls the conversion switch of the DAC when the Q terminal of each high-bit second flip-flop D2 i flips from low to high, so that the DAC output is the current maximum reference voltage corresponding to the high-bit of the current flipped second flip-flop D2 i 's Q terminal. Based on the comparison result between the current maximum reference voltage and the input voltage, the controller can determine whether the current input voltage exceeds the allowable input voltage range or does not meet other requirements. After the controller determines that the input voltage does not exceed the range or meets other requirements and after the end of the delay period, it sends a clock signal to the first flip-flop D1 i to continue and further implement the successive approximation of the input voltage.

[0101] For example, the input voltage of an 8-bit improved SAR analog-to-digital converter is 270V.

[0102] The initial bit of the successive approximation logic circuit of the prior art (the array composed of the outputs of the Q terminals of each second flip-flop D2 i ) is [1, 0, 0, 0, 0, 0, 0, 0], that is, 128V. The successive approximation logic circuit starts successive approximation from the initial bit. After several clock cycles by the controller, that is, when the maximum bit [1, 1, 1, 1, 1, 1, 1, 1] of the successive approximation logic circuit is reached, it can be determined that the input voltage exceeds the allowable input voltage range and exceeds the voltage limit.

[0103] The initial bit of the improved successive approximation logic circuit in this embodiment is also [1, 0, 0, 0, 0, 0, 0, 0], that is, 128V. However, before starting successive approximation with [1, 0, 0, 0, 0, 0, 0, 0] in this embodiment, within a delay period, the current bit is directly maintained at [1, 1, 1, 1, 1, 1, 1, 1], that is, 255V; and it returns to [1, 0, 0, 0, 0, 0, 0, 0] after the end of the delay period. During the delay period, the controller of this embodiment controls the conversion switch of the DAC with [1, 1, 1, 1, 1, 1, 1, 1] to make the DAC generate a reference voltage of 255V for comparison with the input voltage. When the reference voltage of the comparison result is less than the input voltage, the controller can directly determine that the current input voltage exceeds the allowable input voltage range of the improved SAR analog-to-digital converter and communicate with the outside or execute termination and reset of devices such as the successive approximation logic circuit and the DAC; when the reference voltage of the comparison result is less than the input voltage, after the end of the delay period, starting with [1, 0, 0, 0, 0, 0, 0, 0] as the initial bit, the successive approximation logic circuit is driven by a clock signal to execute the logical control of successive approximation.

[0104] It should be noted that in the process of successive approximation of the successive approximation logic circuit, the binary search method is used to approximate from the high bit position to the low bit position. Then, for the second flip-flop D2 at any bit position in the successive approximation logic circuit of this embodiment i when the Q terminal jumps from the low level to the high level, the Q terminals of the second flip-flop D2 at this bit position and the subsequent low bit positions i will be briefly held at the high level.

[0105] For the possible outputs of the Q terminals of each second flip-flop D2 i there are the following references:

[0106] For example,

[0107] [1,0,0,0,0,0,0,0] (initial bit) - [1,1,1,1,1,1,1,1] (briefly held) - [1,0,0,0,0,0,0,0] (restore and perform successive approximation) - [1,1,0,0,0,0,0,0] (current successive approximation result)

[0108] - [1,1,1,1,1,1,1,1] (briefly held) - [1,1,0,0,0,0,0,0] (restore and continue to perform successive approximation)..

[0109] Or,

[0110] [1,0,0,0,0,0,0,0] (initial bit) - [1,1,1,1,1,1,1,1] (briefly held) - [1,0,0,0,0,0,0,0] (restore and perform successive approximation) - [0,1,0,0,0,0,0,0] (current successive approximation result)

[0111] - [0,1,1,1,1,1,1,1] (briefly held) - [0,1,0,0,0,0,0,0] (restore and continue to perform successive approximation)..

[0112] In summary, during the successive approximation process, the improved successive approximation logic circuit with 8-bit positions in this embodiment can be successively held at [1,1,1,1,1,1,1,1], [0,1,1,1,1,1,1,1], [0,0,1,1,1,1,1,1],

[0113] [0,0,0,1,1,1,1,1], [0,0,0,0,1,1,1,1], [0,0,0,0,0,1,1,1], [0,0,0,0,0,0,1,1], so that the DAC can generate reference voltages of 255V, 127V, 63V, 31V, 15V, 7V, and 3V in sequence. Based on the comparison results between these reference voltages and the input voltage, the controller can provide early feedback to the outside or terminate the successive approximation and the operation of related devices before the successive approximation of the successive approximation logic circuit ends.

[0114] The improvement of the successive approximation logic circuit in this embodiment adds an extreme value check on the basis of the successive approximation control logic, expanding the application scenarios of the successive approximation logic circuit. And the improved SAR analog-to-digital converter based on the successive approximation logic circuit in this embodiment can be used in technical scenarios sensitive to the threshold of the input voltage, rejuvenating the traditional SAR analog-to-digital conversion technology.

[0115] Furthermore, in addition to adding the extreme value check, in the successive approximation control logic of this embodiment, a phased extreme value check for each digital level is introduced, such as [0,1,1,1,1,1,1,1],

[0116] [0,0,1,1,1,1,1,1], which provides a basis for the controller to make judgments on the input voltage itself and / or interact with and execute external devices based on more comparison results.

[0117] Furthermore, in this embodiment, the functions of the sample-and-hold circuit and the DAC are integrated into a capacitive DAC with inherent sampling and holding functions. The capacitive DAC includes an array composed of n capacitors arranged in binary, which can realize sample-and-hold and DAC output. The capacitive DAC belongs to the prior art and will not be elaborated here.

[0118] Preferably, the monostable trigger circuit in this embodiment includes a third flip-flop D3, a capacitor C, and a resistor R. The third flip-flop D3, the first flip-flop D1, and the second flip-flop D2 can all be preferably edge D flip-flops. The third flip-flop D3 includes an R terminal for setting the Q terminal to 0. The D terminal of the third flip-flop D3 is connected to the power supply, the Set terminal is grounded, the CLK terminal is connected to the input, the Q terminal is connected to the output, the Q terminal is connected to the R terminal through the resistor R, and is grounded through the capacitor C.

[0119] Then, when the monostable trigger circuit is in the steady state, Ui is 0. When the input signal U0 reaches the CL terminal, the rising edge of UO makes the high potential at the D terminal reach the Q terminal. At this time, the monostable trigger circuit enters the quasi-steady state, Ui is 1 and charges the capacitor C through the resistor R. As the charging progresses, when the voltage of the capacitor C can make the R terminal at a high potential, the Q terminal is set to a low potential, and at this time, the monostable trigger circuit returns to the steady state. This is the capacitor C discharging through the resistor R to prepare for receiving the rising edge of the input signal here.

[0120] It is worth mentioning that for each input port of the D flip-flop of the first to third flip-flops in this embodiment, it can be configured to be active at a high potential or a low potential according to the type of different D flip-flops, such as the R terminal, the S terminal, etc. According to the requirements of signal transmission and input relationship in this embodiment, in order to adapt to different D flip-flops, a flip-flop circuit can be added in front of each port of the D flip-flop according to the selection to realize signal flipping and ensure the normal triggering of each input port.

[0121] In addition, the delay time of each monostable trigger circuit in this embodiment is preferably determined by the parameters of the resistor R and the resistor C, and the combination of the delay times of all the monostable trigger circuits can be regarded as 1 / 2 or less of the delay period of this embodiment.

[0122] Furthermore, this embodiment discloses a control method for an improved SAR analog-to-digital converter, and the control method is applied to the controller of the improved SAR analog-to-digital converter. When the control method is executed, the following steps S100 to S500 are implemented.

[0123] S100 The controller sends a high-level pulse set signal to the Set terminal of the first flip-flop D10.

[0124] At this time, the Set terminal of the first flip-flop D10 is set to a high level, the Q terminal of the first flip-flop D10 is set to a high level, the Set terminal of the second flip-flop D21 is set to a high level, the Q terminal of the second flip-flop D20 is set to a high level, and multiple single quasi-stable pulse circuits sequentially make the Q terminals of the second flip-flop D21 to the second flip-flop D2 n-1 be set to a high level within a delay period.

[0125] S200 The controller controls the DAC to generate the current reference voltage within the delay period and receives the comparison signal of the comparator according to the comparison between the current reference voltage and the input voltage. i control the DAC to generate the current reference voltage, and receive the comparison signal of the comparator according to the comparison between the current reference voltage and the input voltage.

[0126] S300 The controller judges whether the current input voltage exceeds the maximum allowable voltage range according to the comparison signal. If the controller judges that the input voltage exceeds the range, it feeds back an over-limit signal to the outside. If the controller judges that the input voltage does not exceed the range, it enters 400.

[0127] After the end of the delay cycle, the S400 controller generates the current reference voltage according to each second flip-flop D2 i and controls the DAC to generate the current reference voltage, and at the same time starts to send a clock signal to the first flip-flop D1 i

[0128] At this time, the Q terminal of the first flip-flop D1 i shifts forward in turn with the high bit

[0129] For example, when the CLK terminal of the first flip-flop D10 receives the pulse of the clock signal, since the D terminal is grounded, the Q terminal is set to the low level. Synchronously, when the CLK terminal of the first flip-flop D11 receives the pulse of the clock signal, since the D terminal is synchronized with the set bit of the Q terminal of the current first flip-flop D10 to be high, the Q terminal of the first flip-flop D11 will be set to high (because the first flip-flop D10 and the first flip-flop D11 receive the clock pulse synchronously, the setting of the Q terminal of the first flip-flop D10 to the low level will be delayed compared with the setting of the Q terminal of the first flip-flop D11 according to the D terminal, and the principle of a general successive approximation register can be referred to).

[0130] At this time, the Q terminal of the second flip-flop D2 i is set according to the comparison signal fed back by the DAC and the D terminal of the second flip-flop D2 i-1 to achieve successive approximation

[0131] For example, after the delay cycle, the second flip-flop D20 is set to high, and the second flip-flop D21 to the second flip-flop D2 n set to low is the initial bit of successive approximation. The controller starts to send a clock signal to set the Set terminal of the first flip-flop D11 to high and the Q terminal to high. At the same time, if the comparison signal returned by the comparator according to the initial bit is low, the D terminal of the second flip-flop D20 is set to low, and the Q terminal of the first flip-flop D11 generates a pulse from low to high, so that the Q terminal of the first flip-flop D10 is set to low to obtain the current bit of successive approximation

[0132] After the control logic of the successive approximation logic circuit ends, the S500 controller generates a digital signal according to the output of the second flip-flop D2 i

[0133] Based on this, the controller of this embodiment controls the improved SAR analog-to-digital converter through the clock signal and the set signal. On the basis of the control logic of successive approximation, extreme value checking is realized, the application scenario of the successive approximation logic circuit is expanded, and the improved SAR analog-to-digital converter can be used in technical scenarios that are more sensitive to the threshold of the input voltage

[0134] ​​Based on the above description of the embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software and necessary general hardware, and of course, it can also be implemented by hardware. However, in many cases, the former is a better implementation method.

[0135] Note that the above are only the preferred embodiments of the present invention and the technical principles applied. Those skilled in the art will understand that the present invention is not limited to the specific embodiments here. Various obvious changes, re-adjustments, and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments. Without departing from the concept of the present invention, more other equivalent embodiments can be included, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. An improved SAR analog-to-digital converter, comprising a sample-and-hold circuit, a comparator, a DAC, a successive approximation logic circuit, and a controller, characterized in that The successive approximation logic circuit includes n first flip-flops D1 i and n second flip-flops D2 j , where 0 ≤ i, j ≤ n - 1; The D terminal of the first flip-flop D10 is grounded, and the Set terminal receives the set signal sent by the controller; The first flip-flop D1 i receives the clock signal sent by the controller at its CLK terminal; The first flip-flop D1 i 's Q terminal is connected to the D terminal of the adjacent first flip-flop D1 i+1 ; The Q terminal of the first flip-flop D1 i is connected to the Set terminal of the corresponding second flip-flop D2 i ; The second flip-flop D2 j receives the comparison signal sent by the comparator at its D terminal; The second flip-flop D2 j has its CLK terminal connected to the Q terminal of the adjacent second flip-flop D2 j+1 . The second flip-flop D2 n-1 has its CLK terminal and D terminal grounded; The second flip-flop D2 j 's Q terminal is respectively connected to the controller through unidirectional devices; Second flip-flop D2 x There is an edge-triggered short-term hold circuit K connected between the output of the unidirectional device adjacent to the second flip-flop D2 y The input terminal of the edge-triggered short-term hold circuit K x keeps the output terminal at a high potential within a delay period according to a pulse and returns to a low potential after the end of the delay period, where 0 ≤ x < y ≤ n - 2; x ​ i, j, n, x, and y are positive integers.

2. The improved SAR analog-to-digital converter according to claim 1, characterized in that The second flip-flop D2 i The Q terminals of which are respectively connected to the controller through unidirectional devices; The output of the unidirectional device of the second flip-flop D20 is respectively connected to the edge-triggered short-term hold circuit between the outputs of the unidirectional devices of each second flip-flop D2 m ; 1 ≤ m ≤ n - 2.

3. The improved SAR analog-to-digital converter according to claim 1, characterized in that The edge-triggered short-term hold circuit is configured as a monostable trigger circuit.

4. The improved SAR analog-to-digital converter according to claim 3, characterized in that The monostable trigger circuit includes a third flip-flop D3, a capacitor C, and a resistor R; The D terminal of the third flip-flop D3 is connected to the power supply, the Set terminal is grounded, the CLK terminal is connected to the input, the Q terminal is connected to the output, the Q terminal is connected to the R terminal through the resistor R, and is grounded through the capacitor C.

5. The improved SAR analog-to-digital converter according to claim 1, characterized in that The sample-and-hold circuit and the DAC are integrated in a capacitive DAC with an inherent sampling and holding function.

6. The improved SAR analog-to-digital converter according to claim 5, characterized in that The capacitive DAC includes an array composed of n - 1 capacitors arranged in binary weighted form.

7. A successive approximation logic circuit, characterized in that The successive approximation logic circuit includes n first flip-flops D1 i and n second flip-flops D2 j , where 0 ≤ i, j ≤ n - 1; The D terminal of the first flip-flop D10 is grounded, and the Set terminal receives the set signal sent by the controller; The first flip-flop D1 i receives the clock signal sent by the controller at its CLK terminal; The first flip-flop D1 i 's Q terminal is connected to the D terminal of the adjacent first flip-flop D1 i+1 ; The Q terminal of the first flip-flop D1 i is connected to the Set terminal of the corresponding second flip-flop D2 i ; The second flip-flop D2 j receives the comparison signal sent by the comparator at its D terminal; The second flip-flop D2 j 's CLK terminal is connected to the Q terminal of the adjacent second flip-flop D2 j+1 ; The second flip-flop D2 n-1 has its CLK terminal and D terminal grounded; The second flip-flop D2 j The Q terminals of which are respectively connected to the controller through unidirectional devices; The second flip-flop D2 x There is an edge-triggered short-term holding circuit K connected between the output of the unidirectional device of the adjacent second flip-flop D2 y The input terminal of the edge-triggered short-term holding circuit K x keeps the output terminal at a high potential within a delay period according to a pulse, and returns to a low potential after the end of the delay period, 0 ≤ x < y ≤ n - 2; x ​ i, j, n, x, and y are positive integers.

8. A control method for an improved SAR analog-to-digital converter, the control method being applied to the improved SAR analog-to-digital converter according to claim 1, characterized in that The control method includes The controller sends a high-level set signal to the Set terminal of the first flip-flop D10; When the Set terminal of the first flip-flop D10 is set to high, the Q terminal of the first flip-flop D10 is set to high; When the Q terminal of the first flip-flop D10 is set to high, the Set terminal of the second flip-flop D20 is set to high; When the Set terminal of the second flip-flop D20 is set to high, the Q terminal of the second flip-flop D20 is set to high; When the Q terminal of the second flip-flop D20 is set to high, the input terminal of the edge-triggered short-term hold circuit K0 receives a pulse signal, and the output terminal of the edge-triggered short-term hold circuit K0 is set to high and then set to low after a delay time; When the output of the edge-triggered short-term hold circuit K0 is set high, the controller controls the conversion switch of the DAC according to the outputs of all current second flip-flops D2 j to make the comparator output a comparison signal; The controller determines whether the input voltage exceeds the limit according to the comparison signal; When the input voltage exceeds the limit, the controller feeds back voltage overlimit to the outside and / or stops the device operation of the improved SAR analog-to-digital converter; When the input voltage does not exceed the limit, after the end of the delay period, the controller sends a number of clock signals to the first flip-flop D1 i in sequence, and the successive approximation logic circuit performs successive approximation according to the clock signals and the comparison signal; After all the clock signals are sent, the controller generates a digital signal corresponding to the input voltage according to the Q terminals of each second flip-flop D2 j .

9. A control method for an improved SAR analog-to-digital converter, the control method being applied to the improved SAR analog-to-digital converter according to claim 1, characterized in that The control method includes The controller sends a high-level set signal to the Set terminal of the first flip-flop D10; When the Set terminal of the first flip-flop D10 is set to high, the Q terminal of the first flip-flop D10 is set to high; When the Q terminal of the first flip-flop D10 is set to high, the Set terminal of the second flip-flop D21 is set to high; When the Set terminal of the second flip-flop D21 is set high, the Q terminal of the second flip-flop D21 is set high; When the Q terminal of the second flip-flop D21 is set to high, the input terminal of the edge-triggered short-term holding circuit K0 receives a pulse signal, and the output terminals of the edge-triggered short-term holding circuit K i are sequentially set to high and then set to low after a delay period; When all the output terminals of the edge-triggered short-term holding circuit K i are set to high, the controller controls the conversion switch of the DAC according to the outputs of all the current second flip-flops D2 j so that the comparator outputs a comparison signal; The controller determines whether the potential of the input voltage exceeds the limit according to the comparison signal; When the input voltage exceeds the limit, the controller feeds back voltage overlimit to the outside and / or stops the operation of the devices of the improved SAR analog-to-digital converter; When the input voltage does not exceed the limit, after the end of the delay period, the controller sends a number of clock signals to the first flip-flop D1 i sequentially, and the successive approximation logic circuit performs successive approximation according to the clock signals and the comparison signal; After all the clock signals are sent, the controller generates a digital signal corresponding to the input voltage according to the Q terminals of each second flip-flop D2 j .

Images