Simulation system and method based on digital signal processor

Abstract

The present invention provides a simulation system and method based on a digital signal processor, which performs functional verification to confirm that all processor instructions are executed as expected, including mathematical operations, data transfer and control instructions; error detection: discovering potential problems in the code, such as illegal instructions, memory leaks and data inconsistencies; debugging support: providing debugging tools such as breakpoints, single-step execution and register inspection to help developers troubleshoot and fix problems. The present invention solves the problem of needing to fully verify and evaluate the functions and performance of the system when designing a complex DSP system by using the simulation execution function of the digital signal processor.

Description

Technical Field

[0001] The present invention relates to the field of simulation technology, and in particular to a simulation system and method based on a digital signal processor. Background Art

[0002] With the widespread use of digital signal processing (DSP) applications in communications, image processing, audio processing and other fields, the demand for high-performance processors is increasing. As a high-performance DSP processor, the complex architecture and functions of TMS320C6678 require precise verification. When actual hardware is unavailable or costly, simulation provides an efficient verification platform that can simulate the operation of the processor to ensure that its performance in different scenarios meets expectations, while allowing rapid iteration and optimization in the software environment, thereby shortening the product development cycle.

[0003] Although the current processor simulation technology supports some DSP processors, it may not fully support TMS320C6678. It mainly focuses on software development and debugging rather than deep hardware simulation. The configuration and use may be more complicated and require a high learning curve. It may not fully simulate the high-performance characteristics and complex system interactions of the processor.

[0004] Patent document CN109885466A discloses a simulation method, system and medium of processor C8000, including: mechanism simulation step: simulating the operation mechanism of C8000 processor; register and memory simulation step: simulating the register and memory of C8000 processor; on-chip device simulation step: simulating the on-chip device of C8000. However, the patent does not involve the simulation method of DSP architecture, and cannot solve the above-mentioned technical problems. Summary of the invention

[0005] In view of the defects in the prior art, an object of the present invention is to provide a simulation system and method based on a digital signal processor.

[0006] The simulation system based on a digital signal processor provided by the present invention comprises:

[0007] Instruction dynamic translation unit: The simulation system parses the input digital signal processor binary instructions into recognizable intermediate states; based on the current simulation state and runtime environment, generates the instruction set that the simulation system translates into the target simulation chip;

[0008] Instruction execution unit: obtains the instructions converted by the simulation system through the instruction dynamic translation unit, and simulates its behavior on the target processor;

[0009] Memory access unit: The simulation system simulates the processor's read and write operations on the memory, including the simulation of the cache mechanism and the support for shared memory;

[0010] Interrupt processing unit: receives external interrupt requests, according to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the address of the interrupt service program, jumps to execute the interrupt service program, and after completion, restores the context previously saved by the CPU and continues program execution;

[0011] Exception handling unit: The simulation system captures and simulates the exceptions of the processor during runtime, triggers the exception handler, and simulates the process of saving and restoring the processor state;

[0012] Step into the step unit: set the number of instructions to be executed each time through the instruction execution unit, execute the program instructions one by one, and observe the effect and processing process of each step;

[0013] Breakpoint setting unit: The instruction execution unit supports setting breakpoints at key code locations, so that the program can be paused under certain conditions and the program status can be viewed and analyzed;

[0014] Register and memory status viewing unit: Through the operating environment saved by the instruction execution unit, an interface is added to provide the function of viewing the processor registers and memory contents in real time.

[0015] Preferably, the instruction dynamic translation unit includes: extracting instructions to be translated from source code or source instruction set, determining instruction type and execution logic by parsing the binary of the instructions, mapping source instructions into target instructions accordingly, and optimizing and sorting newly generated target instructions.

[0016] Preferably, the instruction execution unit includes: obtaining the current instruction from the memory, decoding the instruction, determining the operation and operand to be executed, executing the instruction according to the decoding result, performing arithmetic operations, logical operations or data transmission, and writing the result into the register or memory.

[0017] Preferably, the memory access unit includes: creating a virtual model of the cache, defining the size, replacement strategy and association of the cache, creating a shared memory area, setting up a synchronization mechanism, permission control and unmapping, and ensuring the consistency of the program's memory access behavior in the simulation environment with that on the actual hardware.

[0018] Preferably, the exception handling unit includes: when an abnormal condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers; searches and jumps to the corresponding exception handling program according to the exception type, performs corresponding recovery or error reporting operations, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

[0019] The simulation method based on a digital signal processor provided by the present invention comprises:

[0020] Step 1: Parse the input digital signal processor binary instructions into an intermediate state recognizable by the simulation system; generate an instruction set that the simulation system translates into the target simulation chip based on the current simulation state and runtime environment;

[0021] Step 2: Use the translated instructions to simulate the behavior on the target processor;

[0022] Step 3: Simulate the processor's read and write operations on the memory, including the simulation of the cache mechanism and the support for shared memory;

[0023] Step 4: Receive external interrupt request. According to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the address of the interrupt service routine, jumps to execute the interrupt service routine, and restores the context saved by the CPU after completion, and continues program execution;

[0024] Step 5: Capture and simulate the exceptions of the processor at runtime, trigger the exception handler, and simulate the process of saving and restoring the processor state;

[0025] Step 6: Set the number of instructions to be executed each time, execute the program instructions one by one, and observe the effect and processing of each step;

[0026] Step 7: Set breakpoints at key code locations to pause program execution under specific conditions and view and analyze program status;

[0027] Step 8: Save the operating environment and view the processor registers and memory contents in real time through the interface.

[0028] Preferably, step 1 includes: extracting instructions to be translated from source code or source instruction set, determining instruction type and execution logic by parsing the binary of the instructions, mapping source instructions into target instructions accordingly, and optimizing and sorting newly generated target instructions.

[0029] Preferably, step 2 includes: obtaining the current instruction from the memory, decoding the instruction, determining the operation and operand to be performed, executing the instruction according to the decoding result, performing arithmetic operations, logical operations or data transfer, and writing the result to the register or memory.

[0030] Preferably, step 3 includes: creating a virtual model of the cache, defining the size, replacement strategy and association of the cache, creating a shared memory area, setting up a synchronization mechanism, permission control and unmapping, and ensuring the consistency of the program's memory access behavior in the simulation environment with that on the actual hardware.

[0031] Preferably, step 4 includes: when an abnormal condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers; searches and jumps to the corresponding exception handler according to the exception type, performs corresponding recovery or error reporting operations, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] (1) By using the simulation execution function of the digital signal processor, the problem of needing to fully verify and evaluate the system's functions and performance when designing complex DSP systems is solved;

[0034] (2) By adopting the simulation debugging function of the digital signal processor, the difficulty of debugging on actual hardware may be limited by debugging tools and real-time monitoring, making it impossible to quickly locate and solve problems in the program. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Other features, objects and advantages of the present invention will become more apparent from the detailed description of non-limiting embodiments made with reference to the following drawings:

[0036] Figure 1 It is a schematic diagram of the structure of the simulation system based on the digital signal processor of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described in detail below in conjunction with specific embodiments. The following embodiments will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those of ordinary skill in the art, several changes and improvements can also be made without departing from the concept of the present invention. These all belong to the protection scope of the present invention.

[0038] Example 1

[0039] The present invention provides a simulation method based on a digital signal processor, comprising:

[0040] Step 1: Parse the input digital signal processor binary instructions into an intermediate state recognizable by the simulation system; generate an instruction set that the simulation system translates into the target simulation chip based on the current simulation state and runtime environment;

[0041] Step 2: Use the translated instructions to simulate the behavior on the target processor;

[0042] Step 3: Simulate the processor's read and write operations on the memory, including the simulation of the cache mechanism and the support for shared memory;

[0043] Step 4: Receive external interrupt request. According to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the address of the interrupt service routine, jumps to execute the interrupt service routine, and restores the context saved by the CPU after completion, and continues program execution;

[0044] Step 5: Capture and simulate the exceptions of the processor at runtime, trigger the exception handler, and simulate the process of saving and restoring the processor state;

[0045] Step 6: Set the number of instructions to be executed each time, execute the program instructions one by one, and observe the effect and processing of each step;

[0046] Step 7: Set breakpoints at key code locations to pause program execution under specific conditions and view and analyze program status;

[0047] Step 8: Save the operating environment and view the processor registers and memory contents in real time through the interface.

[0048] The step 1 comprises: extracting instructions to be translated from source code or source instruction set;

[0049] In the field of computer science, the specific type of each instruction and the execution logic it represents are determined by analyzing the binary code of the instruction set; based on such analysis results, the source instruction (i.e., the original machine code) can be mapped to the target instruction (usually the equivalent machine code under another architecture). This mapping process needs to ensure that the converted new instructions can maintain the original functionality and semantics unchanged; in addition, after these target instructions are generated, they need to be further optimized and reordered to obtain the best performance on the target architecture, including but not limited to improving execution efficiency, reducing resource usage, and improving the overall response speed of the program.

[0050] The step 2 includes: obtaining the current instruction from the memory, decoding the instruction, determining the operation to be performed and the operand, executing the instruction according to the decoding result, performing arithmetic operation, logical operation or data transmission, and writing the result into the register or memory.

[0051] The step 3 includes: creating a virtual model of the cache, defining the size, replacement strategy and relevance of the cache, creating a shared memory area, setting up synchronization mechanisms, permission control and unmapping, and ensuring the consistency of the program's memory access behavior in the simulation environment with that on the actual hardware. Specifically:

[0052] When designing and implementing a virtual model of a cache, you first need to define the basic characteristics of the cache, such as the size of the cache, the replacement policy (such as least recently used (LRU) or random replacement (RAND)), and the associativity (direct mapping, fully associative, or set associative). The cache size determines how many data items can be stored, while the replacement policy specifies which data items to remove to make room for new data items when the cache is full. The associativity determines the mapping between cache lines and main memory blocks, which directly affects the cache hit rate and performance.

[0053] Next, in order to simulate the caching behavior in a multi-process or multi-threaded environment, you need to create a shared memory area. This means defining the size of the shared memory, the allocation method, and how to share the memory between different processes or threads. When creating a shared memory area, you must also set up appropriate synchronization mechanisms, such as semaphores or mutexes, to prevent data inconsistencies caused by multiple processes or threads modifying the same memory at the same time. In addition, you need to consider permission control to ensure that only authorized processes or threads can access the shared memory, and provide a method for unmapping so that resources can be released when the shared memory is no longer needed.

[0054] Throughout the process, it is crucial to ensure that the program's memory access behavior in the simulation environment is consistent with its behavior on the actual hardware. This includes not only the behavior of the cache, but also other aspects of memory management, such as page fault handling, virtual address to physical address mapping, memory protection, etc. To this end, it may be necessary to implement some additional functions, such as recording cache hit and miss statistics, simulating cache consistency protocols, etc., to ensure the accuracy and reliability of the simulation results.

[0055] Through the above steps, we can build a complete cache simulation system to study and evaluate the performance impact of different cache configurations, thereby providing guidance for the cache design of actual systems.

[0056] The step 4 includes: when an abnormal condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers; searches and jumps to the corresponding exception handler according to the exception type, performs corresponding recovery or error reporting operations, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

[0057] Example 2

[0058] The present invention provides a simulation system based on a digital signal processor, targeting the DSP TMS320C6678 processor. The purpose of DSP TMS320C6678 processor simulation is functional verification, confirming that all processor instructions are executed as expected, including mathematical operations, data transfer and control instructions. Error detection: discover potential problems in the code, such as illegal instructions, memory leaks and data inconsistencies. Debugging support: provide debugging tools (such as breakpoints, single-step execution and register checking) to help developers troubleshoot and fix problems. Figure 1 , specifically including the following aspects:

[0059] Instruction dynamic translation unit, the simulation system first parses the input TMS320C6678 binary instructions into a recognizable intermediate state. The instructions to be translated are extracted from the source code or source instruction set, and the type and execution logic of the instructions are determined by parsing the binary of the instructions, and the source instructions are mapped to the target instructions accordingly. At the same time, the newly generated target instructions are optimized and sorted to improve the execution efficiency. Finally, according to the current simulation state and runtime environment, the simulation system generates the instruction set translated into the target simulation chip.

[0060] The instruction execution unit obtains the instructions converted by the simulation system through the instruction dynamic translation unit, and simulates its behavior on the target processor, obtains the current instruction from the memory (instruction fetch), decodes the instruction, determines the operation and operand to be executed (decoding), executes the instruction according to the decoding result, performs arithmetic operations, logical operations or data transfer, etc. (execution), and writes the result to the register or memory (write back).

[0061] Memory access unit, the simulation system simulates the processor's read and write operations on memory, including the simulation of cache mechanisms and support for shared memory. Create a virtual model of the cache, define the cache size, replacement strategy (such as LRU, FIFO), and association (such as direct mapping, fully associative, and group associative). Create a shared memory area, set up synchronization mechanisms, permission control, and unmap. This ensures that the program's memory access behavior in the simulation environment is consistent with that on the actual hardware.

[0062] Interrupt handling unit, the simulation system implements an interrupt controller that can receive external interrupt requests. According to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the interrupt service routine (ISR) address, jumps to execute the interrupt service routine, and after completion, restores the context previously saved by the CPU and continues program execution.

[0063] Exception handling unit, the simulation system captures and simulates the exceptions that may occur during the operation of the processor, such as arithmetic overflow, illegal instruction, memory access error, stack overflow, page fault, bus error, system call exception. When an exception condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers. According to the exception type, it searches and jumps to the corresponding exception handler, performs the corresponding recovery or error reporting operation, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

[0064] Step into the step unit and set the number of instructions to be executed each time through the instruction execution unit, allowing developers to execute program instructions one by one and observe the effect and processing process of each step.

[0065] The breakpoint setting unit supports setting breakpoints at key code locations through the instruction execution unit, so that the program can be paused under specific conditions, making it easier to view and analyze the program status.

[0066] The register and memory status viewing unit adds an interface to provide real-time viewing of processor registers and memory contents through the operating environment saved by the instruction execution unit.

[0067] Those skilled in the art know that, in addition to implementing the system, device and its various modules provided by the present invention in a purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers and embedded microcontrollers by logically programming the method steps. Therefore, the system, device and its various modules provided by the present invention can be considered as a hardware component, and the modules included therein for implementing various programs can also be considered as structures within the hardware component; the modules for implementing various functions can also be considered as both software programs for implementing the method and structures within the hardware component.

[0068] The above describes the specific embodiments of the present invention. It should be understood that the present invention is not limited to the above specific embodiments, and those skilled in the art can make various changes or modifications within the scope of the claims, which does not affect the essence of the present invention. In the absence of conflict, the embodiments of the present application and the features in the embodiments can be combined with each other arbitrarily.

Claims

1. A simulation system based on a digital signal processor, characterized in that: include: Instruction dynamic translation unit: The simulation system parses the input digital signal processor binary instructions into recognizable intermediate states; Generates the instruction set that the simulation system translates into the target simulation chip based on the current simulation state and runtime environment; Instruction execution unit: obtains the instructions converted by the simulation system through the instruction dynamic translation unit, and simulates its behavior on the target processor; Memory access unit: The simulation system simulates the processor's read and write operations on the memory, including the simulation of the cache mechanism and the support for shared memory; Interrupt processing unit: receives external interrupt requests, according to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the address of the interrupt service program, jumps to execute the interrupt service program, and after completion, restores the context previously saved by the CPU and continues program execution; Exception handling unit: The simulation system captures and simulates the exceptions of the processor during runtime, triggers the exception handler, and simulates the process of saving and restoring the processor state; Step into the step unit: set the number of instructions to be executed each time through the instruction execution unit, execute the program instructions one by one, and observe the effect and processing process of each step; Breakpoint setting unit: The instruction execution unit supports setting breakpoints at key code locations, so that the program can be paused under certain conditions and the program status can be viewed and analyzed; Register and memory status viewing unit: Through the operating environment saved by the instruction execution unit, an interface is added to provide the function of viewing the processor registers and memory contents in real time.

2. The digital signal processor-based simulation system according to claim 1, characterized in that: The instruction dynamic translation unit includes: extracting instructions to be translated from source code or source instruction set, determining instruction type and execution logic by analyzing the binary of the instruction, mapping the source instruction into target instruction accordingly, and optimizing and sorting the newly generated target instruction.

3. The digital signal processor-based simulation system according to claim 1, characterized in that: The instruction execution unit includes: obtaining the current instruction from the memory, decoding the instruction, determining the operation to be executed and the operand, executing the instruction according to the decoding result, performing arithmetic operation, logical operation or data transmission, and writing the result into the register or memory.

4. The digital signal processor-based simulation system according to claim 1, characterized in that: The memory access unit includes: creating a virtual model of the cache, defining the size, replacement strategy and association of the cache, creating a shared memory area, setting a synchronization mechanism, permission control and unmapping, and ensuring the consistency of the program's memory access behavior in the simulation environment with that on the actual hardware.

5. The digital signal processor-based simulation system according to claim 1, characterized in that: The exception handling unit includes: when an exception condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers; searches and jumps to the corresponding exception handling program according to the exception type, performs corresponding recovery or error reporting operations, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

6. A simulation method based on a digital signal processor, characterized in that: include: Step 1: Parse the input digital signal processor binary instructions into intermediate states recognizable by the simulation system; Generates the instruction set that the simulation system translates into the target simulation chip based on the current simulation state and runtime environment; Step 2: Use the translated instructions to simulate the behavior on the target processor; Step 3: Simulate the processor's read and write operations on the memory, including the simulation of the cache mechanism and the support for shared memory; Step 4: Receive external interrupt request. According to the priority and registration status of the handler, after the interrupt is triggered, the CPU saves the context, determines the interrupt source, locates the address of the interrupt service routine, jumps to execute the interrupt service routine, and restores the context saved by the CPU after completion, and continues program execution; Step 5: Capture and simulate the exceptions of the processor at runtime, trigger the exception handler, and simulate the process of saving and restoring the processor state; Step 6: Set the number of instructions to be executed each time, execute the program instructions one by one, and observe the effect and processing of each step; Step 7: Set breakpoints at key code locations to pause program execution under specific conditions and view and analyze program status; Step 8: Save the operating environment and view the processor registers and memory contents in real time through the interface.

7. The simulation method based on a digital signal processor according to claim 6, characterized in that: The step 1 includes: extracting instructions to be translated from source code or source instruction set, determining the type and execution logic of the instructions by parsing the binary of the instructions, mapping the source instructions into target instructions accordingly, and optimizing and sorting the newly generated target instructions.

8. The simulation method based on a digital signal processor according to claim 6, characterized in that: The step 2 includes: obtaining the current instruction from the memory, decoding the instruction, determining the operation to be performed and the operand, executing the instruction according to the decoding result, performing arithmetic operation, logical operation or data transmission, and writing the result into the register or memory.

9. The simulation method based on a digital signal processor according to claim 6, characterized in that: The step 3 includes: creating a virtual model of the cache, defining the size, replacement strategy and association of the cache, creating a shared memory area, setting up a synchronization mechanism, permission control and unmapping, and ensuring the consistency of the program's memory access behavior in the simulation environment with that on the actual hardware.

10. The simulation method based on a digital signal processor according to claim 6, characterized in that: The step 4 includes: when an abnormal condition is detected during the operation of the processor, the CPU saves the current program state, including the program counter and registers; searches and jumps to the corresponding exception handler according to the exception type, performs corresponding recovery or error reporting operations, and after the exception handling is completed, restores the previously saved context, and the program continues to execute or terminates from the exception point.

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