High-efficiency analog in-memory computing architecture based on FeFET structure and its working method

Abstract

This invention belongs to the field of memory and discloses a high-efficiency analog in-memory computing architecture based on FeFET structure and its working method, involving a novel analog in-memory computing design applicable to both the current domain and voltage domain. This invention fully utilizes the non-volatility and analog memory characteristics of FeFET, implementing partial multiply-accumulate (MAC) operations per column in the array while inherently integrating 4-bit weighted shift-add operations, eliminating the need for additional shift-add circuitry during weight processing. This invention supports partial MAC operations in both two's complement mode (2CM) and non-two's complement mode (N2CM), flexibly applicable to 4- / 8-bit weighted data represented in two's complement. This invention achieves higher energy efficiency compared to traditional CMOS-based analog in-memory computing architectures and also achieves non-volatility.

Description

Technical Field

[0001] This invention belongs to the field of memory, and particularly relates to a high-efficiency analog in-memory computing architecture based on FeFET structure and its working method. It considers using FeFET device for high-efficiency and high-performance analog in-memory computing design with non-volatility. Background Technology

[0002] In the era of big data, deep neural networks (DNNs) are widely used in the field of artificial intelligence. However, with technological advancements and the exponential growth of data volume, the computational and storage requirements of DNNs have increased dramatically. Consequently, the large amount of data movement between memory and processing units has led to the "memory wall" bottleneck in the traditional von Neumann architecture. In-memory computing architectures integrate computational functions into memory, aiming to solve this problem by reducing the large amount of data movement. At the same time, the parallel processing capabilities of in-memory computing architectures are well-suited for efficiently executing the critical multiply-accumulate (MAC) operation in DNNs.

[0003] In the field of analog in-memory computing, many SRAM-based designs have been proposed, with the two most common implementation categories being analog and current-domain. However, the inherent binary storage characteristics of SRAM complicate the design of multi-bit in-memory computing circuits, and the large cell size and standby power consumption of SRAM limit area and energy efficiency. In contrast, emerging non-volatile memories (NVMs) such as resistive random access memory (ReRAM), magnetic random access memory (MRAM), and ferroelectric field-effect transistors (FeFETs) have attracted attention due to their compact structure and near-zero standby power consumption. In particular, FeFETs hold promise for building efficient analog in-memory computing designs to store weights and perform MAC operations in DNN inference due to their multi-bit storage, high switching ratio, and three-terminal read / write separation characteristics. Furthermore, like complementary metal-oxide-semiconductor (CMOS), FeFETs have both n-type (nFeFET) and p-type (pFeFET) device types and offer good CMOS compatibility.

[0004] In high-precision analog in-memory computing architecture design, multi-bit MAC data flow often uses n cells in adjacent columns to represent the n-bit weight value of each fixed point. External circuitry is used to combine n weighted partial MAC outputs based on different effective weight bits. This process is called weighted shift-addition. Currently, there are two processing methods: the first is called "digital shift-addition," which uses a multiplexer to send a portion of the MAC result of the selected column to an ADC for conversion, and then obtains the result through a digital shift-addition circuit. However, the time multiplexing of the ADC limits the throughput, and multiple selections also increase area overhead. The second is called "analog shift-addition," which completes the weighted shift-addition process before the ADC, thus allowing parallel generation of partial MAC results for each column. However, this scheme requires the design of dedicated analog circuitry, increasing area and power consumption. Furthermore, in both methods, the weighted shift-addition process and the partial MAC operation process are separated, leaving room for joint optimization exploration. Summary of the Invention

[0005] The purpose of this invention is to address the problem of insufficient performance of existing analog in-memory computing architectures by providing a high-energy-efficiency analog in-memory computing architecture based on FeFET structure and its working method, thereby achieving higher computing energy efficiency.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] This invention provides a first high-efficiency analog in-memory computing architecture based on FeFET structure. This high-efficiency analog in-memory computing architecture is a high-efficiency current-domain in-memory computing architecture, including a core 128*128 current-domain in-memory computing array, a word line input driver, a bit line BL / source line SL switch matrix, a reference area, 16 two's complement mode analog-to-digital converters (2CM ADCs), 16 non-two's complement mode analog-to-digital converters (N2CM ADCs), and 16 accumulation modules. The word line input driver is connected to the current-domain in-memory computing array via each word line WL and WLB, and the bit line BL / source line SL switch matrix is ​​connected to the current-domain in-memory computing array via each bit line BL and source line SL.

[0008] The current domain in-memory computing array is divided into 16 regions, each containing 4 high 4-bit blocks (H4B) and 4 low 4-bit blocks (L4B), 16 transmission gates (TG) and 2 transimpedance amplifiers (TIA);

[0009] Each high 4-bit block (H4B) and low 4-bit block (L4B) contains 32 rows * 4 columns of in-memory computation units, storing 32 signed and unsigned 4-bit weight data respectively. For the 32 rows * 4 columns of in-memory computation units in the high 4-bit block (H4B), in-memory computation units located in the same column share the bit line BL and the source line SL. In a row of in-memory computation units, the in-memory computation units corresponding to the sign bit of the high 4-bit block (H4B) share the word line WLS, and the remaining in-memory computation units share another word line WL. For the 32 rows * 4 columns of in-memory computation units in the low 4-bit block (L4B), in-memory computation units located in the same column share the bit line BL and the source line SL, and in-memory computation units located in the same row share another word line WL.

[0010] In the current-domain in-memory computing array, the outputs of two transimpedance amplifiers (TIAs) in each region are connected to one two's complement analog-to-digital converter (2CM ADC) and one non-two's complement analog-to-digital converter (N2CM ADC), respectively. The reference region has the same structure as the regions in the current-domain in-memory computing array, and its two transimpedance amplifiers (TIAs) are connected to 16 two's complement analog-to-digital converters (2CM ADCs) and 16 non-two's complement analog-to-digital converters (N2CM ADCs), respectively. The output of each two's complement analog-to-digital converter (2CM ADC) and non-two's complement analog-to-digital converter (N2CM ADC) is connected to an accumulation module.

[0011] Furthermore, the in-memory computing unit is composed of 1nFeFET1R, storing 1-bit weighted data. The conduction current of the in-memory computing unit presents a binary weighted mode corresponding to the 4-bit weight by adjusting the resistor size. The sign bit of the high 4-bit block (H4B) corresponds to the source of the nFeFET device in the 1nFeFET1R structure of the in-memory computing unit being connected to the bit line BL, the gate being connected to the word line WLS, the drain being connected to one end of the resistor, and the other end of the resistor being connected to the source line SL. The non-sign bit of the high 4-bit block (H4B) corresponds to the source of the nFeFET device in the 1nFeFET1R structure of the in-memory computing unit and all in-memory computing units in L4B being connected to the source line SL, the gate being connected to another word line WL, the drain being connected to one end of the resistor, and the other end of the resistor being connected to the bit line BL.

[0012] The present invention also provides a method for operating a high-efficiency analog in-memory computing architecture based on the FeFET structure as described above, comprising:

[0013] This high-efficiency analog in-memory computing architecture can perform MAC calculations on unsigned multi-bit input data and 4- / 8-bit weight data in two's complement representation in parallel. Before the high-efficiency analog in-memory computing architecture starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in the in-memory computing units of adjacent high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in the same area, respectively.

[0014] During operation, multi-bit input data is calculated serially in multiple cycles.

[0015] In each cycle, single-bit input data is fed into a pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in each region via word line WLS and word line WL. The negative input terminals of the transimpedance amplifiers (TIA) in each pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) are connected to the four bit lines BL through the conduction of the transmission gate (TG). The source line SL[7] corresponding to the weighted sign bit is connected to VDD. i The remaining bits are grounded to the source lines SL[6]-SL[0], thus realizing single-bit multiplication in the memory computing unit. If the result is "1", the memory computing unit generates a binary weighted mode unit conduction current, and the current direction corresponding to the sign bit is opposite to that of the remaining bits. Part of the MAC calculation results of each column in a high 4-bit block (H4B) or low 4-bit block (L4B) are gathered on the bit line BL in the form of current, and the transimpedance amplifier (TIA) in the high 4-bit block (H4B) and low 4-bit block (L4B) respectively gather the current of the four bit lines BL to generate the output voltage; then the two output voltages of each region are converted by 2CMADC and N2CM ADC respectively and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of the period.

[0016] After multiple cycles of calculation, the MAC calculation results are finally obtained in parallel in each cumulative module.

[0017] The present invention also provides a second high-efficiency analog in-memory computing architecture based on FeFET structure. This high-efficiency analog in-memory computing architecture is a high-efficiency charge-domain in-memory computing architecture, including a 128*128 charge-domain in-memory computing array, a word line input driver, a bit line BL / source line SL switch matrix, a reference area, 16 two's complement mode analog-to-digital converters (2CM ADCs), 16 non-two's complement mode analog-to-digital converters (N2CM ADCs), and 16 accumulation modules. The word line input driver is connected to the charge-domain in-memory computing array via each word line WL and WLB, and the bit line BL / source line SL switch matrix is ​​connected to the charge-domain in-memory computing array via each bit line BL and source line SL.

[0018] The charge domain in-memory computing array is divided into 16 regions, each containing 4 high 4-bit blocks (H4B) and 4 low 4-bit blocks (L4B), 16 transmission gates (TG), 8 bit line capacitors (Cap) and 8 bit line precharge transistors (PCT).

[0019] Each high 4-bit block (H4B) and low 4-bit block (L4B) contains 32 rows * 4 columns of in-memory computation units, storing 32 signed and unsigned 4-bit weight data respectively. For the 32 rows * 4 columns of in-memory computation units in the high 4-bit block (H4B), in-memory computation units located in the same column share the bit line BL and the source line SL. In a row of in-memory computation units, the in-memory computation units corresponding to the sign bit of the high 4-bit block (H4B) share the word line WLS, and the remaining in-memory computation units share another word line WL. For the 32 rows * 4 columns of in-memory computation units in the low 4-bit block (L4B), in-memory computation units located in the same column share the bit line BL and the source line SL, and in-memory computation units located in the same row share another word line WL.

[0020] In the charge domain in-memory computing array, each region's two outputs are connected to one two's complement analog-to-digital converter (2CM ADC) and one non-two's complement analog-to-digital converter (N2CM ADC), respectively. The reference region has the same structure as the regions in the charge domain in-memory computing array, and its two TIA outputs are connected to 16 two's complement analog-to-digital converters (2CM ADCs) and 16 non-two's complement analog-to-digital converters (N2CM ADCs), respectively. The output of each two's complement analog-to-digital converter (2CM ADC) and non-two's complement analog-to-digital converter (N2CM ADC) is connected to an accumulation module.

[0021] Furthermore, the in-memory computing unit is composed of 1nFeFET or 1pFeFET, storing 1-bit weighted data. The conduction current of the in-memory computing unit is adjusted by the threshold voltage Vth to present a binary weighted mode corresponding to the 4-bit weight. The sign bit of the high 4-bit block (H4B) corresponds to the drain of the pFeFET device in the 1pFeFET structure of the in-memory computing unit being connected to the bit line BL, the gate being connected to the word line WLS, and the source being connected to the source line SL. The non-sign bit of the high 4-bit block (H4B) corresponds to the drain of the nFeFET device in the 1nFeFET structure of the in-memory computing unit and all in-memory computing units in the low 4-bit block (L4B) being connected to the bit line BL, the gate being connected to another word line WL, and the source being connected to the source line SL.

[0022] The present invention also provides a method for operating a high-energy-efficiency analog in-memory computing architecture as described above, comprising:

[0023] This high-efficiency analog in-memory computing architecture can perform MAC calculations in parallel for unsigned multi-bit input data and 4- / 8-bit weight data in two's complement representation. Before the 1pFeFET starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in the in-memory computing units of adjacent high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in the same area, respectively.

[0024] During operation, multi-bit input data is calculated serially in multiple cycles.

[0025] In each cycle, the source line SL[7] corresponding to the weight sign bit is connected to VDD. q The remaining bits correspond to the source lines SL[6]-SL[0] grounded; firstly, during the pre-charge stage, all transmission gates (TG) are turned off, and the pre-charge transistor (PCT) is turned on to pre-charge the bit line capacitor (Cap) to 1.5V; then, the single-bit input data is sent to a pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in each area through word lines WLS and WL, thereby realizing single-bit multiplication in the in-memory computing unit. Subsequently, if the result is "1", the in-memory computing unit is turned on, causing a binary weighted mode voltage change on the bit line capacitor (Cap), which is equivalent to the in-memory computing unit with the sign bit turned on. The computation unit charges the bit line capacitor (Cap), while the remaining in-memory computation units discharge the bit line capacitor (Cap). Partial MAC calculation results from each column of a high 4-bit block (H4B) or low 4-bit block (L4B) are collected on the bit line capacitor (Cap) in a charging and discharging manner. Then, during the charge sharing phase, input is stopped, and the four bit line capacitors (Cap) in the high 4-bit block (H4B) and low 4-bit block (L4B) are redistributed through the conduction of the transmission gate (TG) to generate output voltages. Next, the two output voltages from each region are converted by a two's complement mode analog-to-digital converter (2CM ADC) and a non-two's complement mode analog-to-digital converter (N2CM ADC), and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of that cycle.

[0026] After multiple cycles of calculation, the MAC calculation results are finally obtained in parallel in each cumulative module.

[0027] The beneficial effects of this invention are as follows:

[0028] The two analog in-memory computing architecture designs in this invention can improve computing energy efficiency.

[0029] (1) For the current-domain in-memory computing architecture design, each in-memory computing unit adopts a 1nFeFET1R structure. The unit's on-state current is adjusted by the resistor value to present a binary weighted mode corresponding to the 4-bit weights, and the current of the four bit lines BL is directly converged through a transimpedance amplifier to generate the output voltage. Thus, the shift and addition process of 4-bit weights is integrated into the array, thereby reducing computing power consumption and overall area overhead. Since the in-memory computing unit area of ​​this design is small, it can bring about a reduction in production costs.

[0030] (2) For the in-memory computing architecture design in the charge domain, each in-memory computing unit adopts a 1nFeFET / 1pFeFET structure. The unit's on-state current adjusts the threshold voltage Vth to present a binary weighted mode corresponding to the 4-bit weights, and acts on the voltage change of the bit line capacitors. The capacitors in the four columns achieve charge sharing through charge redistribution, thereby integrating the shifting and addition process of 4-bit weights in the array, thus reducing computing power consumption and overall area overhead. Since the in-memory computing unit area of ​​this design is small, it can bring about a reduction in production costs. Attached Figure Description

[0031] Figure 1 (a) is a schematic diagram of the current domain in-memory computing architecture. Figure 1 (b) is a schematic diagram of the H4B structure with transmission gates in the current-domain in-memory computing architecture. Figure 1 (c) is a schematic diagram of the L4B structure with transimpedance amplifiers and transmission gates in the current-domain in-memory computing architecture. Figure 1 (d) is a schematic diagram of the 1nFeFET1R structure of the cell corresponding to the sign bit in the current domain in-memory computing architecture. Figure 1 (e) is a schematic diagram of the 1nFeFET1R structure of the remaining bits in the current domain in-memory computing architecture.

[0032] Figure 2 This is the Id-Vg curve of the 1nFeFET1R cell in the current domain in-memory computing architecture.

[0033] Figure 3 (a) is a schematic diagram of the operation of 1-bit input and 8-bit weight multiplication in H4B of the current domain in-memory computing architecture. Figure 3 (b) is a schematic diagram of the operation of 1-bit input and 8-bit weight multiplication in L4B of the current domain in-memory computing architecture. Figure 3 (c) is a transient simulation waveform of the 1-bit input and 8-bit weight multiplication of the current domain in-memory computing architecture operating in (a) H4B and (b) L4B.

[0034] Figure 4 (a) is a schematic diagram of the charge domain in-memory computing architecture. Figure 4(b) is a schematic diagram of the H4B structure with precharged transistors and transmission gates in the charge domain in-memory computing architecture. Figure 4 (c) is a schematic diagram of the L4B structure with bit line capacitance and transmission gate in the charge domain in-memory computing architecture. Figure 4 (d) is a schematic diagram of the 1nFeFET1R structure of the cell corresponding to the sign bit in the charge domain in-memory computing architecture. Figure 4 (e) is a schematic diagram of the 1nFeFET1R structure of the remaining bits in the charge domain in-memory computing architecture;

[0035] Figure 5 (a) is the Id-Vg curve of a 1pFeFET cell. Figure 5 (b) is the Id-Vg curve of 1nFeFET;

[0036] Figure 6 (a) is a schematic diagram of the operation of 1-bit input and 8-bit weight multiplication in H4B of the charge domain in-memory computing architecture. Figure 6 (b) is a schematic diagram of the operation of 1-bit input and 8-bit weight multiplication in L4B of the charge domain in-memory computing architecture. Figure 6 (c) is a transient simulation waveform of the 1-bit input and 8-bit weight multiplication of the charge domain in-memory computing architecture in H4B and L4B.

[0037] Figure 7 (a) is the cell current histogram of the current domain in-memory computing architecture. Figure 7 (b) is the cell current histogram of the charge domain in-memory computing architecture;

[0038] Figure 8 (a) MAC output results of 32 1-bit inputs and 4-bit weights under the H4B current-domain in-memory computing architecture. Figure 8 (b) MAC output results of 32 1-bit inputs and 4-bit weights under L4B in the current domain in-memory computing architecture. Figure 8 (c) MAC output results of 32 1-bit inputs and 4-bit weights under the H4B in-memory computing architecture in the charge domain. Figure 8 (d) MAC output results of 32 1-bit inputs and 4-bit weights under L4B in charge domain in-memory computing architecture;

[0039] Figure 9 This is a comparison chart of the average computational energy efficiency of the current-domain in-memory computing architecture and the charge-domain in-memory computing architecture at different levels of precision, using 32 inputs and weights. Detailed Implementation

[0040] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0041] Please see Figures 1-3 A high-efficiency analog in-memory computing architecture based on FeFET structure, which is a high-efficiency current-domain in-memory computing architecture, such as... Figure 1 As shown in (a), the current-domain in-memory computing architecture includes a core 128*128 current-domain in-memory computing array, a word line input driver, a bit line BL / source line SL switch matrix, a reference area, 16 two's complement mode analog-to-digital converters (2CMADCs), 16 non-two's complement mode analog-to-digital converters (N2CMADCs), 16 accumulation modules, and other peripheral circuits. The word line input driver is connected to the current-domain in-memory computing array via each word line WL and WLB, and the bit line BL / source line SL switch matrix is ​​connected to the current-domain in-memory computing array via each bit line BL and source line SL. The current-domain in-memory computing array is divided into 16 areas, each containing 4 H4Bs and 4 L4Bs, 16 transmission gates, and 2 transimpedance amplifiers. Figure 1 As shown in (b) and (c), each H4B and L4B contains 32 rows * 4 columns of in-memory computing units, storing 32 signed and unsigned 4-bit weight data respectively. Units in the same column share the bit line BL and the source line SL. Units corresponding to the sign bits of the H4B in the same row share the word line WLS, and the remaining units in the same row share another word line WL. The outputs of the two transimpedance amplifiers (TIAs) in each region of the current-domain in-memory computing array are connected to one two's complement mode analog-to-digital converter (2CMADC) and one non-two's complement mode analog-to-digital converter (N2CMADC), respectively. The structure of the reference region is the same as that of the regions in the current-domain in-memory computing array, and the outputs of the two transimpedance amplifiers (TIAs) therein are connected to 16 two's complement mode analog-to-digital converters (2CMADCs) and 16 non-two's complement mode analog-to-digital converters (N2CMADCs), respectively. The output of each two's complement mode analog-to-digital converter (2CMADC) and non-two's complement mode analog-to-digital converter (N2CMADC) is connected to an accumulation module. Figure 1 As shown in (d) and (e), the in-memory computing unit is composed of a 1nFeFET1R, storing 1-bit weighted data. The cell's conduction current adjusts the resistor value to present a binary weighting mode corresponding to the 4-bit weight. In the 1nFeFET1R structure of the H4B sign bit corresponding cell, the source of the nFeFET device is connected to the bit line BL, the gate is connected to the word line WLS, the drain is connected to one end of the resistor, and the other end of the resistor is connected to the source line SL. In the 1nFeFET1R structure of the H4B non-sign bit corresponding cell and all L4B cells, the source of the nFeFET device is connected to the source line SL, the gate is connected to another word line WL, the drain is connected to one end of the resistor, and the other end of the resistor is connected to the bit line BL.

[0042] The working method of the above current-domain in-memory computing architecture is as follows:

[0043] (1) Before the architecture starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in adjacent H4B and L4B cells in the same area respectively.

[0044] (2) During the operation, multi-bit input data is calculated in serial form in multiple cycles.

[0045] (2.1) As Figure 3 As shown, in each cycle, single-bit input data is sent to a pair of H4B and L4B in each region through WLS and WL. The negative input terminals of the transimpedance amplifiers in the two blocks are connected to the four bit lines BL through the conduction of the transmission gate. The source line SL[7] corresponding to the weight sign bit is connected to VDDi, and the source lines SL[6]-SL[0] corresponding to the other bits are grounded, thereby realizing single-bit multiplication in the unit. If the result is "1", such as Figure 2 As shown, the cell generates a binary weighted mode cell conduction current, with the current direction corresponding to the sign bit opposite to the other bits. Partial MAC calculation results from each column of a high 4-bit block (H4B) or low 4-bit block (L4B) are converged onto the bit line BL in the form of current. The transimpedance amplifiers in H4B and L4B respectively converge the currents from the four bit lines BL to generate output voltages. Then, the two output voltages of each region are converted by 2CMADC and N2CMADC respectively and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of that cycle.

[0046] (2.2) After multiple cycles, the MAC calculation results are finally obtained in parallel in each cumulative module.

[0047] Please see Figures 4-6 A high-efficiency analog in-memory computing architecture based on FeFET structure, which is a high-efficiency charge domain in-memory computing architecture, such as... Figure 4 As shown in (a), the charge-domain in-memory computing architecture includes a 128*128 charge-domain in-memory computing array, a word line input driver, a bit line (BL) / source line (SL) switch matrix, a reference region, 16 2CMADCs, 16 N2CMADCs, 16 accumulation modules, and other peripheral circuits. The charge-domain in-memory computing array is divided into 16 regions, each containing 4 H4Bs and 4 L4Bs, 16 transmission gates, 8 bit line capacitors, and 8 bit line precharge transistors. Figure 4 As shown in (b) and (c), each H4B and L4B contains 32 rows * 4 columns of in-memory computation units, storing 32 signed and unsigned 4-bit weight data respectively. Units in the same column share the bit line BL and the source line SL. Units corresponding to the sign bit in the same row of H4B share the word line WLS, and the remaining units in the same row share another word line WL. Figure 4As shown in (d) and (e), the in-memory computing unit is composed of 1nFeFET / 1pFeFET, storing 1-bit weighted data. The cell conduction current is adjusted by the threshold voltage Vth to present a binary weighted mode corresponding to 4-bit weights. In the 1pFeFET structure of the cell corresponding to the H4B sign bit, the drain of the pFeFET device is connected to the bit line BL, the gate is connected to the word line WLS, and the source is connected to the source line SL. In the 1nFeFET structure of the cell corresponding to the H4B non-sign bit and all cells of L4B, the drain of the nFeFET device is connected to the bit line BL, the gate is connected to another word line WL, and the source is connected to the source line SL.

[0048] The working method of the above charge domain in-memory computing architecture is as follows:

[0049] (1) Before the architecture starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in adjacent H4B and L4B cells in the same area respectively;

[0050] (2) During the operation, multi-bit input data is calculated serially in multiple cycles;

[0051] (2.1) As Figure 6 As shown, in each cycle, the source line SL[7] corresponding to the weight sign bit is connected to VDD. q The remaining bits correspond to the source lines SL[6]-SL[0] grounded. First, during the pre-charge phase, all transmission gates are turned off, and the pre-charge transistor is turned on to pre-charge the bit line capacitor to 1.5V; then, the single-bit input data is sent to a pair of H4B and L4B in each region through WLS and WL, thereby realizing single-bit multiplication in the cell. Then, if the result is "1", such as Figure 5 As shown in (a), the conduction of this unit causes a binary weighted voltage change across the capacitor, which is equivalent to the sign bit conducting unit charging the capacitor, as shown in (a). Figure 5 As shown in (b), the remaining bit-conducting units discharge the capacitors, and the partial MAC calculation results of each column in a high 4-bit block (H4B) or low 4-bit block (L4B) are collected on the bit line capacitors in a charging and discharging manner. Subsequently, the input is stopped in the charge sharing stage, and the charge is redistributed to the four bit line capacitors in H4B and L4B respectively through the conduction of the transmission gate to generate the output voltage. Then, the two output voltages of each region are converted by 2CM ADC and N2CM ADC respectively and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of that cycle.

[0052] (2.2) After multiple cycles, the MAC calculation results are finally obtained in parallel in each cumulative module.

[0053] The functions and effects of this invention are further illustrated and demonstrated through the following simulation experiments:

[0054] 1. Simulation conditions

[0055] The experiment used a physical circuit-compatible SPECTRE and SPICE model to simulate FeFETs, based on the Preisach model. This model enables efficient design and analysis and has been widely used in FeFET circuit design. The basic transistor used in the simulation was the UMC 40nm model.

[0056] During simulation, SPECTRE software was used to simulate the in-memory computation design in the current and charge domains. The applicant also compared the results with non-patent literature 1 (X. Si et al., “15.5a 28nm 64kb 6t SRAM computing-in-memory macro with 8b MAC operation for AI edge chips,” in 2020 IEEE ISSCC, pp. 246–248, 2020), non-patent literature 2 (J. Yue et al., “14.3a 65nm computing-in-memory-based CNN processor with 2.9-to-35.8tops / w system energy efficiency using dynamic-sparsityperformance-scaling architecture and energy-efficient inter / intra-macro data reuse,” in 2020 IEEE ISSCC, pp. 234–236, 2020), and non-patent literature 3 (J.-W. Su et al., “16.3a 28nm…”). 384kb 6t-sram computation-in-memory macro with 8bprecision for ai edge chips," in 2021IEEE ISSCC, vol.64, pp.250–252, 2021), Non-Patent Document 4 (C.-X.Xue et al., "16.1a 22nm 4mb 8b-precision reram computing-in-memorymacro with 11.91to 195.7tops / w for tiny ai edge devices," in 2021IEEE ISSCC, pp.245–247, 2021), Non-Patent Document 5 (J.-M.Hung et al., "A four-megabit compute-in-memory macro with eight-bit precision based on cmos and resistive random-access memory for ai edge devices," Nature Electronics, vol.4, no.12, pp.921–930, 2021) and non-patent literature 6 (J.-M).The computational energy efficiency of six analog in-memory computing designs, as described in Hung et al.'s paper, "8-b precision 8-mb reram compute-in-memory macro using direct-current-free time-domain readout scheme for AI edge devices," IEEE JSSC, vol. 58, no. 1, pp. 303–315, 2022, was compared.

[0057] 2. Simulation Results

[0058] 1) Unit robustness analysis

[0059] The applicant first conducted Monte Carlo simulations to evaluate the impact of FeFET threshold voltage variations (σ = 40mV) on the conduction current of each cell. In the current-domain in-memory computing architecture, such as... Figure 7 As shown in (a), the drain resistance of the 1nFeFET1R cell significantly suppresses the fluctuation of the on-current. In the charge-domain in-memory computing architecture, no drain resistance is added to ensure that the FeFET operates in the saturation region and maintains sufficient linearity. The corresponding cell on-current results are as follows. Figure 7 As shown in (b).

[0060] 2) Linearity Analysis

[0061] Then, the applicant thoroughly analyzed all possible input and weight combinations, simulating the MAC output of 32 1-bit inputs and 4-bit weights in H4B and L4B under two designs. For example... Figure 8 As shown, the results under both architectures exhibit good linearity. Furthermore, through 60 Monte Carlo simulations for each case, the applicant observed the effect of the FeFET threshold voltage variation (σ = 40mV) on the output voltage, compared with... Figure 7 The effect on the unit current is consistent.

[0062] 3) Calculate energy efficiency analysis

[0063] In terms of calculating energy efficiency, such as Figure 9 As shown, the applicant evaluated the average computational efficiency of 32 inputs and weights at different accuracies for two designs, with the ADC accuracy set to 5-bit. It can be seen that computational efficiency decreases with increasing input / weight accuracy. At the same accuracy setting, the current-domain in-memory computing architecture has lower computational efficiency than the charge-domain in-memory computing architecture. This is because the transimpedance amplifier in the current-domain in-memory computing architecture consumes more power than the pre-charging power consumption in the charge-domain in-memory computing architecture.

[0064] 4) Performance Comparison

[0065] The table below compares the high-efficiency analog in-memory computing design based on the FeFET structure of this invention with other analog in-memory computing designs. To ensure a relatively fair comparison of energy efficiency, all designs are scaled to a 40nm process node. The design in Non-Patent Document 2 incorporates additional sparsity optimizations.

[0066]

[0067]

[0068] As shown in the table above, without considering sparsity optimization, the high-efficiency analog in-memory computing design based on the FeFET structure of this invention achieves the highest computational efficiency with 8-bit input and weight precision. Furthermore, the computational efficiency of the charge-domain architecture of this invention is slightly higher than that of the current-domain architecture. Specifically, the computational efficiency of the charge-domain in-memory computing architecture of this invention is 1.56 times and 2.22 times higher than the latest SRAM design (Non-Patent Document 3) and ReRAM design (Non-Patent Document 6), respectively. This is mainly attributed to the fact that the design of this invention inherits the weight shift-addition process in the array, which eliminates the additional hardware overhead required to handle the shift-addition process in multi-bit weight processing.

[0069] The results above show that this invention not only possesses the non-volatility that is difficult to achieve in CMOS design, but also features compact design and high computational efficiency.

[0070] The above embodiments are used to explain and illustrate the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A high-efficiency analog in-memory computing architecture based on FeFET structure, characterized in that, This high-efficiency analog in-memory computing architecture is a high-efficiency current-domain in-memory computing architecture, including a core 128*128 current-domain in-memory computing array, a word line input driver, a bit line BL / source line SL switch matrix, a reference area, 16 two's complement mode analog-to-digital converters (2CM ADCs), 16 non-two's complement mode analog-to-digital converters (N2CM ADCs), and 16 accumulation modules. Among them, the word line input driver is connected to the current-domain in-memory computing array through each word line WL and WLB, and the bit line BL / source line SL switch matrix is ​​connected to the current-domain in-memory computing array through each bit line BL and source line SL. The current domain in-memory computing array is divided into 16 regions, each containing 4 high 4-bit blocks (H4B) and 4 low 4-bit blocks (L4B), 16 transmission gates (TG) and 2 transimpedance amplifiers (TIA). Each high 4-bit block (H4B) and low 4-bit block (L4B) contains 32 rows * 4 columns of in-memory computation units, storing 32 signed and unsigned 4-bit weight data respectively. For the 32 rows * 4 columns of in-memory computation units in the high 4-bit block (H4B), in-memory computation units located in the same column share the bit line BL and the source line SL. In a row of in-memory computation units, the in-memory computation units corresponding to the sign bit of the high 4-bit block (H4B) share the word line WLS, and the remaining in-memory computation units share another word line WL. For the 32 rows * 4 columns of in-memory computation units in the low 4-bit block (L4B), in-memory computation units located in the same column share the bit line BL and the source line SL, and in-memory computation units located in the same row share another word line WL. In the current-domain in-memory computing array, the outputs of two transimpedance amplifiers (TIAs) in each region are connected to one two's complement analog-to-digital converter (2CM ADC) and one non-two's complement analog-to-digital converter (N2CM ADC), respectively. The reference region has the same structure as the regions in the current-domain in-memory computing array, and its two transimpedance amplifiers (TIAs) are connected to 16 two's complement analog-to-digital converters (2CM ADCs) and 16 non-two's complement analog-to-digital converters (N2CM ADCs), respectively. The output of each two's complement analog-to-digital converter (2CM ADC) and non-two's complement analog-to-digital converter (N2CM ADC) is connected to an accumulation module.

2. The high-efficiency analog in-memory computing architecture based on FeFET structure according to claim 1, characterized in that, The in-memory computing unit is composed of 1nFeFET1R, which stores 1-bit weighted data. The conduction current of the in-memory computing unit presents a binary weighted mode corresponding to the 4-bit weight by adjusting the size of the resistor. The sign bit of the high 4-bit block (H4B) corresponds to the source of the nFeFET device in the 1nFeFET1R structure of the in-memory computing unit being connected to the bit line BL, the gate being connected to the word line WLS, the drain being connected to one end of the resistor, and the other end of the resistor being connected to the source line SL. The non-sign bit of the high 4-bit block (H4B) corresponds to the source of the nFeFET device in the 1nFeFET1R structure of the in-memory computing unit and all in-memory computing units in the low 4-bit block (L4B) being connected to the source line SL, the gate being connected to another word line WL, the drain being connected to one end of the resistor, and the other end of the resistor being connected to the bit line BL.

3. A method for operating a high-efficiency analog in-memory computing architecture based on a FeFET structure as described in claim 1 or 2, characterized in that, include: This high-efficiency analog in-memory computing architecture can perform MAC calculations on unsigned multi-bit input data and 4- / 8-bit weight data in two's complement representation in parallel. Before the high-efficiency analog in-memory computing architecture starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in the in-memory computing units of adjacent high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in the same area, respectively. During operation, multi-bit input data is calculated serially in multiple cycles. In each cycle, single-bit input data is fed into a pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in each region via word line WLS and word line WL. The negative input terminals of the transimpedance amplifiers (TIA) in each pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) are connected to the four bit lines BL through the conduction of the transmission gate (TG). The source line SL[7] corresponding to the weighted sign bit is connected to VDD. i The remaining bits are grounded to the source lines SL[6]-SL[0], thus realizing single-bit multiplication in the memory computing unit. If the result is "1", the memory computing unit generates a binary weighted mode unit conduction current, and the current direction corresponding to the sign bit is opposite to that of the remaining bits. Part of the MAC calculation results of each column in a high 4-bit block (H4B) or low 4-bit block (L4B) are gathered on the bit line BL in the form of current, and the transimpedance amplifier (TIA) in the high 4-bit block (H4B) and low 4-bit block (L4B) respectively gather the current of the four bit lines BL to generate the output voltage. Then, the two output voltages of each region are converted by the two-complement mode analog-to-digital converter (2CM ADC) and the non-two-complement mode analog-to-digital converter (N2CM ADC) respectively and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of the cycle. After multiple cycles of calculation, the MAC calculation results are finally obtained in parallel in each cumulative module.

4. A high-efficiency analog in-memory computing architecture based on FeFET structure, characterized in that, This high-efficiency analog in-memory computing architecture is a high-efficiency charge-domain in-memory computing architecture, including a 128*128 charge-domain in-memory computing array, a word line input driver, a bit line BL / source line SL switch matrix, a reference area, 16 two's complement mode analog-to-digital converters (2CM ADCs), 16 non-two's complement mode analog-to-digital converters (N2CM ADCs), and 16 accumulation modules. The word line input driver is connected to the charge-domain in-memory computing array via each word line WL and WLB, and the bit line BL / source line SL switch matrix is ​​connected to the charge-domain in-memory computing array via each bit line BL and source line SL. The charge domain in-memory computing array is divided into 16 regions, each containing 4 high 4-bit blocks (H4B) and 4 low 4-bit blocks (L4B), 16 transmission gates (TG), 8 bit line capacitors (Cap) and 8 bit line precharge transistors (PCT). Each high 4-bit block (H4B) and low 4-bit block (L4B) contains 32 rows * 4 columns of in-memory computation units, storing 32 signed and unsigned 4-bit weight data respectively. For the 32 rows * 4 columns of in-memory computation units in the high 4-bit block (H4B), in-memory computation units located in the same column share the bit line BL and the source line SL. In a row of in-memory computation units, the in-memory computation units corresponding to the sign bit of the high 4-bit block (H4B) share the word line WLS, and the remaining in-memory computation units share another word line WL. For the 32 rows * 4 columns of in-memory computation units in the low 4-bit block (L4B), in-memory computation units located in the same column share the bit line BL and the source line SL, and in-memory computation units located in the same row share another word line WL. In the charge domain in-memory computing array, each region's two outputs are connected to one two's complement analog-to-digital converter (2CM ADC) and one non-two's complement analog-to-digital converter (N2CM ADC), respectively. The reference region has the same structure as the regions in the charge domain in-memory computing array, and its two TIA outputs are connected to 16 two's complement analog-to-digital converters (2CM ADCs) and 16 non-two's complement analog-to-digital converters (N2CM ADCs), respectively. The output of each two's complement analog-to-digital converter (2CM ADC) and non-two's complement analog-to-digital converter (N2CM ADC) is connected to an accumulation module.

5. A high-efficiency analog in-memory computing architecture based on FeFET structure according to claim 4, characterized in that, The in-memory computing unit is composed of 1nFeFET or 1pFeFET, storing 1-bit weighted data. The conduction current of the in-memory computing unit is adjusted by the threshold voltage Vth to present a binary weighted mode corresponding to the 4-bit weight. The sign bit of the high 4-bit block (H4B) corresponds to the drain of the pFeFET device in the 1pFeFET structure of the in-memory computing unit, which is connected to the bit line BL, the gate is connected to the word line WLS, and the source is connected to the source line SL. The non-sign bit of the high 4-bit block (H4B) corresponds to the drain of the nFeFET device in the 1nFeFET structure of the in-memory computing unit and all in-memory computing units in the low 4-bit block (L4B), which is connected to the bit line BL, the gate is connected to another word line WL, and the source is connected to the source line SL.

6. A method for operating a high-energy-efficiency analog in-memory computing architecture as described in claim 4 or 5, characterized in that, include: This high-efficiency analog in-memory computing architecture can perform MAC calculations in parallel for unsigned multi-bit input data and 4- / 8-bit weight data in two's complement representation. Before the 1pFeFET starts working, each 8-bit weight data involved in the calculation is divided into high 4 bits and low 4 bits and stored in the in-memory computing units of adjacent high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in the same area, respectively. During operation, multi-bit input data is calculated serially in multiple cycles. In each cycle, the source line SL[7] corresponding to the weight sign bit is connected to VDD. q The remaining bits correspond to the source lines SL[6]-SL[0] grounded; firstly, during the pre-charge phase, all transmission gates (TG) are turned off, and the pre-charge transistor (PCT) is turned on to pre-charge the bit line capacitor (Cap) to 1.5V; then, the single-bit input data is sent to a pair of high 4-bit blocks (H4B) and low 4-bit blocks (L4B) in each region through word lines WLS and WL, thereby realizing single-bit multiplication in the memory computing unit. Subsequently, if the result is "1", the memory computing unit is turned on, causing a binary weighted mode voltage change on the bit line capacitor (Cap), which is equivalent to the sign bit being turned on in the memory computing unit. The computation unit charges the bit line capacitor (Cap), while the remaining in-memory computation units discharge the bit line capacitor (Cap). Partial MAC calculation results from each column of a high 4-bit block (H4B) or low 4-bit block (L4B) are collected on the bit line capacitor (Cap) in a charging and discharging manner. Then, during the charge sharing phase, input is stopped, and the four bit line capacitors (Cap) in the high 4-bit block (H4B) and low 4-bit block (L4B) are redistributed through the conduction of the transmission gate (TG) to generate output voltages. Next, the two output voltages from each region are converted by a two's complement mode analog-to-digital converter (2CM ADC) and a non-two's complement mode analog-to-digital converter (N2CM ADC), and combined in the accumulation module to obtain the calculation result corresponding to the single-bit input of that cycle. After multiple cycles of calculation, the MAC calculation results are finally obtained in parallel in each cumulative module.

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