A selective three-module redundancy method based on improved KL algorithm

Abstract

The selective three-mode redundancy method based on the improved KL algorithm can take into account the anti-SEU capability and the hardware overhead after redundancy, compared with the full three-mode redundancy method, the selective three-mode redundancy can save a large amount of additional overhead, and meanwhile, the circuit anti-single particle reliability requirement can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to a selective triple modular redundancy method based on improved KL algorithm, and belongs to the technical field of integrated circuit anti-radiation hardening. BACKGROUND

[0002] Electronic devices in spacecraft will inevitably be in a complex space radiation environment, and radiation will cause varying degrees of damage to integrated circuits in electronic devices, causing the entire electronic system to malfunction or even collapse. Integrated circuits in space environment will face various forms of radiation effects, and single event upset (SEU) is one of the main radiation effects. Single event upset will cause a series of errors such as jump of circuit logic state, flip of stored data or interruption of system function. Therefore, it is necessary to harden against single event upset effect.

[0003] A common method to alleviate single event upset is triple modular redundancy (TMR), which basically copies the node into three parts, provides the same input to all redundant nodes, and then uses a majority voter to determine the correct output according to the principle of minority submitting to majority. TMR not only can detect the existence of errors, but also can shield errors and output the expected correct value, but it brings large area, power consumption and delay overhead, which has a great impact on circuit performance.

[0004] Recent researches have shown that the sensitivity of nodes in the circuit to soft errors is different, and the sensitivity of some nodes to soft errors is obviously higher than that of other nodes. It is this phenomenon that can harden the soft error sensitive nodes in the circuit and ignore the nodes that almost do not have soft errors, although the reliability is reduced, but the area overhead is significantly reduced, thereby creating an opportunity to get higher reliability with lower area overhead. Therefore, selective hardening has become a new trend in the development of fault-tolerant technology, which can be applied to combinational logic and sequential logic. SUMMARY

[0005] The technical problem solved by the present application is that the present existing technology has too much hardware overhead of full triple modular redundancy, and a selective triple modular redundancy method based on improved KL algorithm is proposed.

[0006] The present application solves the above technical problem by the following technical scheme:

[0007] A selective triple modular redundancy method based on improved KL algorithm, comprising:

[0008] read the circuit netlist file to obtain the circuit connection relationship, estimate the soft error sensitivity of the circuit node according to the topology criterion, and initially group all circuit nodes, the grouping categories are SEU sensitive class and SEU insensitive class;

[0009] perform triple modular redundancy on the SEU sensitive node and construct a triple modular redundancy circuit;

[0010] preset the error threshold and termination condition of each output end of the triple modular redundancy circuit, perform fault injection on the external system, and perform fault tolerance analysis on the external system, judge whether the fault tolerance analysis result meets the termination condition, if the termination condition is met, end the optimization process, otherwise, optimize the SEU sensitive node by using the improved KL algorithm and reconstruct the triple modular redundancy circuit until the termination condition is met;

[0011] complete the optimization of the SEU sensitive node and the optimization of the triple modular redundancy circuit.

[0012] The topology criterion includes criterion one, criterion two and criterion three, which are respectively:

[0013] Criterion one is a fan-in, fan-out node selection criterion, criterion two is a target circuit node influence external system output quantity criterion, and criterion three is a target circuit node feedback loop quantity criterion. Each circuit node is judged by using three topology criteria, and when any one criterion is met, the category of the current circuit node is judged according to the selected criterion and grouped.

[0014] The fan-in, fan-out node selection criterion is:

[0015] Set an n*n adjacency matrix (n∈N), regard the circuit connection relationship as a finite directed graph including n circuit nodes, regard each non-diagonal line a ij As the direct connection between flip-flop i and flip-flop j, regard each diagonal line a ii As the feedback or loop at flip-flop i, if the connection exists, a ij Or a ii Is assigned a value of 1, if the connection does not exist, a ij Or a ii Is assigned a value of 0.

[0016] Fan-in, fan-out assignment is performed on each circuit node.

[0017] r i ∈reg_set(R);

[0018] fan-in(r i )=length(Find(:,r i )=1);

[0019] fan-out(r i )=length(Find(r i ,:)=1);

[0020] Setting fan-in threshold, fan-out threshold, selecting the circuit node which satisfies lower fan-in threshold and higher fan-out threshold as SEU sensitive class node, the rest nodes as SEU insensitive class nodes.

[0021] The number of external system output affected by the target circuit node is:

[0022] Setting n×n adjacency matrix (n∈N), changing the edge weight of the matrix, converting the unweighted graph model of circuit connection relationship into equivalent weighted graph model, determining the weight of corresponding node i and node j in the weighted graph model N c The degree of the net line connecting node i and node j, n is the total number of net lines of node i and node j;

[0023] For each target circuit node r i ∈reg_set(R), determine the output node o i ∈output_set(O), let count(r i )=0, determine the number of outputs associated with each target node by Dijkstra algorithm, if (dijkstra(Adjacency Matrix, r i , o i ))<∞, then count(r i )++;

[0024] When there are multiple output paths for the target node, select the target node with high count value as the SEU sensitive class node, and the rest nodes as the SEU insensitive class nodes.

[0025] The number of feedback loops of the target circuit node is:

[0026] Setting n×n adjacency matrix (n∈N), changing the edge weight of the matrix, converting the unweighted graph model of circuit connection relationship into equivalent weighted graph model, determining the weight of corresponding node i and node j in the weighted graph model

[0027] For each target circuit node r i ∈reg_set(R), determine the feedback output node r i ′∈r-output(r i ), let back(r i) = 0, the number of feedback loops of each target node is determined by Dijkstra algorithm, if (dijkstra(Adjacency Matrix, r i , r i )) < ∞, then back(r i ) ++.

[0028] When the value of the number of feedback loops back is higher than the preset threshold, the current node is taken as the SEU sensitive node, and the rest of the nodes are taken as the SEU insensitive node.

[0029] The error threshold of each output end is preset as 0%, 0.5%, 1%, and the specific selection is determined according to the optimization task demand of the triple modular redundancy circuit; the termination condition includes the reliability constraint and the circuit design area cost constraint, the reliability constraint is determined according to the optimization task demand of the triple modular redundancy circuit, and the area cost constraint is:

[0030] Let S P1 be the area cost obtained after the current optimization, S P2 be the area cost obtained after the last optimization, if the result of each output end does not exceed the required error threshold and the number of times that (S P1 -S P2 ) / S P1 <0 exceeds N, the area cost constraint is met;

[0031] When the fault-tolerant analysis result meets the termination condition, the optimization of the SEU sensitive node is ended.

[0032] The improved KL algorithm is specifically:

[0033] For the initial grouping V1 and V2, two nodes with the maximum number of outer edges minus the number of inner edges in each group are selected to form a 2*2 vertex pair;

[0034] The vertex pair with the maximum reduction or the minimum increase in the size of the cut set in the four transformations is selected as the final exchanged vertex pair, that is, the maximum reduction or the minimum increase in the four transformations , wherein Γ1(v i ) represents the number of connection edges between node v i and other nodes in group V1, and Γ2(v i ) represents the number of connection edges between node v i and other nodes in group V2;

[0035] The vertex pair optimization iteration is repeated, and the circuit nodes that have been changed in the iteration process are not iterated;

[0036] When the circuit nodes in any group are traversed and two circuit nodes to be exchanged cannot be found, the improved optimization of the circuit nodes is ended.

[0037] In the area cost constraint, the number N of times of satisfying the area cost criterion without exceeding the error threshold required to be satisfied is determined according to the optimization task requirement of the corresponding output end of the triple modular redundancy circuit.

[0038] The circuit netlist file is a source of information of the circuit to be tested, the circuit nodes of the circuit to be tested are initially grouped by a topological criterion, the circuit nodes sensitive to SEU are preliminarily judged, and the initial grouping is close to the final grouping; the circuit nodes are optimized and adjusted by using the improved KL algorithm, and according to the judgment result of the fault tolerance analysis and the termination condition, the area cost overhead is reduced while the reliability constraint is ensured.

[0039] Compared with the prior art, the application has the following advantages:

[0040] (1) The selective triple modular redundancy method based on the improved KL algorithm provided by the application performs topological analysis and initial grouping on the circuit nodes, and then performs grouping optimization by using the improved KL algorithm, so that the area overhead caused by the traditional triple modular redundancy mode is reduced while the single particle reliability of the circuit is improved, wherein the circuit nodes are topologically analyzed by using three topological criteria, the circuit nodes sensitive to SEU are preliminarily judged, and the initial grouping is close enough to the final grouping, so that the workload of the subsequent heuristic optimization algorithm is greatly reduced.

[0041] (2) The improved KL algorithm is used as a heuristic optimization engine in the application, and the efficiency is low and the time complexity is large in the traditional Kernighan-Lin algorithm, and in the improved algorithm, the most obvious change is that the selection of nodes is changed, two nodes are selected from two groups to form a 2x2 cycle, and then the vertex pair that makes the cut set size minimum is selected in the 2x2 cycle to be exchanged, so that the time complexity of the algorithm is greatly reduced and the execution efficiency is improved.

[0042] (3) The selective triple modular redundancy method based on the improved KL algorithm is designed by using the accurate soft error sensitivity evaluation, the appropriate triple modular redundancy fault tolerance technology and the efficient heuristic algorithm selection strategy, the area overhead caused by the traditional triple modular redundancy mode is reduced while the single particle reliability of the circuit is improved. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The selective triple modular redundancy method based on the improved KL algorithm provided by the application is provided with a flowchart;

[0044] Figure 2 The single-source shortest path algorithm (dijkstra algorithm) flowchart provided by the application is provided with a flowchart;

[0045] Figure 3 The node exchange process diagram of the improved KL algorithm provided by the application is provided with a flowchart;

[0046] Figure 4 A schematic diagram of a circuit under test is provided for the invention; DETAILED DESCRIPTION

[0047] The selective triple modular redundancy method based on the improved KL algorithm can take into account both the anti-SEU capability and the hardware overhead after redundancy, compared with the full triple modular redundancy method which has the disadvantage of occupying more resources, the selective triple modular redundancy can save a large amount of additional overhead, while meeting the circuit anti-single particle reliability requirements.

[0048] The selective triple modular redundancy method based on the improved KL algorithm has the following steps:

[0049] Read the circuit netlist file to obtain the circuit connection relationship, estimate the soft error sensitivity of the circuit nodes according to the topological criteria, and initially group all circuit nodes, the grouping categories are SEU sensitive class and SEU insensitive class;

[0050] Perform triple modular redundancy on the SEU sensitive nodes and construct a triple modular redundancy circuit;

[0051] Pre-set the error threshold and termination condition of each output end of the triple modular redundancy circuit, and perform system fault-tolerant analysis based on fault injection, judge whether the fault-tolerant analysis result meets the termination condition, if it meets the termination condition, end the optimization process, otherwise, optimize the SEU sensitive nodes using the improved KL algorithm and reconstruct the triple modular redundancy circuit until the termination condition is met;

[0052] Complete the optimization of SEU sensitive nodes and the optimization of triple modular redundancy circuit.

[0053] The topological criteria include criterion one, criterion two and criterion three, which are respectively:

[0054] Criterion one is the fan-in and fan-out node selection criterion, criterion two is the number of system outputs affected by the target circuit node criterion, and criterion three is the number of feedback loops of the target circuit node criterion. Each circuit node is judged using the three topological criteria, and when any one criterion is met, the category of the current circuit node is determined according to the selected criterion and grouped.

[0055] The fan-in and fan-out node selection criterion is:

[0056] Set an n×n adjacency matrix (n∈N), regard the circuit connection relationship as a finite directed graph including n circuit nodes, and regard each non-diagonal line aij Consider the direct connection between flip-flop i and flip-flop j, assign a ii Consider the feedback or loop at flip-flop i, if the connection exists, assign a ij (or a ii ) value of 1, if the connection does not exist, assign a ij (or a ii ) value of 0;

[0057] Fan-in and fan-out values are assigned to each circuit node;

[0058] r i ∈reg_set(R);

[0059] fan-in(r i )=length(Find(:,r i )=1);

[0060] fan-out(r i )=length(Find(r i ,:)=1);

[0061] Select the node with low fan-in value and high fan-out value as the SEU sensitive node, and the rest of the nodes as the SEU insensitive node.

[0062] The number of system outputs affected by the target circuit node is:

[0063] Set the n×n adjacency matrix (n∈N), change the edge weight of the matrix, convert the unweighted graph model of the circuit connection relationship into an equivalent weighted graph model, and determine the weight ω(i,j) of the corresponding node i and node j in the weighted graph model ω(i,j)=∑ c n ＝1 1 / N c , N c is the degree of the net connecting node i and node j, and n is the total number of nets of node i and node j;

[0064] For each target circuit node r i ∈reg_set(R), determine the output node o i ∈output_set(O), let count(r i )=0, and use Dijkstra algorithm to determine the number of outputs associated with each target node, if (dijkstra(Adjacency Matrix,r i ,o i ))<∞, then count(r i )++.

[0065] When there are multiple output paths for the target node, the target node with a high count value is selected as the SEU sensitive node, and the remaining nodes are selected as the SEU insensitive node.

[0066] The number of feedback loops of the target circuit node is determined by the following criteria:

[0067] An n×n adjacency matrix (n∈N) is set, the edge weight of the matrix is changed, the unweighted graph model of the circuit connection relationship is converted into an equivalent weighted graph model, and the weight of the corresponding node i and node j in the weighted graph model is determined.

[0068] For each target circuit node r i ∈reg_set(R), the feedback output node r i ′∈r-output(r i ) is determined, back(r i ) is set to 0, and the Dijkstra algorithm is used to determine the number of feedback loops of each target node. If (dijkstra(Adjacency Matrix, r i , r i ′))<∞, then back(r i )++.

[0069] The node with a high value of the number of feedback loops back is selected as the SEU sensitive node, and the remaining nodes are selected as the SEU insensitive node.

[0070] The error threshold of each output end is set to 0%, 0.5%, and 1% in advance, and the specific selection is determined according to the three-mode redundant circuit optimization task requirement; the termination conditions include the reliability constraint and the circuit design area cost constraint, the reliability constraint is determined according to the three-mode redundant circuit optimization task requirement, and the area cost constraint is:

[0071] Let S P1 be the area cost obtained after the current optimization, S P2 be the area cost obtained after the last optimization, if the results of each output end do not exceed the required error threshold and the number of times that (S P1 -S P2 ) / S P1 <0 exceeds N, the area cost constraint is satisfied.

[0072] When the fault tolerance analysis result satisfies the termination condition, the SEU sensitive node optimization is ended.

[0073] The improved KL algorithm is as follows:

[0074] For the initial grouping V1 and V2, two nodes with the maximum number of outer edges minus inner edges in each group are selected to form a 2×2 vertex pair.

[0075] Select the vertex pair with the largest reduction in cut set size or the smallest increase in cut set size in the four transformations as the final exchange vertex pair, that is, The maximum reduction or the minimum increase, where Γ1(v i ) represents node v i The number of connecting edges Γ2(v i ) represents node v i The number of connected edges with other nodes in group V2;

[0076] Repeat the vertex pair optimization iteration, and the circuit nodes that have been changed during the iteration are not iterated;

[0077] When all circuit nodes in any group are traversed and no two circuit nodes to be exchanged are found, the improvement and optimization of the circuit nodes is terminated.

[0078] In the area cost constraint, the number of times N that the error threshold is not exceeded and the area cost criterion is satisfied is determined according to the optimization task requirements of the output end of the triple-module redundant circuit.

[0079] The circuit netlist file is the source of information about the circuit to be tested. The circuit nodes of the circuit to be tested are initially grouped using topological criteria, and the circuit nodes sensitive to SEU are preliminarily determined so that the initial grouping is sufficiently close to the final grouping. To ensure feasible calculation time, a performance improvement scheme is proposed, which uses an improved KL algorithm to optimize and adjust the circuit nodes. Based on the fault-tolerance analysis and termination condition judgment results, compared with the full triple-module redundancy method, this method reduces area cost while ensuring reliability constraints.

[0080] The following is further described in conjunction with the accompanying drawings and preferred embodiments:

[0081] In the current embodiment, a selective triple-module redundancy method based on an improved KL algorithm aims to improve circuit single-event reliability while reducing circuit area and power consumption. The key concept is to analyze the soft error sensitivity of circuit nodes, classify them into two categories: SEU-sensitive and SEU-insensitive, using topological criteria and an improved KL algorithm. Triple-module redundancy is then added only to SEU-sensitive nodes. This selective triple-module redundancy method, based on the improved KL algorithm, balances SEU mitigation with redundant hardware overhead. Therefore, compared to full triple-module redundancy, which increases resource usage by at least 200% over the original circuit, selective triple-module redundancy can save significant overhead while still meeting the circuit's single-event reliability requirements.

[0082] like Figure 1The selective three-module redundancy method based on the improved KL algorithm in the application is shown in the flow chart, which includes the following five steps:

[0083] Step 1: read the circuit netlist file to obtain the circuit connection relationship, estimate the soft error sensitivity of the circuit node (which can be a flip-flop, a register) according to the topological criterion, and initially divide all nodes into two categories of SEU sensitive and SEU insensitive;

[0084] Step 2: perform three-module redundancy for the SEU sensitive node to construct a three-module redundancy circuit;

[0085] Step 3: set the error threshold that each output end must meet in advance, perform system fault-tolerant analysis based on fault injection, and judge whether the termination condition is met, if the result meets the reliability constraint and the area cost is small, jump to step (5), otherwise jump to step (4);

[0086] Step 4: optimize the existing partition using the improved KL algorithm, select the two nodes with the largest number of external edges minus internal edges in each group to form a 2x2 vertex pair, then select the node pair with the largest reduction in cut set size or the least increase in cut set size among the four transformations as the exchanged nodes, and finally generate a new partition, jump to step (2) for circulation;

[0087] Step 5: end the flow and output the result.

[0088] In order to further explain the application, refer to Figure 4 The measured circuit (containing 48 flip-flops) calculates the sum of three 7-bit data buses X, Y and Z, that is, (X+Y), (Y+Z) and (X+Z), and provides the result to a single 8-bit output bus within three consecutive clock cycles.

[0089] Referring to the specific embodiment as Figure 4 shown, the implementation method of step 1 is as follows:

[0090] The topological criterion 1-fan-in, fan-out includes the following steps:

[0091] 1) input n x n adjacency matrix (n e N), in order to facilitate the characterization of each node according to the topological criterion, the circuit is regarded as a finite directed graph containing n vertices (nodes), each non-diagonal line a ij is regarded as a direct connection between flip-flop i and flip-flop j, and each diagonal line a ii is regarded as feedback or loop at flip-flop i, if there is a connection, a ij (or a ii ) is 1, and if there is no connection, a ij (or aii ) is assigned 0;

[0092] 2) For each target node r i ∈ reg_set(R), fan-in(r i ) = length(Find(:,r i ) = 1), fan-out(r i ) = length(Find(r i ,:) = 1);

[0093] 3) Since the more fan-in, the less likely SEU stored in it; and the more fan-out, the SEU in the node propagates its state to several paths, more likely to have a greater impact on the system output, so for topology criterion 1, the node with low fan-in and high fan-out can be selected as the node to be protected by TMR.

[0094] Topology criterion 2 - the number of system outputs affected by the target node includes the following steps:

[0095] 1) Input the n x n (n ∈ N) adjacency matrix, change the edge weight value, and convert the circuit system's unweighted graph model into an equivalent weighted graph model, that is, the weight of the corresponding node i and node j in the equivalent weighted graph model should be Where N c represents the degree of the net connecting i and j, and n is the total number of nets connecting i and j;

[0096] 2) For each target node r i ∈ reg_set(R), system output node o i ∈ output_set(O), let count(r i ) = 0, and use Dijkstra algorithm to find the number of outputs associated with each target node, that is:

[0097] If (dijkstra(Adjacency Matrix, r i , o i )) < ∞, then count(r i ) ++;

[0098] 3) When the SEU in the node has multiple output paths, there is a higher probability of propagating errors to at least one system output, so for topology criterion 2, the node with high count value can be selected as the node to be protected by TMR.

[0099] Topology criterion 3 - the number of feedback loops of the target node includes the following steps:

[0100] 1) input n x n (n e N) adjacency matrix, change the relevant edge weight, convert the circuit system's unweighted graph model to the equivalent weighted graph model, that is, the weight of the corresponding node i and node j in the equivalent weighted graph model should be where N c represents the degree of the net line connecting i and j, and n is the total number of net lines connecting i and j;

[0101] 2) for each target node r i e reg_set(R), feedback output node r i ' e r-output(r i ), let back(r i ) = 0, use Dijkstra algorithm to find the number of feedback loops of the target node, that is: if (dijkstra(Adjacency Matrix, r i ', r i )) < ∞, then back(r i ) ++;

[0102] 3) Since the SEU in the node (with feedback loop) can be stored in the loop, the influence of the SEU is permanent, so the node with high back value can be selected as the node to be protected by TMR according to the topology criterion 3.

[0103] Further, as Figure 2 shown, the flow chart of the single-source shortest path algorithm (Dijkstra algorithm) in the topology criteria 2 and 3 is given, which specifically includes the following steps:

[0104] 1) input the weighted directed graph G = (V, E, W), V = {v1, v2, …, v n}, s: = v1;

[0105] 2) initial S = {v1}, calculate all dist[s, v i ] = w(s, v i ), v i e V-{s}

[0106] 3) check the distance from all marked points v k to unmarked points v i , and take dist[s, v i ] = min{dist[s, v i ], dist[s, v k ]+w(v k , v i )};

[0107] 4) select marked v j and remove this vj Put into the set S, update the dist value of vertex in V-S;

[0108] 5) Repeat the above process until S = V, short[s, v i ] = dist[s, v i ] (global dist value from source s to vertex v i ).

[0109] According to the analysis of the measured circuit according to the topological criteria 1-3, it can be obtained that X_D has the maximum fan-in value, so it can be initially considered that it is not sensitive to SEU; X_Ca, In_D, Y_D, Z_D have a larger fan-out value, and the count value of In_D, Y_D, Z_D nodes is higher, which affects two main outputs of the system, so it can be initially considered that they are sensitive to SEU; in addition, X_E_D, Out_Ca, T_Ca, X_Ca_D are close to the main output, but compared with X_E_D, X_Ca_D is composed of more flip-flops, so it needs a larger area cost to perform triple modular redundancy, so it can be initially considered that X_E_D, Out_Ca, T_Ca are sensitive to SEU. According to the above analysis, the circuit shown in FIG. 1 is initially grouped, wherein: SEU sensitive nodes {X_Ca, In_D, Y_D, Z_D, X_E_D, Out_Ca, T_Ca}, SEU insensitive nodes {X_Ca_D, X_D, Y_Ca, Z_Ca}. Figure 4

[0110] In step 2, triple modular redundancy is performed for the SEU sensitive nodes, and a triple modular redundancy circuit is constructed;

[0111] In step 3, the error threshold that each output end must meet is set to 0.5%, all tests are run for 100000 clock cycles of simulation, and 10000 seu are randomly injected. Then, fault injection-based system fault tolerance analysis is performed, and it is judged whether the result meets the termination condition, that is, the result of each output end does not exceed the required error threshold 0.5% and the number of times that (S P1 -S P2 ) / S P1 <0 exceeds 5, wherein S P1 is the area cost obtained after the current integration, S P2 is the area cost obtained after the last integration, if it does not meet, step 4 is performed;

[0112] In step 4, the existing partition is optimized by using the improved KL algorithm as a heuristic algorithm to generate a new partition, and step 2 is jumped to continue to perform triple modular redundancy for the SEU sensitive nodes of the new partition, and the above process is repeated until the termination condition is met. For example, Figure 3 ​The figure shows the improved KL algorithm node exchange process diagram in the application, the two white points in the left figure are the points to be exchanged, and the right figure is the result after exchange.

[0113] Further, the specific steps of the KL algorithm in step 4 are as follows:

[0114] 1) For the initial groups V1 and V2, two node groups with the maximum number of outer edges minus the number of inner edges in each group are selected to form a 2x2 vertex pair;

[0115] 2) The vertex pair with the maximum reduction or the minimum increase in the size of the cut set in the four transformations is selected as the final exchanged vertex pair, that is, in the four possible transformations The maximum reduction or the minimum increase, wherein Γ1(v i ) represents the number of connection edges between node v i and other nodes in group V1, and Γ2(v i ) represents the number of connection edges between node v i and other nodes in group V2;

[0116] 3) Repeat the above steps, and the exchanged nodes are no longer involved;

[0117] 4) Until two exchangeable nodes cannot be found in a group, the algorithm ends.

[0118] By applying the proposed method to the circuit as shown in Figure 4 , the result of selective TMR automatic insertion is finally obtained, which is shown in the following table. As shown by the data in the table, the area cost of the circuit is reduced by 30.4% while meeting the single particle reliability constraint of the circuit.

[0119]

[0120] Although the application has been disclosed with the above preferred embodiments, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the application by using the disclosed methods and technical contents without departing from the spirit and scope of the application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the application, which does not deviate from the technical solutions of the application, belongs to the protection scope of the technical solutions of the application.

[0121] The contents not described in detail in the specification of the application belong to the known technology of those skilled in the art.

Claims

1. A selective triple modular redundancy method based on an improved KL algorithm, characterized in that include: Read the circuit netlist file to obtain the circuit connection relationship, estimate the soft error sensitivity of the circuit nodes according to the topology criteria, and initially group all circuit nodes into SEU-sensitive and SEU-insensitive categories; Implement triple-mode redundancy for SEU-sensitive nodes and build triple-mode redundant circuits; The error thresholds and termination conditions for each output terminal of the triple-module redundant circuit are preset, and a fault-tolerance analysis of the external system after fault injection is performed to determine whether the fault-tolerance analysis results meet the termination conditions. If so, the optimization process ends. Otherwise, the improved KL algorithm is used to optimize the SEU-sensitive nodes and rebuild the triple-module redundant circuit until the termination conditions are met. Completed SEU sensitive node optimization and triple-mode redundant circuit optimization; The topology criteria include criteria 1, 2, and 3, which are: Criterion 1 is the criterion for selecting fan-in and fan-out nodes, Criterion 2 is the criterion for the number of external system outputs affected by the target circuit node, and Criterion 3 is the criterion for the number of feedback loops of the target circuit node. Each circuit node is judged using these three topological criteria. When any of the criteria is met, the category of the current circuit node is determined and grouped according to the selected criterion. The fan-in and fan-out node selection criteria are: Set n×n adjacency matrix (n∈N), regard the circuit connection relationship as a finite directed graph including n circuit nodes, and regard each non-diagonal a ij As a direct connection between trigger i and trigger j, each diagonal a ii is considered as a feedback or loop at trigger i. If the connection exists, a ij or a ii Assign a value of 1. If the connection does not exist, a ij or a ii Assign a value of 0; Perform fan-in assignment and fan-out assignment for each circuit node; r i ∈reg_set(R); fan-in(r i )=length(Find(:,r i )=1); fan-out(r i )=length(Find(r i ,:)=1); Set the fan-in threshold and fan-out threshold, select circuit nodes that are lower than the fan-in threshold and higher than the fan-out threshold as SEU-sensitive nodes, and the remaining nodes as SEU-insensitive nodes.

2. The selective triple modular redundancy method based on the improved KL algorithm according to claim 1, characterized in that: The criterion for the number of external system outputs affected by the target circuit node is: Set the n×n adjacency matrix, n∈N, change the matrix edge weights, convert the unweighted graph model of the circuit connection relationship into an equivalent weighted graph model, and determine the corresponding node i and node j weights in the weighted graph model N c is the degree of the network line connecting node i and node j, n is the total number of network lines between node i and node j; For each target circuit node r i ∈reg_set(R), determine the output node o i ∈output_set(O), let count(r i )=0, Dijkstra algorithm is used to determine the number of outputs associated with each target node. If (dijkstra(Adjacency Matrix,r i ,o i ))<∞, then count(r i ) value increases; When there are multiple output paths to a target node, the target node with the highest count value is selected as the SEU-sensitive node, and the remaining nodes are selected as SEU-insensitive nodes.

3. The selective triple modular redundancy method based on the improved KL algorithm according to claim 2, characterized in that: The feedback loop quantity criterion of the target circuit node is: Set the n×n adjacency matrix, n∈N, change the matrix edge weights, convert the unweighted graph model of the circuit connection relationship into an equivalent weighted graph model, and determine the corresponding node i and node j weights in the weighted graph model For each target circuit node r i ∈reg_set(R), determine the feedback output node r i ′∈r_output(r i ), let back(r i )=0, Dijkstra algorithm is used to determine the number of feedback loops for each target node. If (dijkstra(AdjacencyMatrix,r i ,r i ′))<∞, then back(r i ) value increases; When the value of the number of selected feedback loops back is higher than the preset threshold, the current node is regarded as an SEU-sensitive node, and the remaining nodes are regarded as SEU-insensitive nodes.

4. The selective triple modular redundancy method based on the improved KL algorithm according to claim 3, characterized in that: The error thresholds of each output terminal are pre-set to 0%, 0.5%, and 1%, and the specific selection is determined according to the requirements of the triple-module redundant circuit optimization task; the termination conditions include reliability constraints and circuit design area cost constraints. The reliability constraint is determined according to the requirements of the triple-module redundant circuit optimization task, and the area cost constraint is: Let S P1 is the area cost after current optimization, S P2 is the area cost obtained after the last optimization, if the output results do not exceed the required error threshold and (S P1 -S P2 ) / S P1 When the number of times <0 exceeds N, the area cost constraint is met; When the fault-tolerance analysis results meet the termination conditions, the SEU sensitive node optimization ends.

5. The selective triple modular redundancy method based on the improved KL algorithm according to claim 4, characterized in that: The improved KL algorithm is specifically as follows: For the initial groups V1 and V2, select the two nodes with the largest number of external edges minus the number of internal edges in each group to form 2×2 vertex pairs; Select the vertex pair with the largest reduction in cut set size or the smallest increase in cut set size in the four transformations as the final exchange vertex pair, that is, the vertex pair with the largest reduction in cut set size or the smallest increase in cut set size in the four transformations The maximum reduction or the minimum increase, where Γ1(v i ) represents node v i The number of connecting edges between other nodes in group V1, Γ2(v i ) represents node v i The number of connected edges with other nodes in group V2; Repeat the vertex pair optimization iteration, and the circuit nodes that have been changed during the iteration are not iterated; When all circuit nodes in any group are traversed and no two circuit nodes to be exchanged are found, the improvement and optimization of the circuit nodes is terminated.

6. The selective triple modular redundancy method based on the improved KL algorithm according to claim 5, characterized in that: In the area cost constraint, the number of times N that the error threshold is not exceeded and the area cost criterion is satisfied is determined according to the optimization task requirements of the output end corresponding to the triple-module redundant circuit.

7. The selective triple modular redundancy method based on the improved KL algorithm according to claim 6, characterized in that: The circuit netlist file is the source of information about the circuit to be tested. The circuit nodes of the circuit to be tested are initially grouped using topological criteria, and circuit nodes sensitive to SEU are preliminarily determined, so that the initial grouping is close to the final grouping. The circuit nodes are optimized and adjusted using an improved KL algorithm. Based on the results of fault tolerance analysis and termination condition judgment, the area cost overhead is reduced while ensuring reliability constraints.

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