Data generation circuit, memory, and method for determining data generation circuit

Abstract

The present disclosure provides a data generation circuit, a memory, and a method for determining a data generation circuit, and relates to the field of semiconductor technology. The data generation circuit includes: a first generation circuit corresponding to a first bit, the first generation circuit includes a first input terminal and a first output terminal, the first input terminal is used to receive a first selection signal, so that when the first selection signal is a first level, the first level is output through the first output terminal as the value of the first bit in the first data group, or, when the first selection signal is a second level, the second level is output through the first output terminal as the value of the first bit in the second data group. It can be seen that the embodiment of the present disclosure can multiplex the first generation circuit for the first data group and the second data group, so as to generate the value of the first bit of the first data group or the value of the first bit of the second data group under the control of the first selection signal, thereby reducing the complexity of the data generation circuit.

Description

Technical Field

[0001] The present application relates to, but is not limited to, a data generation circuit, a memory, and a method for determining a data generation circuit. Background Art

[0002] Memory is a semiconductor device used to store data, which relies on multiple parameters to work. A parameter can correspond to different values ​​under different application conditions. These values ​​are stored in a table to select different values ​​to run the memory under different conditions. For example, the data retention time is the maximum storage time of the memory for data. When the delay between reading data and the last write or refresh of data is greater than or equal to the data retention time, the data will be lost. Therefore, the data retention time can correspond to values ​​at different temperatures. The higher the temperature, the shorter the data retention time.

[0003] In the prior art, each value of the above parameters is binary data, and each value is typically a data group consisting of multiple binary data. Each binary data in the data group is generated by a corresponding data generation circuit, and different data groups are generated by different data generation circuits. For example, if the parameter has 36 values, then 36 data generation circuits are required to generate these 36 different values ​​respectively; if the parameter is expanded to 72 values, then 72 data generation circuits are required to generate these 72 different values ​​respectively.

[0004] However, the above data generation circuit has the problem of high complexity. Summary of the Invention

[0005] An embodiment of the present application provides a data generation circuit, a memory, and a method for determining the data generation circuit to reduce the complexity of the data generation circuit.

[0006] In a first aspect, an embodiment of the present disclosure provides a data generation circuit, comprising:

[0007] The first generating circuit corresponding to the first bit position includes a first input terminal and a first output terminal, the first input terminal is used to receive a first selection signal, so that when the first selection signal is a first level, the first level is output through the first output terminal as the value of the first bit position in the first data group, or, when the first selection signal is a second level, the second level is output through the first output terminal as the value of the first bit position in the second data group.

[0008] In one embodiment, the data generating circuit further includes:

[0009] a second generating circuit corresponding to the second bit, the second generating circuit comprising a second input terminal and a second output terminal, the second input terminal being configured to receive a second selection signal that is in phase with the first selection signal, so as to output the first level as the value of the second bit in the second data group through the second output terminal when the second selection signal is at a first level, or to output the second level as the value of the second bit in the first data group through the second output terminal when the second selection signal is at a second level;

[0010] The first bit and the second bit are two different bits with different values ​​in the same data group.

[0011] In one embodiment, the data generating circuit further includes:

[0012] An inverting circuit is connected to the first generating circuit and the second generating circuit, and is used to invert the first selection signal to obtain the second selection signal, or invert the second selection signal to obtain the first selection signal.

[0013] In one embodiment, the output end of the inverting circuit is connected to the first input end of the first generating circuit, and is used to invert the received second selection signal to obtain the first selection signal;

[0014] Alternatively, the output end of the inverting circuit is connected to the second input end of the second generating circuit, so as to invert the first selection signal to obtain the second selection signal.

[0015] In one embodiment, the first generating circuit further includes: a first switch, wherein two ends of the first switch are respectively connected to the first input end and the first output end.

[0016] In one embodiment, the second generating circuit further includes: a second switch, wherein two ends of the second switch are respectively connected to the second input end and the second output end.

[0017] In one embodiment, when the first data group and the second data group include a third bit with the same value, the data generation circuit further includes a third generation circuit corresponding to the third bit, and the third generation circuit includes a first level terminal, a second level terminal, a third switch, and a third output terminal;

[0018] When the value of the third bit is the first value, the third switch connects the third output end to the first level end;

[0019] When the value of the third bit is the second value, the third switch connects the third output end to the second level end.

[0020] In a second aspect, an embodiment of the present disclosure provides a memory comprising the data generation circuit of the first aspect.

[0021] In a third aspect, an embodiment of the present disclosure provides a method for determining a data generation circuit, the method comprising:

[0022] determining a first data set and a second data set;

[0023] If the values ​​of the first bit in the first data group and the first bit in the second data group are different, it is determined that the data generation circuit includes a first generation circuit corresponding to the first bit, and the first generation circuit is used to output a first level as the value of the first bit in the first data group when the received first selection signal is a first level, or, when the first selection signal is a second level, output a second level as the value of the first bit in the second data group.

[0024] In one embodiment, the method further comprises:

[0025] If the second bit in the first data group and the second bit in the second data group have different values, and the first bit in the first data group and the second bit in the first data group have different values, and the first bit in the second data group and the second bit in the second data group have different values, then it is determined that the data generation circuit also includes a second generation circuit corresponding to the second bit, and the second generation circuit is used to receive a second selection signal that is inverted to the first selection signal, so as to output the first level as the value of the second bit in the second data group when the second selection signal is a first level, or, when the second selection signal is a second level, output the second level as the value of the second bit in the first data group.

[0026] In one embodiment, the method further comprises:

[0027] If the third bit in the first data group and the third bit in the second data group have the same value, it is determined that the data generation circuit also includes a third generation circuit corresponding to the third bit, and the third generation circuit includes a first level end, a second level end, a third switch and a third output end. When the value of the third bit is the first value, the third switch is connected to the first level end; when the value of the third bit is the second value, the third switch is connected to the second level end.

[0028] In one embodiment, determining the first data set and the second data set includes:

[0029] After determining the second data group, determine a first data group whose number of corresponding bit values ​​is the same as that of the second data group and satisfies a preset condition; the preset condition includes at least one of the following: the number is greater than or equal to a preset number threshold, and the number is the largest.

[0030] The embodiments of the present application provide a data generation circuit, a memory, and a method for determining a data generation circuit, wherein the data generation circuit includes: a first generation circuit corresponding to a first bit, the first generation circuit including a first input terminal and a first output terminal, the first input terminal being used to receive a first selection signal, so that when the first selection signal is at a first level, the first level is output through the first output terminal as the value of the first bit in the first data group, or, when the first selection signal is at a second level, the second level is output through the first output terminal as the value of the first bit in the second data group. It can be seen that the embodiments of the present disclosure can multiplex the first generation circuit for the first data group and the second data group, so that under the control of the first selection signal, the values ​​of the first bit of the first data group or the first bit of the second data group are generated respectively, which can reduce the complexity of the data generation circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0032] Figure 1 is a structural diagram of a data generation circuit provided by an embodiment of the present disclosure;

[0033] Figure 2 1 is a bit diagram of a first data group and a second data group provided by an embodiment of the present disclosure;

[0034] Figure 3 is a structural diagram of another data generation circuit provided by an embodiment of the present disclosure;

[0035] Figure 4 This is a flowchart of the steps of a method for determining a data generation circuit provided by an embodiment of the present disclosure.

[0036] The above drawings illustrate specific embodiments of the present application, which will be described in more detail below. These drawings and the textual description are not intended to limit the scope of the present application in any way, but rather to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0037] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0038] The embodiment of the present disclosure is used to generate multiple data groups for parameters in a memory. These data groups can be the values ​​of the parameters under different conditions, and each data group is used to represent the value of the parameter under one condition. The values ​​of the parameter under different conditions can be stored in the table corresponding to the parameter. For example, for the data retention time of the memory, a table can be used to represent the values ​​of the data retention time at different temperatures and different scenarios. The various values ​​in Table 1 are different values ​​of the data retention time provided by the embodiment of the present disclosure. Referring to Table 1, the data retention time D of the memory corresponds to the values ​​under 9 ambient temperatures and 4 scenarios 00 to 11. Among them, 00 to 11 are numbers representing different scenarios, and the unit of the above ambient temperature can be degrees Celsius.

[0039] D -6 10 26 42 58 74 90 106 122 00 54 53 52 42 21 10 6 2 2 01 45 44 44 37 17 8 5 2 2 10 83 70 70 56 29 14 8 3 1 11 29 29 29 21 10 4 2 2 2

[0040] Table 1

[0041] For each of the above values, there is a corresponding data group, and each bit of each data group needs to be provided with a circuit for generating the bit value. This will result in a high complexity of the data generation circuit for the above parameters, and the complexity increases as the table is expanded. For example, each value of the data retention time in Table 1 can be represented by 7 bits of binary, that is, each value in Table 1 corresponds to a data group consisting of 7 bits. Therefore, the data generation circuit for the parameters shown in Table 1 needs to include 36×7=252 circuits for generating bit values. Moreover, when Table 1 is expanded to 72 values, 72×7=504 circuits for generating bit values ​​are required.

[0042] To reduce the complexity of the data generation circuit, the present disclosure implements the use of bits in the same position and with different values ​​in two data groups as first bits, so that the first bits of the two data groups reuse the same first generation circuit. This reduces the number of circuits used to generate bit values ​​in the parameter data generation circuit, thereby reducing the complexity of the data generation circuit.

[0043] Figure 1 This is a schematic diagram of a data generation circuit provided by an embodiment of the present disclosure, referring to Figure 1As shown, the data generation circuit 20 may include: a first generation circuit 201 corresponding to the first bit. The first generation circuit 201 includes a first input terminal 2011 and a first output terminal 2014. The first input terminal 2011 is used to receive a first selection signal, and when the first selection signal is at a first level, output the first level through the first output terminal 2014 as the value of the first bit in the first data group, or when the first selection signal is at a second level, output the second level through the first output terminal 2014 as the value of the first bit in the second data group.

[0044] The data generation circuit 20 is used to generate a first data set and a second data set for a parameter. The first data set and the second data set are two different values ​​of the parameter under the same conditions but in different scenarios. Therefore, when the number of scenarios for the parameter is at least three, multiple such data generation circuits 20 are required, with each two values ​​sharing a set of data generation circuits 20. For example, the first value 54 at the first temperature condition of -6°C in the first scenario 00 and the first value 45 at the first temperature condition of -6°C in the second scenario 01 share the same data generation circuit, while the second value 53 at the second temperature condition of 10°C in the first scenario 00 and the second value 44 at the second temperature condition of 10°C in the second scenario 01 share another data generation circuit.

[0045] When expanding the table, for example, from only three scenarios to four scenarios, when the values ​​under the same temperature conditions in the third scenario and the fourth scenario share a common data generation circuit, the initial value of the common data generation circuit can be either the value under the third scenario or the value under the fourth scenario.

[0046] Since the values ​​corresponding to the first data group and the values ​​corresponding to the second data group are different, there is at least one bit in the first data group and the second data group whose corresponding values ​​are different. In the embodiment of the present disclosure, the bit at the same position that is the first level in the first data group and the second level in the second data group is called the first bit. The first level and the second level are levels corresponding to two different binary values. When the first level is low, the second level is high; when the first level is high, the second level is low. For example, referring to Figure 2 As shown, the values ​​corresponding to the bits B6 to B0 of the first data group 0100101 are 0, 1, 0, 0, 1, 0, 1, respectively, and the values ​​corresponding to the bits B6 to B0 of the second data group 1010011 are 1, 0, 1, 0, 0, 1, 1, respectively. Figure 2 As shown, when the first level is low and the second level is high, the first bit positions are B1, B4 and B6. Of course, when the first level is high and the second level is low, the first bit positions are B2, B5, Figure 2 Not shown in the figure.

[0047] In order for the first generation circuit 201 to generate a value corresponding to a first level and a value corresponding to a second level for the first bit in the first and second data groups, respectively, the first generation circuit 201 can be a transmission line that uses the input first selection signal as the output value of the first bit. The first selection signal is used to indicate whether to output data from the first data group or data from the second data group. Therefore, when the first selection signal is at a first level, the first level is output as the value of the first bit in the first data group; when the first selection signal is at a second level, the second level is output as the value of the first bit in the second data group.

[0048] It can be seen that in the embodiment of the present disclosure, the first level value of the first bit in the first data group can be generated, or the second level value of the first bit in the second data group can be generated through the reused first generation circuit 201, thereby realizing circuit multiplexing and reducing the complexity of the data generation circuit.

[0049] It should be noted that, in one example, all bits of the first data group are 0, and all bits of the second data group are 1. In this case, the data generation circuit 20 includes M first generation circuits 201, where M is the number of bits corresponding to the first data group or the second data group, and the number of bits of the two data groups is the same. For example, M can be 7, which is used to represent the first data group and the second data group using 7-bit binary.

[0050] In another example, the first data group and the second data group include a second bit in addition to the first bit. The second bit is a bit at the same position in the first data group whose value corresponds to the second level and whose value corresponds to the first level in the second data group. The first bit and the second bit are two different bits with different values ​​in the same data group. For example, referring to Figure 2 As shown, when the first level is low and the second level is high, the second bit positions are B2 and B5. Of course, when the first level is high and the second level is low, the second bit positions are B1, B4 and B6. Figure 2 Not shown in the figure.

[0051] For the second bit, a corresponding second generating circuit 202 needs to be set to generate the value of the second bit in the first data group and the value of the second bit in the second data group. Figure 1As shown, the second generating circuit 202 includes a second input terminal 2022 and a second output terminal 2024, and the second input terminal 2022 is used to receive a second selection signal that is inverted to the first selection signal, so that when the second selection signal is a first level, the first level is output through the second output terminal as the value of the second bit in the second data group, or, when the second selection signal is a second level, the second level is output through the second output terminal as the value of the second bit in the first data group.

[0052] The second selection signal is the inverted signal of the first selection signal. The first selection signal is effective for indicating that the value of one of the two scenarios of the shared data generation circuit is selected as the current parameter of the memory, and the second selection signal is effective for indicating that the value of the other scenario is selected as the current parameter of the memory. The term "effective" can be either a low level or a high level, and can be adjusted according to actual needs. This application uses a low level as an example for explanation.

[0053] Like the first generation circuit 201, the second generation circuit 202 can also be a transmission line to use the input second selection signal as the output second bit value. Therefore, when the first selection signal is at the first level and the second selection signal is at the second level, the first generation circuit 201 outputs the first level as the value of the first bit in the first data group, and the second generation circuit 202 outputs the second level as the value of the second bit in the first data group. When the first selection signal is at the second level and the second selection signal is at the first level, the first generation circuit 201 outputs the second level as the value of the first bit in the second data group, and the second generation circuit 202 outputs the first level as the value of the second bit in the second data group.

[0054] It can be seen that in the embodiment of the present disclosure, the first level value of the second bit in the second data group can be generated, or the second level value of the second bit in the first data group can be generated through the reused second generation circuit 202, thereby realizing the multiplexing of the second bit generation circuit and further reducing the complexity of the data generation circuit.

[0055] As can be seen from the above description, the first selection signal and the second selection signal are mutually inverted signals. Figure 1 As shown, the data generating circuit 20 may further include an inverting circuit 203. Figure 1As shown, the inverting circuit 203 is connected to the first generating circuit 201 and the second generating circuit 202, and is configured to invert the first selection signal to obtain the second selection signal. In this example, the input end of the inverting circuit 203 is connected to the first input end 2011 of the first generating circuit 201, and is configured to receive the first selection signal together with the first generating circuit 201. The output end of the inverting circuit 203 is connected to the second input end 2022 of the second generating circuit 202, and is configured to invert the first selection signal to obtain the second selection signal, and output it to the second generating circuit 202.

[0056] Of course, the inverting circuit 203 can also invert the second selection signal to obtain the first selection signal. Figure 1 At this time, the input end of the inverting circuit 203 is connected to the second input end 2022 of the second generating circuit 202, so that both the inverting circuit 203 and the second generating circuit 202 receive the second selection signal. The output end of the inverting circuit 203 is connected to the first input end 2011 of the first generating circuit 201, so as to invert the second selection signal to obtain the first selection signal, and output the first selection signal to the first generating circuit 201.

[0057] The inverter circuit 203 may be formed by connecting an odd number of inverters in series. For example, the inverter circuit 203 may be one inverter or three inverters in series. The embodiment of the present disclosure does not limit the number of inverters included in the inverter circuit 203.

[0058] In another example, the first data group and the second data group may include a third bit in addition to the first bit and / or the second bit. The third bit is the bit at the same position with the same corresponding value in the first data group and the second data group. Figure 2 As shown, the third bit is B0 and B3. It can be seen that the third bit is different from the first and second bits mentioned above. The first and second bits can be understood as active bits, and the third bit can be understood as a fixed bit.

[0059] For the third bit, a corresponding third generating circuit 204 needs to be set to generate the same value for the third bit of the first data group and the third bit of the second data group. Figure 1As shown, the third generating circuit 204 includes a first level terminal 2041, a second level terminal 2042, a third switch 2043, and a third output terminal 2044. When the value of the third bit is the first value, the third switch 2043 connects the third output terminal 2044 to the first level terminal 2041 to output the first value corresponding to the first level terminal 2041; when the value of the third bit is the second value, the third switch 2043 connects the third output terminal 2044 to the second level terminal 2042 to output the second value corresponding to the second level terminal 2042.

[0060] When the first value is 1, the first level terminal 2041 is a power supply terminal. When the second value is 0, the second level terminal 2042 is a ground terminal.

[0061] It can be seen that the embodiment of the present disclosure generates the same value of the third bit for the first data group and the second data group through the multiplexed third generation circuit 204. This can further reduce the complexity of the data generation circuit.

[0062] Based on the fact that the third generating circuit 204 includes the third switch 2043, in order to ensure the basic structural consistency of the first generating circuit 201, the second generating circuit 202 and the third generating circuit 204 in the data generating circuit 20 and reduce the manufacturing complexity of the data generating circuit, the first generating circuit 201 and the second generating circuit 202 may also include switches.

[0063] Specifically, the first generating circuit 201 further includes a first switch 2013, wherein two ends of the first switch 2013 are respectively connected to the first input terminal 2011 and the first output terminal 2014, so as to form a path between the first input terminal 2011 and the first output terminal 2014 of the first generating circuit 201. When the first selection signal received by the first input terminal 2011 is at a first level, the first output terminal 2014 outputs the first level as the value of the first bit in the first data group of the first data group. Alternatively, when the first selection signal is at a second level, the first output terminal 2014 outputs the second level as the value of the first bit in the second data group.

[0064] from Figure 1 As can be seen from FIG, the first generating circuit 201 further includes a second input terminal 2012 connected to the ground terminal VSS.

[0065] Accordingly, the second generation circuit 202 further includes a second switch 2023, wherein two ends of the second switch 2023 are respectively connected to the second input terminal 2022 and the second output terminal 2024, so as to form a path between the second input terminal 2022 and the second output terminal 2024 of the second generation circuit 202. When the second selection signal received at the second input terminal 2022 is at a first level, the second output terminal 2024 outputs the first level as the value of the second bit in the second data group. Alternatively, when the second selection signal is at a second level, the second output terminal 2024 outputs the second level as the value of the second bit in the first data group.

[0066] from Figure 1 As can be seen from FIG, the second generating circuit 202 further includes a first input terminal 2021 connected to the power supply terminal VCC.

[0067] To sum up, the embodiment of the present disclosure can generate the value of the first bit for the first data group and the second data group respectively by multiplexing the first generation circuit 201, and generate the value of the second bit for the second data group and the first data group respectively by multiplexing the second generation circuit 202, and then generate the value of the third bit for the first data group and the second data group respectively by multiplexing the third generation circuit 204. In this way, the multiplexing of the generation circuits for the first data group and the second data group is realized, which can effectively reduce the complexity of the data generation circuit and reduce the complexity of the data generation circuit of one parameter by about half.

[0068] It should be noted that, in actual applications, the first data group and the second data group include at least the first bit, so the data generation circuit 20 includes at least one first generation circuit 201. On this basis, a second bit and / or a third bit may also be included. Assume that the number of first bits is M, the number of second bits is N, and the number of third bits is L, where M, N, and L are all integers greater than or equal to 0. Therefore, the data generation circuit 20 includes M first generation circuits 201, N second generation circuits 202, and L third generation circuits 204.

[0069] An example of a data generation circuit in which the first level is a low level and the second level is a high level is given below. Figure 3 is a structural diagram of another data generation circuit provided by an embodiment of the present disclosure, Figure 3The data generation circuit 20 includes a first data group of 0100101 and a second data group of 1010011. When the first level is low and the second level is high, as shown in FIG2 , B1, B4, and B6 are first bits, whose values ​​are output by the first generation circuit 201; B2 and B5 are second bits, whose values ​​are output by the second generation circuit 202; B0 and B3 are third bits, whose values ​​are output by two third generation circuits 204, respectively. The third switch 2043 in the third generation circuit 204 corresponding to B0 connects the third output terminal 2044 to the first level terminal 2041, so that the high level is used as the value 1 of the third bit B0; and the third switch 2043 in the third generation circuit 204 corresponding to B3 connects the third output terminal 2044 to the first level terminal 2041, so that the low level is used as the value 0 of the third bit B3.

[0070] Reference Figure 3 As shown, when the first selection signal is at a low level, the second selection signal is at a high level, which is used to instruct outputting the first data group. Specifically, the first generating circuit 201 corresponding to the first bit B6 outputs the value 0 of the first bit B6 in the first data group through the first output terminal 2014; the second generating circuit 202 corresponding to the second bit B5 outputs the value 1 of the second bit B5 in the first data group through the second output terminal; the first generating circuit 201 corresponding to the first bit B4 outputs the value 0 of the first bit B4 in the first data group through the first output terminal 2014; the third generating circuit 204 corresponding to the third bit B3 outputs the value 0 of the third bit B3 in the first data group through the third output terminal 2044; the second generating circuit 202 corresponding to the second bit B2 outputs the value 1 of the second bit B2 in the first data group through the second output terminal 2024; the first generating circuit 201 corresponding to the first bit B1 outputs the value 0 of the first bit B1 in the first data group through the first output terminal 2014; the third generating circuit 204 corresponding to the third bit B0 outputs the value 1 of the third bit B0 in the first data group through the third output terminal 2044. therefore, Figure 3 The first data group output by the data generating circuit 20 is shown to be 0100101.

[0071] Reference Figure 3As shown, when the first selection signal is at a high level, the second selection signal is at a low level, indicating that the second data group is output. Specifically, the first generation circuit 201 corresponding to the first bit B6 outputs the value 1 of the first bit B6 in the second data group through the first output terminal 2014; the second generation circuit 202 corresponding to the second bit B5 outputs the value 0 of the second bit B5 in the second data group through the second output terminal 2024; the first generation circuit 201 corresponding to the first bit B4 outputs the value 1 of the first bit B4 in the second data group through the first output terminal 2014; the third generation circuit 204 corresponding to the third bit B3 outputs the value 1 of the first bit B6 in the second data group through the third output terminal 2024. Output terminal 2044 outputs the value 0 of the third bit B3 in the second data group; the second generation circuit 202 corresponding to the second bit B2 outputs the value 0 of the second bit B2 in the second data group through the second output terminal 2024; the first generation circuit 201 corresponding to the first bit B1 outputs the value 1 of the first bit B1 in the second data group through the first output terminal 2014; the third generation circuit 204 corresponding to the third bit B0 outputs the value 1 of the third bit B0 in the second data group through the third output terminal 2044. Therefore, Figure 3 The second data group output by the data generating circuit 20 is shown to be 1010011.

[0072] It should be noted that the above-mentioned first level and second level can be set flexibly, and the first bit, second bit and third bit, as well as the corresponding first generation circuit 201, second generation circuit 202 and third generation circuit 204 can be re-determined according to the first level and second level.

[0073] The present disclosure also provides a memory including the aforementioned data generation circuit 20. The present disclosure is a memory embodiment corresponding to the aforementioned circuit embodiment, and has the same technical effects as the circuit embodiment. For detailed description, please refer to the specific description of the aforementioned circuit embodiment, and will not be repeated here.

[0074] Figure 4 This is a flowchart of a method for determining a data generation circuit according to an embodiment of the present disclosure. Figure 4 As shown, the method for determining the data generating circuit includes the following steps S401 to S402.

[0075] S401: Determine a first data group and a second data group.

[0076] In one example, the data groups corresponding to two values ​​of the same environmental conditions in any two different scenarios can be determined as the first data group and the second data group. However, this approach cannot minimize the complexity of the data generation circuit. To minimize the complexity of the data generation circuit, the disclosed embodiments consider circuit multiplexing similar first and second data groups.

[0077] Specifically, similar first and second data groups can be determined by the following steps: first, a parameter value can be randomly selected to be binary as the second data group, and then a first data group is determined that has the same number of bit values ​​as the second data group and satisfies a preset condition; the preset condition includes at least one of the following: the number of bit values ​​that are the same is greater than or equal to a preset threshold, or the number of bit values ​​that are the same is the largest. In this way, the first and second data groups include as many third bits as possible, and the data generation circuit includes as many third generation circuits 204 as possible, which can reduce the number of circuits to which the first selection signal and / or the second selection signal in the data generation circuit need to be connected, simplify the connection relationship in the data generation circuit, and thereby reduce the complexity of the data generation circuit.

[0078] For example, when the first data group is 0100101 and the second data group is 1010011, the number of third bits included in both is 2; when the first data group is 0100101 and the second data group is 1010010, the number of third bits included in both is 1. Therefore, when the first data group is 0100101, 1010011, which has a larger number of third bits than the first data group, can be selected as the second data group. In this way, the total number of first and second generation circuits to be connected to the first selection signal and / or the second selection signal is 5, which can simplify the connection relationship in the data generation circuit and reduce the complexity of the data generation circuit.

[0079] It should be noted that in some cases, except for one first bit or one second bit, all other bits in the first data group and the second data group are third bits. In this case, only the first selection signal is required, and the first selection signal only needs to be connected to one first generation circuit. This can greatly simplify the connection relationship in the data generation circuit and reduce the complexity of the data generation circuit.

[0080] Since there are different temperature conditions in the same scenario, and there are corresponding parameters under different temperature conditions, when determining which two scenarios share the data generation circuit, the total number of the third bit corresponding to the parameters under all temperature conditions can be counted, that is, the third bit of the corresponding parameters under each corresponding temperature condition and other environmental conditions of different scenarios is counted, and then the total sum of the third bits under all environmental conditions is counted. The data generation circuit shared with which scenario is determined according to the total number. For example, when expanding from two scenarios to three scenarios, the total sum of the third bits of all temperature conditions of the third scenario 10 and the first scenario 00 is X, and the total sum of the third bits of all temperature conditions of the third scenario 10 and the second scenario 01 is Y, and Y < X. At this time, the third scenario selects to share the data generation circuit with the first scenario. Taking Table 1 as an example, it can be understood that the total sum of the third bits under all the above temperature conditions is equal to the number of the third bits of the two data groups corresponding to the two values of the two scenarios under the first temperature condition + the number of the third bits of the two data groups corresponding to the two values of the two scenarios under the second temperature condition +... + the number of the third bits of the two data groups corresponding to the two values of the two scenarios under the ninth temperature condition.

[0081] S402: If the values of the first bit in the first data group and the first bit in the second data group are different, it is determined that the data generation circuit includes the first generation circuit corresponding to the first bit. The first generation circuit is configured to output the first level as the value of the first bit in the first data group when the received first selection signal is at the first level, or output the second level as the value of the first bit in the second data group when the first selection signal is at the second level.

[0082] In one embodiment, the above method further includes:

[0083] S403: If the values of the second bit in the first data group and the second bit in the second data group are different, and the values of the first bit and the second bit in the first data group are different, and the values of the first bit and the second bit in the second data group are different, it is determined that the data generation circuit further includes the second generation circuit corresponding to the second bit. The second generation circuit is configured to receive the second selection signal that is inverted with respect to the first selection signal, so as to output the first level as the value of the second bit in the second data group when the second selection signal is at the first level, or output the second level as the value of the second bit in the first data group when the second selection signal is at the second level.

[0084] In one embodiment, the above method further includes:

[0085] S404: If the third bit of the first data group and the third bit of the second data group have the same value, it is determined that the data generation circuit also includes a third generation circuit corresponding to the third bit, and the third generation circuit includes a first level end, a second level end, a third switch and a third output end. When the value of the third bit is the first value, the third switch is connected to the first level end; when the value of the third bit is the second value, the third switch is connected to the second level end.

[0086] The embodiment of the present disclosure is a method embodiment corresponding to the aforementioned circuit embodiment, and has the same technical effect as the circuit embodiment. Its detailed description can refer to the specific description of the aforementioned circuit embodiment, and will not be repeated here.

[0087] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of the present application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0088] It should be understood that the present application is not limited to the exact structure described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A data generation circuit, characterized in that: include: a first generating circuit corresponding to the first bit, the first generating circuit comprising a first input terminal and a first output terminal, the first input terminal being configured to receive a first selection signal, and to output a first level as the value of the first bit in the first data group via the first output terminal when the first selection signal is at a first level, or to output a second level as the value of the first bit in the second data group via the first output terminal when the first selection signal is at a second level; The data generating circuit further includes: a second generating circuit corresponding to the second bit, the second generating circuit comprising a second input terminal and a second output terminal, the second input terminal being configured to receive a second selection signal that is in phase with the first selection signal, so as to output the first level as the value of the second bit in the second data group through the second output terminal when the second selection signal is at a first level, or to output the second level as the value of the second bit in the first data group through the second output terminal when the second selection signal is at a second level; the first bit and the second bit are two different bits having different values ​​in the same data group; When the first data group and the second data group include a third bit with the same value and the same position, the data generation circuit further includes a third generation circuit corresponding to the third bit, and the third generation circuit includes a first level terminal, a second level terminal, a third switch, and a third output terminal; When the value of the third bit is the first value, the third switch connects the third output end to the first level end; when the value of the third bit is the second value, the third switch connects the third output end to the second level end.

2. The data generating circuit according to claim 1, wherein: The data generating circuit further includes: An inverting circuit is connected to the first generating circuit and the second generating circuit, and is used to invert the first selection signal to obtain the second selection signal, or invert the second selection signal to obtain the first selection signal.

3. The data generating circuit according to claim 2, wherein: The output end of the inverting circuit is connected to the first input end of the first generating circuit, and is used to invert the received second selection signal to obtain the first selection signal; Alternatively, the output end of the inverting circuit is connected to the second input end of the second generating circuit, so as to invert the first selection signal to obtain the second selection signal.

4. The data generating circuit according to any one of claims 1 to 3, characterized in that: The first generating circuit further includes: a first switch, wherein two ends of the first switch are respectively connected to the first input end and the first output end.

5. The data generating circuit according to any one of claims 1 to 3, characterized in that: The second generating circuit further includes: a second switch, wherein two ends of the second switch are respectively connected to the second input end and the second output end.

6. A memory, characterized in that: The data generating circuit according to claim 1 is included.

7. A method for determining a data generation circuit, characterized in that: The method comprises: determining a first data set and a second data set; If the values ​​of the first bit in the first data group and the first bit in the second data group are different, determining that the data generation circuit includes a first generation circuit corresponding to the first bit, the first generation circuit being configured to output a first level as the value of the first bit in the first data group when a received first selection signal is at a first level, or to output a second level as the value of the first bit in the second data group when the first selection signal is at a second level; If the second bit in the first data group and the second bit in the second data group have different values, and the first bit in the first data group and the second bit in the first data group have different values, and the first bit in the second data group and the second bit in the second data group have different values, then determine that the data generation circuit further includes a second generation circuit corresponding to the second bit, the second generation circuit being configured to receive a second selection signal that is inverted to the first selection signal, and to output the first level as the value of the second bit in the second data group when the second selection signal is at a first level, or to output the second level as the value of the second bit in the first data group when the second selection signal is at a second level; If the third bit of the first data group and the third bit of the second data group have the same position and the same value, it is determined that the data generation circuit also includes a third generation circuit corresponding to the third bit, and the third generation circuit includes a first level end, a second level end, a third switch and a third output end. When the value of the third bit is the first value, the third switch is connected to the first level end; when the value of the third bit is the second value, the third switch is connected to the second level end.

8. The method according to claim 7, characterized in that The determining of the first data group and the second data group comprises: After determining the second data group, determine a first data group whose number of corresponding bit values ​​is the same as that of the second data group and satisfies a preset condition; the preset condition includes at least one of the following: the number is greater than or equal to a preset number threshold, and the number is the largest.

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