Semiconductor structure and semiconductor chip

Abstract

The application relates to a semiconductor structure and a semiconductor chip, wherein the semiconductor structure comprises a substrate; a chip structure located on the substrate in a product area; a test circuit structure located on the substrate in a scribe lane area; and a first test transfer layer located on the test circuit structure, extending from the scribe lane area to the product area, and electrically connected to the test circuit structure and spaced apart from the chip structure. The embodiments of the application can solve the chip processing problem when the scribe lane area is compressed.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a semiconductor chip. Background Art

[0002] In semiconductor manufacturing, wafers are typically divided into multiple product zones for chip production. Chips within multiple product zones on the same wafer are processed and prepared simultaneously. Slicing is then performed in the scribe zones to separate the chips within each product zone into individual chip products.

[0003] During chip processing, various auxiliary processing structures are also formed in the dicing area. These auxiliary processing structures can include alignment marks for exposure alignment, overlay marks for overlay accuracy measurement, and test structures used in wafer acceptance testing (WAT).

[0004] However, with the advancement of semiconductor technology, the size of the saw lanes has been continuously compressed to enable the processing of more chips on a single wafer. This has led to a continuous reduction in the space required to accommodate the various auxiliary processing structures required for chip processing, and it has even become difficult to provide sufficient auxiliary processing structures in the saw lanes, thus affecting chip processing. Summary of the Invention

[0005] Based on this, embodiments of the present application provide a semiconductor structure and a semiconductor chip, and solve the chip processing problem when the saw street area is compressed.

[0006] A semiconductor structure having a scribe line area and a product area, the semiconductor structure comprising:

[0007] substrate;

[0008] a chip structure, located on the substrate of the product area;

[0009] a test circuit structure, located on the substrate in the scribe line area;

[0010] The first test transfer layer is located on the test circuit structure and extends from the dicing area to the product area. The first test transfer layer is electrically connected to the test circuit structure and is spaced apart from the chip structure.

[0011] In one embodiment, the first test switching layer includes:

[0012] a conductive connection structure, located in the scribe line area and connected to the test circuit structure;

[0013] The first test adapter is connected to the conductive connection structure, extends from the dicing area to the product area, and is spaced apart from the chip structure.

[0014] In one embodiment, the semiconductor structure further comprises:

[0015] The first passivation layer covers the first test connection line, and the first passivation layer has an electrode opening located in the product area, and the electrode opening exposes the first test connection line.

[0016] In one embodiment,

[0017] The product area includes a first seal ring area and a chip area, wherein the first seal ring area is located between the dicing street area and the chip area;

[0018] The first test connection line passes through the first sealing ring area and extends to the chip area. The electrode opening is located in the chip area.

[0019] In one embodiment,

[0020] The semiconductor structure further includes a second passivation layer, the second passivation layer covers the conductive connection structure and has a transfer hole exposing the conductive connection structure;

[0021] The first test connection line is located in the connection hole and on the upper surface of the second passivation layer, and the first test connection line extends from the dicing area to the product area on the upper surface of the second passivation layer.

[0022] In one embodiment, the first test connection line is located on the sidewall of the connection hole, the bottom of the connection hole, and the upper surface of the second passivation layer.

[0023] In one embodiment, the semiconductor structure further comprises:

[0024] The first passivation layer covers the first test transfer wire and the second passivation layer and is recessed into the transfer hole.

[0025] In one embodiment, the conductive connection structure includes:

[0026] a plurality of wiring layers arranged at intervals, wherein the wiring layer at the bottom is connected to the test circuit structure, and the wiring layer at the top is connected to the first test patch cord;

[0027] The conductive plug is located between adjacent wiring layers.

[0028] A semiconductor chip, comprising:

[0029] substrate;

[0030] A chip structure is located on the substrate;

[0031] The second test transfer layer extends from the edge of the semiconductor chip into the semiconductor chip and is spaced apart from the chip structure.

[0032] In one embodiment, the second test switching layer includes:

[0033] The second test connecting wire is spaced apart from the chip structure and extends from the edge of the semiconductor chip into the semiconductor chip.

[0034] In one embodiment, the semiconductor chip further includes:

[0035] The first passivation layer covers the second test connection line, and the first passivation layer has an electrode opening, and the electrode opening exposes the second test connection line.

[0036] In one embodiment,

[0037] The semiconductor chip has a first seal ring area and a chip area, wherein the first seal ring area is located between the chip area and the edge of the semiconductor chip;

[0038] The second test connection line passes through the first sealing ring area and extends to the chip area. The electrode opening is located in the chip area.

[0039] The semiconductor structure and semiconductor chip of the embodiments of the present application have the following beneficial effects:

[0040] By setting a first test transfer layer extending from the cutting road area to the product area, the test of the test circuit structure can be carried out in the product area. At this time, the test electrodes of the test circuit structure may not be set or may not be completely set in the cutting road area. Therefore, when the space in the cutting road area is limited, the cutting road area can reserve more area to form a sufficient number of other processing auxiliary structures (such as alignment marks and overlay marks, etc.). Moreover, the arrangement of alignment marks and overlay marks in the cutting road area will not make it difficult to form a sufficient number of test electrodes in the cutting road area, thereby affecting the test of the test circuit structure. Therefore, a sufficient number of test circuit structures can also be effectively tested at this time. Therefore, the embodiment of the present application can also set up sufficient processing auxiliary structures when the space in the cutting road area is limited, so that chip processing can be carried out in an orderly and reliable manner, thereby improving the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0042] Figure 1a The available arrangements of alignment marks, overlay marks, and test electrodes for the 90μm scribe line area;

[0043] Figure 1b Unusable arrangement of alignment marks, overlay marks, and test electrodes in the 60μm scribe line area;

[0044] Figure 1c Unusable arrangement of alignment marks, overlay marks, and test electrodes in the 60μm scribe line area;

[0045] Figure 2 is a schematic cross-sectional structural diagram of a semiconductor structure provided in one embodiment;

[0046] Figure 3 is a schematic top view of a semiconductor structure provided in one embodiment;

[0047] Figure 4 FIG. 4 is a schematic diagram of a cross-sectional structure of a semiconductor chip provided in one embodiment.

[0048] Description of reference numerals:

[0049] 100-substrate, 110-metal electrode layer, 200-chip structure, 300-test circuit structure, 400-first test transfer layer, 410-conductive connection structure, 411-conductive plug, 4111-first plug, 4112-second plug, 4113-third plug, 4114-fourth plug, 412-wiring layer, 4121-first wiring layer, 4122-second wiring layer, 4123-third wiring layer, 4124-fourth wiring layer, 420-first test transfer line, 500-first passivation layer, 500a-electrode opening, 600-second passivation layer, 600a-transfer hole, 700-second test transfer layer, 710-second test transfer line, 10-alignment mark, 20-overlay mark, 30-test electrode. DETAILED DESCRIPTION

[0050] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0052] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0053] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0054] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0055] As mentioned in the background art, when the size of the scribe line area is continuously compressed, it is difficult to arrange sufficient processing auxiliary structures in the scribe line area, thereby affecting chip processing.

[0056] For example, see Figure 1a In the 90μm cutting street area, an alignment mark 10 for exposure alignment, an overlay mark 20 for overlay accuracy measurement, and a test electrode 30 for WAT can be set at the same time.

[0057] When using a 60μm dicing area to increase the number of chips produced on a single wafer and reduce costs, please refer to Figure 1b , the alignment marks 10 and the overlay marks 20 will exceed the cutting street area, that is, the cutting street area can no longer accommodate two rows of alignment marks 10 and two rows of overlay marks 20.

[0058] Therefore, when using a 60μm scribe line area, please refer to Figure 1c , only one row of alignment marks 10 and one row of overlay marks 20 can be placed in the cutting area. If the alignment marks 10 and overlay marks 20 originally placed in two rows are placed in one row again, the space for the test electrodes 30 will be squeezed. The minimum number of test electrodes 30 required for process monitoring is fixed. This may result in that in the preset area, while arranging the alignment marks 10 and overlay marks 20, a sufficient number of test electrodes 30 cannot be arranged (such as Figure 1c The test electrode 30a in the WAT will exceed the preset area), thereby affecting the process monitoring process of the WAT and thus affecting chip processing.

[0059] Based on this, embodiments of the present application provide a semiconductor structure and a semiconductor chip.

[0060] In one embodiment, see Figure 2 as well as Figure 3 , provides a semiconductor structure having a cutting street area A1 and a product area A2. At the same time, the semiconductor structure includes a substrate 100, a chip structure 200, a test circuit structure 300 and a first test transfer layer 400. Among them, Figure 2 In order to make the figure clear, Figure 2The main structure of the semiconductor structure is shown in the figure, while some structures are omitted. Figure 2 The detailed structures of the chip structure 200 and the test circuit structure 300 are not shown. Figure 3 In order to make the figure clear, the main structure of the semiconductor structure is also shown, while some structures are omitted.

[0061] The substrate 100 may include a semiconductor substrate. The semiconductor substrate (not shown) may include, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the semiconductor substrate may include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI) substrate, or silicon germanium-on-insulator (SiGe-on-insulator) substrate. Therefore, the type of substrate should not limit the scope of protection of this application.

[0062] In addition, the base 100 may further include other structures formed on the semiconductor substrate and a metal electrode layer 110 for performing WAT testing on the other structures. The other structures formed on the semiconductor substrate may include, for example, transistors. The transistors may be formed based on the semiconductor substrate.

[0063] The chip structure 200 is located on the substrate 100 in a product area A2. As an example, the substrate 100 may be provided with multiple product areas A2 arranged in an array. Adjacent product areas A2 are separated by scribe line areas A1. Each product area A2 may contain a chip structure 200.

[0064] The chip structure 200 may include, for example, a storage structure. The storage structure may include, for example, a capacitor storage structure. In this case, the product area A2 may include an array area and a peripheral area. The storage structure may be located in the array area and may form a storage cell with the transistors on the substrate 100 in the array area. The storage cells may be arranged in an array in the array area. The peripheral area may include peripheral logic circuits to control operations such as reading and writing the storage cells. Of course, the chip structure 200 may also have other forms, which are not limited here.

[0065] The test circuit structure 300 is located on the substrate 100 in the scribe line area A1. The test circuit structure 300 can be manufactured simultaneously with the chip structure 200. Furthermore, the test circuit structure 300 is used for testing, and by testing the test circuit structure 300, the relevant performance of the chip structure 200 can be characterized.

[0066] The first test transfer layer 400 is located on the test circuit structure 300 and extends from the scribe line area A1 to the product area A2. The first test transfer layer 400 is electrically connected to the test circuit structure 300. At this point, the test circuit structure 300 can be electrically connected to the product area A2 via the first test transfer layer 400, allowing testing of the test circuit structure 300 in the product area A2.

[0067] At the same time, the first test transfer layer 400 is spaced apart from the chip structure 200 in the product area A2 , so as not to affect the chip structure 200 .

[0068] In this embodiment, by providing a first test transfer layer 400 extending from the cutting street area A1 to the product area A2, the test of the test circuit structure 300 can be performed in the product area A2. At this time, the test electrodes 30 of the test circuit structure 300 may not be provided or may not be completely provided in the cutting street area A1. Therefore, when the space in the cutting street area A1 is limited, the cutting street area A1 can reserve more area to form a sufficient number of other processing auxiliary structures (such as alignment marks and overlay marks, etc.). Moreover, the arrangement of alignment marks and overlay marks in the cutting street area A1 will not make it difficult to form a sufficient number of test electrodes 30 in the cutting street area A1, thereby affecting the test of the test circuit structure 300. Therefore, a sufficient number of test circuit structures 300 can also be effectively tested at this time. Therefore, in this embodiment, when the space in the cutting street area A1 is limited, sufficient processing auxiliary structures can also be provided, so that chip processing can be carried out in an orderly and reliable manner, thereby improving the chip yield.

[0069] In one embodiment, please refer to Figure 2 The first test transfer layer 400 includes a conductive connection structure 410 and a first test transfer line 420 .

[0070] The conductive connection structure 410 is located in the scribe line area A1 and is connected to the test circuit structure 300. The conductive connection structure 410 may include one or more film layers. "Multiple" means two or more.

[0071] During the semiconductor structure preparation process, after forming the test circuit structure 300 , one or more dielectric layers may be formed on the test circuit structure 300 , and a conductive connection structure 410 may be formed within the dielectric layer, so that the test circuit structure 300 is connected to the conductive connection structure 410 .

[0072] The first test connecting line 420 is connected to the conductive connection structure 410 . Furthermore, the first test connecting line 420 extends from the scribe line area A1 to the product area A2 and is spaced apart from the chip structure 200 .

[0073] At this time, the conductive connection structure 410 is disposed in the scribe line area A1 , and the first test connection line 420 extends from the scribe line area A1 to the product area A2 , thereby preventing the conductive connection structure 410 from affecting the chip structure 200 and the like formed in the product area A2 .

[0074] In one embodiment, the conductive connection structure 410 may include a conductive plug 411 and a wiring layer 412. The number of wiring layers 412 may be multiple. The multiple wiring layers 412 may be spaced apart. Adjacent wiring layers 412 may be connected by the conductive plug 411.

[0075] At the same time, the bottom wiring layer 412 can be connected to the test circuit structure 300. In this case, the bottom wiring layer 412 can be connected to the test circuit structure 300, for example, via a conductive plug. Of course, the bottom wiring layer 412 can also be directly connected to the test circuit structure 300. This is not limited here.

[0076] The top wiring layer 412 can be connected to the first test patch cord 420 , thereby effectively electrically connecting the first test patch cord 420 to the test circuit structure 300 .

[0077] As an example, see Figure 2 The plurality of wiring layers 412 may include a first wiring layer 4121 , a second wiring layer 4122 , a third wiring layer 4123 , and a fourth wiring layer 4124 . The conductive plugs 411 may include a first plug 4111 , a second plug 4112 , a third plug 4113 , and a fourth plug 4114 .

[0078] During semiconductor structure processing, the chip structure 200 and the test circuit structure 300 can be formed simultaneously. After the chip structure 200 and the test circuit structure 300 are formed, a first dielectric layer (not shown) can be formed. The first dielectric layer can cover the test circuit structure 300 and the chip structure 200. Multiple first plugs 4111 can then be formed within the first dielectric layer. Different first plugs 4111 can be used to connect the chip structure 200 and the test circuit structure 300, respectively.

[0079] Then, a first wiring layer 4121 may be formed on the first dielectric layer and the first plug 4111. The first wiring layer 4121 may cover the first plug 4111. The first wiring layer 4121 may be made of aluminum, copper, or the like, and may be formed by a photolithography process or a damascene process.

[0080] For example, when the material of the first wiring layer 4121 is aluminum, a first wiring material layer can be first formed on the first dielectric layer and the first plug 4111. Then, the first wiring material layer is patterned and etched through a photolithography process to form the first wiring layer 4121. When the material of the first wiring layer 4121 is copper, an insulating dielectric material layer can be first formed on the first dielectric layer and the first plug 4111, and then the insulating dielectric material layer is etched to form an insulating dielectric layer with a groove. Then, a first wiring material layer can be formed in the groove and on the upper surface of the insulating dielectric layer. The first wiring material layer is then subjected to a chemical mechanical polishing (CMP) process to remove the first wiring material layer on the upper surface of the insulating dielectric layer, and the remaining first wiring material layer filling the groove forms the first wiring layer.

[0081] The first wiring layer 4121 may include a plurality of first patterned wirings. The first plugs 4111 respectively connecting the chip structure 200 and the test circuit structure 300 may be connected to different first patterned wirings.

[0082] Afterwards, a second dielectric layer may be formed covering the first wiring layer 4121. Then, a plurality of second plugs 4112 may be formed in the second dielectric layer. Different first patterned wirings may be connected through different first plugs 4112.

[0083] Then, a second wiring layer 4122 can be formed on the second dielectric layer and the second plug 4112. The second wiring layer 4122 can cover the second plug 4112. The materials and formation process of the second wiring layer 4122 can be similar to those of the first wiring layer 4121. The second wiring layer 4122 can include multiple second patterned wirings. Different first plugs 4112 can be connected to different second patterned wirings.

[0084] Thereafter, a third plug 4113 , a third wiring layer 4123 , a fourth plug 4114 and a fourth wiring layer 4124 may be sequentially formed in a similar manner.

[0085] It can be understood that the number of wiring layers 412 here is just an example and not a limitation.

[0086] In this embodiment, the arrangement of multiple wiring layers 412 and conductive plugs 411 can make the arrangement position of the test circuit structure 300 more flexible.

[0087] Of course, in other embodiments, the configuration of the conductive connection structure 410 may differ. For example, the conductive connection structure 410 may include only one conductive plug 411 connecting the test circuit structure 300 and the first test patch cord 420. In another example, the conductive connection structure 410 may include one conductive plug 411 and one wiring layer 412. In this case, the conductive plug 411 may connect the test circuit structure 300 and the wiring layer 412. The wiring layer 412 may connect to the first test patch cord 420.

[0088] In one embodiment, see Figure 2 The semiconductor structure further includes a first passivation layer 500 . The first passivation layer 500 covers the first test connecting wire 420 .

[0089] The first passivation layer 500 can fully cover the dicing area A1 and the product area A2, thereby passivating and protecting the first test transfer line 420, the conductive connection structure 410, the test circuit structure 300, and the chip structure 200 thereunder.

[0090] The material of the first passivation layer 500 may include an inorganic passivation material and / or an organic passivation material, such as, but not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), or silicon oxynitride (SiON).

[0091] Meanwhile, the first passivation layer 500 has an electrode opening 500 a located in the product area A2 , and the electrode opening 500 a exposes the first test connection line 420 .

[0092] The first passivation layer 500 can be formed by forming a first passivation material layer that fully covers the scribe line area A1 and the product area A2 after forming the first test patch cord 420. The first passivation material layer is then etched to form the electrode opening 500a. The remaining first passivation material layer after etching forms the first passivation layer 500.

[0093] At this time, the portion of the first test patch cord 420 exposed by the electrode opening 500a can form the test electrode 30. When testing the test circuit structure 300, a test probe can be passed through the electrode opening 500a to contact the first test patch cord 420 serving as the test electrode 30, thereby applying an electrical signal to the test circuit structure 300 or receiving an electrical signal sent by the test circuit structure 300.

[0094] In this embodiment, the electrode opening 500 a is formed in the first passivation layer 500 , so that the portion of the first test patch cord 420 exposed by the electrode opening 500 a forms the test electrode 30 , thereby enabling the test electrode 30 for acupuncture to be obtained simply and effectively.

[0095] In other embodiments, the test electrodes 30 may be formed in other ways. For example, after forming the first test patch cord 420, a third passivation layer may be formed to cover the first test patch cord 420. Then, contact holes may be formed in the third passivation layer, and then patterned test electrodes 30 may be formed on the upper surface of the third passivation layer. In this case, the test electrodes 30 may be connected to the first test patch cord 420 through the contact holes.

[0096] In one embodiment, see Figure 2 The product area A2 includes a first seal ring area A21 and a chip area A22. The first seal ring area A21 is located between the scribe line area A1 and the chip area A22.

[0097] The first seal ring area A21 can be used to prevent cracks from extending to the chip area A22 during cutting in the scribe line area A1. As an example, the first seal ring area A21 can also include a seal ring formed by multiple wiring layers 412 and conductive plugs 411. As an example, the area near the product area A2 in the scribe line area A1 can also include a second seal ring area A11, which has at least one seal ring. This can better prevent crack extension when cutting along the center of the scribe line area A1.

[0098] The first test connection line 420 passes through the first seal ring area A21 and extends to the chip area A22. Meanwhile, the electrode opening 500a in the first passivation layer 500 is located in the chip area A22. At this time, the test electrode 30 can be formed in the chip area A22.

[0099] In this embodiment, the first passivation layer 500 in the first seal ring area A21 does not have an opening. Therefore, when cutting in the scribe line area A1, cracks are less likely to be caused by the opening in the first seal ring area A21, thereby more effectively preventing cracks from extending to the chip area A22 during cutting.

[0100] In one embodiment, see Figure 2 The semiconductor structure further includes a second passivation layer 600. The second passivation layer 600 covers the conductive connection structure 410 and has a via hole 600a exposing the conductive connection structure 410;

[0101] The first test connecting line 420 is located in the connecting hole 600 a and on the upper surface of the second passivation layer 600 , and the first test connecting line 420 extends from the scribe line area A1 to the product area A2 on the upper surface of the second passivation layer 600 .

[0102] At this time, in the preparation process of forming the semiconductor structure, after forming the conductive connection structure 410, for example, after the fourth wiring layer 4124 in the above embodiment example is formed, a second passivation material layer can be formed to fully cover the cutting area A1 and the product area A2.

[0103] Afterwards, the second passivation material layer may be etched to form a second passivation layer 600 having a via hole 600 a . The via hole 600 a may expose at least a portion of the conductive connection structure 410 .

[0104] Then, a transfer line material layer may be formed in the transfer hole 600a and on the upper surface of the second passivation layer 600. The transfer line material layer is then patterned to form a first test transfer line 420 in the transfer hole 600a and on the upper surface of the second passivation layer 600.

[0105] As an example, the first test patch cord 420 may be located on the sidewalls of the patch hole 600a, the bottom of the patch hole 600a, and the upper surface of the second passivation layer 600. In this case, the raw material of the first test patch cord 420 can be effectively saved and the process efficiency can be improved.

[0106] Of course, the first test patch cord 420 may also fill the patch hole 600 a , which is not limited here.

[0107] In this embodiment, through the setting of the second passivation layer 600, on the one hand, the first test adapter line 420 can be extended from the cutting area A1 to the product area A2; on the other hand, the second passivation layer 600 can play an insulating isolation role, so that the conductive connection structure 410 or the top wiring layer of the conductive connection structure 410 (such as the fourth wiring layer 4124 in the above embodiment example) can be set on the same layer as the wiring layer connecting other structures (such as the chip structure 200), thereby facilitating circuit design and preparation.

[0108] Of course, in some embodiments, the configuration of the first test patch cord 420 may be different. For example, the conductive connection structure 410 may only include a conductive plug connected to the test circuit structure 300. In this case, the first test patch cord 420 may be formed directly on the surface of the conductive plug after the conductive plug is formed, without first forming a passivation layer on the surface of the conductive plug and forming a patch hole in the passivation layer.

[0109] In one embodiment, see Figure 2 Alternatively, the first passivation layer 500 and the second passivation layer 600 may be provided simultaneously. The second passivation layer 600 and the first passivation layer 500 may both play a role in passivation protection, and the materials of the two layers may be the same or different.

[0110] At this time, the second passivation layer 600 covers the conductive connection structure 410 and has a transfer hole 600a that exposes the conductive connection structure 410. The first test transfer line 420 is connected to the conductive connection structure 410 through the transfer hole 600a. The first passivation layer 500 can cover the first test transfer line 420 and the second passivation layer 600 and have an electrode opening 500a that exposes the first test transfer line 420.

[0111] At the same time, the first passivation layer 500 may be recessed into the via hole 600a. In this case, the thickness of the first passivation layer 500 does not need to be too high, thereby saving the raw material of the first passivation layer 500 and improving the process efficiency.

[0112] Of course, in other embodiments, the first passivation layer 500 may have other forms. For example, the first passivation layer 500 may have a planarized upper surface. Alternatively, in other embodiments, the second passivation layer 600 having the transfer hole 600 a and the first passivation layer 500 having the electrode opening 500 a may not be provided at the same time.

[0113] In one embodiment, see Figure 4 , a semiconductor chip is also provided. The semiconductor chip includes a substrate 100, a chip structure 200, and a second test transfer layer 700. The semiconductor chip can be formed by cutting the semiconductor structure in the above embodiment.

[0114] For example, see also Figure 2 and Figure 4 After completing the chip manufacturing process based on the above-mentioned semiconductor structure, it can be cut along the cutting path area A1. After cutting, the test circuit structure 300 formed on the cutting path area A1 can be removed. At the same time, the structures located in each product area A2 are cut to form multiple independent semiconductor chips. At this time, the chip structure 200 located in the product area A2 is retained on the semiconductor chip. At the same time, the portion of the first test transfer layer 400 of the semiconductor structure located in the cutting path area A1 is removed, while the portion located in the product area A2 can be retained. The retained first test transfer layer 400 forms the second test transfer layer 700 of the semiconductor chip.

[0115] The substrate 100 may include a semiconductor substrate. The semiconductor substrate (not shown) may include, for example, a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the semiconductor substrate may include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI) substrate, or silicon germanium-on-insulator (SiGe-on-insulator) substrate. Therefore, the type of substrate should not limit the scope of protection of this application.

[0116] In addition, the base 100 may further include other structures formed on the semiconductor substrate. For example, the other structures formed on the semiconductor substrate may include transistors. The transistors may be formed based on the semiconductor substrate.

[0117] The chip structure 200 is located on the substrate 100. For example, the chip structure 200 may include a storage structure. The storage structure may include a capacitor storage structure. The semiconductor substrate may include an array region and a peripheral region. The storage structure may be located in the array region and may form a storage cell with the transistors on the substrate 100 in the array region. The storage cells may be arranged in an array in the array region. The peripheral region may include peripheral logic circuits to control operations such as reading and writing the storage cells. Of course, the chip structure 200 may also have other forms, which are not limited here.

[0118] The second test transfer layer 700 is formed by cutting the first test transfer layer 400 of the semiconductor structure, so it extends from the edge of the semiconductor chip into the semiconductor chip and is spaced apart from the chip structure 200 .

[0119] In one embodiment, the second test patch cord layer 700 includes a second test patch cord 710 .

[0120] The second test connecting line 710 is spaced apart from the chip structure 200 and may be located above the chip structure 200. Furthermore, the second test connecting line 710 extends from an edge of the semiconductor chip into the interior of the semiconductor chip.

[0121] The second test vias 710 may be formed by cutting the first test vias 410 of the semiconductor structure.

[0122] In one embodiment, the semiconductor chip further includes a first passivation layer 500 . The first passivation layer 500 covers the second test connection line 710 and has an electrode opening 500 a . The electrode opening 500 a exposes the second test connection line 710 .

[0123] In one embodiment, the semiconductor chip has a first seal ring area A21 and a chip area A22 , wherein the first seal ring area A21 is located between the chip area A22 and an edge of the semiconductor chip;

[0124] The first test connecting line 710 passes through the first seal ring area A21 and extends to the chip area A22 . The electrode opening 500 a is located in the chip area A22 .

[0125] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0126] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure has a dicing area and a product area, and includes: substrate; a chip structure, located on the substrate of the product area; a test circuit structure, located on the substrate in the scribe line area; The first test transfer layer is located on the test circuit structure and extends from the dicing area to the product area. The first test transfer layer is electrically connected to the test circuit structure and is spaced apart from the chip structure.

2. The semiconductor structure according to claim 1, wherein: The first test switching layer includes: a conductive connection structure, located in the scribe line area and connected to the test circuit structure; The first test adapter is connected to the conductive connection structure, extends from the dicing area to the product area, and is spaced apart from the chip structure.

3. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a first passivation layer covering the first test patch cord, the first passivation layer having an electrode opening located in the product area, the electrode opening exposing the first test patch cord; the product area including a first seal ring area and a chip area, the first seal ring area being located between the dicing street area and the chip area; The first test connection line passes through the first sealing ring area and extends to the chip area. The electrode opening is located in the chip area.

4. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes a second passivation layer, the second passivation layer covers the conductive connection structure and has a transfer hole exposing the conductive connection structure; The first test connection line is located in the connection hole and on the upper surface of the second passivation layer, and the first test connection line extends from the dicing area to the product area on the upper surface of the second passivation layer.

5. The semiconductor structure according to claim 4, wherein: The first test transfer wire is located on the sidewall of the transfer hole, the bottom of the transfer hole and the upper surface of the second passivation layer. The semiconductor structure according to claim 4 , wherein: The semiconductor structure further comprises: The first passivation layer covers the first test transfer wire and the second passivation layer and is recessed into the transfer hole.

7. The semiconductor structure according to claim 2, wherein: The conductive connection structure includes: a plurality of wiring layers arranged at intervals, wherein the wiring layer at the bottom is connected to the test circuit structure, and the wiring layer at the top is connected to the first test patch cord; The conductive plug is located between adjacent wiring layers.

8. A semiconductor chip, characterized in that: include: substrate; A chip structure is located on the substrate; The second test transfer layer extends from the edge of the semiconductor chip into the semiconductor chip and is spaced apart from the chip structure.

9. The semiconductor chip according to claim 8, wherein The second test switching layer includes: The second test connecting wire is spaced apart from the chip structure and extends from the edge of the semiconductor chip into the semiconductor chip.

10. The semiconductor chip according to claim 9, wherein The semiconductor chip further includes: a first passivation layer covering the second test patch cord, wherein the first passivation layer has an electrode opening, and the electrode opening exposes the second test patch cord; The semiconductor chip has a first seal ring area and a chip area, wherein the first seal ring area is located between the chip area and the edge of the semiconductor chip; The second test connection line passes through the first sealing ring area and extends to the chip area. The electrode opening is located in the chip area.

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