A packaging method for vertically integrated superlattice infrared detector

Abstract

The invention provides a packaging method for a vertically integrated superlattice infrared detector, belonging to the field of infrared detectors; the method solves the problems of low signal transmission reliability and low integration of infrared detector components obtained by traditional packaging methods; the method comprises the following steps: taking a wafer and an epitaxial wafer with a prepared readout circuit, and directly bonding the epitaxial wafer and the readout circuit through a plasma low-temperature direct bonding process to form a heterogeneous integrated structure; wherein the epitaxial wafer is obtained by epitaxially growing an epitaxial layer of a second type of superlattice material on a substrate; completely removing the substrate on the epitaxial wafer through a wet stripping process; forming a focal plane array on the epitaxial wafer through an ICP etching process and a metallization process; and leading the metal electrode of each pixel on the focal plane array to the corresponding electrode area of ​​the readout circuit through a through hole, so that the focal plane array is directly connected to the readout circuit to obtain an infrared detector chip; the invention is applied to the packaging of superlattice infrared detectors.

Description

Technical Field

[0001] The invention provides a packaging method for a vertically integrated superlattice infrared detector, belonging to the technical field of infrared detectors. Background Art

[0002] The traditional InAs / GaSb type II superlattice material and the readout circuit are connected in the form of flip-chip interconnection to form an infrared detector chip. The infrared detector chip is flipped 180°, with the back facing up, and the In column on the front is cold-pressed to the In column of the readout circuit. The infrared detector chip is then connected to the transfer substrate by gold wire bonding to achieve electrical signal output. The infrared detector component is assembled on the transfer substrate by flip chip, wire bonding or fan-out packaging. The integration is low and belongs to two-dimensional integration. Wire bonding has a small wire contact point and poor vibration and impact resistance. Under high-intensity vibration conditions, the gold wire wire can easily fall off at the welding point, resulting in the interruption of the connection between the infrared detector chip electrode and the ceramic substrate electrode, resulting in a fault, which seriously affects the reliability of the detector component. In addition, as the infrared detector detects larger and larger bands, the requirements for resistance, heat dissipation and noise in the package are getting higher and higher, which poses a great challenge to the infrared detector component.

[0003] In order to meet the needs of highly integrated, miniaturized and highly reliable infrared detector components, multi-wafer stacking technology is gradually becoming the mainstream of heterogeneous integration. Heterogeneous integration technology promotes the cross-border integration of different materials and processes, and can realize the combination of traditional silicon-based readout circuits with optical materials such as III-V compound semiconductors. This fusion not only realizes the efficient integration of electrons and photons, but also promotes the wafer-level manufacturing of complete photonic integrated circuits including emission, modulation and detection functions, demonstrating the great potential of heterogeneous integration in the field of optoelectronics. With the advancement of technology, heterogeneous structures are developing from single small-size devices to large-area integration. This trend requires achieving uniformity and consistency on a larger scale while ensuring performance to meet the needs of large-area applications such as display and sensing. Summary of the invention

[0004] In order to solve the problems of low signal transmission reliability and low integration of infrared detector components obtained by traditional packaging methods, the present invention proposes a packaging method for a vertically integrated superlattice infrared detector.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a packaging method of a vertically integrated superlattice infrared detector, comprising the following steps:

[0006] S1: Take the wafer and epitaxial wafer with the prepared readout circuit, and form a heterogeneous integrated structure by plasma low-temperature direct bonding process between the epitaxial wafer and the readout circuit; wherein the epitaxial wafer is obtained by epitaxially growing an epitaxial layer of the second type superlattice material on a substrate;

[0007] The substrate is completely removed by a wet stripping process on the epitaxial wafer;

[0008] S2: Using ICP etching process and metallization process to form a focal plane array on the epitaxial wafer;

[0009] S3: Lead the metal electrode of each pixel on the focal plane array to the corresponding electrode area of ​​the readout circuit through the through hole, so that the focal plane array is directly connected to the readout circuit, and an infrared detector chip is obtained.

[0010] In step S1, the epitaxial wafer and the readout circuit may also be formed into a heterogeneous integrated structure by an indirect bonding process.

[0011] Before bonding the epitaxial wafer to the readout circuit, surface treatment is first performed on the epitaxial wafer and the wafer of the readout circuit, wherein the surface treatment includes wet cleaning treatment and plasma activation treatment.

[0012] The metallization process in step S2 adopts a contact lithography process, firstly realizing photoresist pixel patterning on the epitaxial wafer through the contact lithography process, and then realizing pixel patterning of the second type superlattice material through the ICP etching process.

[0013] The process also includes S4: interconnecting the infrared detector chip and the transfer substrate by using co-situ soldering or electroplating technology to obtain an infrared detector assembly.

[0014] The wet cleaning process is implemented by using a megasonic cleaning machine, and the wafer is cleaned multiple times by using an acetone solution, an ethanol solution and deionized water respectively.

[0015] The plasma activation process step is placed after the wet cleaning process step.

[0016] The pad positions on the adapter substrate correspond one-to-one to the pad positions on the infrared detector chip.

[0017] Before performing step S4, the wafer-level infrared detector chips formed through steps S1 to S3 are first diced to obtain a plurality of independent infrared detector chips.

[0018] The epitaxial wafer is obtained by epitaxially growing an epitaxial layer of an InAs / GaSb two-type superlattice material on a GaSb substrate.

[0019] Compared with the prior art, the present invention has the following beneficial effects: the traditional packaging process of the infrared detector assembly is to first cut the wafer into small pieces, and then thin and polish the individual infrared detector chips after flip-chip interconnection, while the method of the present invention can achieve wafer-level bonding, save costs, and is suitable for mass production; and the method of the present invention can completely remove the substrate, enhance the infrared light absorption intensity, improve the response rate, and realize the reuse of the GaSb substrate, thereby reducing the production cost; the direct bonding method of the readout circuit and the epitaxial wafer realizes a more flexible material combination and structural design, and reduces the difficulty of subsequent processes; and the direct welding of the infrared detector chip and the adapter substrate makes the infrared detector assembly more integrated, which can improve the stability and reliability of the signal transmission of the electrical interconnection. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The present invention will be further described below in conjunction with the accompanying drawings:

[0021] Figure 1 It is a schematic diagram of the process of bonding and stripping of the InAs / GaSb type II superlattice material and the readout circuit of the present invention;

[0022] Figure 2 It is a schematic diagram of the structure of the interconnection between the focal plane array and the readout circuit of the infrared detector chip of the present invention;

[0023] Figure 3 It is a structural schematic diagram of an infrared detector assembly packaged by the method of the present invention;

[0024] In the figure: 1 is the readout circuit, 2 is the epitaxial layer, 3 is the GaSb substrate, 4 is the readout circuit pad, 5 is the metal electrode, 6 is the transfer substrate, and 7 is the substrate pad. DETAILED DESCRIPTION

[0025] like Figures 1 to 3 As shown, the present invention provides a packaging method for a vertically integrated superlattice infrared detector, comprising the following steps:

[0026] S1: Take the wafer and epitaxial wafer with the prepared readout circuit 1, and form a heterogeneous integrated structure by plasma low-temperature direct bonding process between the epitaxial wafer and the readout circuit 1; wherein the epitaxial wafer is obtained by epitaxially growing an epitaxial layer 2 of a type-II superlattice material of InAs / GaSb on a GaSb substrate 3; the direct bonding process realizes a more flexible material combination and structural design, and reduces the difficulty of subsequent processes;

[0027] The GaSb substrate 3 is completely removed by wet stripping process on the epitaxial wafer, thereby enhancing the infrared light absorption intensity, improving the response rate, realizing the reuse of the GaSb substrate 3, and reducing the production cost;

[0028] S2: Using ICP (Inductively Coupled Plasma) etching process and metallization process to form a focal plane array on the epitaxial wafer; the focal plane array consists of arranged single pixels, and isolation grooves are etched between pixels;

[0029] S3: etching a through hole in the isolation groove, and leading the metal electrode 5 of each pixel to the corresponding electrode area of ​​the readout circuit 1 through the through hole, so as to directly connect them, thereby realizing electrical interconnection and obtaining an infrared detector chip; this step does not require flip-chip interconnection, reduces the process difficulty, and the signal transmission is stable and reliable;

[0030] S4: interconnect the infrared detector chip and the transfer substrate 6 by using in-situ soldering or electroplating technology to obtain an infrared detector assembly. This step can make the infrared detector chip and the transfer substrate 6 more integrated and more reliable.

[0031] In step S1, before bonding the epitaxial wafer and the readout circuit 1, the wafers of both wafers need to be surface treated. The surface treatment is divided into two parts:

[0032] On the one hand, the wafer surface needs to be wet cleaned, and the implementation steps are as follows: clean the wafer for 5 minutes with acetone and ethanol solutions through a megasonic cleaning machine, with a cleaning power of 100~330W, and rinse with deionized water 20 times; then clean the wafer for 5 minutes with deionized water through a megasonic cleaning machine, with a cleaning power of 100~330W, and rinse with deionized water 20 times; finally blow dry with nitrogen. Megasonic cleaning technology uses high-frequency sound waves to efficiently clean fine particles in the solution through sound pressure and acoustic flow effects, ensuring that no contaminants remain, providing a high-quality foundation for the bonding process. In addition, this technology can also increase the hydroxyl density on the wafer surface and enhance its affinity. The high-frequency sound waves of megasonic cleaning are not easy to damage the cleaning object.

[0033] On the other hand, in order to further reduce the roughness of the wafer surface and improve the degree of wafer activation, strong hydrophilicity (i.e. contact angle <5°) is formed, which is conducive to hydrophilic bonding. The implementation steps are as follows: Use a plasma stripper to treat the wafer surface with oxygen plasma for 2 minutes at 300W power and 150mTorr pressure. Plasma activation in an oxygen atmosphere has physical and chemical effects, which can remove impurities, break chemical bonds, and form hydroxyl groups and hydrogen bonds on the surface by reacting with water, thereby enhancing hydrophilicity.

[0034] Then, under normal temperature and pressure conditions, the cleaned and activated InAs / GaSb type II superlattice material epitaxial wafer is aligned and contacted with the activated surface of the wafer of the readout circuit 1. By applying pressure, the hydroxyl groups on the surfaces of the two wafers are brought close enough, and the interface force is utilized to bond them together, so that pre-bonding can be spontaneously completed. Subsequently, the pre-bonded wafers are loaded into a bonding machine to complete bonding and form a heterogeneous integrated structure. The bonding conditions are: temperature 200~300℃, pressure 8~10MPa, and time 30~60 min.

[0035] Finally, the GaSb substrate 3 is peeled off from the epitaxial wafer using a wet etching solution, thereby achieving the reusability of the GaSb substrate 3 .

[0036] The wafer of the readout circuit 1 may be a silicon-based readout circuit wafer.

[0037] In step S2, the circuit structure of a single pixel on the focal plane array is determined on the heterogeneous integrated structure by contact photolithography and ICP etching process. The parameters of the ICP etching process in this step are: using Cl2, BCl3, and Ar as etching gases, ICP power of 400-600W, radio frequency (RF) power of 100-200W, chamber pressure of 2-4mTorr, and table temperature of 60-200°C. The table temperature is the temperature of the workbench (also called base plate or substrate) that supports the wafer.

[0038] In step S2, a through hole is etched on the isolation groove of the epitaxial wafer to expose the pad of the readout circuit 1, and then 50nm thick Ti, 50nm thick Pt, and 300nm thick Au are deposited between each pad of the readout circuit 1 and the pixel of the corresponding epitaxial wafer to form a metal electrode 5. The metal electrode 5 is used to realize the interconnection and integration of the pixel of the InAs / GaSb type II superlattice material and the readout circuit 1 to obtain an infrared detector chip.

[0039] The infrared detector chip is diced as required to obtain a plurality of independent infrared detector chips.

[0040] In step S3, an assembled adapter substrate 6 is used, and the pad positions on the adapter substrate 6 correspond one-to-one to the pad positions on the individual infrared detector chips after dicing. The readout circuit pads 4 and the substrate pads 7 are interconnected by soldering or electroplating technology to achieve high integration of the adapter substrate 6 and the infrared detector chip; the problems of traditional gold wire bonding, small wire contact points, and long wiring are avoided, the vibration and impact resistance of the infrared detector assembly is improved, and the working reliability of the infrared detector assembly is enhanced.

[0041] The transfer substrate 6 may be a ceramic substrate.

[0042] In the bonding method of the readout circuit 1 and the epitaxial wafer in step S1, an indirect bonding process may also be adopted, and some medium is added between the two to achieve the bonding between the two.

[0043] The present invention achieves a stable electrical connection between the pad of the readout circuit 1 and the second type superlattice material by directly or indirectly bonding the readout circuit 1 to the epitaxial wafer and then depositing the metal electrode 5 by through-hole etching.

[0044] The packaging method of the present invention can realize highly vertically integrated packaging and signal transmission of infrared detectors, which is mainly reflected in two parts:

[0045] 1. For the first transmission of the electrical signal, the epitaxial wafer can be directly connected to the readout circuit 1 through the through hole of the isolation groove, and there is no chip spacing between the epitaxial wafer and the readout circuit 1; while the traditional infrared detector that requires flip-chip soldering of indium pillars to realize signal transmission has a chip spacing of several um, and it is also necessary to fill the gap between the chips with glue to improve the stability of the interconnection, and the process route is complicated.

[0046] 2. The second transmission of the electric signal, the electric signal output by the readout circuit 1 is transmitted in situ to the electrode of the transfer substrate 7 through the through-hole metallization. The traditional process uses wire bonding to transmit the electric signal, which reduces the reliability.

[0047] In this way, the two signal transmissions are in the same vertical direction, thus achieving vertical integration and higher integration.

[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging method for a vertically integrated superlattice infrared detector, characterized in that: The following steps are involved: S1: Take the wafer and epitaxial wafer with the prepared readout circuit, and form a heterogeneous integrated structure by plasma low-temperature direct bonding process between the epitaxial wafer and the readout circuit; The epitaxial wafer is obtained by epitaxially growing an epitaxial layer of two types of superlattice materials on a substrate; The substrate is completely removed by a wet stripping process on the epitaxial wafer; The epitaxial wafer is obtained by epitaxially growing an epitaxial layer of a second type InAs / GaSb superlattice material on a GaSb substrate; S2: Using ICP etching process and metallization process to form a focal plane array on the epitaxial wafer; S3: Leading the metal electrode of each pixel on the focal plane array to the corresponding electrode area of ​​the readout circuit through the through hole, so that the focal plane array is directly connected to the readout circuit, and an infrared detector chip is obtained; S4: interconnecting the infrared detector chip and the adapter substrate via the adapter substrate pad and the readout circuit pad located in the readout circuit through hole to obtain an infrared detector assembly.

2. The packaging method of a vertically integrated superlattice infrared detector according to claim 1, characterized in that: In step S1, the epitaxial wafer and the readout circuit may also be formed into a heterogeneous integrated structure by an indirect bonding process.

3. A packaging method for a vertically integrated superlattice infrared detector according to claim 1 or 2, characterized in that: Before bonding the epitaxial wafer to the readout circuit, surface treatment is first performed on the epitaxial wafer and the wafer of the readout circuit, wherein the surface treatment includes wet cleaning treatment and plasma activation treatment.

4. The packaging method of a vertically integrated superlattice infrared detector according to claim 3, characterized in that: The metallization process in step S2 adopts a contact photolithography process, firstly realizing photoresist pixel patterning on the epitaxial wafer through the contact photolithography process, and then realizing pixel patterning of the second type superlattice material through the ICP etching process.

5. The packaging method of a vertically integrated superlattice infrared detector according to claim 3, characterized in that: The wet cleaning process is implemented by using a megasonic cleaning machine, and the wafer is cleaned multiple times by using an acetone solution, an ethanol solution and deionized water respectively.

6. The packaging method of a vertically integrated superlattice infrared detector according to claim 3, characterized in that: The plasma activation process step is placed after the wet cleaning process step.

7. The packaging method of a vertically integrated superlattice infrared detector according to claim 5, characterized in that: The pad positions on the adapter substrate correspond one-to-one to the pad positions on the infrared detector chip.

8. The packaging method of a vertically integrated superlattice infrared detector according to claim 5, characterized in that: Before performing step S4, the wafer-level infrared detector chips formed through steps S1 to S3 are first diced to obtain a plurality of independent infrared detector chips.

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