Heterojunction field effect transistor device structure and preparation method thereof

Abstract

The invention provides a heterojunction field effect transistor device structure and a preparation method thereof. The heterojunction field effect transistor device structure comprises: a substrate; a heterogeneous crystal circle is arranged on the substrate, the heterogeneous crystal circle comprises a quantum well layer, and a buried channel is formed in the quantum well layer; a gate oxide layer is arranged on the heterogeneous crystal circle; a gate is arranged on the gate oxide layer; a P-type source-drain electrode is arranged at intervals with the gate, passes through the gate oxide layer and extends to the quantum well layer, and forms a P-type field effect transistor with the quantum well layer and the gate; an N-type source-drain electrode is arranged at intervals with the gate and the P-type source-drain electrode, passes through the gate oxide layer and extends to the quantum well layer, and forms an N-type field effect transistor with the quantum well layer and the gate; and the direction of the electric field applied to the gate is changed so that energy level defects in the forbidden band of the interface between the heterogeneous crystal circle and the gate oxide layer store or recombine charge carriers, thereby controlling the threshold voltage of the N-type field effect transistor and the P-type field effect transistor, wherein the charge carriers include electrons or holes.

Description

Technical Field

[0001] At least one embodiment of the present invention relates to the technical field of heterojunction field effect transistor device structures, and in particular to a heterojunction field effect transistor device structure with adjustable threshold voltage and a preparation method thereof. Background Art

[0002] Quantum computing is a new computer architecture that uses quantum superposition and entanglement to read, write, and manipulate data. Parallel computing allows this architecture to perform both fast and complex operations, making it a crucial area of ​​future technological advancement. Semiconductor-gated quantum dots, one of many potential solutions for quantum computing, are experiencing rapid development due to their flexibility and compatibility with modern semiconductor integrated circuit processes.

[0003] There are various solid-state systems for realizing semiconductor quantum computing. Among them, the hole system in the silicon-germanium / germanium / silicon-germanium heterojunction (SiGe / Ge / SiGe, also known as the planar strained germanium structure, hereinafter referred to as the strained germanium structure) is favored by many researchers as a carrier for encoding spin quantum bits (qubits) due to its strong spin-orbit coupling.

[0004] In fact, the interface state density of gate oxide fabricated on silicon germanium is two orders of magnitude higher than that of silicon. Therefore, to address the poor interface properties of strained germanium, a silicon cap layer (Si cap) is usually added to the surface during the fabrication process as a sacrificial layer to reduce the interface state density. However, this structure still has a large amount of interface state density. On the one hand, this is due to the large lattice mismatch between silicon and germanium, which creates a large number of dangling bonds at the interface between the Si cap layer and silicon germanium (SiGe). On the other hand, the Si cap layer is not grown using the normal single crystal silicon growth method, but is formed by residual gas adhesion reaction during low-temperature reduced pressure chemical vapor deposition (RPCVD) without proper passivation, resulting in many defects in the Si cap itself.

[0005] In addition, due to the lower valence band difference of Ge / SiGe / Si cap, the holes in the strained germanium buried channel are easily trapped in the interface state of the Sicap surface by Fowder-Nordheim (FN) surface tunneling. The holes trapped in the interface state are difficult to be released at low temperatures due to the asymmetric potential barrier, thus forming a series of positively charged centers. These charged centers increase the charge noise while also causing the absolute value of the threshold voltage of the hole-type device to increase. The high interface state density makes it difficult for surface tunneling to reach an equilibrium state, causing the threshold to drift.

[0006] In order to solve the problem of threshold drift in heterojunction field-effect transistor device structures, the solution proposed in related technologies is to thicken the silicon germanium barrier layer to reduce the electric field of the barrier layer, thereby reducing the probability of FN surface tunneling to achieve rapid equilibrium. However, this solution is only applicable to situations where the gate voltage is small and changes slowly. Summary of the Invention

[0007] In order to solve at least one of the technical problems in the existing technical solutions, the present invention provides a heterojunction field effect transistor device structure capable of adjusting the threshold voltage.

[0008] As one aspect of an embodiment of the present invention, a heterojunction field effect transistor device structure is provided, including a substrate, a heterojunction crystal circle, a gate oxide layer, a gate, a P-type source-drain electrode, and an N-type source-drain electrode. A heterogeneous crystal circle is arranged on the above-mentioned substrate, and the above-mentioned heterogeneous crystal circle includes a quantum well layer, and a buried channel is formed in the above-mentioned quantum well layer; a gate oxide layer is arranged on the above-mentioned heterogeneous crystal circle; a gate is arranged on the above-mentioned gate oxide layer; a P-type source and drain electrode is arranged at intervals from the above-mentioned gate, extends through the above-mentioned gate oxide layer to the above-mentioned quantum well layer, and forms a P-type field effect transistor with the above-mentioned quantum well layer and the above-mentioned gate; an N-type source and drain electrode is arranged at intervals from the above-mentioned gate and the above-mentioned P-type source and drain electrode, extends through the above-mentioned gate oxide layer to the above-mentioned quantum well layer, and forms an N-type field effect transistor with the above-mentioned quantum well layer and the above-mentioned gate; wherein, the direction of the electric field applied to the above-mentioned gate is changed so that the energy level defects in the band gap at the interface between the above-mentioned heterogeneous crystal circle and the above-mentioned gate oxide layer store or recombine charge carriers, so as to change the charge amount of the above-mentioned energy level defects, thereby controlling the threshold voltage of the above-mentioned N-type field effect transistor and the above-mentioned P-type field effect transistor, wherein the above-mentioned charge carriers include electrons or holes.

[0009] According to an embodiment of the present invention, under low temperature conditions of less than 10K, the electric field strength applied to the above-mentioned gate exceeds the Fowler-Nordheim critical tunneling field strength of electrons, so that the above-mentioned charge carriers tunnel into the above-mentioned energy level defects under the action of the above-mentioned electric field, forming fixed charges.

[0010] According to an embodiment of the present invention, the above-mentioned P-type source-drain electrode is connected to an external circuit, and a negative gate voltage is applied to the above-mentioned gate. The holes introduced into the above-mentioned buried channel through the above-mentioned P-type source-drain electrode tunnel to the above-mentioned interface and are trapped in the above-mentioned energy level defects, forming positive fixed charges, thereby increasing the threshold voltage of the above-mentioned P-type field effect transistor and reducing the threshold voltage of the above-mentioned N-type field effect transistor.

[0011] According to an embodiment of the present invention, the above-mentioned heterojunction field effect transistor device structure also includes: connecting the above-mentioned N-type source and drain electrodes to an external circuit, applying a positive gate voltage to the above-mentioned gate, and the electrons introduced from the above-mentioned N-type source and drain electrodes and located in the above-mentioned buried channel tunnel to the interface under the induction of the electric field provided by the above-mentioned positive gate voltage, and relax to the shallow energy level defects located at the edge of the above-mentioned band gap and the deep energy level defects located at the center of the band gap, and the holes captured by the above-mentioned shallow energy level defects are re-injected into the above-mentioned buried channel under the induction of the above-mentioned electric field and flow out through the above-mentioned P-type source and drain, and the holes captured by the above-mentioned deep energy level defects are recombined with the injected electrons and return to the initial state.

[0012] According to an embodiment of the present invention, the above-mentioned N-type source-drain electrode is connected to an external circuit, a positive gate voltage is applied to the above-mentioned gate, and electrons introduced into the above-mentioned buried channel through the above-mentioned N-type source-drain electrode tunnel to the above-mentioned interface and relax in the above-mentioned energy level defects. They are captured by the above-mentioned energy level defects to form negative fixed charges, thereby increasing the threshold voltage of the above-mentioned N-type field effect transistor and reducing the threshold voltage of the above-mentioned P-type field effect transistor.

[0013] According to an embodiment of the present invention, the heterojunction field effect transistor device structure further includes controlling the intensity and maintenance time of the electric field to control the number of charge carriers captured in the energy level defects to achieve threshold voltage adjustment.

[0014] According to an embodiment of the present invention, the heterogeneous crystal circle includes a first barrier layer, a second barrier layer, and a cap layer. The first barrier layer is disposed on the substrate, wherein the quantum well layer is disposed on the first barrier layer; the second barrier layer is disposed on the quantum well layer and is adapted to cooperate with the first barrier layer to confine electrons or holes in the quantum well layer; the cap layer is disposed on the second barrier layer; wherein the interface is located between the cap layer and the gate oxide layer.

[0015] According to an embodiment of the present invention, the quantum well layer maintains compressive strain, the second barrier layer relaxes, the cap layer and the second barrier layer form a tensile strain state, and a heterojunction straddling energy band is formed at the interface, so that the buried channel can trap holes or electrons.

[0016] According to an embodiment of the present invention, the N-type source and drain electrodes include two spaced N-type injection regions and two N-type ohmic contact electrodes. The two N-type injection regions extend downward from the surface of the heterogeneous crystal circle to the quantum well layer; the two N-type ohmic contact electrodes are spaced from the gate electrode and extend through the gate oxide layer to the two N-type injection regions to connect to external circuits.

[0017] The P-type source and drain electrodes include two spaced-apart P-type injection regions and two P-type ohmic contact electrodes. The two P-type injection regions extend downward from the surface of the heterogeneous crystal circle to the quantum well layer. The two P-type ohmic contact electrodes are spaced apart from the gate electrode and extend through the gate oxide layer to the two P-type injection regions for connection to external circuits.

[0018] As another aspect of an embodiment of the present invention, a method for preparing any of the above-mentioned heterojunction field-effect transistor device structures is provided, comprising:

[0019] Using chemical vapor deposition technology to grow heterogeneous crystal circles on the substrate;

[0020] Using reactive ion etching technology to perform mesa etching on the heterogeneous crystal circle to form four alignment mark areas;

[0021] Using a photoresist as a mask, performing P-type implantation in two alignment mark regions and activating them by rapid thermal annealing to form P-type implantation regions; performing N-type implantation in the other two alignment mark regions and activating them by rapid thermal annealing to form N-type implantation regions;

[0022] The gate oxide layer is grown using atomic layer deposition technology;

[0023] The gate electrode is deposited using electron beam evaporation technology;

[0024] Etching the gate oxide layer above the local ion implantation area to form two P-type windows and two N-type windows;

[0025] P-type ohmic contact electrodes are deposited in the two P-type windows, and N-type ohmic contact electrodes are deposited in the two N-type windows.

[0026] According to the heterojunction field effect transistor device structure of an embodiment of the present invention, a P-type field effect transistor and an N-type super effect transistor with a common gate structure are formed on a heterojunction crystal circle. By changing the direction of the battery applied to the gate, the energy level defects in the band gap at the interface between the heterojunction crystal circle and the gate oxide layer store or recombine charge carriers to change the charge amount of the energy level defects, thereby controlling the threshold voltage of the N-type field effect transistor and the P-type field effect transistor, achieving the purpose of controllable threshold voltage, and the threshold voltage can be adjusted without restoring the heterojunction field effect transistor device structure to room temperature. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 shows a top view of a heterojunction field effect transistor device structure in an XY plane according to some embodiments of the present invention;

[0028] Figure 2 Shown Figure 1A cross-sectional view taken along line AA of the heterojunction field effect transistor device structure shown;

[0029] Figure 3 Shown Figure 1 A cross-sectional view of a BB of the heterojunction field effect transistor device structure shown;

[0030] Figure 4 shows a carrier distribution diagram of a P-type field effect transistor according to some embodiments of the present invention;

[0031] Figure 5 shows an energy band diagram of a P-type field effect transistor according to some embodiments of the present invention;

[0032] Figure 6 shows a first carrier distribution diagram of an N-type field effect transistor according to some embodiments of the present invention;

[0033] Figure 7 shows a first energy band diagram of an N-type field effect transistor according to some embodiments of the present invention;

[0034] Figure 8 shows a second carrier distribution diagram of a P-type field effect transistor according to some embodiments of the present invention;

[0035] Figure 9 shows a second energy band diagram of a P-type field effect transistor according to some embodiments of the present invention;

[0036] Figure 10 A flow chart of preparing a heterojunction field effect transistor device structure according to some embodiments of the present invention is shown.

[0037] Description of reference numerals:

[0038] 1-heterogeneous crystal circle;

[0039] 11-quantum well layer;

[0040] 12-first barrier layer;

[0041] 13- second barrier layer;

[0042] 14-cap layer;

[0043] 2-gate oxide layer;

[0044] 3-gate;

[0045] 4-P type source and drain electrodes;

[0046] 41-P type injection region;

[0047] 42-P type ohmic contact electrode;

[0048] 5-N-type source and drain electrodes;

[0049] 51-N type injection region;

[0050] 52-N type ohmic contact electrode. DETAILED DESCRIPTION

[0051] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete and to fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity, and like reference numerals denote like elements throughout.

[0052] The figures described below are only some embodiments of the present invention. For those skilled in the art, other methods for initializing the threshold voltage of a heterojunction field-effect transistor device structure by utilizing energy level defects and trapping charges opposite to channel carriers to form fixed charges to achieve controllable channel thresholds obtained based on these figures are also within the scope of protection of the present invention without inventive effort. At the same time, the present invention is applicable to a variety of buried channel device structures with barrier layers, and is applicable to a variety of materials and device structures. Applicable materials include gallium arsenide (with aluminum), silicon, germanium, gallium nitride (with aluminum), indium arsenide (with aluminum), etc. Applicable structures include buried channel field-effect transistors with barriers, such as various heterojunction field-effect transistor device structures, various floating gate transistors, and various back-gate floating body (buried channel that can accommodate holes or electrons and has a barrier to inhibit low-voltage reverse tunneling) transistors.

[0053] During the implementation of the present invention, it was discovered that heterojunction field-effect transistor (HFET) device structures may experience various electrostatic disturbances during measurement (under extremely low temperatures, less than 10K). This static electricity can reach thousands of volts, sufficient to cause the FN surface tunneling electric field to reach its critical tunneling field strength. If the static discharge time is sufficient, holes in the buried channel will tunnel back to the surface, causing threshold shift. In severe cases, the device threshold can drift beyond the maximum voltage applicable to the measurement equipment. Therefore, if this occurs during measurement, the device under test generally needs to be restored to room temperature to allow the holes in the defect to gain sufficient kinetic energy to break free from the defect, thereby achieving initialization. However, this process is cumbersome and inconvenient to operate. Moreover, repeated heating and cooling may cause changes in the device's state, such as reliability issues caused by the expansion and contraction of various contacts across large temperature differences, leading to aging and expansion.

[0054] Furthermore, at extremely low temperatures, strained germanium quantum dot devices often experience significant differences in threshold values ​​at various gate locations due to disorder, significantly limiting the device's fan-out resources. Controlling the threshold values ​​at each location would allow for the use of shared electrodes to conserve fan-out resources. Furthermore, controllable channel thresholds allow for the free definition of active regions, reducing losses in microwave devices caused by carriers in inactive regions.

[0055] Figure 1 FIG2 shows a top view of a heterojunction field effect transistor device structure in an XY plane according to some embodiments of the present invention, Figure 2 Shown Figure 1 The cross-sectional view of the heterojunction field effect transistor device structure is shown in FIG. Figure 3 Shown Figure 1 A cross-sectional view of a BB heterojunction field effect transistor device structure is shown.

[0056] As one aspect of an embodiment of the present invention, a heterojunction field effect transistor device structure is provided, such as Figures 1 to 3 As shown, the heterojunction field-effect transistor device structure includes a substrate (not shown), a heterojunction wafer 1, a gate oxide layer 2, a gate 3, a P-type source-drain electrode 4, and an N-type source-drain electrode 5. The heterojunction wafer is disposed on the substrate. The heterojunction wafer 1 includes a quantum well layer 11, within which a buried channel is formed. The gate oxide layer 2 is disposed on the heterojunction wafer 1, and the gate 3 is disposed on the gate oxide layer 2. The P-type source-drain electrode 4 is spaced apart from the gate 3, extending through the gate oxide layer 3 to the quantum well layer 11, and forming a P-type field-effect transistor (PMOS) with the quantum well layer 11 and the gate 3. The N-type source-drain electrode 5 is spaced apart from the gate 3 and the P-type source-drain electrode 4, extending through the gate oxide layer 2 to the quantum well layer 11, and forming an N-type field-effect transistor (NMOS) with the quantum well layer 11 and the gate 3. Among them, the direction of the electric field applied to the gate 3 is changed, so that the energy level defects in the band gap at the interface between the heterogeneous crystal circle 1 and the gate oxide layer 2 store or recombine charge carriers to change the charge amount of the energy level defects, thereby controlling the threshold voltage of the N-type field effect transistor and the P-type field effect transistor, where the charge carriers include electrons or holes.

[0057] According to the heterojunction field effect transistor device structure of an embodiment of the present invention, a P-type field effect transistor and an N-type super effect transistor with a common gate structure are formed on a heterojunction crystal circle. By changing the direction of the battery applied to the gate, the energy level defects in the band gap at the interface between the heterojunction crystal circle and the gate oxide layer store or recombine charge carriers to change the charge amount of the energy level defects, thereby controlling the threshold voltage of the N-type field effect transistor and the P-type field effect transistor, achieving the purpose of controllable threshold voltage, and the threshold voltage can be adjusted without restoring the heterojunction field effect transistor device structure to room temperature.

[0058] According to an embodiment of the present invention, energy level defects are additional energy levels generated during the fabrication of heterojunction field-effect transistor device structures due to defects in material preparation or device structure. These energy levels are located in the band structure of the semiconductor material, typically in the band gap.

[0059] According to an embodiment of the present invention, under low temperature conditions of less than 10K (for example, 4K), the electric field strength applied to the gate exceeds the Fowler-Nordheim critical tunneling field strength of electrons, causing charge carriers to tunnel into energy level defects under the action of the electric field, forming fixed charges.

[0060] According to an embodiment of the present invention, in the heterojunction field effect transistor device structure provided by the present invention, when the threshold value adjustment is not required and the device is used normally, the length of the electric field applied to the gate is greater than or equal to the threshold voltage of the N-type field effect transistor used, or greater than or equal to the threshold voltage of the P-type field effect transistor, and at the same time needs to be less than the Fowler-Nordheim critical tunneling field strength of electrons to avoid threshold voltage drift of the heterojunction field effect transistor device structure under normal use.

[0061] According to an embodiment of the present invention, energy level defects capture charges opposite to channel carriers to form fixed charges.

[0062] According to an embodiment of the present invention, the intensity and maintenance time of the electric field are controlled to control the number of charge carriers trapped in the energy level defects, thereby achieving adjustment of the threshold voltage.

[0063] The heterojunction field-effect transistor device structure provided according to an embodiment of the present invention can be used to freely control the threshold value in the channel through which charge carriers flow. In particular, by adopting a multi-gate discrete structure (such as semiconductor quantum dots, etc.), highly uniform threshold voltages at different positions can be achieved.

[0064] According to an embodiment of the present invention, Figure 2 and Figure 3 As shown, the heterogeneous crystal circle 1 includes a first barrier layer 12, a second barrier layer 13 and a cap layer 14. The first barrier layer 12 is arranged on the substrate, wherein the quantum well layer 11 is arranged on the first barrier layer 12. The second barrier layer 13 is arranged on the quantum well layer 11, and the second barrier layer 13 is suitable for cooperating with the first barrier layer 12 to confine electrons or holes in the quantum well layer 11. The cap layer 14 is arranged on the second barrier layer 13. The interface is located between the cap layer 14 and the gate oxide layer 2.

[0065] According to an embodiment of the present invention, the quantum well layer maintains compressive strain, the second barrier layer relaxes, and the cap layer and the second barrier layer form a tensile strain state. A heterojunction straddling band is formed at the interface, enabling the buried channel to trap holes or electrons.

[0066] According to an embodiment of the present invention, the quantum well layer may be a multi-layer stacked structure.

[0067] In an exemplary embodiment, the quantum well layer may be a strained silicon structure or a strained germanium structure.

[0068] According to an embodiment of the present invention, Figure 1 and Figure 3 As shown, the N-type source-drain electrode 5 includes two spaced-apart N-type injection regions 51 and two N-type ohmic contact electrodes 52. The two spaced-apart N-type injection regions 51 extend downward from the surface of the heterogeneous crystal circle 1 to the quantum well layer 11. The two N-type ohmic contact electrodes 52 are spaced-apart from the gate 3 and extend through the gate oxide layer 2 to the two N-type injection regions 51 to connect to external circuits.

[0069] According to an embodiment of the present invention, Figure 1 As shown, the P-type source and drain electrode 4 includes two spaced-apart P-type injection regions 41 and two P-type ohmic contact electrodes 42. The two spaced-apart P-type injection regions, spaced apart from the two N-type injection regions, extend downward from the surface of the heterogeneous crystal disk to the quantum well layer. The two P-type ohmic contact electrodes, spaced apart from the gate, extend through the gate oxide layer to the two P-type injection regions for connection to external circuits.

[0070] Figure 4 shows a carrier distribution diagram of a P-type field effect transistor according to some embodiments of the present invention, Figure 5 shows an energy band diagram of a P-type field effect transistor according to some embodiments of the present invention, Figure 6 shows a first carrier distribution diagram of an N-type field effect transistor according to some embodiments of the present invention, Figure 7 A first energy band diagram of an N-type field effect transistor according to some embodiments of the present invention is shown.

[0071] Figure 5 and Figure 7 The perspective shown, Figure 5 and Figure 7 In the equation, Ev represents the top of the valence band, Ec represents the bottom of the conduction band, E represents the electron potential, and Z represents the Z direction. Figure 4 and Figure 5 As shown in , when a sufficiently negative gate voltage is applied to the gate, the holes introduced by the P-type source and drain electrodes form buried channel holes and FN surface tunneling. Figure 6 and Figure 7 As shown in FIG, when a sufficiently positive gate voltage is applied to the gate, the holes introduced by the N-type source and drain electrodes form buried channel holes and FN surface tunneling.

[0072] During the implementation of the present invention, it was discovered that the quantum well layer is a germanium (Ge) quantum well, the first and second barrier layers are made of silicon-germanium (SiGe), and the cap layer is made of silicon (Si). In a SiGe / Ge / SiGe / Si cap heterojunction structure, to ensure low hole disorder within the germanium channel and excellent hole physical properties, the Ge quantum well must maintain compressive strain, the barrier layers must relax, and the surface cap layer (Si cap) and the SiGe barrier layer must be in a tensile strain state. In this heterojunction stack, a tape I heterojunction band forms at the SiGe / Ge / SiGe interface. This band structure allows the Ge quantum well to trap both holes and electrons, forming a buried channel with higher mobility away from the interface. Despite this, this structure still exhibits a large number of defects at the interface between the Si cap and the gate oxide. These defects create a series of discrete energy levels in the band gap at the surface interface, thereby creating charge carrier defects.

[0073] In the above-mentioned heterojunction field-effect transistor device structure, the Si cap layer located at the surface has a large defect state density. These defects are distributed in discrete energy levels in the surface band gap and are difficult to completely eliminate, such as Figure 4 and Figure 5 As shown in the figure, when a negative gate voltage is applied to the gate, the valence band top potential in the Ge quantum well (Ge QW) decreases. When it drops to a certain level, holes can be injected from the P-type source and drain electrodes across the nearby potential barrier into the buried channel of the Ge QW, at which point a hole channel is formed. When the negative gate voltage is further increased and the electric field strength of the barrier layer reaches the critical field strength for FN tunneling, holes will undergo surface tunneling and rapidly relax into surface energy level defects, forming charged defects. These holes trapped in the energy level defects are difficult to release from the defects due to the asymmetric potential barrier and reverse electric field. To maintain the previous operating state, the gate voltage must be continued. Due to the large number of interface states, holes continue to tunnel, which will cause the threshold voltage of the PMOS device to increase, ultimately leading to gate-source breakdown.

[0074] The surface Si cap layer has not only hole-type defects but also electron-type defects, such as Figure 6 and 7As shown in the figure, when a positive gate voltage is applied to the gate, the bottom potential of the conduction band in the Ge quantum well decreases. When it drops to a certain level, electrons can be injected from the N-type source and drain electrodes into the Ge QW buried channel to form a conductive electron channel. When the gate voltage continues to increase and the electric field strength of the barrier layer reaches the FN tunneling critical field strength, the electrons will undergo surface tunneling and quickly relax to the surface energy level defects to form charged defects. These electrons captured by the energy level defects are difficult to be released by the defects due to the asymmetric potential barrier (the surface layer has a potential well with a depth of approximately 300-400meV and this surface layer has a silicon germanium barrier with a higher potential barrier). Their behavior is similar to that of fixed charges in the gate dielectric, so this charge also has the ability to regulate the threshold voltage.

[0075] Since the amount of injected charge will determine the amount of threshold voltage shift, and the amount of injected charge is related to the applied gate voltage, the greater the positive gate voltage applied, the higher the Fermi level, the more curved the surface energy band, the more electrons injected into the surface defects, and the more serious the threshold shift of the PMOS device. Therefore, the threshold voltage of the PMOS can be freely regulated according to the reverse gate voltage. This regulation can realize the transformation of the PMOS device from enhancement mode to depletion mode. In addition, since electrons are only injected into the region where electrons flow to change the threshold of the region, then for multi-gate discrete structures (such as quantum dot structures), the threshold under each electrode can be independently regulated to achieve the uniformity of the threshold voltage.

[0076] According to an embodiment of the present invention, Figure 4 and Figure 5 As shown, connect the P-type source and drain electrodes to the external circuit and apply a negative gate voltage to the gate. Figure 4 As shown by the middle arrow, the holes introduced into the buried channel through the P-type source and drain electrodes tunnel to the interface and are trapped in energy level defects, forming positive fixed charges, which increases the threshold voltage of the P-type field effect transistor and reduces the threshold voltage of the N-type field effect transistor.

[0077] According to an embodiment of the present invention, by applying a negative gate voltage to the gate, when the electric field applied by the negative gate voltage exceeds the FN critical tunneling field strength, the holes introduced from the P-type source and drain electrodes in the buried channel tunnel to the interface under the induction of the electric field and are captured by energy level defects. The holes captured by the energy level defects can enter the shallow energy level defects (fast interface states) located at the edge of the band gap or the deep energy level defects (slow interface states) located at the center of the band gap. The holes captured by the shallow energy level defects can be released when a smaller positive gate voltage is applied, and the holes captured by the deep energy level defects are difficult to be released, forming a positive fixed charge.

[0078] According to an embodiment of the present invention, after the heterojunction field-effect transistor device structure is cooled to a low temperature (below 10K), a positive gate voltage is first applied. Once the applied electric field exceeds the electron's FN critical tunneling field strength, the electrons will tunnel to the surface and become trapped in surface energy level defects. If the second barrier layer is thicker (or an electron barrier layer is superimposed on the original barrier layer), the trapped electrons, due to the deep barrier, will find it difficult to release from the energy level defects even when a relatively low negative voltage (sufficient to open the hole channel but not exceeding the FN critical tunneling field strength) is applied, forming a "fixed charge" that achieves the purpose of regulating the PMOS device threshold.

[0079] According to an embodiment of the present invention, shallow energy level defects are located in the energy band structure near the bottom of the conduction band or the top of the valence band, and deep energy level defects are located inside the forbidden band, far away from the bottom of the conduction band and the top of the valence band.

[0080] According to an embodiment of the present invention, Figure 6 and Figure 7 As shown, the N-type source and drain electrodes are connected to an external circuit, a positive gate voltage is applied to the gate, and electrons introduced into the buried channel through the N-type source and drain electrodes tunnel to the interface and relax in energy level defects. They are captured by the energy level defects to form negative fixed charges, thereby increasing the threshold voltage of the N-type field effect transistor and reducing the threshold voltage of the P-type field effect transistor.

[0081] Figure 8 shows a second carrier distribution diagram of a P-type field effect transistor according to some embodiments of the present invention, Figure 9 A second energy band diagram of a P-type field effect transistor according to some embodiments of the present invention is shown.

[0082] Figure 9 The perspective shown is as follows: Ev represents the top of the valence band, Ec represents the bottom of the conduction band, E represents the electron potential, and Z represents the Z direction.

[0083] According to an embodiment of the present invention, after connecting the P-type source and drain electrodes to an external circuit, applying a negative gate voltage to the gate, and introducing holes into the buried channel through the P-type source and drain electrodes, tunneling to the interface and being trapped in energy level defects, forming positive fixed charges, thereby increasing the threshold voltage of the P-type field effect transistor and reducing the threshold voltage of the N-type field effect transistor, when it is necessary to initialize the threshold voltage of the heterojunction field effect transistor device structure, the method further includes:

[0084] Connect the N-type source and drain electrodes to the external circuit (it is understood that this step can be completed simultaneously with the operation of connecting the P-type source and drain electrodes to the external circuit), and apply a positive gate voltage to the gate, such as Figure 8 and Figure 9As shown, electrons introduced from the N-type source and drain electrodes into the buried channel tunnel to the interface under the induction of the electric field provided by the positive gate voltage and relax into the shallow energy level defects at the edge of the band gap and the deep energy level defects at the center of the band gap. Holes captured by the shallow energy level defects are re-injected into the buried channel under the induction of the electric field and flow out through the P-type source and drain. Holes captured by the deep energy level defects are recombined with the injected electrons and return to the initial state. The initialization of the heterojunction field effect transistor device structure can be achieved without changing the temperature of the heterojunction field effect transistor device structure. It can be understood that a positive gate voltage is first applied to the gate so as to increase the threshold voltage of the N-type field effect transistor and reduce the threshold voltage of the P-type field effect transistor. Thereafter, when it is necessary to initialize the threshold voltage of the heterojunction field effect transistor device structure, a negative gate voltage is also applied to the gate to initialize the heterojunction field effect transistor device structure. It can be understood that when the heterojunction field effect transistor device structure is initialized, the electric field provided by the applied gate voltage is greater than the FN critical tunneling field strength.

[0085] According to an embodiment of the present invention, holes trapped in deep-level defects have a very low probability of FN tunneling due to the large barrier height, and are therefore difficult to release unless a large positive gate voltage is applied and maintained for a long time (increasing the FN tunneling probability). However, such an electric field can easily cause gate leakage in the heterojunction field-effect transistor device structure, posing a significant reliability issue. However, if N-type injection is turned on at this time and a low positive gate voltage is applied, electrons introduced from the N-type source and drain electrodes in the Ge channel will tunnel to the surface under the induction of the electric field. Electrons tunneling to the surface can relax to shallow-level defects or deep-level defects of electrons. At the same time, shallow-level defects captured by hole defects will be re-injected into the germanium channel under the induction of the electric field and flow out of the ohmic contact, while holes captured by deep-level defects will recombine with the injected electrons and return to their initial state.

[0086] According to an embodiment of the present invention, the N-type ohmic contact electrode of the connected device applies a sufficient positive voltage to the gate of the heterojunction field effect transistor device structure to which a negative gate voltage is pre-applied, resulting in energy level defects capturing holes, and waits for a certain period of time so that the holes in the shallow energy level defects are discharged under the action of the electric field and the holes in the deep energy level defects recombine with the tunneling electrons.

[0087] In such an embodiment, in order to eliminate the threshold shift phenomenon caused by hole trapping in the defect state, as Figure 8 and Figure 9As shown, applying a sufficient positive gate voltage to the gate reduces the bottom potential of the conduction band in the quantum well layer. When it drops to a certain level, electrons can be injected from the N-type source and drain electrodes across the nearby potential barrier into the buried channel of the quantum well layer, forming an electron channel. When the gate voltage is further increased and the electric field strength of the barrier layer reaches the critical field strength for FN tunneling, electrons will undergo surface tunneling and rapidly relax to shallow or deep energy level defects, forming negatively charged charge centers. After a certain period of time, these negatively charged shallow energy level defects gradually relax the captured electrons to deep energy level defects, where there is a certain probability of recombination with holes trapped by the deep energy level defects, thereby eliminating the influence of the deep energy level charged defects. On the other hand, under a strong electric field, holes trapped at the shallow energy level will tunnel back to the quantum well layer and flow out from the P-type source and drain electrodes, initializing the deep and shallow energy level hole defects to a certain extent.

[0088] Figure 10 A flow chart of preparing a heterojunction field effect transistor device structure according to some embodiments of the present invention is shown.

[0089] As another aspect of the present invention, a method for preparing the above-mentioned heterojunction field effect transistor device structure is provided. Figure 10 As shown, the preparation method includes operations S100 to S106.

[0090] In operation S100 , a heterogeneous crystal wafer is grown on a substrate using a chemical vapor deposition technique.

[0091] In operation S101 , a reactive ion etching technique is used to mesa-etch the heterogeneous wafer to form four alignment mark regions.

[0092] In operation S102, using a photoresist as a mask, performing P-type implantation in two alignment mark regions and activating them by rapid thermal annealing to form P-type implantation regions; performing N-type implantation in the other two alignment mark regions and activating them by rapid thermal annealing to form N-type implantation regions;

[0093] In operation S103 , a gate oxide layer is grown using an atomic layer deposition technique.

[0094] In operation S104 , a gate electrode is deposited using an electron beam evaporation technique.

[0095] In operation S105 , two P-type windows and two N-type windows are formed by etching the gate oxide layer above the ion implanted local area.

[0096] In operation S106 , a P-type ohmic contact electrode is deposited in the two P-type windows, and an N-type ohmic contact electrode is deposited in the two N-type windows.

[0097] In an illustrative embodiment, a method for preparing any of the above-mentioned field effect transistors is provided, comprising calculating the stacking parameters of the heterojunction field effect transistor device structure according to requirements, designing various process parameters and drawing the corresponding process layout, including the following steps.

[0098] The design of heterogeneous crystal stacks, for example, requires a second barrier layer with a certain thickness (or the construction of other electronically high barrier stacks) to prevent surface electrons from tunneling back into the buried channels of the quantum well layer. Furthermore, to prevent lattice mismatch, the quantum well layer should also be within the critical lattice mismatch thickness (in the Z direction).

[0099] The design of micro-nano processing parameters includes the etching depth of the mesa, the dose and activation conditions of ion implantation, the growth parameters and film thickness of the gate oxide layer, and the subsequent preparation parameters of the P-type source and drain electrodes and the N-type source and drain electrodes, etc.

[0100] Patterns used for functional testing, including unipolar heterojunction field-effect transistor device structures, bipolar heterojunction field-effect transistor device structures, and corresponding Hall bar field-effect transistors, are used to detect the impact of initialization and threshold control on their device performance, etc.

[0101] Using micro-nano processing technology, a heterojunction field effect transistor device structure with both P-type source and drain electrodes and N-type source and drain electrodes is prepared on a heterogeneous crystal wafer.

[0102] According to an embodiment of the present invention, micro-nano processing technology in semiconductor processing may include one or more combinations of technologies such as laser direct writing, reactive ion etching, ion implantation, rapid thermal processing, atomic layer deposition, electron beam evaporation, and wet etching.

[0103] In an illustrative embodiment, an enhancement mode heterojunction field effect transistor device structure is taken as an example for description.

[0104] Heterogeneous crystal circles , the second barrier layer is , the cap layer is Si (also called Si cap), the thickness of the Ge quantum well layer is 16nm, the thickness of the second barrier layer is 100nm, and the surface Si cap layer is 2nm

[0105] The heterogeneous wafer is grown using chemical vapor deposition. After the wafer is obtained, a reactive ion etcher (RIE) is used to etch the mesa to a depth of 120nm. This process not only defines the active area but also creates four alignment marks for subsequent alignment. Ion implantation is then performed on the heterogeneous wafer in the alignment mark areas.

[0106] Using a multilayer photoresist mask, a P-type implant (e.g., boron) is performed in two alignment mark regions at an implant energy of 19 keV. An N-type implant (e.g., phosphorus) is performed in the other two alignment mark regions at an implant energy of 25 keV. After cleaning, a rapid thermal annealing process is used to activate the implanted ions. It is understood that the implant energy can be adjusted according to actual needs.

[0107] Atomic layer deposition (ALD) is used to grow a 30nm thick aluminum oxide layer as the gate oxide layer to prevent leakage of the heterogeneous crystal circle.

[0108] After the above processes are completed, a layer of titanium / gold with a thickness of 10 / 70 nm is deposited as the gate material using a lift-off process and an electron beam evaporation process.

[0109] A wet etching process is used to etch the aluminum oxide above the local ion implantation area, and the silicon oxide is rinsed with hydrofluoric acid to prepare P-type source and drain electrodes (for example, made of aluminum) and N-type source and drain electrodes (for example, made of titanium / gold), respectively.

[0110] The prepared heterojunction field-effect transistor device structure is cooled to an extremely low temperature (less than 10K), the P-type source and drain electrodes are connected to the external circuit, and a sufficiently negative gate voltage is applied to the gate voltage so that holes tunnel to the surface and are captured by energy level defects.

[0111] The preparation method provided in the embodiment of the present invention is compatible with the existing semiconductor industry, has a mature and simple process, and can efficiently and mass-produce field-effect transistors (FETs).

[0112] Furthermore, unless specifically described or required to occur sequentially, the order of the steps is not limited to the order listed above and may be varied or rearranged based on desired design requirements. Furthermore, the above embodiments may be mixed and matched with each other or with other embodiments based on design and reliability considerations. That is, the technical features of different embodiments may be freely combined to form more embodiments.

[0113] The above specific embodiments further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A heterojunction field effect transistor device structure, characterized in that: include: substrate; A heterogeneous crystal circle is arranged on the substrate, wherein the heterogeneous crystal circle includes a quantum well layer, and a buried channel is formed in the quantum well layer; A gate oxide layer is disposed on the heterogeneous crystal circle; A gate, disposed on the gate oxide layer; A P-type source-drain electrode is spaced apart from the gate, extends through the gate oxide layer to the quantum well layer, and forms a P-type field effect transistor with the quantum well layer and the gate; An N-type source-drain electrode is spaced apart from the gate and the P-type source-drain electrode, extends through the gate oxide layer to the quantum well layer, and forms an N-type field effect transistor with the quantum well layer and the gate; Wherein, the direction of the electric field applied to the gate is changed so that the energy level defects in the forbidden band of the interface between the heterogeneous crystal circle and the gate oxide layer store or recombine charge carriers to change the charge amount of the energy level defects, thereby controlling the threshold voltage of the N-type field effect transistor and the P-type field effect transistor, wherein the charge carriers include electrons or holes; The heterogeneous crystal circle also includes: A first barrier layer is disposed on the substrate, wherein the quantum well layer is disposed on the first barrier layer; A second barrier layer, disposed on the quantum well layer, adapted to cooperate with the first barrier layer to confine electrons or holes in the quantum well layer; A cap layer, disposed on the second barrier layer; Wherein, the interface is located between the cap layer and the gate oxide layer.

2. The heterojunction field effect transistor device structure according to claim 1, characterized in that: Under low temperature conditions of less than 10K, the electric field strength applied to the gate exceeds the Fowler-Nordheim critical tunneling field strength of electrons, so that the charge carriers tunnel into the energy level defects under the action of the electric field to form fixed charges.

3. The heterojunction field effect transistor device structure according to claim 2, characterized in that: The P-type source-drain electrode is connected to an external circuit, and a negative gate voltage is applied to the gate. Holes introduced into the buried channel through the P-type source-drain electrode tunnel to the interface and are trapped in the energy level defects to form positive fixed charges, thereby increasing the threshold voltage of the P-type field effect transistor and reducing the threshold voltage of the N-type field effect transistor.

4. The heterojunction field effect transistor device structure according to claim 3, characterized in that: Also includes: The N-type source-drain electrode is connected to an external circuit, a positive gate voltage is applied to the gate, and the electrons introduced from the N-type source-drain electrode and located in the buried channel are tunneled to the interface under the induction of the electric field provided by the positive gate voltage, and relax to the shallow energy level defects located at the edge of the bandgap and the deep energy level defects located at the center of the bandgap; The holes captured by the shallow energy level defects are re-injected into the buried channel under the induction of the electric field and flow out through the P-type source and drain electrodes, and the holes captured by the deep energy level defects are recombined with the injected electrons to return to the initial state.

5. The heterojunction field effect transistor device structure according to claim 2, characterized in that: The N-type source-drain electrode is connected to an external circuit, a positive gate voltage is applied to the gate, and electrons introduced into the buried channel through the N-type source-drain electrode tunnel to the interface and relax in the energy level defects. They are captured by the energy level defects to form negative fixed charges, thereby increasing the threshold voltage of the N-type field effect transistor and reducing the threshold voltage of the P-type field effect transistor.

6. The heterojunction field effect transistor device structure according to claim 2, characterized in that: The method also includes controlling the intensity and the maintenance time of the electric field to control the number of charge carriers captured in the energy level defects to adjust the threshold voltage.

7. The heterojunction field effect transistor device structure according to claim 1, characterized in that: The quantum well layer maintains compressive strain, the second barrier layer relaxes, the cap layer and the second barrier layer form a tensile strain state, and a heterojunction straddling energy band is formed at the interface of the first barrier layer / quantum well layer / second barrier layer, so that the buried channel can trap holes or electrons.

8. The heterojunction field effect transistor device structure according to any one of claims 1 to 7, characterized in that: The N-type source-drain electrode comprises: Two N-type implantation regions are spaced apart and extend downward from the surface of the heterogeneous crystal circle to the quantum well layer; Two N-type ohmic contact electrodes are respectively spaced apart from the gate and extend through the gate oxide layer to the two N-type implantation regions to be connected to an external circuit; The P-type source-drain electrode comprises: Two spaced-apart P-type implantation regions extending downward from the surface of the heterogeneous crystal circle to the quantum well layer; Two P-type ohmic contact electrodes are respectively spaced apart from the gate and extend through the gate oxide layer to the two P-type injection regions to be connected to an external circuit.

9. A method for preparing a heterojunction field effect transistor device structure as claimed in any one of claims 1 to 8, characterized in that: include: Using chemical vapor deposition technology to grow heterogeneous crystal circles on a substrate; Using reactive ion etching technology to perform mesa etching on the heterogeneous crystal circle to form four alignment mark areas; Using the photoresist as a mask, performing P-type implantation in two alignment mark regions, and activating by rapid thermal annealing to form P-type implantation regions; performing N-type implantation in the other two alignment mark regions, and activating by rapid thermal annealing to form N-type implantation regions; Growing the gate oxide layer using atomic layer deposition technology; The gate electrode is deposited using electron beam evaporation technology; Two P-type windows and two N-type windows are formed by etching the gate oxide layer above the ion implanted local area; A P-type ohmic contact electrode is deposited in the two P-type windows, and an N-type ohmic contact electrode is deposited in the two N-type windows.

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