A GaN Schottky barrier diode with a polarization terminal structure and a preparation method thereof

Abstract

The application discloses a GaN Schottky barrier diode with a polarization terminal structure and a preparation method thereof, and relates to the technical field of semiconductors. + A GaN layer, an n ‑ GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer; a layer stack composed of the i-GaN layer and the p-GaN layer generates a two-dimensional hole gas through polarization with the AlGaN layer; a normal projection of the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer is located in a first region of a normal projection of the n ‑ GaN drift layer; a normal projection of the n ‑ GaN drift layer includes the first region and a second region; an anode is located on the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer and extends into the n ‑ GaN drift layer; a normal projection of the anode overlaps with the first region and the second region of the normal projection of the n ‑ GaN drift layer; a cathode is located on the n + GaN layer and is spaced apart from the n ‑ GaN drift layer. The application can reduce reverse leakage current and improve device voltage resistance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a GaN Schottky barrier diode with a polarization terminal structure and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) is a typical representative of the third generation of semiconductor materials, has many advantages such as a large band gap, a high breakdown field strength, a high electron mobility, and can be used in harsh environments such as high frequency, high temperature and radiation, can greatly meet the demand of power electronic devices in the fields of 5G communication, electric vehicles, aerospace and the like, and has a wide application prospect.

[0003] The GaN Schottky barrier diode (SBD) has advantages such as low power consumption, super high speed and short reverse recovery time, is suitable for high-frequency rectification in a medium-low voltage and large current output occasion, and is widely used in the fields of consumer electronics and automotive electronics.

[0004] Although the GaN SBD has many advantages at present, the Schottky barrier height is low, there is a mirror force effect, the peak value of the electric field under reverse bias is close to the anode metal-semiconductor contact interface, the surface state and the interface state affect the quality of the Schottky junction, the leakage current of the GaN SBD under reverse bias is large, and the device is broken down in advance. In the prior art, the breakdown voltage of the GaN SBD is usually improved by using a field plate or a junction terminal. The traditional junction terminal adopts ion implantation of fluorine ions, nitrogen ions or magnesium ions on the edge of the anode metal to form a high resistance, so as to reduce the electric field strength of the anode metal-semiconductor contact interface and improve the breakdown voltage of the GaN SBD. However, the process of forming the junction terminal by using ion implantation is too complex, the cost is high, and the stability is poor. Therefore, it is urgent to provide a GaN Schottky barrier diode to improve the defects of the prior art, such as a complex process, high cost and poor stability. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides a GaN Schottky barrier diode with a polarization terminal structure and a preparation method thereof. The technical problem to be solved by the application is solved by the following technical scheme:

[0006] In a first aspect, the application provides a GaN Schottky barrier diode with a polarization terminal structure, comprising:

[0007] a substrate, a buffer layer, an n + GaN layer, an n - GaN drift layer, AlGaN layer, i-GaN layer and p-GaN layer; wherein,

[0008] The layer stack composed of the i-GaN layer and the p-GaN layer generates a two-dimensional hole gas along a direction perpendicular to the substrate, and a normal projection of the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers is located in the first region of the normal projection of the GaN drift layer - The normal projection of the GaN drift layer includes the first region and the second region, and the first region is arranged around the second region - The normal projection of the GaN drift layer includes the first region and the second region, and the first region is arranged around the second region

[0009] An anode is located on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extends into the GaN drift layer - The normal projection of the anode is located in the first region of the normal projection of the GaN drift layer - The first region and the second region of the normal projection of the GaN drift layer are overlapped

[0010] A cathode is located on the n + GaN layer and is spaced apart from the n - GaN drift layer

[0011] A passivation layer covers surfaces of the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - GaN drift layer and the cathode exposed, and the passivation layer includes a first opening and a second opening, the first opening exposes the anode, and the second opening exposes the cathode

[0012] In a second aspect, the present application further provides a preparation method of a GaN Schottky barrier diode with a polarization terminal structure, comprising:

[0013] Providing a substrate

[0014] Epitaxially growing a buffer layer on the substrate, epitaxially growing an n + GaN layer on the buffer layer, epitaxially growing an n + GaN layer on the n - GaN layer, epitaxially growing an n - GaN drift layer, epitaxially growing an AlGaN layer on the n

[0015] Defining a diode isolation region by photolithography, and etching the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - GaN drift layer by an inductive coupling plasma etching process to form the isolation region

[0016] Defining a cathode region on the isolation region by photolithography, and sequentially depositing titanium, aluminum, nickel and gold on the cathode region by an electron beam evaporation process to form the cathode, and making the cathode and the n +The GaN layer forms an ohmic contact;

[0017] An anode etching region is defined on the p-GaN layer by photolithography, and the p-GaN layer, the i-GaN layer and the AlGaN layer are etched by an inductively coupled plasma etching process to obtain the anode etching region.

[0018] An anode region is defined on the anode etching region by photolithography, and nickel and gold are deposited on the anode region by an electron beam evaporation process to form an anode. - The GaN drift layer forms a Schottky contact, and the anode forms an ohmic contact with the p-GaN layer; wherein the anode region is partially located on the n - The GaN drift layer and partially on the p-GaN layer.

[0019] The anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - A passivation layer is epitaxially grown on the GaN drift layer and the surface exposed by the cathode.

[0020] A first opening region is defined on the anode by photolithography, a second opening region is defined on the cathode by photolithography, the passivation layer of the first opening region is etched by a reactive ion etching process to form a first opening, and the passivation layer of the second opening region is etched by a reactive ion etching process to form a second opening.

[0021] The GaN Schottky barrier diode with a polarization terminal structure and the preparation method thereof have the following beneficial effects:

[0022] The GaN Schottky barrier diode with a polarization terminal structure and the preparation method thereof have the following beneficial effects: + The GaN layer, the n - The GaN drift layer, the AlGaN layer, the i-GaN layer and the p-GaN layer, and the cathode, the anode and the passivation layer are provided, wherein the layered structure composed of the i-GaN layer and the p-GaN layer and the AlGaN layer polarize to generate a two-dimensional hole gas to form a terminal, or in other words, the two-dimensional hole gas generated by the polarization of the p-GaN / i-GaN and the AlGaN is used as a terminal, and the p-GaN / i-GaN / AlGaN structure can generate a two-dimensional hole gas with a high concentration at the i-GaN / AlGaN interface; so that the two-dimensional hole gas at the i-GaN / AlGaN interface and the AlGaN / n -The two-dimensional electron gas generated by polarization at the interface of the GaN drift layer forms a depletion region, which improves the electric field distribution at the anode metal edge and reduces the electric field peak at the anode metal edge, reduces the reverse leakage current, and improves the device withstand voltage; compared with the traditional high-resistance junction terminal structure based on ion implantation, the application avoids the complex ion implantation process, simplifies the process, and improves the reliability of the device.

[0023] The application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 is a structural schematic diagram of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application;

[0025] Figure 2 is a top view of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application;

[0026] Figure 3 is a flowchart of a preparation method of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application;

[0027] FIG. 4 is a schematic diagram of a preparation method of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application;

[0028] FIG. 5 is another flowchart of a preparation method of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application. DETAILED DESCRIPTION

[0029] The application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0030] Please refer to Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application, Figure 2 is a top view of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the application, the GaN Schottky barrier diode with a polarization terminal structure provided by the application comprises: a substrate, a buffer layer, an n + -GaN layer, an n - -GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer which are sequentially stacked;

[0031] The layer stack structure composed of the i-GaN layer and the p-GaN layer and the AlGaN layer polarize to generate a two-dimensional hole gas along a direction perpendicular to the substrate, and a normal projection of the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers is located in the first region of the normal projection of the GaN drift layer - The normal projection of the GaN drift layer includes the first region and the second region, and the first region is arranged around the second region - The normal projection of the GaN drift layer includes the first region and the second region, and the first region is arranged around the second region

[0032] The anode is located on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extends into the GaN drift layer - The anode is located on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extends into the GaN drift layer - The first region and the second region of the normal projection of the GaN drift layer both overlap

[0033] The cathode is located on the n + The cathode is located on the n - The cathode is located on the n

[0034] The passivation layer covers surfaces of the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the GaN drift layer and the cathode exposed, and the passivation layer includes a first opening and a second opening, the first opening exposes the anode, and the second opening exposes the cathode - The passivation layer covers surfaces of the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the GaN drift layer and the cathode exposed, and the passivation layer includes a first opening and a second opening, the first opening exposes the anode, and the second opening exposes the cathode

[0035] Specifically, the GaN Schottky barrier diode with a polarization terminal structure provided in the embodiment is sequentially arranged in layers from bottom to top as a substrate, a buffer layer, an n + -GaN layer, an n - -GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer, and an anode, a cathode and a passivation layer are arranged, wherein the layer stack structure composed of the i-GaN layer and the p-GaN layer and the AlGaN layer polarize to generate a two-dimensional hole gas, form a terminal, and can also be understood as that the two-dimensional hole gas generated by polarization of the p-GaN / i-GaN and the AlGaN is used as the terminal, and the p-GaN / i-GaN / AlGaN structure is used to generate a two-dimensional hole gas with a higher concentration at the i-GaN / AlGaN interface; so that the two-dimensional hole gas at the i-GaN / AlGaN interface and the two-dimensional electron gas polarized at the AlGaN / n - -GaN drift layer interface form a depletion region, which improves the electric field distribution and reduces the electric field peak value of the anode metal edge, reduces the reverse leakage current and improves the device withstand voltage; compared with the traditional high-resistance junction terminal structure based on ion implantation, the present application avoids the complex ion implantation process, simplifies the process and improves the reliability of the device.

[0036] In an alternative embodiment of the present application, the thickness of the i-GaN layer and the p-GaN layer is greater than the thickness of the AlGaN layer in the direction perpendicular to the substrate.

[0037] In an alternative embodiment of the present application, the thickness of the AlGaN layer is 15-30 nm and the Al component ratio is 0.15-0.4 in the direction perpendicular to the substrate.

[0038] Specifically, in the present embodiment, the thickness of the AlGaN layer can be 18 nm, 20 nm, 25 nm or 28 nm, and the Al component ratio can be 0.2, 0.25, 0.3 or 0.35, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0039] In an alternative embodiment of the present application, the thickness of the i-GaN layer is 20-50 nm in the direction perpendicular to the substrate.

[0040] Specifically, in the present embodiment, the thickness of the i-GaN layer can be 25 nm, 30 nm, 33 nm, 38 nm, 42 nm or 48 nm, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0041] In an alternative embodiment of the present application, the thickness of the p-GaN layer is 50-100 nm and the doping concentration of the p-GaN layer is 1×10 19 cm -3 -5×10 19 cm -3 .

[0042] Specifically, in the present embodiment, the thickness of the p-GaN layer can be 50 nm, 60 nm, 70 nm, 80 nm or 90 nm, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0043] In an alternative embodiment of the present application, the Mg doping concentration of the p-GaN layer is 1×10 19 cm -3 -5×10 19 cm -3 , which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0044] In an alternative embodiment of the present application, the substrate comprises any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

[0045] Specifically, in the embodiment, the thickness of the sapphire substrate is 300-500 μm, the thickness of the silicon substrate is 600-1000 μm, the thickness of the silicon carbide substrate is 300-500 μm, and the thickness of the gallium nitride substrate is 300-1000 μm, which are not limited in the embodiment and can be determined according to actual application.

[0046] In an optional embodiment of the application, the buffer layer is made of GaN material or graded AlGaN material or AlGaN / GaN superlattice material, and the thickness of the buffer layer is 500 nm-3 μm in the direction perpendicular to the substrate, which is not limited in the embodiment and can be determined according to actual application.

[0047] In an optional embodiment of the application, the n + The Si doping concentration of the GaN layer is 1×10 19 cm -3 -5×10 19 cm -3 The thickness of the n + GaN layer is 1 μm-3 μm in the direction perpendicular to the substrate, which is not limited in the embodiment and can be determined according to actual application.

[0048] In an optional embodiment of the application, the n - The Si doping concentration of the GaN drift layer is 1×10 16 cm -3 -5×10 16 cm -3 The thickness of the n - GaN drift layer is 1 μm-10 μm in the direction perpendicular to the substrate, which is not limited in the embodiment and can be determined according to actual application.

[0049] In an optional embodiment of the application, the thickness of the anode is 100-300 nm in the direction perpendicular to the substrate, and the anode is a nickel and gold laminated metal.

[0050] Specifically, in the embodiment, the thickness of the anode can be 150 nm, 180 nm, 200 nm or 280 nm, which is not limited in the embodiment and can be determined according to actual application.

[0051] In an optional embodiment of the application, the anode is in contact with the p-GaN layer to form an ohmic contact, and the anode is in contact with the n - GaN drift layer to form a Schottky contact.

[0052] In an optional embodiment of the present invention, the thickness of the cathode is 200–500 nm along a direction perpendicular to the substrate, and the cathode material includes titanium, aluminum, nickel, and gold. + -GaN layer contact, forming an ohmic contact.

[0053] Specifically, in this embodiment, the thickness of the cathode is 250nm, 300nm, 350nm, 400nm and 450nm. This embodiment does not make a specific limitation, and it can be determined according to the actual application.

[0054] In an optional embodiment of the present invention, the thickness of the passivation layer is 200-1000 nm along the direction perpendicular to the substrate, and the material of the passivation layer includes silicon nitride.

[0055] Specifically, in this embodiment, the thickness of the passivation layer can be 200nm, 300nm, 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm. This embodiment does not impose a specific limitation and can be determined according to the actual application.

[0056] Based on the same inventive concept, please refer to Figure 3 And Figure 4, Figure 3 Figure 4 is a flowchart of a method for fabricating a GaN Schottky barrier diode with a polarized termination structure according to an embodiment of the present invention. Figure 5 is a schematic diagram of a method for fabricating a GaN Schottky barrier diode with a polarized termination structure according to an embodiment of the present invention. The present invention also provides a method for fabricating a GaN Schottky barrier diode with a polarized termination structure, used to fabricate the diode provided in the above embodiments. The structure of the diode is described above and will not be repeated here. The fabrication method includes:

[0057] S101, Provide a substrate.

[0058] Specifically, in this embodiment, the substrate can be any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate.

[0059] S102. Epitaxially grow a buffer layer on the substrate, and epitaxially grow n on the buffer layer. + -GaN layer, in n + -Epithelial growth of n on GaN layer - -GaN drift layer, in n - An AlGaN layer is grown on the GaN drift layer, an i-GaN layer is epitaxially grown on the AlGaN layer, and a p-GaN layer is epitaxially grown on the i-GaN layer.

[0060] Specifically, the preparation of p-GaN / i-GaN / AlGaN / n - -GaN / n +An epitaxial wafer of GaN / buffer layer / substrate structure, using metal organic chemical vapor deposition technology, epitaxially growing GaN material or graded AlGaN material or AlGaN / GaN superlattice material, n + A GaN layer, n - A GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer, obtaining a p-GaN / GaN / AlGaN / n - A GaN / n + An epitaxial wafer of GaN / buffer layer / substrate structure.

[0061] S103, using photolithography to define a diode isolation region, and using inductive coupled plasma etching technology to etch the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - A GaN drift layer, forming an isolation region.

[0062] Specifically, in this embodiment, photolithography is used to define a diode isolation region, and inductive coupled plasma etching technology is used to etch the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - A GaN drift layer, forming a diode isolation region, and then using an organic solution to clean off the photoresist.

[0063] S104, using photolithography to define a cathode region on the isolation region, using electron beam evaporation technology to sequentially deposit titanium, aluminum, nickel and gold on the cathode region to form a cathode, and using rapid thermal annealing to make the cathode form ohmic contact with the n + A GaN layer forms ohmic contact.

[0064] Specifically, in this embodiment, photolithography is used to define a cathode electrode region, a BOE solution is used to clean the sample, and the anode region oxide is removed; electron beam evaporation technology is used to sequentially deposit 20-30nm thick titanium, 120-140nm thick aluminum, 40-55nm thick nickel and 40-55nm thick gold on the n + GaN, and rapid thermal annealing at 850°C in a nitrogen atmosphere for 30s, so that the cathode forms ohmic contact with the n + GaN.

[0065] S105, using photolithography to define an anode etching region on the p-GaN layer, and using inductive coupled plasma etching technology to etch the p-GaN layer, the i-GaN layer and the AlGaN layer to obtain an anode etching region.

[0066] Specifically, in this embodiment, photolithography is used to define an anode etching region, inductive coupled plasma etching technology is used to etch the p-GaN layer, the i-GaN layer and the AlGaN layer to obtain an anode etching region, and then an organic solution is used to clean off the photoresist.

[0067] S106, define anode region by lithography in the anode etching region, deposit nickel and gold in the anode region by electron beam evaporation process to form anode, and make the anode and n - -GaN drift layer forms Schottky contact, and the anode and p-GaN layer form ohmic contact; wherein the anode region is partially located on the n - -GaN drift layer and partially on the p-GaN layer.

[0068] Specifically, in the embodiment, the anode electrode region is defined by lithography, the sample is cleaned by BOE solution to remove the oxide in the anode region, and the n - -GaN drift layer and p-GaN layer are sequentially deposited with 20-50nm thick nickel and 200-250nm thick gold by electron beam evaporation process, so that the anode and n - -GaN layer form Schottky contact; and the anode and n - -GaN layer form Schottky contact, and the p-GaN layer form ohmic contact.

[0069] S107, epitaxially grow a passivation layer on the anode, p-GaN layer, i-GaN layer, AlGaN layer, n - -GaN drift layer and the surface exposed by the cathode.

[0070] Specifically, the passivation layer of the GaN SBD is deposited by plasma enhanced chemical vapor deposition technology with 200nm-1000nm silicon nitride.

[0071] S108, define a first opening region on the anode by lithography, define a second opening region on the cathode by lithography, etch the passivation layer of the first opening region by reactive ion etching process to form a first opening, and etch the passivation layer of the second opening region by reactive ion etching process to form a second opening.

[0072] Specifically, in the embodiment, the opening region is defined by lithography, and the silicon nitride passivation layer of the opening region is etched by dry etching process, i.e. using fluorine-based gas to etch the silicon nitride passivation layer of the opening region by reactive ion etching (RIE) equipment.

[0073] In an alternative embodiment of the present application, please continue to refer to FIG. 4, the preparation of the polar terminal structure GaN Schottky barrier diode is realized by the following steps, specifically:

[0074] S101, prepare a p-GaN / i-GaN / AlGaN / n - -GaN / n + -GaN / Buffer layer / substrate structure epitaxial wafer.

[0075] Specifically, in this embodiment, metal-organic chemical vapor deposition (MOCVD) is used to sequentially epitaxially grow a 2 μm thick gradient AlGaN buffer layer and a Si doping concentration of 5 × 10⁻⁶ on a silicon substrate. 19 cm -3 and n with a thickness of 1μm + -GaN layer, Si doping concentration is 1×10 16 cm -3 and n with a thickness of 4μm - -GaN drift layer, Al composition of 0.3, 25nm thick AlGaN layer, 20nm thick i-GaN layer, Mg doping concentration of 1×10 19 cm -3 And with a thickness of 50 nm, p-GaN / i-GaN / AlGaN / n are obtained. - -GaN / n + - An epitaxial wafer with a GaN / buffer layer / substrate structure is shown in Figure 4(a).

[0076] S102, Countertop isolation.

[0077] Specifically, in this embodiment, the mesa isolation pattern is defined using photolithography, and then the p-GaN layer, i-GaN layer, AlGaN layer, and n-GaN layer are etched using inductively coupled plasma etching (ICP-C) with a chlorine-based etching method. - -GaN drift layer, with an etching depth greater than that of p-GaN layer, i-GaN layer, AlGaN layer and n - -The sum of the GaN drift layer thicknesses, etched to n + -GaN forms the device isolation region, as shown in Figure 4(b).

[0078] S103, Prepare the cathode electrode.

[0079] The cathode region was defined using photolithography, and the sample was cleaned with BOE solution to remove oxides from the cathode region. + - Titanium, aluminum, nickel, and gold metals with thicknesses of 20 nm, 120 nm, 40 nm, and 50 nm were deposited on top of the GaN layer using electron beam evaporation. Then, the layers were rapidly annealed for 30 seconds at 850 °C in a nitrogen atmosphere to integrate the titanium, aluminum, nickel, and gold metals with the nitrogen. + Ohmic contacts are formed between GaN elements, as shown in Figure 4(c).

[0080] S104, Etching anode area.

[0081] The p-GaN layer, the i-GaN layer and the AlGaN layer are etched by using a photoetching method to define the anode region and then using an inductively coupled plasma etching process to perform chlorine-based etching, the etching depth being greater than the sum of the thicknesses of the p-GaN layer, the i-GaN layer and the AlGaN layer, and the n - -GaN, to obtain the anode region, and then using an organic solvent to remove the photoresist, as shown in Fig. 4(d).

[0082] S105, preparing an anode electrode.

[0083] The anode electrode region is defined by using a photoetching method, the sample is cleaned by using a BOE solution to remove the oxide in the anode region. The n - -GaN drift layer and the p-GaN layer, 20 nm-thick nickel metal and 200 nm-thick gold metal are deposited on the n - -GaN region by using an electron beam evaporation method as an anode metal, and then the anode metal is annealed in an oxygen atmosphere at a temperature of 500 ℃ for 5 minutes, so that the anode metal forms a Schottky contact with the n

[0084] S106, preparing a passivation layer.

[0085] Specifically, in this embodiment, a 1000 nm-thick silicon nitride is grown on the sample in S105 by using a plasma-enhanced chemical vapor deposition technology as the passivation layer of the GaN SBD, as shown in Fig. 4(g).

[0086] S107, etching the passivation layer and opening a hole.

[0087] Specifically, in this embodiment, the interconnection opening region is defined by using a photoetching method, and the silicon nitride passivation layer in the opening region is etched by using a reactive ion etching (RIE) device with fluorine-based gas, the etching depth being slightly greater than 1000 nm, as shown in Fig. 4(g).

[0088] In an alternative embodiment of the present application, please refer to Fig. 5, which is another flow chart of a preparation method of a GaN Schottky barrier diode with a polarization terminal structure provided by an embodiment of the present application, the preparation of the GaN Schottky barrier diode with the polarization terminal structure is realized through the following steps, specifically:

[0089] S101, preparing an epitaxial wafer with a p-GaN / i-GaN / AlGaN / n--GaN / n+-GaN / buffer layer / substrate structure.

[0090] A GaN buffer layer with a thickness of 1 μm and a Si doping concentration of 5×10 19 cm -3and n-GaN with thickness of 1.5 μm + - GaN layer, Si doping concentration of 1 x 1018cm 16 - cm -3 and n-GaN with thickness of 10 μm - - GaN drift layer, Al composition of 0.4 and AlGaN layer with thickness of 30 nm, i-GaN layer with thickness of 20 nm, Mg doping concentration of 1 x 1018cm 19 - cm -3 and p-GaN with thickness of 50 nm, resulting in p-GaN / i-GaN / AlGaN / n - - GaN / n + - GaN / buffer layer / substrate structure, as shown in Fig. 5(a).

[0091] S102, preparing a cathode electrode.

[0092] The sample is cleaned with acetone, isopropyl alcohol, deionized water and BOE solution in sequence to remove contamination and oxide layer on the surface of the sample. Aluminum metal with thickness of 200 nm is deposited on the back of the n-type gallium nitride substrate by magnetron sputtering to form a cathode electrode, as shown in Fig. 5(b).

[0093] S103, mesa isolation.

[0094] The mesa isolation pattern is defined by photolithography, and then the p-GaN layer, i-GaN layer, AlGaN layer and n - - GaN drift layer are etched by chlorine-based etching of inductively coupled plasma etching process to a depth greater than the sum of the thicknesses of the p-GaN layer, i-GaN layer and AlGaN layer, and etched to the n + - GaN, forming a device isolation region, as shown in Fig. 5(c).

[0095] S104, etching an anode region.

[0096] The anode region is defined by photolithography, and then the p-GaN layer, i-GaN layer and AlGaN layer are etched by chlorine-based etching of inductively coupled plasma etching process to a depth greater than the sum of the thicknesses of the p-GaN layer, i-GaN layer and AlGaN layer, and etched to the n - - GaN, obtaining an anode region, and then the photoresist is removed by using an organic solvent, as shown in Fig. 5(d).

[0097] S105, preparing an anode electrode.

[0098] The anode electrode region is defined by photolithography, and the sample is cleaned by using BOE solution to remove oxide in the anode region. An anode electrode is prepared by electron beam evaporation process on the n -- On the GaN drift layer and the p-GaN layer, 20 nm thick nickel metal and 200 nm thick gold metal are deposited as anode metal by electron beam evaporation, and then annealed in an oxygen atmosphere at a temperature of 500°C for 5 minutes to make the anode metal and the n - - The GaN region forms a Schottky contact, and the p-GaN region forms an ohmic contact, as shown in Fig. 5(e).

[0099] S106, a passivation layer is prepared.

[0100] A 1000 nm thick silicon nitride layer is grown on the sample of step 5 as a passivation layer of the GaN SBD by plasma enhanced chemical vapor deposition, as shown in Fig. 5(f).

[0101] S107, etching and opening the passivation layer.

[0102] The silicon nitride passivation layer in the interconnection opening region is etched by a reactive ion etching (RIE) device using fluorine-based gas, and the etching depth is slightly greater than 1000 nm, as shown in Fig. 5(g).

[0103] It should be noted that the relational terms herein such as first and second, and the like are used only to differentiate one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Also, the terms "include", "contain" or any other variants are intended to cover non-exclusive inclusion, so that the article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed. Without more limitations, the element defined by the statement "including a" does not exclude the presence of additional identical elements in the article or device including the element. "Connected" or "connected" and the like are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0104] In the description of the specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In the specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in the specification.

[0105] The above is a further detailed description of the present application in combination with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the protection scope of the present application.

Claims

1. A GaN Schottky barrier diode of a polarization terminal structure, characterized by, Comprising: The substrate, the buffer layer, the n + -GaN layer, the n - -GaN drift layer, AlGaN layer, i-GaN layer and p-GaN layer; wherein, The laminated structure of the i-GaN layer and the p-GaN layer and the AlGaN layer polarize to generate a two-dimensional hole gas, and the orthographic projection of the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers in the direction perpendicular to the substrate is located in the n - The orthographic projection of the GaN drift layer includes a first region and a second region, and the first region is arranged around the second region. - The orthographic projection of the GaN drift layer includes a first region and a second region, and the first region is arranged around the second region. an anode located on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extending to the n - - a first region and a second region of the n - - the first region and the second region of the n a cathode, located on the n + - on the GaN layer and in contact with the n - - GaN drift layer is arranged in between; a passivation layer covering the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - - a GaN drift layer and a surface of the cathode exposed, the passivation layer comprising a first opening exposing the anode and a second opening exposing the cathode.

2. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, characterized in that, In a direction perpendicular to the substrate, thicknesses of the i-GaN layer and the p-GaN layer are both greater than thickness of the AlGaN layer.

3. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein In a direction perpendicular to the substrate, thickness of the AlGaN layer is 15-30 nm, and Al component ratio is 0.15-0.

4.

4. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein In a direction perpendicular to the substrate, thickness of the i-GaN layer is 20-50 nm.

5. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein The thickness of the p-GaN layer is 50-100 nm in a direction perpendicular to the substrate, and the doping concentration of the p-GaN layer is 1 x 1018-5 x 1019cm-3. 19 cm -3 ~5×10 19 cm -3 .

6. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein The substrate comprises any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

7. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein In a direction perpendicular to the substrate, thickness of the anode is 100-300 nm, and the anode is a nickel and gold stacked metal.

8. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein The anode is in contact with the p-GaN layer forming an ohmic contact, the anode is in contact with the n - - GaN drift layer contact forming a Schottky contact.

9. The GaN Schottky barrier diode of a polarization terminal structure according to claim 1, wherein The thickness of the cathode in a direction perpendicular to the substrate is 200-500 nm, the material of the cathode includes titanium, aluminum, nickel and gold, the cathode is in contact with the n + - the GaN layer is contacted, forming an ohmic contact.

10. A method for fabricating a GaN Schottky barrier diode with a polarization-terminated structure, characterized in that, Comprising: Providing a substrate; A buffer layer is epitaxially grown on the substrate, and n is epitaxially grown on the buffer layer. + -GaN layer, in the n + -Epithelial growth of n on GaN layer - -GaN drift layer, in the n - An AlGaN layer is grown on a GaN drift layer, an i-GaN layer is epitaxially grown on the AlGaN layer, and a p-GaN layer is epitaxially grown on the i-GaN layer; the stacked structure composed of the i-GaN layer and the p-GaN layer polarizes with the AlGaN layer to generate a two-dimensional cavitation gas. The p-GaN layer, the i-GaN layer, the AlGaN layer and the n-GaN layer are etched by using an inductive coupling plasma etching process after the diode isolation region is defined by using photoetching. - - a GaN drift layer, forming an isolation region; A photoetching is used to define a cathode region on the isolation region, an electron beam evaporation process is used to deposit titanium, aluminum, nickel and gold on the cathode region in sequence to form a cathode, and a rapid thermal annealing is used to make the cathode and the n + - The GaN layer forms an ohmic contact. Defining an anode etching area on the p-GaN layer by photolithography, etching the p-GaN layer, the i-GaN layer and the AlGaN layer by an inductively coupled plasma etching process to obtain the anode etching area; The anode region is defined by etching the anode region using photolithography, and nickel and gold are deposited on the anode region by using an electron beam evaporation process to form an anode. The anode is made to form a Schottky contact with the n - -GaN drift layer, and the anode forms an ohmic contact with the p-GaN layer. The anode region is partially located on the n - -GaN drift layer and partially on the p-GaN layer. - a p-GaN layer on said anode, said i-GaN layer, said AlGaN layer, said n - - a passivation layer epitaxially grown on the surface of the GaN drift layer and exposed by said cathode Defining a first opening area on the anode by photolithography, defining a second opening area on the cathode by photolithography, etching the passivation layer of the first opening area by a reactive ion etching process to form a first opening, and etching the passivation layer of the second opening area by a reactive ion etching process to form a second opening.

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