A gallium nitride junction barrier schottky diode with a polarization structure and a preparation method thereof

Abstract

The application discloses a gallium nitride junction barrier Schottky diode with a polarization structure and a preparation method thereof, and relates to the technical field of semiconductors. + A GaN layer, an n ‑ GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer; a layer stack composed of the i-GaN layer and the p-GaN layer generates a two-dimensional hole gas through polarization with the AlGaN layer; an anode is located on the layer-stacked AlGaN layer, i-GaN layer and p-GaN layer and extends into an opening, and is in contact with the n ‑ GaN drift layer; a cathode is located on the GaN layer and is in contact with the n + GaN drift layer, and the cathode is spaced apart from the n ‑ GaN drift layer; a passivation layer covers exposed surfaces of the anode, p-GaN layer, i-GaN layer, AlGaN layer, n ‑ GaN drift layer and the cathode, and the passivation layer comprises a first opening and a second opening; the first opening exposes the anode, and the second opening exposes the cathode. The application can reduce reverse leakage current and improve device voltage resistance.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to a gallium nitride junction barrier Schottky diode with a polarization structure and a preparation method thereof. BACKGROUND

[0002] As a typical representative material of the third generation of semiconductors, GaN material has many advantages such as a large band gap, a high breakdown field strength, and a high electron mobility, so that GaN material and devices can work in harsh environments such as radiation and high temperature. Meanwhile, GaN can withstand a higher working voltage in a smaller size, thereby reducing the forward conduction resistance and improving the system power conversion efficiency. Therefore, GaN material and devices can greatly meet the demand of power electronic devices in the fields of power supply, electric vehicles, aerospace, etc., and have a wide application prospect.

[0003] GaN junction barrier Schottky (JBS) diodes are based on the structure of GaN Schottky Barrier Diodes (SBDs), and realize the alternate arrangement of n regions and p regions by selective doping in the anode of the device. When the device is reverse biased, a lateral depletion region is formed at the PN junction interface, effectively preventing the increase of the contact interface electric field strength, thereby reducing the leakage and improving the breakdown voltage of the device. When the device is forward biased, the current is conducted through the Schottky junction, and a low opening voltage similar to SBDs can be obtained. The JBS structure combines the advantages of low opening voltage, high switching speed of GaN Schottky diodes and high voltage resistance, low leakage of GaN PIN diodes, and has a wide application scenario in switching and rectification.

[0004] Although GaN JBS diodes have many advantages, there is still a problem that p-type GaN material is difficult to prepare. At present, p-type doping in traditional GaN JBS diodes is usually realized by p-type GaN secondary epitaxy or ion implantation. However, these technologies have their own problems: p-type GaN secondary epitaxy has problems such as poor interface quality and large leakage; ion implantation has great challenges in activating Mg in p-type GaN material, such as a high activation temperature generally above 1200℃, which leads to the decomposition of GaN surface, and a low Mg activation efficiency, so that the hole concentration obtained by activation is 2-3 orders of magnitude lower than the actual doping concentration. Therefore, it is of great significance to break through the above technical limitations by using a structure and method different from traditional GaN JBS diodes. SUMMARY

[0005] In order to solve the above problems in the prior art, the application provides a gallium nitride junction barrier Schottky diode with a polarization structure and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical scheme:

[0006] In a first aspect, the application provides a polar structure gallium nitride junction barrier Schottky diode, comprising: a substrate, a buffer layer, an n + -GaN layer, an n - -GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer, wherein,

[0007] The layer stack of the i-GaN layer and the p-GaN layer generates a two-dimensional hole gas by polarization with the AlGaN layer, the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer comprises a plurality of openings; along a direction perpendicular to the substrate, the orthographic projection of the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer comprises a plurality of first regions, and the orthographic projection of the openings is located between adjacent first regions;

[0008] an anode, located on the layer stack of the AlGaN layer, the i-GaN layer and the p-GaN layer and extending into the openings, and in contact with the n - -GaN layer;

[0009] a cathode, located on the n + -GaN layer and spaced apart from the n - -GaN drift layer;

[0010] a passivation layer, covering the surfaces of the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - -GaN drift layer and the cathode, the passivation layer comprising a first opening and a second opening, the first opening exposing the anode, and the second opening exposing the cathode.

[0011] In a second aspect, the application further provides a preparation method of a polar structure gallium nitride junction barrier Schottky diode, comprising:

[0012] providing a substrate;

[0013] epitaxially growing a buffer layer on the substrate, epitaxially growing an n + -GaN layer on the buffer layer, epitaxially growing an n + -GaN drift layer on the n - -GaN layer, epitaxially growing an n - -GaN drift layer, growing an AlGaN layer on the n - -GaN drift layer, epitaxially growing an i-GaN layer on the AlGaN layer, and epitaxially growing a p-GaN layer on the i-GaN layer;

[0014] defining a diode isolation region by photolithography, and etching the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - -GaN drift layer by an inductive coupled plasma etching process to form the isolation region;

[0015] The cathode region is defined on the isolation region by photolithography, Ti, Al, Ni and Au are deposited on the cathode region by electron beam evaporation process to form the cathode, and the cathode is connected to the n + The GaN layer forms an ohmic contact.

[0016] The anode etching region is defined on the p-GaN layer by photolithography, and the p-GaN layer, the i-GaN layer and the AlGaN layer are etched by an inductively coupled plasma etching process to obtain the anode etching region.

[0017] The anode region is defined on the anode etching region by photolithography, and Ni and Au are deposited on the anode region by electron beam evaporation process to form the anode, and the anode is connected to the n - The GaN drift layer forms a Schottky contact, and the anode forms an ohmic contact with the p-GaN layer; wherein the anode region is partially located on the n - GaN drift layer and partially on the p-GaN layer.

[0018] The passivation layer is epitaxially grown on the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - GaN drift layer and the exposed surface of the cathode.

[0019] The first opening region is defined on the anode by photolithography, the second opening region is defined on the cathode by photolithography, the passivation layer of the first opening region is etched by a reactive ion etching process to form the first opening, and the passivation layer of the second opening region is etched by a reactive ion etching process to form the second opening.

[0020] The beneficial effects of the present application are as follows:

[0021] The present application provides a polarized structure gallium nitride junction barrier Schottky diode and a preparation method thereof, which are sequentially stacked from bottom to top with a substrate, a buffer layer, an n + GaN layer, an n - GaN drift layer, AlGaN layer, i-GaN layer and p-GaN layer, and a cathode, anode and passivation layer, wherein the i-GaN layer and the p-GaN layer form a two-dimensional hole gas by polarization of the AlGaN layer, and the p-GaN / i-GaN / AlGaN structure can generate a two-dimensional hole gas with high concentration at the i-GaN / AlGaN interface; and the n region and the p region under the anode metal are alternately arranged, and when the device is reverse biased, the two-dimensional hole gas at the i-GaN / AlGaN interface under the anode metal and the AlGaN / n -The two-dimensional electron gas generated by polarization at the interface of the GaN drift layer forms alternatingly arranged depletion regions, thereby realizing a GaN JBS diode with high withstand voltage and low conduction. Compared with a conventional GaN JBS diode formed by secondary epitaxy, the diode provided by the application can effectively avoid the leakage problem caused by the PN junction interface defects of the complex secondary epitaxy process; compared with a conventional GaN JBS formed by ion implantation, the diode avoids problems such as decomposition of surface GaN caused by high-temperature activation and low Mg activation efficiency.

[0022] The application will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figure 1 is a structural schematic diagram of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application;

[0024] Figure 2 is a top view of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application;

[0025] Figure 3 is a flowchart of a preparation method of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application;

[0026] FIG. 4 is a schematic diagram of a preparation method of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application. DETAILED DESCRIPTION

[0027] The application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0028] Please refer to Figure 1 and Figure 2 , Figure 1 is a structural schematic diagram of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application, Figure 2 is a top view of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the application, the polar structure gallium nitride junction barrier Schottky diode provided by the application comprises: a substrate, a buffer layer, an n + -GaN layer, an n - -GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer, which are sequentially stacked,

[0029] The layer stack structure composed of the i-GaN layer and the p-GaN layer and the AlGaN layer polarize to generate a two-dimensional hole gas, the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers include a plurality of openings; in a direction perpendicular to the substrate, the orthographic projection of the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers includes a plurality of first regions, and the orthographic projection of the opening is located between adjacent first regions;

[0030] An anode is located on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extends into the opening, and is in contact with the n - -GaN drift layer;

[0031] A cathode is located on the n + -GaN layer and is spaced apart from the n - -GaN drift layer;

[0032] A passivation layer covers the exposed surfaces of the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - -GaN drift layer and the cathode, and the passivation layer includes a first opening and a second opening, the first opening exposes the anode, and the second opening exposes the cathode.

[0033] Specifically, the gallium nitride junction barrier Schottky diode with a polarization structure provided in the embodiment is sequentially arranged in layers from bottom to top as a substrate, a buffer layer, an n + -GaN layer, an n - -GaN drift layer, an AlGaN layer, an i-GaN layer and a p-GaN layer, and is provided with a cathode, an anode and a passivation layer, wherein the layer stack structure composed of the i-GaN layer and the p-GaN layer and the AlGaN layer polarizes to generate a two-dimensional hole gas, which can also be understood as that the p-GaN / i-GaN / AlGaN structure can generate a two-dimensional hole gas with a high concentration at the i-GaN / AlGaN interface, and since the n region and the p region under the anode metal are arranged alternately, when the device is reverse biased, the two-dimensional hole gas at the i-GaN / AlGaN interface under the anode metal and the two-dimensional electron gas polarized at the AlGaN / n - -GaN drift layer interface form an alternating arrangement of depletion regions, thereby realizing a GaN JBS diode with high withstand voltage and low conduction. Compared with the conventional GaN JBS diode formed by secondary epitaxy, the diode provided by the application can effectively avoid the leakage problem caused by the PN junction interface defects of the complex secondary epitaxy process; and compared with the conventional GaN JBS formed by ion implantation, the diode avoids problems such as decomposition of surface GaN caused by high-temperature activation and low Mg activation efficiency.

[0034] In an optional embodiment of the present application, the thickness of the AlGaN layer is 15-30nm in the direction perpendicular to the substrate, and the Al component ratio is 0.15-0.4.

[0035] Specifically, in the present embodiment, the thickness of the AlGaN layer can be 18nm, 20nm, 25nm or 28nm, and the Al component ratio can be 0.2, 0.25, 0.3 or 0.35, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0036] In an optional embodiment of the present application, the thickness of the i-GaN layer is 20-50nm in the direction perpendicular to the substrate.

[0037] Specifically, in the present embodiment, the thickness of the i-GaN layer can be 25nm, 30nm, 33nm, 38nm, 42nm or 48nm, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0038] In an optional embodiment of the present application, the thickness of the p-GaN layer is 50-100nm in the direction perpendicular to the substrate, and the Mg doping concentration of the p-GaN layer is 1x1018cm-2-5x1019cm-2. 19 cm -3 -5x1019cm 19 -2. -3

[0039] Specifically, in the present embodiment, the thickness of the p-GaN layer can be 50nm, 60nm, 70nm, 80nm or 90nm, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0040] In an optional embodiment of the present application, the substrate comprises any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

[0041] Specifically, in the present embodiment, the thickness of the sapphire substrate is 300-600μm in the direction perpendicular to the substrate, the thickness of the silicon substrate is 600-1000μm, the thickness of the silicon carbide substrate is 300-600μm, and the thickness of the gallium nitride substrate is 300-1000μm, which are not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0042] In an optional embodiment of the present application, the buffer layer adopts GaN material or gradually changing AlGaN material or AlGaN / GaN superlattice material, and the thickness of the buffer layer is 500nm-3μm in the direction perpendicular to the substrate, which is not specifically limited in the present embodiment and can be determined according to actual application conditions.

[0043] ​In an alternative embodiment of the present application, n + The Si doping concentration of the GaN layer is 1x10 19 cm -3 ~5x10 19 cm -3 In the direction perpendicular to the substrate, n + The thickness of the GaN layer is 1 μm ~ 3 μm, which is not specifically limited in the present embodiment and can be determined according to the actual application.

[0044] In an alternative embodiment of the present application, n - The Si doping concentration of the GaN drift layer is 1x10 16 cm -3 ~5x10 16 cm -3 In the direction perpendicular to the substrate, n - The thickness of the GaN drift layer is 1 μm ~ 10 μm, which is not specifically limited in the present embodiment and can be determined according to the actual application.

[0045] In an alternative embodiment of the present application, in the direction perpendicular to the substrate, the thickness of the anode is 100 ~ 300 nm, and the anode is a nickel and gold laminated metal.

[0046] Specifically, in the present embodiment, the thickness of the anode can be 150 nm, 180 nm, 200 nm, 280 nm, which is not specifically limited in the present embodiment and can be determined according to the actual application.

[0047] In an alternative embodiment of the present application, the anode is in contact with the p-GaN layer to form an ohmic contact, and the anode is in contact with the n - -GaN drift layer to form a Schottky contact.

[0048] In an alternative embodiment of the present application, in the direction perpendicular to the substrate, the thickness of the cathode is 200 ~ 500 nm, and the material of the cathode includes titanium, aluminum, nickel and gold, the cathode is in contact with the n + -GaN layer to form an ohmic contact.

[0049] Specifically, in the present embodiment, the thickness of the cathode is 250 nm, 300 nm, 350 nm, 400 nm and 450 nm, which is not specifically limited in the present embodiment and can be determined according to the actual application.

[0050] In an alternative embodiment of the present application, in the direction perpendicular to the substrate, the thickness of the passivation layer is 200 ~ 1000 nm, and the material of the passivation layer includes silicon nitride material.

[0051] Specifically, in this embodiment, the thickness of the passivation layer can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, which is not specifically limited herein and can be determined according to actual application.

[0052] Based on the same inventive concept, see Figure 3 and Fig. 4, Figure 3 is a flowchart of a preparation method of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the present application, Fig. 4 is a schematic diagram of a preparation method of a polar structure gallium nitride junction barrier Schottky diode provided by an embodiment of the present application, and the present application further provides a preparation method of a polar structure gallium nitride junction barrier Schottky diode, which is used for preparing the diode provided in the above embodiments, and the structure of the diode is described above and will not be repeated here; the preparation method comprises the following steps:

[0053] S101, providing a substrate.

[0054] Specifically, in this embodiment, the substrate can be any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

[0055] S102, epitaxially growing a buffer layer on the substrate, epitaxially growing an n + -GaN layer on the buffer layer, epitaxially growing an n + -GaN layer on the n - -GaN layer, epitaxially growing an n - -GaN drift layer on the n

[0056] S103, defining a diode isolation region by lithography, and etching the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - -GaN drift layer by an inductive coupled plasma etching process to form an isolation region.

[0057] S104, defining a cathode region on the isolation region by lithography, and sequentially depositing titanium, aluminum, nickel and gold on the cathode region by an electron beam evaporation process to form a cathode, and forming an ohmic contact between the cathode and the n + -GaN layer by rapid thermal annealing.

[0058] S105, defining an anode etching region on the p-GaN layer by lithography, and etching the p-GaN layer, the i-GaN layer and the AlGaN layer by an inductive coupled plasma etching process to obtain an anode etching region.

[0059] S106. The anode region is defined by photolithography in the anode etching area. Nickel and gold are deposited in the anode region using electron beam evaporation to form the anode. Rapid thermal annealing is then performed in an oxygen atmosphere to bond the anode with the nitrogen. - - The GaN drift layer forms a Schottky contact, and the anode forms an ohmic contact with the p-GaN layer; wherein, the anode region is partially located at n - -On the GaN drift layer, partly located on the p-GaN layer.

[0060] S107, at the anode, p-GaN layer, i-GaN layer, AlGaN layer, n - - Passivation layers are epitaxially grown on the GaN drift layer and the cathode-exposed surface.

[0061] S108. A first opening region is defined on the anode by photolithography, a second opening region is defined on the cathode by photolithography, the passivation layer of the first opening region is etched by reactive ion etching process to form the first opening, and the passivation layer of the second opening region is etched by reactive ion etching process to form the second opening.

[0062] In an optional embodiment of the present invention, please continue to refer to Figure 4. The fabrication of a gallium nitride junction barrier Schottky diode with a polarization structure is achieved through the following steps:

[0063] S101, Provide a substrate.

[0064] S102, Preparation of p-GaN / i-GaN / AlGaN / n - -GaN / n + - An epitaxial wafer with a GaN / buffer layer / substrate structure.

[0065] Specifically, in this embodiment, metal-organic chemical vapor deposition (MOCVD) is used to sequentially epitaxially grow a 1.5 μm thick gradient AlGaN buffer layer and a Si doping concentration of 5 × 10⁻⁶ on a silicon substrate. 19 cm -3 and n with a thickness of 1μm + -GaN layer, Si doping concentration is 1×10 16 cm -3 and n with a thickness of 3μm - -GaN drift layer, Al composition of 0.3 and AlGaN layer with a thickness of 20 nm, i-GaN with a thickness of 20 nm, and Mg doping concentration of 1×10⁻⁶. 19 cm -3 And a 50nm thick p-GaN layer, resulting in p-GaN / i-GaN / AlGaN / n - -GaN / n + - An epitaxial wafer with a GaN / buffer layer / substrate structure is shown in Figure 4(a).

[0066] S103, mesa isolation.

[0067] Specifically, in this embodiment, the mesa isolation pattern is defined by photolithography, and then the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - -GaN drift layer are etched by a chlorine-based etching method using an inductively coupled plasma etching process, with the etching depth being greater than the sum of the thicknesses of the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - -GaN drift layer, and the n + -GaN is etched to form a device isolation region, as shown in Fig. 4(b).

[0068] S104, preparation of a cathode electrode.

[0069] Specifically, in this embodiment, the cathode region is defined by photolithography, and the sample is cleaned using a BOE solution to remove the oxide in the cathode region. The n + -GaN layer is deposited with titanium, aluminum, nickel and gold metals having thicknesses of 20 nm, 120 nm, 40 nm and 50 nm, respectively, by an electron beam evaporation method, and then rapid annealing is performed at a temperature of 850°C in a nitrogen atmosphere for 30 seconds, so that the titanium, aluminum, nickel and gold layered metals form an ohmic contact with the n + -GaN, as shown in Fig. 4(c).

[0070] S105, etching of an anode region.

[0071] Specifically, in this embodiment, the anode region is defined by photolithography, with the n region d1 being 1.5 μm wide and the p region d2 being 3 μm wide, and then the p-GaN layer, the i-GaN layer and the AlGaN layer are etched by a chlorine-based etching method using an inductively coupled plasma etching process, so that the sum of the thicknesses of the p-GaN layer, the i-GaN layer and the AlGaN layer is obtained, and then an organic solvent is used to remove the photoresist, as shown in Fig. 4(d).

[0072] S106, preparation of an anode electrode.

[0073] Specifically, in this embodiment, the anode electrode region is defined by photolithography, and the sample is cleaned using a BOE solution to remove the oxide in the anode region. A 20-nm-thick nickel metal and a 200-nm-thick gold metal are deposited on the n - -GaN drift layer and the p-GaN layer by an electron beam evaporation process, and then annealing is performed at a temperature of 500°C in an oxygen atmosphere for 5 minutes, so that the anode forms a Schottky contact with the n - -GaN region and forms an ohmic contact with the p-GaN region, as shown in Fig. 4(e).

[0074] S107, preparation of a passivation layer.

[0075] Specifically, in this embodiment, a 1000 nm silicon nitride layer is grown on the sample of S106 as a passivation layer of the GaN JBS diode by using plasma enhanced chemical vapor deposition technology, as shown in Fig. 4(f).

[0076] S108, etching of the passivation layer and opening of holes.

[0077] Specifically, in this embodiment, the interconnection opening area is defined by using photolithography, and the silicon nitride passivation layer of the opening area is etched by using a fluorine-based gas by using a reactive ion etching (RIE) device, and the etching depth is about 1000 nm, as shown in Fig. 4(g).

[0078] In an alternative embodiment of the present application, please continue to refer to Fig. 4, the preparation of the polar structure GaN JBS diode is realized by the following steps, specifically:

[0079] S101, providing a substrate.

[0080] S102, preparing a p-GaN / n - -GaN / AlGaN / n + -GaN / buffer layer / substrate structure epitaxial wafer.

[0081] A GaN buffer layer with a thickness of 1 μm, an n 19 -GaN layer with a Si doping concentration of 5×10 -3 cm + and a thickness of 1 μm, an n 16 -GaN drift layer with a Si doping concentration of 5×10 -3 cm - and a thickness of 4 μm, an AlGaN layer with an Al component of 0.15 and a thickness of 15 nm, an i-GaN layer with a thickness of 20 nm, a p-GaN layer with a Mg doping concentration of 5×10 19 cm -3 and a thickness of 50 nm are sequentially epitaxied on the sapphire substrate by using metal organic chemical vapor deposition technology, to obtain a p-GaN / i-GaN / AlGaN / n - -GaN / n + -GaN / buffer layer / substrate structure epitaxial wafer, as shown in Fig. 4(a).

[0082] S103, mesa isolation.

[0083] The mesa isolation pattern is defined by using photolithography, and then the p-GaN layer, the i-GaN layer, the AlGaN layer and the n - -GaN drift layer are etched by using a chlorine-based etching method of inductively coupled plasma etching process, and the etching depth is greater than that of the p-GaN layer, the i-GaN layer, the AlGaN layer and the n -The sum of the thicknesses of the GaN drift layers is etched to the n + GaN, forming a device isolation region, as shown in Fig. 4(b).

[0084] S104, preparing a cathode electrode.

[0085] The cathode region is defined using photolithography, and the sample is cleaned using a BOE solution to remove the oxide in the cathode region. The n + A 20 nm, 120 nm, 40 nm, and 50 nm thick titanium, aluminum, nickel, and gold metal layer is deposited on the GaN layer using electron beam evaporation, followed by rapid annealing at a temperature of 850°C for 30 seconds in a nitrogen atmosphere, so that the titanium, aluminum, nickel, and gold metal layer forms an ohmic contact with the n + GaN, as shown in Fig. 4(c).

[0086] S105, etching an anode region.

[0087] The anode region is defined using photolithography, and the n region d1 of the anode region is 1.5 μm wide and the p region d2 is 3 μm wide, followed by etching the sum of the thicknesses of the p-GaN layer, i-GaN, and AlGaN layer using an inductively coupled plasma etching process with a chlorine-based etching method to obtain the anode region, followed by removing the photoresist using an organic solvent, as shown in Fig. 4(d).

[0088] S106, preparing an anode electrode.

[0089] The anode electrode region is defined using photolithography, and the sample is cleaned using a BOE solution to remove the oxide in the anode region. A 30 nm thick nickel metal layer and a 200 nm thick gold metal layer are deposited on the n - GaN drift layer and the p-GaN layer using an electron beam evaporation process, followed by annealing at a temperature of 500°C for 5 minutes in an oxygen atmosphere, so that the anode forms a Schottky contact with the n - GaN region and an ohmic contact with the p-GaN region, as shown in Fig. 4(e).

[0090] S107, preparing a passivation layer.

[0091] An 800 nm thick silicon nitride layer is grown on the sample of S106 using a plasma enhanced chemical vapor deposition technique as a passivation layer of the GaN JBS diode, as shown in Fig. 4(f).

[0092] S108, etching the passivation layer and opening a hole.

[0093] The interconnection opening region is defined using photolithography, and the silicon nitride passivation layer in the opening region is etched using a fluorine-based gas using a reactive ion etching (RIE) device, and the etching depth is about 800 nm, as shown in Fig. 4(g).

[0094] It is to be understood that the terminology "first", "second", and the like used herein is merely intended to differentiate one element from another element, and does not imply or suggest any actual relationship or sequence between the elements. Also, the terms "comprise", "comprising", or any other variant thereof are intended to cover non-exclusive inclusions, such that an item or apparatus that comprises a list of elements does not exclude other elements not expressly listed. An element defined by the phrase "comprising a... " does not exclude the presence of additional identical elements in the item or apparatus comprising the element. The terms "connected", "coupled", and the like are not limited to direct connections or physical connections, but can include indirect connections or indirect physical connections between devices or elements such as electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are used only for the purpose of facilitating the description of the present application and simplifying the description, and thus cannot be construed as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be construed as limiting the present application.

[0095] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. The illustrative expressions of the above terms in the present specification do not necessarily refer to the same embodiment or example. Also, the specific feature or characteristic described can be combined in any suitable manner in one or more embodiments or examples. In addition, a person skilled in the art can combine and combine different embodiments or examples described in the present specification.

[0096] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.

Claims

1. A gallium nitride junction barrier Schottky diode of polarization structure, characterized by, Comprise: The substrate, the buffer layer, the n + -GaN layer, the n - -GaN drift layer, AlGaN layer, i-GaN layer and p-GaN layer; wherein, The i-GaN layer and the p-GaN layer constitute a laminated structure with the AlGaN layer, and the polarized two-dimensional hole gas is generated; the AlGaN layer, the i-GaN layer and the p-GaN layer are laminated and arranged, and comprise a plurality of openings; along the direction perpendicular to the substrate, the orthographic projection of the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers comprises a plurality of first regions, and the orthographic projection of the opening is located between adjacent first regions; an anode on the AlGaN layer, the i-GaN layer and the p-GaN layer arranged in layers and extending into the opening, in contact with the n - - GaN drift layer contact; a cathode, located on the n + - on the GaN layer and in contact with the n - - GaN drift layer is arranged in between; a passivation layer covering the anode, the p-GaN layer, the i-GaN layer, the AlGaN layer, the n - - a GaN drift layer and a surface of the cathode exposed, the passivation layer comprising a first opening exposing the anode and a second opening exposing the cathode.

2. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, Along the direction perpendicular to the substrate, the thickness of the AlGaN layer is 15-30nm, and the Al component accounts for 0.15-0.

4.

3. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, Along the direction perpendicular to the substrate, the thickness of the i-GaN layer is 20-50nm.

4. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, In a direction perpendicular to the substrate, the thickness of the p-GaN layer is 50-100 nm, and the Mg doping concentration of the p-GaN layer is 1 x 1019-5 x 1020cm-3. 19 cm -3 ~5×10 19 cm -3 .

5. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, The substrate comprises any one of a sapphire substrate, a silicon substrate, a silicon carbide substrate or a gallium nitride substrate.

6. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, Along the direction perpendicular to the substrate, the thickness of the anode is 100-300nm, and the anode is a nickel and gold laminated metal.

7. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, The anode is in contact with the p-GaN layer forming an ohmic contact, the anode is in contact with the n - - GaN drift layer contact forming a Schottky contact.

8. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, The thickness of the cathode in a direction perpendicular to the substrate is 200-500 nm, the material of the cathode includes titanium, aluminum, nickel and gold, the cathode is in contact with the n + - the GaN layer is contacted, forming an ohmic contact.

9. The polarization-structured gallium nitride junction barrier Schottky diode of claim 1, wherein, Along the direction perpendicular to the substrate, the thickness of the passivation layer is 200-1000nm, and the material of the passivation layer comprises a silicon nitride material.

10. A method for fabricating a gallium nitride junction barrier Schottky diode with a polarization structure, characterized in that, Comprise: A substrate is provided; epitaxially growing a buffer layer on the substrate, epitaxially growing an n + -GaN layer on the n + -GaN layer, epitaxially growing an n - -GaN drift layer on the n - -growing an AlGaN layer on the n-GaN drift layer, epitaxially growing an i-GaN layer on the AlGaN layer, epitaxially growing a p-GaN layer on the i-GaN layer; the i-GaN layer and the p-GaN layer constitute a laminated structure, and a two-dimensional hole gas is generated by polarization of the AlGaN layer; The p-GaN layer, the i-GaN layer, the AlGaN layer and the n-GaN layer are etched by using an inductive coupling plasma etching process, and the p-GaN layer, the i-GaN layer, the AlGaN layer and the n-GaN layer are etched to form a diode isolation region. - a GaN drift layer, forming an isolation region; A photoetching is used to define a cathode region on the isolation region, and an electron beam evaporation process is used to sequentially deposit titanium, aluminum, nickel and gold on the cathode region to form a cathode, and a rapid thermal annealing is used to make the cathode and the n + - The GaN layer forms an ohmic contact; An anode etching area is defined on the p-GaN layer by lithography, and the p-GaN layer, the i-GaN layer and the AlGaN layer are etched by an inductive coupling plasma etching process to obtain the anode etching area; The anode region is defined by etching the anode region using photolithography, and nickel and gold are deposited on the anode region by using an electron beam evaporation process to form an anode. The anode is made to form a Schottky contact with the n - -GaN drift layer, and the anode forms an ohmic contact with the p-GaN layer; wherein the anode region is partially located on the n - -GaN drift layer and partially on the p-GaN layer. - a p-GaN layer on said anode, said i-GaN layer, said AlGaN layer, said n - - a passivation layer epitaxially grown on the surface exposed to said cathode. A first opening area is defined on the anode by lithography, a second opening area is defined on the cathode by lithography, the passivation layer of the first opening area is etched by a reactive ion etching process to form a first opening, and the passivation layer of the second opening area is etched by a reactive ion etching process to form a second opening.

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