Single voltage monitoring power comparison circuit

Abstract

The application discloses a single-voltage detection power comparison circuit and belongs to the field of analog integrated circuit design.The circuit is composed of a switch circuit (1), a voltage difference to current circuit (2), a current mirror circuit (3), a voltage to current circuit (4) and a comparison output circuit (5).The switch circuit (1) comprises two complementary switches and five switch arrays; the voltage difference to current circuit (2) comprises a first operational amplifier, a first resistor, a load current mirror and a diode-connected MOS tube; the current mirror circuit (3) comprises six P-type MOS tubes and a pair of N-type MOS tubes; the voltage to current circuit (4) comprises a second operational amplifier, a second resistor, an N-type MOS tube and a diode-connected MOS tube; and the comparison output circuit (5) comprises a current adder-subtracter and two buffers.The application supports an MPPT dynamic tracking algorithm, the comparator output indicates the disturbance direction, the impedance matching and the control strategy are integrated, the adaptability to different DC-DC topologies is enhanced, the system design is simplified and the cost is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of analog integrated circuit design, and particularly relates to a single-voltage detection power comparison circuit. BACKGROUND

[0002] The growing demand for clean renewable energy has driven the field of energy conversion to become the focus of current research. The emergence of new materials has brought new opportunities for the development of power electronics technology, which can convert various forms of energy into electrical energy. In nonlinear energy conversion systems, there is a nonlinear relationship between output and input. The power-voltage (P-V) curve of some systems exhibits a single peak characteristic. The use of maximum power point tracking technology (MPPT) to improve energy conversion efficiency has become a hot topic in the industry.

[0003] Traditional power electronic systems often face complex circuit topologies and control algorithms in new energy conversion. Dynamic tracking algorithms require continuous power comparison, so two sets of monitoring circuits (voltage and current monitoring) are needed. However, additional circuits are used to accurately collect, process, and compare the two signals, increasing system complexity and energy consumption, which in turn affects the overall efficiency of the system. SUMMARY

[0004] To overcome the shortcomings of the prior art, the present application provides a single-voltage detection power comparison circuit, which can be used in MPPT control strategies, significantly reducing the complexity and number of devices, and improving the overall reliability of the system.

[0005] To achieve the above purpose, the present application provides the following technical solutions:

[0006] A single-voltage monitoring power comparison circuit, composed of a switching circuit, a voltage difference to current circuit, a current mirror circuit, a voltage to current circuit, and a comparison output circuit.

[0007] The switching circuit includes complementary switches S1 and S2, and switching arrays SQ5, SQ4, SQ3, SQ2, and SQ1, which are used to connect input voltages to make the voltage difference positive and connect the ratio of current to bias current. One end of switches S1 and S2 is connected to the input voltage before and after perturbation, and the other end is connected to MOS tubes MN1 and MN2; one end of switching arrays SQ5, SQ4, SQ3, SQ2, and SQ1 is connected to the current mirror circuit, and the other end is connected to the comparison output circuit.

[0008] The voltage difference to current circuit includes a first operational amplifier, a first resistor, load current mirrors MP1 and MP2, and diode-connected MOS tubes MN1 and MN2; the first operational amplifier is used for voltage clamping to clamp the voltage difference |V in1 -V in2| The signal is converted into current signal I3 through the first resistance R.

[0009] The current mirror circuit comprises five P-type MOS transistors MP4, MP5, MP6, MP7 and MP8, a pair of N-type MOS transistors MN3 and MN4 and a P-type MOS transistor MP3; the current mirror circuit is used to copy the bias currents I3 and I1 to generate currents proportional to the bias currents.

[0010] The voltage-to-current circuit comprises a second operational amplifier, a second resistance, an N-type MOS transistor MN5 and a diode-connected MOS transistor MP9; the second operational amplifier is used as an emitter follower to convert the voltage V in1 The signal is converted into current signal I1.

[0011] The comparison output circuit comprises a current adder and two buffers; the comparison output circuit converts the current into a voltage flag signal to mark the positive and negative of the power comparison, and can also be used for observing the positive and negative directions of the perturbation.

[0012] Further, the switches of the switch circuit are composed of transmission gates, the complementary switch control signals are controlled by the switch signals obtained by comparing the input voltages before and after the perturbation, and the switch array control signals are controlled by an external counter.

[0013] Further, in the voltage difference-to-current circuit, the inverting input terminal of the first operational amplifier is connected with the first resistance and the load current mirror MP2, the non-inverting input terminal is connected with the gate and the drain of the diode-connected MOS transistor MN1 and the load current mirror MP1, and the output terminal of the first operational amplifier is connected with the gates of the load current mirrors MP1 and MP2; one end of the first resistance is connected with the gate and the drain of the diode-connected MOS transistor MN2; the source terminals of the load current mirrors MP1 and MP2 are connected with a power supply; and the source terminals of the diode-connected MOS transistors MN1 and MN2 are grounded.

[0014] Further, in the current mirror circuit, the gates of the MOS transistors MP4, MP5, MP6, MP7 and MP8 are connected with each other and with the gate of MP9, the drains are connected with the switch array, the addition of the currents is selected through the switch array; the gates of the pair of N-type MOS transistors MN3 and MN4 are connected with each other, and the source terminals are grounded; the gate and the drain of MN3 are connected with each other, the drain is connected with the drain of MP3, and the drain of MN4 is connected with the comparison output.

[0015] Further, in the voltage-to-current circuit, the inverting input terminal of the second operational amplifier is connected with the second resistor and the source of the MN5, the non-inverting input terminal is connected with the input voltage terminal before the disturbance, and the output terminal is connected with the gate of the MN5; the other end of the second resistor is grounded; the drain of the MOS tube MN5 is connected with the drain of the MP9; the drain and the gate of the diode-connected MOS tube MP9 are connected, and the source is connected with the power supply.

[0016] Further, in the comparison output circuit, the current adder and subtractor are realized through the line common node line and the logic; the two buffers convert the compared current into voltage and output the compared result to indicate the disturbance direction.

[0017] Compared with the prior art, the present application has the following beneficial effects:

[0018] The present application reduces the number of monitors, significantly reduces the design complexity and the number of devices compared with the traditional comparator, and improves the overall reliability of the system. Simplified design reduces the material and labor cost in the development and production process, and facilitates the standardization and large-scale production of products.

[0019] The circuit structure of the present application is simple, which eliminates the need for complex conversion and processing, so that the system can quickly respond to the change of input power. The fast reaction capability ensures that the system can quickly adjust under changing environmental conditions and maintain the optimal operating state.

[0020] The present application selects a voltage monitoring circuit instead of a current monitoring circuit as a monitoring element. Voltage monitoring can use resistance voltage division, which is simpler and more economical in design and manufacturing, and has lower energy consumption.

[0021] The scheme provided by the present application can be applied to the design of single-channel (voltage / power) monitoring power comparators of other DC-DC topologies. BRIEF DESCRIPTION OF DRAWINGS

[0022] Fig. 1 The present application is a single-voltage monitoring power comparison circuit;

[0023] Fig. 2 The present application is a Buck-Boost circuit topology and a current image when the inductor works in the BCM mode;

[0024] Fig. 3 The present application is an MPPT control chip scheme case applied to the Buck-Boost circuit topology-based MPPT control chip scheme case. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described in detail below with the accompanying drawings of the embodiments of the present application. The described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0027] Please refer to Figs. 1 to 3 The present application provides a single voltage monitoring power comparison circuit technical scheme, and the specific design method is as follows:

[0028] As shown in Fig. 1 A single voltage monitoring power comparison circuit is composed of a switching circuit (1), a voltage difference to current circuit (2), a current mirror circuit (3), a voltage to current circuit (4), and a comparison output circuit (5).

[0029] The switching circuit (1) includes complementary switches S1 and S2 and a switching array SQ5, SQ4, SQ3, SQ2 and SQ1, which are respectively used for inputting voltage, making the voltage difference positive, and inputting current and the proportional coefficient of the bias current. One end of the S1 and S2 switches is connected with the input voltage before and after disturbance, and the other end is connected with MOS tubes MN1 and MN2. One end of the switching array SQ5, SQ4, SQ3, SQ2 and SQ1 is connected with the current mirror circuit (3), and the other end is connected with the comparison output circuit (5).

[0030] The voltage difference to current circuit (2) includes a first operational amplifier, a first resistor, load current mirrors MP1 and MP2, and diode-connected MOS tubes MN1 and MN2. The first operational amplifier is used for voltage clamping to convert the voltage difference |V in1 -V in2 | signal into a current signal I3 through the first resistor R.

[0031] The current mirror circuit (3) includes five parallel P-type MOS tubes MP4, MP5, MP6, MP7 and MP8, a pair of N-type MOS tubes MN3 and MN4, and a P-type MOS tube MP3. The current mirror circuit (3) is used for copying the bias currents I3 and I1 to generate a current proportional to the bias current.

[0032] The voltage-to-current circuit (4) comprises a second operational amplifier, a second resistor, an N-type MOS tube MN5, and a diode-connected MOS tube MP9; the second operational amplifier serves as an emitter follower for converting the pre-disturbance voltage V in1 The signal is converted into a current signal I1.

[0033] The comparison output circuit (5) comprises a current adder-subtracter and two buffers. The comparison output circuit (5) converts the current into a voltage flag signal for marking the positive and negative of the power comparison, and can also be used for marking the positive and negative directions of the disturbance observation.

[0034] Further, the switches of the switch circuit (1) are composed of transmission gates, the complementary switch control signals are controlled by the switch signals obtained by comparing the input voltages before and after the disturbance, and the switch array control signals are controlled by an external counter.

[0035] Further, in the voltage difference-to-current circuit (2), the inverting input terminal of the first operational amplifier is connected with the first resistor and the load current mirror MP2, the non-inverting input terminal is connected with the gate and the drain of the diode-connected MOS tube MN1, and is connected with the load current mirror MP1, the output terminal of the first operational amplifier is connected with the gates of the load current mirrors MP1 and MP2; one end of the first resistor is connected with the gate and the drain of the diode-connected MOS tube MN2; the source terminals of the load current mirrors MP1 and MP2 are connected with a power supply; the source terminals of the diode-connected MOS tubes MN1 and MN2 are grounded.

[0036] Further, in the current mirror circuit (3), the gates of the MOS tubes MP4, MP5, MP6, MP7, and MP8 are connected with the gate of MP9, and the drains are connected with the switch array; the sum of the currents is selected through the switch array; the gates of the N-type MOS tubes MN3 and MN4 are connected, and the source terminals are grounded; the gate and the drain of MN3 are connected, and the drain is connected with the drain of MP3, and the drain of MN4 is connected with the comparison output.

[0037] Further, in the voltage-to-current circuit (4), the inverting input terminal of the second operational amplifier is connected with the second resistor and the source terminal of MN5, the non-inverting input terminal is connected with the input voltage terminal before the disturbance, and the output terminal is connected with the gate of MN5; the other end of the second resistor is grounded; the MOS tube MN5 is connected with the drain of MP9; the drain and the gate of the diode-connected MOS tube MP9 are connected, and the source terminal is connected with a power supply.

[0038] Further, in the comparison output circuit (5), the current adder-subtracter is connected with the logic through a line common node line.

[0039] The current flowing into the buffer satisfies: ,

[0040] When I D When the voltage crosses zero, the level of the buffer changes, and the level of the flag bit responds accordingly, affecting the counter and controlling its on / off operation. This allows for adjustment of the input voltage level after power comparison, controlling it to fluctuate near the maximum power point.

[0041] like Fig. 2 As shown, based on the characteristics of the Buck-Boost circuit, operating in BCM mode (the derivation of DCM is the same), the relationship between input power and input voltage can be obtained:

[0042] ,

[0043] Furthermore, this invention employs a fixed-frequency variable duty cycle strategy. By perturbing the duty cycle by ΔD, the input voltage will also be perturbed accordingly, and the difference between the two input power values ​​can be obtained as follows:

[0044] ,

[0045] Furthermore, comparing the input power can be done by comparing the numerator term with the 0 term, since it is V in Much larger than ΔV in D is much larger than ΔD, and the higher order ΔD 2 , △V in 2 and △D△V in They will be eliminated.

[0046] ,

[0047] The duty cycle that changes simultaneously on both sides of the equation is inversely related to the duty cycle, so the equation can be transformed into: ,

[0048] Furthermore, assume the relationship between the disturbance's duty cycle and the original duty cycle: ,

[0049] Furthermore, the final derivation is: ,

[0050] From the above derivation, we can see that the voltage relationship can realize the comparison between power and the zero term, and the power comparator can be designed based on the derivation.

[0051] An MPPT control chip based on a Buck-Boost circuit, used in the power comparator of this invention, such as... Fig. 3 As shown.

[0052] The chip employs a built-in Buck-Boost architecture, configured with six input pins (VIN_DC, GND, EN, VIN_SAMPLE, L_P, L_N) and one output pin (VOUT). VIN_DC is connected to the power output terminal, and GND is used as ground. L_P and L_N are connected to the two ends of an external inductor, respectively. The EN pin serves as the enable pin, primarily used to activate MPPT (Maximum Power Point Tracking) control, while the VIN_SAMPLE pin is responsible for initiating the internal sampling signal.

[0053] Regarding the chip's operating principle, power is input through the VIN_DC port. The logic control circuit SH_1 issues a control signal to control the sampling and holding of the initial voltage VIN1. Before a disturbance, VIN1 is compared with zero voltage via a power comparator. If the comparison result is low, the counter performs a subtraction operation and transmits the result to the variable duty cycle switch driver, generating switch signals SW1 and SW2 to adjust the input voltage to move in the positive direction. Subsequently, the logic control circuit SH_2 controls the sampling and holding of the second voltage VIN2. After a disturbance, VIN2 is compared with VIN1 before the disturbance. If Flag is high, it indicates an increase in power, and the counter continues to perform a subtraction operation; if Flag is low, it indicates a decrease in power, and the counter performs an addition operation. The counter's output value is again transmitted to the variable duty cycle switch driver, generating switch signals SW1 and SW2 to adjust the input voltage in response to power changes. SW1 and SW2 adjust the input voltage to respond to power changes, ensuring stable system operation and maximizing energy utilization efficiency.

[0054] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing specific embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing specific embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A single-voltage monitoring power comparison circuit, characterized in that, The circuit consists of a switching circuit (1), a voltage difference to current conversion circuit (2), a current mirror circuit (3), a voltage to current conversion circuit (4), and a comparison output circuit (5); The switching circuit (1) includes: complementary switches S1 and S2 and switch array SQ5, SQ4, SQ3, SQ2 and SQ1; one end of switches S1 and S2 is connected to the input voltage before and after the disturbance, and the other end is connected to MOSFETs MN1 and MN2; one end of switch array SQ5, SQ4, SQ3, SQ2 and SQ1 is connected to the current mirror circuit (3), and the other end is connected to the comparison output circuit (5); The voltage differential current circuit (2) includes: a first operational amplifier, a first resistor, load current mirrors MP1 and MP2, and diode-connected MOS transistors MN1 and MN2; The current mirror circuit (3) includes: five P-type MOS transistors connected in parallel, MP4, MP5, MP6, MP7, MP8, a pair of N-type MOS transistors MN3, MN4 and a P-type MOS transistor MP3; The voltage-to-current circuit (4) includes: a second operational amplifier, a second resistor, an N-type MOSFET MN5, and a diode-connected MOSFET MP9; The comparison output circuit (5) includes: a current adder / subtractor and two buffers; In the voltage differential to current circuit (2), the inverting input terminal of the first operational amplifier is connected to the first resistor and the load current mirror MP2, the non-inverting input terminal is connected to the gate and drain of the MOS transistor MN1 connected to the diode, and is connected to the load current mirror MP1, and the output terminal of the first operational amplifier is connected to the gates of the load current mirrors MP1 and MP2. One end of the first resistor is connected to the gate and drain of the MOS transistor MN2, which is connected to the diode; The source terminals of the load current mirrors MP1 and MP2 are connected to the power supply. The source terminals of the MOS transistors MN1 and MN2 connected to the diodes are both grounded; Based on the characteristics of Buck-Boost circuits, the circuit employs a fixed-frequency variable duty cycle strategy, by applying duty cycle perturbations. The input voltage will also be disturbed accordingly. After sampling for two consecutive switching cycles, the difference between the two input power values ​​Δ is established. P in With input voltage V in The mapping relationship of duty cycle D is as follows: ， Among them, △ P in The difference in input power over two switching cycles. P in1 The input power for the first switching cycle. P in2 The input power for the second switching cycle. T For the switching cycle, L For inductance, V in Input voltage, The input voltage disturbance is represented by D, and the duty cycle is represented by D. For duty cycle perturbation; To compare input power, the numerator term can be compared with the 0 term; V in Much larger than ΔV in D is much larger than ΔD, and higher order ΔD D 2 , △ V in 2 and △ D , △ V in Eliminated, resulting in: ， Right now Define the relationship between the duty cycle perturbation and the original duty cycle: ,get: ， Among them, the definition k It is the ratio of the disturbance duty cycle to the duty cycle.

2. The single-voltage monitoring power comparison circuit according to claim 1, characterized in that, The switch of the switching circuit (1) is composed of transmission gates. The complementary switch control signal is controlled by the switch signal after comparing the input voltage before and after the disturbance. The switch array control signal is controlled by an external counter.

3. The single-voltage monitoring power comparison circuit according to claim 1, characterized in that, In the current mirror circuit (3), the gates of MOS transistors MP4, MP5, MP6, MP7, and MP8 are connected and connected to the gate of MP9. Current is copied from the MP9 circuit, and the drain is connected to the switch array. The sum of currents is selected through the switch array. The gates of the pair of N-type MOS transistors MN3, MN4 are connected, and their sources are all grounded; the gate and drain of MN3 are connected, and its drain is connected to the drain of MP3; the drain of MN4 is connected to the comparator output.

4. The single-voltage monitoring power comparison circuit according to claim 1, characterized in that, In the voltage-to-current circuit (4), the inverting input terminal of the second operational amplifier is connected to the source of the second resistor MN5, the non-inverting input terminal is connected to the input voltage terminal before the disturbance, and the output terminal is connected to the gate of MN5. The other end of the second resistor is grounded; The drains of the MOS transistors MN5 and MP9 are connected; The drain and gate of the MOS transistor MP9 connected to the diode are connected, and the source is connected to the power supply.

5. A single-voltage monitoring power comparison circuit according to claim 1, characterized in that, In the comparison output circuit (5), the current adder and subtractor are based on Kirchhoff's current law and realize the addition and subtraction of current through the topology of the line with common nodes; the two buffers convert the compared current into voltage and output the comparison result to indicate the direction of disturbance.

Images