Method and apparatus for symmetric aging of a clock tree

Abstract

In some aspects, a device includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The device further includes a switching circuit having an output, wherein the switching circuit is configured to switch a logic state at the output of the switching circuit based on the enable signal. The device further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, and the second input of the multiplexer is coupled to the output of the switching circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and couple the selected one of the first input and the second input to the output of the multiplexer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of U.S. Non - provisional application Ser. No. 17 / 655,697, filed on March 21, 2022, in the United States Patent Office, the entire content of which is incorporated herein by reference in its entirety as set forth in full text below and for all applicable purposes. Background Technical Field

[0004] Aspects of the present disclosure generally relate to aging, and more particularly, to aging mitigation. Background Art

[0006] A system may include a clock source (e.g., a phase - locked loop) configured to generate a clock signal for timing the operation of one or more circuits (e.g., sequential logic, processors, memories, etc.) in the system. The system may also include a clock path for distributing the clock signal from the clock source to the one or more circuits. A challenge in clock distribution is that asymmetric aging in the clock path may cause duty - cycle distortion in the clock signal, which may lead to timing issues (e.g., timing violations) in the one or more circuits. Summary of the Invention

[0007] The following presents a simplified generalization of one or more specific implementations in order to provide a basic understanding of such specific implementations. This generalization is not an exhaustive overview of all expected specific implementations, and is neither intended to identify key or important elements of all specific implementations nor to depict the scope of any or all specific implementations. Its sole purpose is to present some concepts of one or more specific implementations in a simplified form as a prelude to the more detailed description that follows.

[0008] A first aspect relates to an apparatus, including. The apparatus includes a gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal. The apparatus further includes a switching circuit having an output, wherein the switching circuit is configured to switch a logical state at the output of the switching circuit based on the enable signal. The apparatus further includes a multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, and the second input of the multiplexer is coupled to the output of the switching circuit. The multiplexer is configured to select one of the first input and the second input based on the enable signal and couple the selected one of the first input and the second input to the output of the multiplexer.

[0009] The second aspect relates to a method for aging balance in a clock path. The method includes: receiving an enable signal; if the enable signal has a first logic state, passing a clock signal to the clock path, and if the enable signal has a second logic state, gating the clock signal; switching the logic state of a switching circuit in response to an edge of the enable signal; and when the clock signal is gated, passing the logic state of the switching circuit to the clock path. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 An example of a system including a clock source, a gating circuit, a clock path, and a circuit in accordance with certain aspects of the present disclosure is shown.

[0011] Figure 2A An example of a clock path including a clock buffer in accordance with certain aspects of the present disclosure is shown.

[0012] Figure 2B An example in which the input dwell of a clock path is low in an idle mode in accordance with certain aspects of the present disclosure is shown.

[0013] Figure 2C A timing diagram that illustrates an example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0014] Figure 2D An example in which the input dwell of a clock path is high in an idle mode in accordance with certain aspects of the present disclosure is shown.

[0015] Figure 2E A timing diagram that illustrates another example of a duty cycle shift in a clock path due to asymmetric aging in accordance with certain aspects of the present disclosure.

[0016] Figure 3 An example of a system including a switching circuit and a multiplexer in accordance with certain aspects of the present disclosure is shown.

[0017] Figure 4A An exemplary embodiment of a switching circuit in accordance with certain aspects of the present disclosure is shown.

[0018] Figure 4B Another exemplary embodiment of a switching circuit in accordance with certain aspects of the present disclosure is shown.

[0019] Figure 5 An exemplary embodiment of a gating circuit in accordance with certain aspects of the present disclosure is shown.

[0020] Figure 6 An example of a latch between a gating circuit and a selection input of a multiplexer in accordance with certain aspects of the present disclosure is shown.

[0021] Figure 7 is a timing diagram illustrating an example of a handover according to certain aspects of the present disclosure.

[0022] Figure 8 illustrates an example of a system including a duty cycle monitor and a control circuit according to certain aspects of the present disclosure.

[0023] Figure 9 is a flowchart illustrating a method of aging in a balanced clock path according to certain aspects of the present disclosure. Detailed Description

[0024] The detailed description set forth below in connection with the appended drawings is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. For a thorough understanding of the various concepts, the detailed description includes specific details. It will be apparent, however, to one of ordinary skill in the art that the concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring such concepts.

[0025] Figure 1 illustrates an example of a system 110 according to certain aspects, the system including a clock source 115, a gating circuit 120, a clock path 130, and a circuit 140. The circuit 140 may include sequential logic, a processor, a memory, etc. The clock source 115 is configured to generate a clock signal and output the clock signal at output 118. The clock source 115 may be implemented using a phase-locked loop (PLL) or another type of clock source. The clock signal is used for the timing operations of the circuit 140.

[0026] The clock path 130 has an input 132 and an output 134. The output 134 is coupled to the circuit 140. The clock path 130 is configured to receive the clock signal at the input 132 and distribute the clock signal to the circuit 140. As used herein, a "clock signal" may be a periodic signal that oscillates between a high level and a low level. The clock signal has a duty cycle, which may be expressed as a percentage or fraction of the clock period (i.e., clock cycle) during which the clock signal is at the high level (i.e., 1).

[0027] The gating circuit 120 (also referred to as a clock gating unit) has a signal input 122, an enable input 124, and an output 126. The signal input 122 is coupled to the output 118 of the clock source 115, and the output 126 is coupled to the input 132 of the clock path 130. The enable input 124 is configured to receive an enable signal, and the signal input 122 is configured to receive a clock signal. In operation, the gating circuit 120 is configured to pass or gate (i.e., block) the clock signal to the output 126 based on the enable signal. For example, the gating circuit 120 can be configured to pass the clock signal to the output 126 when the enable signal has a first logic state and to gate the clock signal when the enable signal has a second logic state. The first logic state can be high (i.e., 1), and the second logic state can be low (i.e., 0), and vice versa. Thus, in this example, when the enable signal transitions from the first logic state to the second logic state, the gating circuit 120 begins to gate the clock signal. When the enable signal transitions from the second logic state to the first logic state, the gating circuit 120 stops gating the clock signal.

[0028] In some aspects, the enable signal is provided by a power management circuit 160 coupled to the enable input 124. In these aspects, the power management circuit 160 controls whether the gating circuit 120 uses the enable signal to pass the clock signal to the clock path 130 or to gate (i.e., block) the clock signal. In one example, the power management circuit 160 can cause the gating circuit 120 to pass the clock signal using the enable signal when the circuit 140 is active (e.g., setting the enable signal to the first logic state), and cause the gating circuit 120 to gate the clock signal using the enable signal when the circuit 140 is in an idle mode (i.e., inactive) to save power. Clock gating is a known technique for reducing dynamic power consumption when a circuit is inactive.

[0029] Although in Figure 1 a single gating circuit 120 is shown between the clock source 115 and the clock path 130, it should be understood that the system 110 can include two or more clock gating circuits (e.g., at different locations along the clock path 130). It should also be understood that the clock path 130 can include multiple branches (not shown) forming a clock tree to distribute the clock signal to one or more other circuits (not shown) in addition to Figure 1 the circuit 140 shown.

[0030] Aging effects such as bias temperature instability (BTI) may degrade the performance of clock path 130 over time. For example, BTI stress in clock path 130 during the idle mode may cause a duty cycle shift in clock path 130 over time, and this duty cycle shift may cause timing problems (e.g., timing violations) in circuit 140.

[0031] Now an example of a duty cycle shift caused by aging will be described with reference to Figures 2A to 2E FIG. Figure 2A An example is shown in which clock path 130 includes clock buffers 220-1 to 220-4 serially coupled between an input 132 and an output 134. Although four clock buffers 220-1 to 220-4 are shown for simplicity in Figure 2A FIG., it should be understood that clock path 130 may include a large number of clock buffers. In the example shown in Figure 2A FIG., each of clock buffers 220-1 to 220-4 is implemented using a respective complementary inverter, which includes a respective transistor (e.g., an n-type field effect transistor) among transistors 225-1 to 225-4 and a respective transistor (e.g., a p-type field effect transistor) among transistors 230-1 to 230-4. However, it should be understood that each of clock buffers 220-1 to 220-4 may be implemented using another type of circuit or logic gate.

[0032] When circuit 140 is in the active mode, gating circuit 120 passes the clock signal to input 132 of clock path 130, and this clock signal propagates through clock buffers 220-1 to 220-4 to circuit 140. When circuit 140 is in the idle mode, gating circuit 120 gates the clock signal and holds (i.e., keeps) input 132 of clock path 130 high or low.

[0033] Figure 2B An example is shown in which gating circuit 120 holds input 132 of clock path 130 low (i.e., logic 0) in the idle mode. Figure 2B Also shown are the logic states at the inputs and outputs of each of clock buffers 220-1 to 220-4. In this example, output 134 of clock path 130 is low (i.e., logic 0) in the idle mode. In this example, transistors 230-1, 225-2, 230-3, and 225-4 are turned on in the idle mode, and transistors 225-1, 230-2, 225-3, and 230-4 are turned off in the idle mode. In Figure 2BAmong them, the transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in the idle mode are shown as thick lines. The transistors 230-1, 225-2, 230-3, and 225-4 that are turned on in the idle mode are stressed in the idle mode, while the transistors 225-1, 230-2, 225-3, and 230-4 that are turned off in the idle mode are not stressed in the idle mode. This results in asymmetric aging, where the transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in the idle mode age faster than the transistors 225-1, 230-2, 225-3, and 230-4 that are not stressed in the idle mode.

[0034] In this example, this asymmetric aging causes the threshold voltages of the transistors 230-1, 225-2, 230-3, and 225-4 that are stressed in the idle mode to shift, resulting in an increase in the falling-edge delay at the output 134 of the clock path 130 relative to the rising-edge delay at the output 134 of the clock path 130. The increase in the falling-edge delay relative to the rising-edge delay causes a duty-cycle shift in the clock path 130. Figure 2C An example of the duty-cycle shift is illustrated in the timing diagram shown. In Figure 2C the example shown, a clock signal 250 with a 50% duty cycle is input to the clock path 130 in the active mode. Figure 2C Also shown is the clock signal 260 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rising edge of the clock signal 250 by a delay T r , and delays the falling edge of the clock signal 250 by a delay T f . As Figure 2C shown, due to asymmetric aging, the delay T f of the falling edge is longer than the delay T r of the rising edge. In this example, the longer delay of the falling edge results in an increased duty cycle of the clock signal 260 at the output 134 of the clock path 130 (i.e., results in a duty cycle greater than 50%).

[0035] In Figure 2B and Figure 2C the example shown, the gating circuit 120 holds the input 132 of the clock path 130 low in the idle mode. For the case where the gating circuit 120 holds the input 132 of the clock path 130 high in the idle mode, asymmetric aging also occurs. In this regard, Figure 2D shown is an example where the gating circuit 120 holds the input 132 of the clock path 130 high (i.e., logic 1) in the idle mode. Figure 2DAlso shown are the logical states at the inputs and outputs of each of the clock buffers 220-1 through 220-4. In this example, the output 134 of the clock path 130 is high (i.e., logic 1) in the idle mode. In this example, the transistors 225-1, 230-2, 225-3, and 230-4 are turned on in the idle mode, and the transistors 230-1, 225-2, 230-3, and 225-4 are turned off in the idle mode. In Figure 2D , the transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are shown in thick lines. The transistors 225-1, 230-2, 225-3, and 230-4 that are turned on in the idle mode are stressed in the idle mode, while the transistors 230-1, 225-2, 230-3, and 225-4 that are turned off in the idle mode are not stressed in the idle mode, which results in asymmetric aging, where the transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in the idle mode age faster than the transistors 230-1, 225-2, 230-3, and 225-4.

[0036] In this example, this asymmetric aging causes the threshold voltages of the transistors 225-1, 230-2, 225-3, and 230-4 that are stressed in the idle mode to shift, resulting in an increase in the rise-edge delay at the output 134 of the clock path 130 relative to the fall-edge delay at the output 134 of the clock path 130. The increase in the rise-edge delay relative to the fall-edge delay causes a duty-cycle shift in the clock path 130. Figure 2E An example of the duty-cycle shift is illustrated in the timing diagram shown. In Figure 2E the example shown, a clock signal 250 having a 50% duty cycle is input to the clock path 130 in the active mode. Figure 2E Also shown is the clock signal 270 at the output 134 of the clock path 130 after propagating through the clock path 130. The clock path 130 delays the rise edge of the clock signal 250 by a delay T r and delays the fall edge of the clock signal 250 by a delay T f . As Figure 2E shown, due to the asymmetric aging, the delay T r of the rise edge is longer than the delay T f of the fall edge. In this example, the longer delay of the rise edge results in a decrease in the duty cycle of the clock signal 270 at the output 134 of the clock path 130 (i.e., results in a duty cycle of less than 50%).

[0037] Thus, the asymmetric aging in the idle mode causes a duty cycle shift (i.e., duty cycle distortion) over time in the clock path 130. The duty cycle shift increases or decreases the duty cycle of the clock signal depending on, for example, whether the input 132 of the clock path 130 is held low or high in the idle mode by the gating circuit 120 and the number of clock buffers 220-1 to 220-4 in the clock path 130. The duty cycle shift may cause timing issues in the circuit 140. For an example where the circuit 140 includes sequential logic (e.g., flip-flops), the duty cycle shift may cause setup time and / or hold time violations.

[0038] To address the duty cycle shift (i.e., distortion) caused by asymmetric aging, aspects of the present disclosure provide a switching circuit that alternately holds the input of the clock path low and high in the idle mode, rather than holding the input of the clock path in the same logic state in the idle mode. By alternately holding the input of the clock path low and high, the switching circuit helps balance the aging of the transistors in the clock path to reduce duty cycle distortion, as further discussed below.

[0039] Figure 3 An example of a system 310 is shown that includes the clock source 115, gating circuit 120, clock path 130, and circuit 140 discussed above. According to certain aspects, the system 310 further includes a switching circuit 320 and a multiplexer 330 to help balance the aging in the clock path 130, as further discussed below.

[0040] In this example, the switching circuit 320 has an input 322 and an output 324. The switching circuit 320 is configured to receive an enable signal at the input 322 and switch (i.e., change) the logic state at the output 324 in response to an edge of the enable signal. Thus, if the current logic state at the output 324 is 1 (i.e., high), the switching circuit 320 changes the logic state at the output 324 to 0 (i.e., low) at the edge of the enable signal. If the current logic state at the output 324 is 0, the switching circuit 320 changes the logic state at the output 324 to 1 at the edge of the enable signal. In one example, the switching circuit 320 is positive edge-triggered, where the switching circuit 320 switches the logic state at the output 324 on the rising edge of the enable signal. In another example, the switching circuit 320 is negative edge-triggered, where the switching circuit 320 switches the logic state at the output 324 on the falling edge of the enable signal. The switching circuit 320 can be implemented using a switching flip-flop or another type of switching circuit. As further discussed below, the switching circuit 320 is used to alternately hold the input 132 of the clock path 130 low and high in the idle mode to balance the aging in the clock path 130.

[0041] The multiplexer 330 has a first input 332, a second input 334, an output 336, and a select input 338. The first input 332 is coupled to the output 126 of the gating circuit 120, the second input 334 is coupled to the output 324 of the switching circuit 320, and the output 336 is coupled to the input 132 of the clock path 130. In some aspects, the multiplexer 330 is configured to receive an enable signal at the select input 338, select one of the first input 332 and the second input 334 based on the enable signal, and couple the selected one of the first input 332 and the second input 334 to the output 336.

[0042] In one example, the multiplexer 330 is configured to select the first input 332 when the enable signal has a first logic state and to select the second input 334 when the enable signal has a second state. As discussed above, the gating circuit 120 is configured to pass the clock signal when the enable signal has a first logic state and to gate the clock signal when the enable signal has a second logic state. Thus, in this example, when the gating circuit 120 passes the clock signal, the multiplexer 330 couples the output 126 of the gating circuit 120 to the input 132 of the clock path 130. In this case, the multiplexer 330 passes the clock signal from the gating circuit 120 to the clock path 130. Moreover, in this example, when the gating circuit 120 gates the clock signal in the idle mode, the multiplexer 330 couples the output 324 of the switching circuit 320 to the input 132 of the clock path 130. Thus, the output 324 of the switching circuit 320 controls whether the input 132 of the clock path 130 stays low or high in the idle mode.

[0043] Exemplary operation of the system 310 will now be described according to some aspects.

[0044] In this example, when the circuit 140 is in the idle mode (i.e., inactive), the power management circuit 160 causes the gating circuit 120 to gate the clock signal to save power. To this end, the power management circuit 160 sets the enable signal to a second logic state in the idle mode, which causes the gating circuit 120 to gate the clock signal and the multiplexer 330 to select the second input 334. Since the multiplexer 330 selects the second input 334 in the idle mode, the output 324 of the switching circuit 320 is coupled to the input 132 of the clock path 130 in the idle mode, and thus determines whether the input 132 of the clock path 130 stays low or high in the idle mode.

[0045] Over time, the power management circuit 160 causes the gating circuit 120 to gate the clock signal during many idle cycles, where each "idle cycle" is a period of time during which the circuit 140 is in an idle mode (i.e., inactive). The idle cycles are separated by active cycles, where each "active cycle" is a period of time during which the circuit 140 is active. During each active cycle, the power management circuit 160 causes the gating circuit 120 to pass the clock signal and causes the multiplexer 330 to select the first input 332 (e.g., by setting an enable signal to a first logic state).

[0046] For each idle cycle, the enable signal has a rising edge and a falling edge. This is because the enable signal transitions from a first logic state to a second logic state at the start of the idle cycle to gate the clock signal, and transitions from the second logic state to the first logic state at the end of the idle cycle to ungate the clock signal. For an example where the first logic state is 1 and the second logic state is 0, the gating circuit 120 starts gating the clock signal at the falling edge of the enable signal at the start of the idle cycle, and stops gating the clock signal at the rising edge of the enable signal at the end of the idle cycle. For an example where the first logic state is 0 and the second logic state is 1, the gating circuit 120 starts gating the clock signal at the rising edge of the enable signal at the start of the idle cycle, and stops gating the clock signal at the falling edge of the enable signal at the end of the idle cycle. Thus, in both examples, the enable signal has both a rising edge and a falling edge for each idle cycle.

[0047] Since the enable signal has both a rising edge and a falling edge for each idle cycle, the switching circuit 320 switches the logic state at the output 324 once for each idle cycle, regardless of whether the switching circuit 320 is positive-edge triggered or negative-edge triggered. The switching for each idle cycle causes the output 324 of the switching circuit 320 to alternate between low (i.e., 0) and high (i.e., 1) during multiple idle cycles. Thus, if the output 324 of the switching circuit 320 is 1 during the current idle cycle, the output 324 will be 0 during the next idle cycle, and vice versa.

[0048] Because the output 324 of the switching circuit 320 alternates between low and high during multiple idle cycles, and the multiplexer 330 couples the output 324 of the switching circuit 320 to the input 132 of the clock path 130 in the idle mode, the output 324 of the switching circuit 320 alternately holds the input 132 of the clock path 130 low and high during the multiple idle cycles. Thus, if the input 132 of the clock path 130 holds low during the current idle cycle, the input 132 of the clock path 130 will hold high during the next idle cycle, and vice versa.

[0049] Assume that the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays low is approximately equal to the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays high. Then, the input 132 of the clock path 130 spends approximately equal amounts of time staying low and staying high in the idle mode. Thus, the aging of the transistors (e.g., transistors 225-1 to 225-4 and 230-1 to 230-4) in the clock path 130 is approximately balanced (i.e., symmetric). Compared with the case where the input 132 of the clock path 130 stays in the same logic state for each idle cycle (which results in asymmetric aging of the transistors in the clock path 130), the balanced (i.e., symmetric) aging reduces the duty cycle distortion.

[0050] Figure 4A An exemplary embodiment of the switching circuit 320 according to certain aspects is shown. In this example, the switching circuit 320 includes a flip-flop 410 (e.g., a D flip-flop) and an inverter 420. The flip-flop 410 has a clock input 412, a data input 414, and an output 416. The clock input 412 is coupled to the input 322 of the switching circuit 320 to receive an enable signal, and the output 416 is coupled to the output 324 of the switching circuit 320. The inverter 420 has an input 422 and an output 424. The input 422 of the inverter 420 is coupled to the output 416 of the flip-flop 410, and the output 424 of the inverter 420 is coupled to the data input 414 of the flip-flop 410. Thus, the inverter 420 inverts the logic state at the output 416 of the flip-flop 410 and inputs the inverted logic state at the data input 414 of the flip-flop 410.

[0051] In one example, the flip-flop 410 is positive-edge triggered, where the flip-flop 410 is configured to latch the logic state at the data input 414 at the rising edge of the enable signal and output the latched logic state at the output 416. In this example, the inverter 420 between the output 416 of the flip-flop 410 and the data input 414 of the flip-flop 410 causes the logic state at the output 416 of the flip-flop 410 (and thus at the output 324 of the switching circuit 320) to switch at the rising edge of the enable signal.

[0052] In another example, the flip-flop 410 is negative-edge triggered, where the flip-flop 410 is configured to latch the logic state at the data input 414 at the falling edge of the enable signal and output the latched logic state at the output 416. In this example, the inverter 420 between the output 416 of the flip-flop 410 and the data input 414 of the flip-flop 410 causes the logic state at the output 416 of the flip-flop 410 (and thus at the output 324 of the switching circuit 320) to switch at the falling edge of the enable signal.

[0053] Figure 4B Shows another exemplary embodiment of the switching circuit 320 according to certain aspects. In this example, the switching circuit 320 includes a flip-flop 430 (e.g., a D flip-flop) having a clock input 432, a data input 434, a first output 436, and a second output 438. The first output 436 and the second output 438 are complementary (i.e., the logical state at the second output 438 is the inverse of the logical state at the first output 436). In this example, the clock input 432 is coupled to the input 322 of the switching circuit 320 to receive an enable signal, and the first output 436 is coupled to the output 324 of the switching circuit 320. The second output 438 of the flip-flop 430 is coupled to the data input 434 of the flip-flop 430.

[0054] In one example, the flip-flop 430 is positive edge-triggered, where the flip-flop 430 is configured to latch the logical state at the data input 434 at the rising edge of the enable signal, output the latched logical state at the first output 436, and output the inverse of the latched logical state at the second output 438. In this example, coupling the data input 434 to the second output 438 causes the logical state at the first output 436 of the flip-flop 430 (and thus at the output 324 of the switching circuit 320) to switch at the rising edge of the enable signal.

[0055] In another example, the flip-flop 430 is negative edge-triggered, where the flip-flop 430 is configured to latch the logical state at the data input 434 at the falling edge of the enable signal, output the latched logical state at the first output 436, and output the inverse of the latched logical state at the second output 438. In this example, coupling the data input 434 to the second output 438 causes the logical state at the first output 436 of the flip-flop 430 (and thus at the output 324 of the switching circuit 320) to switch at the falling edge of the enable signal.

[0056] It should be understood that the switching circuit 320 is not limited to Figure 4A and Figure 4B the exemplary embodiments shown, and the switching circuit 320 can be implemented using other types of switching circuits.

[0057] Figure 5Illustrates an exemplary embodiment of the gating circuit 120 in accordance with certain aspects. In this example, the gating circuit 120 includes a latch 510 and a gate 520. The latch 510 has a first input 512, a second input 514, and an output 516. The first input 512 is coupled to the enable input 124 of the gating circuit 120 to receive an enable signal, and the second input 514 is coupled to the signal input 122 of the gating circuit 120 to receive a clock signal. In certain aspects, the latch 510 is configured to latch the logical state of the enable signal at the falling edge of the clock signal and output the latched logical state of the enable signal at the output 516. In these aspects, the latch 510 can be implemented using a negative-edge-triggered flip-flop or another type of latch.

[0058] The gate 520 has a first input 522, a second input 524, and an output 526. The first input 522 is coupled to the output 516 of the latch 510, the second input 524 is coupled to the signal input 122 of the gating circuit 120 to receive a clock signal, and the output 526 is coupled to the output 126 of the gating circuit 120. In Figure 5 the example, the gate 520 includes an "AND" gate, which can be implemented using a NAND gate and an inverter. However, it should be understood that the gate 520 is not limited to this example.

[0059] In this example, the first logical state of the enable signal discussed above is 1 and the second logical state of the enable signal discussed above is 0. When the enable signal is 1, the latch 510 latches the 1 at the falling edge of the clock signal and outputs the 1 to the first input 522 of the gate 520. The 1 at the first input 522 of the gate 520 causes the gate 520 to pass the clock signal at the second input 524 to the output 526 (and thus to the output 126 of the gating circuit 120). Thus, in this example, when the enable signal is 1, the gating circuit 120 passes the clock signal.

[0060] When the enable signal is 0, the latch 510 latches the 0 at the falling edge of the clock signal and outputs the 0 to the first input 522 of the gate 520. The 0 at the first input 522 of the gate 520 causes the gate 520 to output a 0 at the output 526 (and thus at the output 126 of the gating circuit 120), regardless of the logical state of the clock signal at the second input 524 of the gate 520. This effectively blocks the clock signal at the second input 524 from reaching the output 526, thereby gating the clock signal. Thus, in this example, when the enable signal is 0, the gating circuit 120 gates the clock signal. By latching the logical state of the enable signal at the falling edge of the clock signal, the latch 510 helps ensure that the gate 520 begins gating the clock signal when the clock signal is low (i.e., 0) to prevent glitches at the output 126 of the gating circuit 120.

[0061] It should be understood that the gating circuit 120 is not limited to Figure 5 the exemplary specific implementation shown, and the gating circuit 120 can be implemented using various arrangements of one or more logic gates and one or more latches.

[0062] In some aspects, one or more latches can be used to control the timing of the input of the enable signal to the selection input 338 of the multiplexer 330. In this regard, Figure 6 an example of a second latch 610 coupled between the output 516 of the latch 510 in the gating circuit 120 and the selection input 338 of the multiplexer 330 is shown. In this example, the second latch 610 has a first input 612, a second input 614, and an output 616. The first input 612 is coupled to the output 516 of the latch 510 in the gating circuit 120 and thus receives the enable signal from the output 516 of the latch 510. The second input 614 is coupled to the clock source 115 ( Figure 3 shown in) to receive a clock signal, and the output 616 is coupled to the selection input 338 of the multiplexer 330. In some aspects, the second latch 610 is configured to latch the logical state of the enable signal at the rising edge of the clock signal and output the latched logical state of the enable signal to the selection input 338 of the multiplexer 330 via the output 616. In these aspects, the second latch 610 can be implemented using a positive edge-triggered flip-flop or another type of latch.

[0063] In this example, the multiplexer 330 can be configured to select the first input 332 when the enable signal is 1 and select the second input 334 when the enable signal is 0. Thus, in this example, when the gating circuit 120 passes the clock signal, the multiplexer 330 selects the first input 332, and when the gating circuit 120 gates the clock signal, the multiplexer 330 selects the second input 334. As discussed above, the gating circuit 120 in this example starts gating the clock signal when the enable signal transitions from 1 to 0. In this example, the second latch 610 delays the transition of the enable signal from 1 to 0 by half a cycle of the clock signal with respect to the output 516 of the latch 510 in the gating circuit 120. Thus, when the gating circuit 120 starts gating the clock signal, the multiplexer 330 switches from the first input 332 to the second input 334 after a delay of approximately half a clock cycle. This helps ensure that the multiplexer 330 does not switch from the first input 332 to the second input 334 before the clock signal is gated.

[0064] Figure 7 is a timing diagram showing an example of switching according to some aspects of the present disclosure. More specifically, Figure 7An example of an enable signal (labeled "Enable") and a signal at the output 336 of the multiplexer 330 (labeled "Multiplexed Output") is shown. In Figure 7 the example, when the enable signal is 1, the clock signal is ungated, and when the enable signal is 0, the clock signal is gated. Thus, in this example, the enable signal is 0 during the idle period. As Figure 7 shown, the output 336 of the multiplexer 330 switches between 1 and 0 across the idle period due to the switching of the switching circuit 320. In Figure 7 the example, the output 336 of the multiplexer 330 is 1 (i.e., high) during odd idle periods (e.g., t1, t3,...) and 0 (i.e., low) during even idle periods (e.g., t2, t4,...). However, it should be understood that the present disclosure is not limited to this example.

[0065] Assuming that the cumulative duration of the idle periods during which the input 132 of the clock path 130 is 0 (i.e., dwells low) is approximately equal to the cumulative duration of the idle periods during which the input 132 of the clock path 130 is 1 (i.e., dwells high), then the input 132 of the clock path 130 spends approximately equal amounts of time dwelling low and dwelling high in the idle mode, which balances the aging of the transistors in the clock path 130. Balanced (i.e., symmetric) aging reduces the duty cycle shift in the clock path 130.

[0066] However, in some cases, the cumulative duration of the idle periods during which the input 132 of the clock path 130 is 0 (i.e., dwells low) is not approximately equal to the cumulative duration of the idle periods during which the input 132 of the clock path 130 is 1 (i.e., dwells high). This can lead to a duty cycle offset in the clock path 130, which can push the duty cycle of the clock signal at the output 134 of the clock path 130 outside the acceptable range. The duty cycle shift in the clock path 130 can also be caused by environmental conditions and / or other factors.

[0067] To address this issue, the system may include circuitry configured to deactivate (i.e., override) the switching in the idle mode when a duty cycle shift in clock path 130 pushes the clock signal at output 134 of clock path 130 outside an acceptable range. In such a case, the circuitry may hold input 132 of clock path 130 high or low depending on whether the cumulative duration of the idle cycles during which input 132 of clock path 130 stays low is greater than or less than the cumulative duration of the idle cycles during which input 132 of clock path 130 stays high. For example, if the duty cycle shift in clock path 130 is caused by the cumulative duration of the idle cycles during which input 132 of clock path 130 stays low being greater than the cumulative duration of the idle cycles during which input 132 of clock path 130 stays high, the circuitry may hold input 132 of clock path 130 high in the idle mode to shift the duty cycle shift in the opposite direction. When the duty cycle of the clock signal shifts back within the acceptable range, the circuitry may re-enable the switching in the idle mode.

[0068] In this regard, Figure 8 An example of system 805 is shown that includes gating circuit 120, switching circuit 320, multiplexer 330, and clock path 130 discussed above. According to certain aspects, system 805 also includes duty cycle monitor 810 and control circuit 820. Moreover, in this example, switching circuit 320 also has a reset input 832 and a set input 834.

[0069] In one example, reset input 832 is asserted by inputting a 1 to reset input 832, and set input 834 is asserted by inputting a 1 to set input 834. However, it should be understood that the present disclosure is not limited to this example. When reset input 832 is asserted, switching circuit 320 deactivates (i.e., overrides) the switching and outputs a 0 at output 324. When set input 834 is asserted, switching circuit 320 deactivates (i.e., overrides) the switching and outputs a 1 at output 324. When neither reset input 832 nor set input 834 is asserted, switching circuit 320 enables the switching and operates in the manner discussed above with reference to Figure 3 as described.

[0070] Duty cycle monitor 810 has an input 812 and an output 814. Input 812 may be coupled to output 134 of clock path 130. In certain aspects, duty cycle monitor 810 is configured to measure the duty cycle of the clock signal at output 134 of clock path 130 and output a measurement signal indicative of the measured duty cycle at output 814. Since in this example duty cycle monitor 810 is coupled to output 134 of clock path 130, duty cycle monitor 810 is able to measure the shift in the duty cycle of the clock signal caused by clock path 130.

[0071] The control circuit 820 has an input 822, a first output 824, and a second output 826. The input 822 is coupled to the output of the duty cycle monitor 810, the first output 824 is coupled to the reset input 832 of the switching circuit 320, and the second output 826 is coupled to the set input 834 of the switching circuit 320.

[0072] In operation, the control circuit 820 receives a measurement signal from the duty cycle monitor 810 via the input 822. The control circuit 820 can then determine whether the measurement signal is within an acceptable range. The acceptable range can correspond to a duty cycle range that does not cause a timing violation in the circuit 140. In one example, the acceptable range can be defined by a first threshold and a second threshold. In this example, when the measurement signal is between the first threshold and the second threshold, the control circuit 820 can determine that the measurement signal is within the acceptable range. When the measured value is between the first threshold and the second threshold, the control circuit 820 de-asserts both the reset input 832 and the set input 834 of the switching circuit 320. In this case, as discussed above with reference to Figure 3 the switching circuit 320 switches the output 324.

[0073] In this example, the first threshold can define the upper limit of the acceptable range, where when the measurement signal is higher than the first threshold, the duty cycle is considered too high. When the measurement signal is higher than the first threshold, the control circuit 820 asserts one of the reset input 832 and the set input 834. For example, if the measurement signal is higher than the first threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays low is greater than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays high, the control circuit 820 can assert the set input 834 to keep the input 132 of the clock path 130 high. On the other hand, if the measurement signal is higher than the first threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays low is less than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays high, the control circuit 820 can assert the reset input 832 to keep the input 132 of the clock path 130 low. Whether the measurement signal is higher than the first threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays low is greater than or less than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 stays high can depend on (for example) the number of clock buffers in the clock path 130 and / or the specific implementation of the clock buffers in the clock path 130.

[0074] In this example, the second threshold may define the lower limit of an acceptable range, where when the measurement signal is below the second threshold, the duty cycle of the clock signal is considered too low. When the measurement signal is below the second threshold, the control circuit 820 asserts one of the reset input 832 and the set input 834. For example, if the measurement signal is below the second threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides low is greater than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides high, the control circuit 820 may assert the set input 834 to hold the input 132 of the clock path 130 high. On the other hand, if the measurement signal is below the second threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides low is less than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides high, the control circuit 820 may assert the reset input 832 to hold the input 132 of the clock path 130 low. Whether the measurement signal is below the second threshold when the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides low is greater than or less than the cumulative duration of the idle cycles during which the input 132 of the clock path 130 resides high may depend on (for example) the number of clock buffers in the clock path 130 and / or the specific implementation of the clock buffers in the clock path 130.

[0075] In this example, when the measurement signal is above the first threshold and when the measurement signal is below the second threshold, the control circuit 820 asserts different ones of the reset input 832 and the set input 834. For example, if the control circuit 820 asserts the reset input 832 when the measurement signal is above the first threshold, the control circuit 820 asserts the set input 834 when the measurement signal is below the second threshold. On the other hand, if the control circuit 820 asserts the set input 834 when the measurement signal is above the first threshold, the control circuit 820 asserts the reset input 832 when the measurement signal is below the second threshold.

[0076] Figure 9 A method 900 for aging compensation in a balanced clock path is illustrated. The clock path may correspond to the clock path 130.

[0077] At block 910, an enable signal is received. For example, the enable signal may be received by the gating circuit 120, the switching circuit 320, and / or the multiplexer 330.

[0078] At block 920, if the enable signal has a first logic state, the clock signal is passed to the clock path. The clock signal may be passed by the gating circuit 120 and / or the multiplexer 330.

[0079] At block 930, gate the clock signal if the enable signal has a second logic state. For example, the clock signal may be gated by gating circuit 120. The first logic state may be 1 and the second logic state may be 0, or vice versa.

[0080] At block 940, switch the logic state of the switching circuit in response to an edge of the enable signal. For example, the logic state of the switching circuit may be switched by switching circuit 320. The edge of the enable signal may be a rising edge or a falling edge.

[0081] At block 950, transfer the logic state of the switching circuit to the clock path when the clock signal is gated. For example, the logic state of the switching circuit may be transferred to the clock path by multiplexer 330.

[0082] Power management circuit 160 and control circuit 620 may each be implemented using a general-purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete hardware components (e.g., logic gates), or any combination thereof, designed to perform the functions described herein. The processor may perform the functions by executing software including code for performing the functions described herein. The software may be stored on a computer-readable storage medium such as RAM, ROM, EEPROM, optical disk, and / or magnetic disk.

[0083] Specific implementation examples are described in the following numbered clauses:

[0084] 1. An apparatus, the apparatus comprising:

[0085] A gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal;

[0086] A switching circuit having an output, wherein the switching circuit is configured to switch the logic state at the output of the switching circuit based on the enable signal; and

[0087] A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the switching circuit, and wherein the multiplexer is configured to:

[0088] Select one of the first input and the second input based on the enable signal; and

[0089] Couple the selected one of the first input and the second input to the output of the multiplexer.

[0090] 2. The device according to clause 1, wherein the signal input of the gating circuit is coupled to a clock source.

[0091] 3. The device according to clause 2, wherein the output of the multiplexer is coupled to a clock path including a clock buffer coupled in series.

[0092] 4. The device according to any one of clauses 1 to 3, wherein the switching circuit is configured to switch the logic state at the output of the switching circuit in response to an edge of the enable signal.

[0093] 5. The device according to any one of clauses 1 to 4, wherein:

[0094] The gating circuit is configured to receive a clock signal at the signal input, pass the clock signal to the output of the gating circuit if the enable signal is high, and gate the clock signal if the enable signal is low;

[0095] And

[0096] The multiplexer is configured to: select the first input if the enable signal is high, and select the second input if the enable signal is low.

[0097] 6. The device according to any one of clauses 1 to 4, wherein:

[0098] The gating circuit is configured to receive a clock signal at the signal input, pass the clock signal to the output of the gating circuit if the enable signal is low, and gate the clock signal if the enable signal is high;

[0099] And

[0100] The multiplexer is configured to: select the first input if the enable signal is low, and select the second input if the enable signal is high.

[0101] 7. The device according to any one of clauses 1 to 6, wherein the switching circuit includes:

[0102] A flip - flop having a data input, a clock input, and an output, wherein

[0103] The clock input of the flip - flop is configured to receive the enable signal, and the output of the flip - flop is coupled to the output of the switching circuit; and

[0104] An inverter coupled between the output of the flip - flop and the data input of the flip - flop.

[0105] 8. The device according to any one of clauses 1 to 6, wherein the switching circuit comprises:

[0106] A flip-flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flip-flop is configured to receive the enable signal, the first output is coupled to the output of the switching circuit, the second output is coupled to the data input, and the first output and the second output are complementary.

[0107] 9. The device according to any one of clauses 1 to 8, further comprising:

[0108] A clock path coupled to the output of the multiplexer, the clock path comprising clock buffers coupled in series;

[0109] A duty cycle monitor coupled to the clock path; and

[0110] A control circuit coupled to the duty cycle monitor and coupled to at least one of the set input and the reset input of the switching circuit.

[0111] 10. The device according to clause 9, wherein:

[0112] The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; and

[0113] The control circuit is configured to: assert one of the set input and the reset input of the switching circuit if the measurement signal is higher than a threshold.

[0114] 11. The device according to clause 9, wherein:

[0115] The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; and

[0116] The control circuit is configured to: assert one of the set input and the reset input of the switching circuit if the measurement signal is lower than a threshold.

[0117] 12. The device according to clause 9, wherein:

[0118] The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; and

[0119] The control circuit is configured to: assert the reset input of the switching circuit if the measurement signal is higher than a first threshold, and assert the set input of the switching circuit if the measurement signal is lower than a second threshold.

[0120] 13. The apparatus according to clause 9, wherein:

[0121] The duty cycle monitor is configured to measure the duty cycle of a clock signal on the clock path and output a measurement signal indicative of the measured duty cycle to the control circuit; and

[0122] The control circuit is configured to: assert the set input of the switching circuit if the measurement signal is higher than a first threshold, and assert the reset input of the switching circuit if the measurement signal is lower than a second threshold.

[0123] 14. The apparatus according to any one of clauses 1 to 13, wherein the gating circuit comprises:

[0124] A latch having a first input, a second input, and an output, wherein

[0125] The first input of the latch is coupled to the enable input of the gating circuit, and the second input of the latch is coupled to the signal input of the gating circuit; and

[0126] A gate having a first input, a second input, and an output, wherein the first input of the gate is coupled to the output of the latch, the second input of the latch is coupled to the signal input of the gating circuit, and the output of the gate is coupled to the output of the gating circuit.

[0127] 15. The apparatus according to clause 14, wherein the gate comprises an AND gate.

[0128] 16. A method for equalizing aging in a clock path, the method comprising:

[0129] Receiving an enable signal;

[0130] If the enable signal has a first logic state, passing a clock signal to the clock path;

[0131] If the enable signal has a second logic state, gating the clock signal;

[0132] Switching the logic state of a switching circuit in response to an edge of the enable signal; and

[0133] When the clock signal is gated, the logic state of the switching circuit is passed to the clock path.

[0134] 17. The method according to clause 16, wherein the first logic state is one and the second logic state is zero.

[0135] 18. The method according to clause 16, wherein the first logic state is zero and the second logic state is one.

[0136] 19. The method according to any one of clauses 16 to 18, wherein the edge of the enable signal is a rising edge.

[0137] 20. The method according to any one of clauses 16 to 18, wherein the edge of the enable signal is a falling edge.

[0138] Within this disclosure, the term "exemplary" is used to mean "serving as an example, instance, or illustration". Any particular implementation or aspect described herein as "exemplary" is not necessarily to be construed as superior to or better than other aspects of the disclosure. Similarly, the term "aspect" does not require that all aspects of the disclosure include the recited features, advantages, or modes of operation. The term "coupled" is used herein to refer to a direct or indirect electrical coupling between two structures.

[0139] The foregoing description of the disclosure has been provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device, the device comprising: A gating circuit having an enable input, a signal input, and an output, wherein the enable input is configured to receive an enable signal; A switching circuit having an output, wherein the switching circuit is configured to switch a logical state at the output of the switching circuit based on the enable signal; And A multiplexer having a first input, a second input, and an output, wherein the first input of the multiplexer is coupled to the output of the gating circuit, the second input of the multiplexer is coupled to the output of the switching circuit, and wherein the multiplexer is configured to: Select one of the first input and the second input based on the enable signal; And Couple the selected one of the first input and the second input to the output of the multiplexer.

2. The device according to claim 1, wherein the signal input of the gating circuit is coupled to a clock source.

3. The device according to claim 2, wherein the output of the multiplexer is coupled to a clock path including clock buffers coupled in series.

4. The device according to claim 1, wherein the switching circuit is configured to switch the logical state at the output of the switching circuit in response to an edge of the enable signal.

5. The device according to claim 1, wherein: The gating circuit is configured to receive a clock signal at the signal input, pass the clock signal to the output of the gating circuit if the enable signal is high, and gate the clock signal if the enable signal is low; And The multiplexer is configured to: select the first input if the enable signal is high, and select the second input if the enable signal is low.

6. The device according to claim 1, wherein: The gating circuit is configured to receive a clock signal at the signal input, pass the clock signal to the output of the gating circuit if the enable signal is low, and gate the clock signal if the enable signal is high; And The multiplexer is configured to: select the first input if the enable signal is low, and select the second input if the enable signal is high.

7. The device according to claim 1, wherein the switching circuit comprises: A flip-flop having a data input, a clock input, and an output, wherein the clock input of the flip-flop is configured to receive the enable signal, and the output of the flip-flop is coupled to the output of the switching circuit; And An inverter coupled between the output of the flip-flop and the data input of the flip-flop.

8. The device according to claim 1, wherein the switching circuit comprises: A flip-flop having a data input, a clock input, a first output, and a second output, wherein the clock input of the flip-flop is configured to receive the enable signal, the first output is coupled to the output of the switching circuit, the second output is coupled to the data input, and the first output and the second output are complementary.

9. The apparatus according to claim 1, further comprising: A clock path coupled to the output of the multiplexer, the clock path including clock buffers coupled in series; A duty cycle monitor coupled to the clock path; And A control circuit coupled to the duty cycle monitor and coupled to at least one of the set input and the reset input of the switching circuit.

10. The apparatus according to claim 9, wherein: The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; And The control circuit is configured to assert one of the set input and the reset input of the switching circuit if the measurement signal is higher than a threshold.

11. The apparatus according to claim 9, wherein: The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; And The control circuit is configured to assert one of the set input and the reset input of the switching circuit if the measurement signal is lower than a threshold.

12. The apparatus according to claim 9, wherein: The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; And The control circuit is configured to assert the reset input of the switching circuit if the measurement signal is higher than a first threshold and assert the set input of the switching circuit if the measurement signal is lower than a second threshold.

13. The apparatus according to claim 9, wherein: The duty cycle monitor is configured to measure the duty cycle of the clock signal on the clock path and output a measurement signal indicating the measured duty cycle to the control circuit; And The control circuit is configured to assert the set input of the switching circuit if the measurement signal is higher than a first threshold and assert the reset input of the switching circuit if the measurement signal is lower than a second threshold.

14. The apparatus according to claim 1, wherein the gating circuit includes: A latch having a first input, a second input, and an output, wherein the first input of the latch is coupled to the enable input of the gating circuit and the second input of the latch is coupled to the signal input of the gating circuit; And a gate having a first input, a second input, and an output, wherein the first input of the gate is coupled to the output of the latch, the second input of the latch is coupled to the signal input of the gating circuit, and the output of the gate is coupled to the output of the gating circuit.

15. The apparatus of claim 14, wherein the gate comprises an AND gate.

16. A method for aging compensation in a balanced clock path, the method comprising: receiving an enable signal; if the enable signal has a first logic state, passing a clock signal to the clock path; if the enable signal has a second logic state, gating the clock signal; switching a logic state of a switching circuit in response to an edge of the enable signal; and when the clock signal is gated, passing the logic state of the switching circuit to the clock path.

17. The method of claim 16, wherein the first logic state is one and the second logic state is zero.

18. The method of claim 16, wherein the first logic state is zero and the second logic state is one.

19. The method of claim 16, wherein the edge of the enable signal is a rising edge.

20. The method of claim 16, wherein the edge of the enable signal is a falling edge.

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