A bridging system and computing architecture

Abstract

The present invention discloses a bridge system and computing architecture in the field of computer technology. The bridge system provided by the present invention is divided into a root device bridge controller and a slave device bridge controller. The two controllers communicate using the target bus standard, and the address configuration of the two controllers can be realized without the help of a host processor. The communication process does not require the participation of an external CPU, which reduces the complexity of chip configuration and communication; while ensuring high-speed data transmission, the system architecture is streamlined and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a bridging system and a computing architecture. Background Art

[0002] At present, the communication between the two chips is generally implemented based on private protocols, and the cost of designing and maintaining private protocols is relatively high, and the relevant configuration of the chips needs to be controlled by the host. For example, the host processor configures the bus address of the GPU (Graphics Processing Unit) device, which increases the complexity of chip configuration and communication.

[0003] Therefore, how to reduce the complexity of chip configuration and communication is a problem that needs to be solved by those skilled in the art. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a bridge system and computing architecture to reduce the complexity of chip configuration and communication. The specific scheme is as follows:

[0005] In a first aspect, the present invention provides a bridging system, comprising: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate via a target bus standard;

[0006] Wherein, the root device bridge controller includes: a target bus configuration module, a request management module and a first address management module;

[0007] The target bus configuration module is used to: configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs;

[0008] The request management module is used to: respond to the first request packet sent by the slave device bridge controller;

[0009] The first address management module is used to: convert the first request packet from the object bus standard to the target bus standard;

[0010] Wherein, the slave device bridge controller includes: a request parsing module, a second address management module, a data mover and an interrupt management module;

[0011] The request parsing module is used to: parse the second request packet sent by the root device bridge controller;

[0012] The second address management module is used to: convert the second request packet from the target bus standard to the object bus standard;

[0013] The data mover is used to implement direct memory access according to the parsing result of the second request packet;

[0014] The interrupt management module is used to manage the interrupt signal between the root device bridge controller and the target bus standard.

[0015] Optionally, the target bus configuration module includes:

[0016] A slave device configuration unit, used for performing base address configuration, register configuration and interrupt configuration on the slave device;

[0017] The root device configuration unit is used to perform base address configuration and register configuration on the root device.

[0018] Optionally, the slave device configuration unit is used to: after writing all 1s to the base address register in the slave device, read a register value from the base address register, invert the read register value and increment it by one to obtain the bus space size corresponding to the base address register.

[0019] Optionally, the first address management module includes:

[0020] A first root conversion unit, configured to convert a request based on the object bus standard into a request based on the object bus standard of LITE;

[0021] The second root conversion unit is used to convert a request based on the LITE object bus standard into a transaction layer data packet based on the target bus standard.

[0022] Optionally, the request management module includes:

[0023] An interrupt request management unit, used for storing interrupt requests using registers;

[0024] A write request management unit, used to calculate a corresponding write address according to a write request, and complete a write operation according to the write address;

[0025] The read request management unit is used to process the read request.

[0026] Optionally, the write request management unit includes:

[0027] An address calculation subunit, configured to calculate the write address according to a write request start address, a data length and a first information group in the write request;

[0028] A write length calculation subunit, used to calculate the bus address length according to the write address;

[0029] The write control subunit is used to complete the corresponding write operation according to the bus address length.

[0030] Optionally, the read request management unit includes:

[0031] A cache subunit, for caching read requests as a first-in-first-out queue;

[0032] A parsing subunit, used for parsing a read request to obtain read address information;

[0033] An address subunit, used for parsing the read address information to obtain an address parsing result;

[0034] The read control subunit is used to complete the corresponding read operation according to the address resolution result.

[0035] Optionally, the second address management module includes:

[0036] A first slave conversion unit, configured to parse and convert a transaction layer data packet based on a target bus standard;

[0037] A second slave conversion unit is used for converting and obtaining a transaction layer data packet based on a target bus standard;

[0038] The third slave conversion module is used to realize the conversion from the internal bus to the object bus standard.

[0039] Optionally, the request parsing module includes:

[0040] A write operation parsing unit, used to complete a corresponding write operation according to a write descriptor obtained by parsing a write address;

[0041] The read operation parsing unit is used to complete the corresponding read operation according to the read descriptor obtained by parsing the read address.

[0042] Optionally, the write operation parsing unit is specifically used to: detect whether the write address is legal; if legal, calculate the write start address and the data bit width alignment address, and concatenate the write start address and the data bit width alignment address to obtain the write descriptor.

[0043] Optionally, the read operation parsing unit is specifically used to: detect whether the read address is legal, if legal, parse the read address to obtain a read descriptor, and complete a corresponding read operation according to the read descriptor.

[0044] Optionally, the data mover includes:

[0045] A write mover, used to encapsulate write data into a transaction layer data packet based on the target bus standard;

[0046] The read shifter is used for outputting the read data to the read data interface based on the object bus standard.

[0047] Optionally, the write mover includes:

[0048] A write descriptor processing unit, used for processing write descriptor information of write data;

[0049] A packet processing unit, used for processing write request packet information;

[0050] The write encapsulation unit is used to encapsulate a transaction layer data packet based on the target bus standard according to the processing result of the descriptor information and the processing result of the request packet information.

[0051] Optionally, the read mover includes:

[0052] A read descriptor processing unit, used for processing read descriptor information of read data;

[0053] Data parsing and alignment unit, used to complete the parsing and alignment of read data;

[0054] A read cache unit, used to cache data;

[0055] A mapping unit, used to complete the mapping of data packets to a read data interface based on the object bus standard;

[0056] The read encapsulation unit is used to complete the encapsulation of read data.

[0057] In a second aspect, the present invention provides a computing architecture, comprising: a root device and a slave device; the root device and the slave device communicate based on any one of the bridging systems described above.

[0058] It can be seen from the above scheme that the present invention provides a bridging system, including: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate through a target bus standard; wherein the root device bridge controller includes: a target bus configuration module, a request management module and a first address management module; the target bus configuration module is used to: configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs; the request management module is used to: respond to the first request packet sent by the slave device bridge controller; the first address management module is used to: convert the first request packet from the object bus standard to the target bus standard; wherein the slave device bridge controller includes: a request parsing module, a second address management module, a data mover and an interrupt management module; the request parsing module is used to: parse the second request packet sent by the root device bridge controller; the second address management module is used to: convert the second request packet from the target bus standard to the object bus standard; the data mover is used to implement direct memory access according to the parsing result of the second request packet; the interrupt management module is used to manage the interrupt signal between the root device bridge controller and the root device bridge controller through the target bus standard.

[0059] It can be seen that the beneficial effects of the present invention are: utilizing the root device bridge controller and the slave device bridge controller to enable the root device and the slave device to communicate; wherein the root device bridge controller and the slave device bridge controller communicate through the target bus standard; and the root device bridge controller includes: a target bus configuration module for configuring the slave device and the root device, a request management module for responding to the first request packet sent by the slave device bridge controller, and a first address management module for converting the first request packet from the object bus standard to the target bus standard; the slave device bridge controller includes: a request parsing module for parsing the second request packet sent by the root device bridge controller, a second address management module for converting the second request packet from the target bus standard to the object bus standard, a data mover for implementing direct memory access, and an interrupt management module for managing interrupt signals through the target bus standard. It can be seen that the bridge system provided by the present invention is divided into two parts, namely, a root device bridge controller and a slave device bridge controller. The two controllers communicate using the target bus standard. The address configuration of the two controllers can be realized without the help of a host processor. The communication process does not require the participation of an external CPU (Central Processing Unit), thereby reducing the complexity of chip configuration and communication. While ensuring high-speed data transmission, the system architecture is streamlined and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0060] Correspondingly, a computing architecture provided by the present invention also has the above-mentioned technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0062] Figure 1 A schematic diagram of a bridging system disclosed in the present invention;

[0063] Figure 2 A schematic diagram of a PCIe-AXI bridge controller at the RC end disclosed in the present invention;

[0064] Figure 3 A flow chart of a method for configuring an EP end BAR address disclosed in the present invention;

[0065] Figure 4 A schematic diagram of a write operation process disclosed in the present invention;

[0066] Figure 5 A schematic diagram of a read operation process disclosed in the present invention;

[0067] Figure 6 A schematic diagram of an EP-side PCIe-AXI bridge controller disclosed in the present invention;

[0068] Figure 7 A schematic diagram of an AXI write operation disclosed in the present invention;

[0069] Figure 8 A structural diagram of a write data mover provided by the present invention;

[0070] Fig. 9 A structural diagram of a read data mover provided by the present invention;

[0071] Fig.10 This is a schematic diagram of another bridging system disclosed in the present invention. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other examples obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] At present, the communication between the two chips is generally implemented based on a private protocol, and the cost of designing and maintaining the private protocol is relatively high, and the relevant configuration of the chip needs to be controlled by the host. For example, the host processor configures the bus address of the GPU device, which increases the complexity of chip configuration and communication. To this end, the present invention provides a bridge communication solution that can reduce the complexity of chip configuration and communication.

[0074] See also Figure 1 As shown, an embodiment of the present invention discloses a bridge system, including: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate via a target bus standard. The target bus standard may specifically be PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard).

[0075] The root device bridge controller includes: a target bus configuration module, a request management module and a first address management module; the slave device bridge controller includes: a request parsing module, a second address management module, a data mover and an interrupt management module.

[0076] Furthermore, the functions of each module in the root device bridge controller are as follows:

[0077] The target bus configuration module is used to configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs.

[0078] The request management module is used to respond to a first request packet sent from the device bridge controller.

[0079] The first address management module is used to convert the first request packet from an object bus standard to a target bus standard. The object bus standard is specifically AXI (Advanced eXtensible Interface, a bus protocol).

[0080] When the target bus standard is PCIe and the object bus standard is AXI, the root device bridge controller can be used as a PCIe-AXI bridge controller and the slave device bridge controller can be used as a PCIe-AXI bridge controller.

[0081] In one embodiment, the target bus configuration module includes: a slave device configuration unit, which is used to configure the base address, register configuration and interrupt configuration of the slave device; a root device configuration unit, which is used to configure the base address and register configuration of the root device. For example: the CFG0 TLP packet is used to mainly configure the BAR bus start address, Enable enable, MPS / MRRS configuration and MSI interrupt enable and address of the slave device; the root device configuration space initialization adopts the internal APB (Advanced Peripheral Bus, peripheral bus) method, mainly including Enable enable and MPS / MRRS configuration. Among them, MPS (MaxPayload Size) indicates the maximum value of the effective payload carried in a TLP packet. The MRRS (Max ReadRequest Size) indicates how many bytes can be requested to be read from the receiving end at a time in a TLP read request packet.

[0082] In one embodiment, the slave device configuration unit is used to: after writing all 1s to the base address register in the slave device, read the register value from the base address register, invert the read register value and increment by one, and obtain the bus space size corresponding to the base address register. For example: write all 1s to the bar base address register, then read the value of the register, invert the returned result and add 1 to obtain the preset space size of the current bar. If the current bar space is 32 bits, write the 32-bit preset address; if the current bar space is 64 bits, further determine whether the current bar space size exceeds 32 bits. If it does not exceed 32 bits, the starting address of the current bar and the next bar (combined into a 64-bit bar) can be directly set, otherwise it is necessary to further write all 1s to the next bar (high 32 bits) and read the written value, thereby obtaining the 64-bit preset space size of the entire bar, and finally set the starting addresses of the lower 32 bits and the upper 32 bits of the bar in turn; if the current bar is not enabled (that is, the value read after writing all 1s to the bar is all 0), then directly skip the bar and initialize the next bar, and so on until the last bar.

[0083] In one embodiment, the first address management module includes: a first conversion unit, which is used to convert a request based on the object bus standard into a request based on the object bus standard of LITE, including: conversion of data bit width, address and burst storage, etc. A second conversion unit is used to convert a request based on the object bus standard of LITE into a transaction layer data packet based on the target bus standard. For example: completing the conversion of the AXILITE interface and the TLP (Transaction Layer Packet) packet and the corresponding conversion of the AXI address range and the BAR space, the conversion formula is: (INPUT_ADDR-CH_RANGE_L)+BAR base address, INPUT_ADDR is the AXI address, CH_RANGE_L is the corresponding BAR range low address, and the BAR base address is the BAR base address output by the EP initialization module. AXI-LITE is a lightweight AXI protocol and a type of AXI4 protocol.

[0084] In one embodiment, the request management module includes: an interrupt request management unit for storing interrupt requests using registers; a write request management unit for calculating a corresponding write address according to a write request and completing a write operation according to the write address; and a read request management unit for processing a read request.

[0085] In one embodiment, the write request management unit includes: an address calculation subunit, which is used to calculate the write address according to the write request starting address, data length and first information group in the write request; for example, the AXI write starting address and ending address are calculated according to the starting address, FBE (First DW Byte Enable), LBE (Last DW Byte Enable) and length LENGTH of the TLP packet. A write length calculation subunit is used to calculate the bus address length according to the write address; for example, the AXI write length is calculated according to the calculated starting address and ending address. A write control subunit is used to complete the corresponding write operation according to the bus address length; specifically, the logical control of the AXI write address and write data is completed under the control of the state machine according to the address length information. FBE and LBE respectively indicate whether the data Byte in the first DW (Double Word) and the last DW of the TLP is valid, and each bit indicates a byte; one DW represents 4 bytes.

[0086] In one embodiment, the read request management unit includes: a cache subunit, used to cache the read request as a first-in-first-out queue; a parsing subunit, used to parse the read request to obtain read address information; an address subunit, used to parse the read address information to obtain an address resolution result; and a read control subunit, used to complete a corresponding read operation according to the address resolution result.

[0087] Furthermore, the functions of each module in the slave bridge controller are as follows:

[0088] The request parsing module is used to: parse the second request packet sent by the root device bridge controller.

[0089] The second address management module is used to convert the second request packet from the target bus standard to the object bus standard.

[0090] The data mover is used to implement direct memory access according to the parsing result of the second request packet.

[0091] An interrupt management module is used to manage interrupt signals between the root device bridge controller and the target bus standard.

[0092] In one embodiment, the second address management module includes: a first slave conversion unit, which is used to parse and convert transaction layer data packets based on the target bus standard, including: receiving TLP packets, 32bit / 64bit Mwr (DMA write), Mrd (BMA read) protocol parsing and local data bus conversion. A second slave conversion unit is used to convert transaction layer data packets based on the target bus standard, including: conversion from local data bus to internal APB bus, APB bus to TLP packets and address conversion; a third slave conversion module is used to realize the conversion from internal bus to object bus standard, for example: completing the conversion from internal APB bus to AXI bus.

[0093] In one embodiment, the request parsing module includes:

[0094] The write operation parsing unit is used to complete the corresponding write operation according to the write descriptor obtained by parsing the write address. For example: the legitimacy of the AXI write address is judged to determine whether it is within the preset range of each channel. If so, the corresponding conversion is performed according to the formula. At this time, the output start address is aligned according to the large data bit width. The data channel first undergoes a beat processing, and then calculates the corresponding byte offset and byte count. If the byte count does not match the burst length Aw_len of the AXI write address channel transmitted by the above address channel or the address is not within the range of each channel, the AXI response signal Bresp returns an exception message and does not move data. Otherwise, the starting byte offset address is spliced ​​with the large data bit width alignment address to calculate the start address of the write descriptor, and the data is sent to the large cache after the beat cache, and the data stream is written under the control of the state machine.

[0095] The read operation parsing unit is used to complete the corresponding read operation according to the read descriptor obtained by parsing the read address; specifically, the read address is judged for legality and the response address is converted, and the read descriptor length needs to be converted from Arlen to Byte length unit.

[0096] In one implementation, the write operation parsing unit is specifically used to: detect whether the write address is legal; if legal, calculate the write start address and the data bit width alignment address, and concatenate the write start address and the data bit width alignment address to obtain a write descriptor.

[0097] In one implementation, the read operation parsing unit is specifically used to: detect whether the read address is legal, if legal, parse the read address to obtain a read descriptor, and complete the corresponding read operation according to the read descriptor.

[0098] In one embodiment, the data mover includes: a write mover, which is used to encapsulate write data into a transaction layer data packet based on the target bus standard. For example: according to the descriptor output by the AXI write analysis and the preset max_payload (i.e., MPS), the data cached by the AXI write analysis is encapsulated into a TLP packet and sent to the PCIe module. A read mover is used to output read data to a read data interface based on the object bus standard. For example: according to the read descriptor output by the AXI read analysis and the preset max_read_req_size (i.e., MRRS), several TLP packet read requests (4K, including max_read_req_size and RCB boundary) are split and tag management is performed at the same time, wherein each Non-Posted operation that needs to be returned has its own separate tag; finally, the CplD (return packet) from the PCIe module is parsed, cached, and output to the AXI read data port. RCB (Read Completion Boundary) is the maximum aligned byte boundary of the data packet that can be returned when requesting a PCIe memory read. cplD (Completion with data TLP) is specifically: a read completion message with data.

[0099] In one embodiment, the write mover includes: a write descriptor processing unit for processing write descriptor information of write data; a packet processing unit for processing write request packet information; and a write encapsulation unit for encapsulating a transaction layer data packet based on the target bus standard according to the processing results of the descriptor information and the processing results of the request packet information.

[0100] In one embodiment, the read mover includes: a read descriptor processing unit for processing read descriptor information of read data; a data parsing and alignment unit for completing parsing and alignment of read data; a read cache unit for caching data; a mapping unit for completing mapping of data packets to a read data interface based on an object bus standard; and a read encapsulation unit for completing encapsulation of read data.

[0101] It can be seen that this embodiment uses the root device bridge controller and the slave device bridge controller to enable the root device and the slave device to communicate; wherein the root device bridge controller and the slave device bridge controller communicate through the target bus standard; and the root device bridge controller includes: a target bus configuration module for configuring the slave device and the root device, a request management module for responding to the first request packet sent by the slave device bridge controller, and a first address management module for converting the first request packet from the object bus standard to the target bus standard; the slave device bridge controller includes: a request parsing module for parsing the second request packet sent by the root device bridge controller, a second address management module for converting the second request packet from the target bus standard to the object bus standard, a data mover for implementing direct memory access, and an interrupt management module for managing interrupt signals through the target bus standard. It can be seen that the bridge system provided by the present invention is divided into two parts, the root device bridge controller and the slave device bridge controller, and the two controllers communicate using the target bus standard, and the address configuration of the two controllers can be realized without the help of the host processor, and the communication process does not require the participation of an external CPU, which reduces the complexity of chip configuration and communication; while ensuring high-speed data transmission, the system architecture is streamlined and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0102] It should be noted that PCIe is a third-generation high-performance universal IO bus used for interconnecting peripheral devices in computer and communication platform applications, and can realize serial point-to-point dual-channel high-bandwidth transmission. PCIe adopts a tree topology, generally composed of a root device component (Root Complex), a switch device (Switch), and a terminal slave device (End Point). Root Complex is a bridge between CPU instructions and PCIe TLP packets, used to complete mutual decoding between the two. The main purpose of Switch is to expand the PCIe bus, generally with one upstream port and multiple downstream ports. Endpoint is a leaf node of the PCIe tree structure.

[0103] The AXI protocol is the most important part of the AMBA (Advanced Microcontroller Bus Architecture) 3.0 protocol proposed by ARM. It is a high-performance, high-bandwidth, low-latency on-chip bus. The AXI4 protocol supports three types of interfaces: AXI4, AXI4-LITE, and AXI4-Stream. Among them, AXI4 is a high-performance memory-mapped interface used for high-speed data transmission scenarios such as accessing memory that require specified addresses. AXI4-LITE is a simplified version of the AXI4 interface used to access registers in some low-speed peripherals. AXI4-Stream is a high-speed data stream transmission interface used for continuous data reading and writing between master and slave devices without the need for addresses.

[0104] Generally, the PCIe hard core provided by FPGA (Field-Programmable Gate Array) can be instantiated as a Root Complex or Endpoint, and the interface provided to the user is an AXI-Stream interface for sending and receiving TLP packets. The FPGA local memory interface generally uses the common AXI4 interface. If data interaction between local memory and remote memory is to be realized, address conversion between the AXI domain and the PCI domain needs to be completed.

[0105] The PCIe-AXI bridge controller can realize the AXI interface communication between the RC and EP ends based on the PCIe protocol. The RC-side AXIMASTER can read and write the storage space corresponding to the BAR address of the EP end, and the EP-side AXI MASTER reads and writes the local storage space of the RC end with large amounts of DMA (Direct Memory Access). Specifically, it can be fully designed in RTL (Register Transfer Level) to facilitate porting on various FPGA platforms, with flexible and efficient design to match multiple design scenarios. The PCIe-AXI bridge controller mainly completes the mutual conversion between the PCIe transaction layer TLP packet and the AXI read and write request. The EP end can use the memory space of the RC end like using local memory. The RC end can access the BAR space of the EP end like accessing local memory.

[0106] Based on the above, this embodiment implements a PCIe-AXI bridge controller based on FPGA design, which is divided into two parts: an RC-end PCIe-AXI bridge controller and an EP-end PCIe-AXI bridge controller.

[0107] RC-side PCIe-AXI bridge controller can refer to Figure 2 , mainly including PCIe configuration space initialization (i.e. target bus configuration module), BAR read and write management (i.e. first address management module) and Mwr / Mrd read and write management (request management module). PCIe configuration space initialization completes EP Bar space base address configuration, RC and EP MPS / MRRS configuration, and EP-side MSI interrupt enable and address configuration. BAR read and write management completes the conversion of AXI read and write requests to TLP packets (including address space conversion). Mwr / Mrd read and write management completes the processing of Mrd / Mwr / MSI requests from the EP side.

[0108] The PCIe configuration space initialization is controlled separately by EP and RC. The EP configuration space initialization adopts the CFG0 TLP package, which mainly configures the BAR start address, Enable, MPS / MRRS configuration and MSI interrupt enable and address; while the RC configuration space initialization adopts the internal APB bus method, which mainly includes Enable and MPS / MRRS configuration.

[0109] The configuration of the BAR starting address on the EP side requires determining the address space size for each BAR. First, write all 1s to the bar base address register, then read the value of the register, invert the returned result and add 1 to obtain the preset space size of the current bar. If the current bar space is 32 bits, write the 32-bit preset address; if the current bar space is 64 bits, further determine whether the current bar space size exceeds 32 bits. If it does not exceed 32 bits, you can directly set the starting address of the current bar and the next bar (combined into a 64-bit bar). Otherwise, you need to further write all 1s to the next bar (high 32 bits) and read the written value to obtain the 64-bit preset space size of the entire bar. Finally, set the starting addresses of the lower 32 bits and the upper 32 bits bar in turn; if the current bar is not enabled (that is, the value read after writing all 1s to the bar is all 0), then skip the bar directly to initialize the next bar, and repeat this cycle until the last bar. The specific configuration flow chart is as follows Figure 3 shown.

[0110] BAR read and write management mainly consists of two parts: AXI2AXILITE (i.e., the first conversion unit) and AXILITE2TLP (i.e., the second conversion unit). AXI2AXILITE completes the conversion from AXI to AXILITE interface, including the conversion of data width, address, and burst storage, and is divided into AXI read adapter module and AXI write adapter module. AXILITE2TLP completes the conversion of AXILITE interface and TLP packet, and the conversion of AXI address range and BAR space. The conversion formula is (INPUT_ADDR-CH_RANGE_L)+BAR base address, INPUT_ADDR is the AXI address, CH_RANGE_L is the corresponding BAR range low address, and the BAR base address is the BAR base address output by the EP initialization module.

[0111] Mwr / Mrd management mainly processes and responds to Mwr / Mrd requests from EP. Mwr is divided into two categories: MSI interrupt request and data write request. MSI interrupt write request is parsed and saved in the internal APB register.

[0112] Mwr data write request includes four modules: Rx_ctrl (receive control), Cal_len (length calculation), Addr_ctrl (address management) and Data_ctrl (data management). Rx_ctrl calculates the AXI write start address and end address based on the start address, FBE, LBE and LENGTH of the TLP packet. Cal_len then calculates the AXI write length based on the start address and end address calculated by Rx_ctrl. Addr_ctrl and Data_ctrl complete the logical control of AXI write address and write data under the control of the state machine according to the address length information. Figure 4 shown.

[0113] Mrd data read request includes four modules: FIFO cache (i.e. cache subunit), Fork (parse split subunit), Axim2s (read address data management, corresponding to address subunit) and CplD Tx (return packet sending, corresponding to read control subunit). FIFO caches Mrd TLP requests from EP (tentatively 32), Fork is used to parse the source address, length, FBE, LBE, TAG and Request_id of the TLP packet and replicate two outputs, one to the AXI read address data processing module Axim2s, and the other to the CplD encapsulation and sending module CplD Tx. The Axim2s module mainly completes address parsing, alignment and AXI read address and read data logic control. The CplD Tx module completes the phase alignment and encapsulation of the data packet, as shown below: Figure 5 As shown in the figure, the Request_id field includes the bus number, device number and function number of the PCIe device that generates this TLP message.

[0114] The design block diagram of the EP-side PCIe-AXI bridge controller is as follows: Figure 6 As shown, it mainly consists of four parts: BAR read and write management (corresponding to the second address management module), AXI read and write analysis (corresponding to the request analysis module), read and write data mover and interrupt management. BAR read and write management mainly completes the conversion of TLP (Transaction Layer Packet) packet read and write requests to AXI read and write control (including address space conversion). AXI read and write analysis mainly completes the conversion of AXI read and write instructions to read and write descriptors, write data cache analysis and address space conversion. The read and write data mover mainly completes DMA read and write logic control and TLP header encapsulation. Interrupt management mainly completes traditional interrupt and MSI interrupt reporting management.

[0115] BAR read and write management mainly includes three parts: TLP2LB (corresponding to the first slave conversion unit), LB2TLP (corresponding to the second slave conversion unit) and APB2AXIMM (corresponding to the third slave conversion module). TLP2LB mainly completes the reception of TLP packets, 32bit / 64bit Mwr, Mrd protocol parsing and local data bus conversion. LB2TLP mainly completes the conversion of local data bus to internal APB bus, APB bus to TLP packet and address conversion. APB2AXIMM mainly completes the conversion of internal APB bus to AXI bus and supports byte mask. PCIe Bar is converted to AXI domain, supporting up to bar0-bar5. The bar space size is configured on the hard core module. When each channel is mapped to the AXI domain, the offset address can be set according to requirements.

[0116] AXI write parsing completes the conversion of AXI write commands to write descriptors, as well as AXI write data caching and parsing (wstrb and the starting byte offset of the write address). First, the AXI write address is judged for legality to determine whether it is within the preset range of each channel. If so, it is converted accordingly according to the formula. At this time, the output starting address is aligned according to the large data bit width. The data channel first undergoes a beat-beat process to calculate the corresponding byte offset and byte count. If the byte count does not match the Aw_len passed in by the above address channel or the address is not within the range of each channel, Bresp returns an exception message and does not move data. Otherwise, the starting byte offset address is concatenated with the large data bit width alignment address to calculate the write descriptor starting address, and the data is sent to the large cache after the beat-beat cache. The data stream is written under the control of the state machine, as shown below. Figure 7 shown.

[0117] AXI read parsing is relatively simple. It only requires checking the legitimacy of the read address and converting the response address. The read descriptor length needs to be converted from Arlen to Byte length unit.

[0118] The write data mover mainly encapsulates the data in the AXI write parsing cache into TLP packets and sends them to the PCIe module based on the descriptor output by the AXI write parsing and the preset max_payload. The write data mover mainly includes three modules: mwr_ctrl (write control management), axim2s (data flow parsing) and tx_mw (transmission management). mwr_ctrl completes the parsing and splitting (4K and max_payload boundaries) of the write descriptor as well as the FBE and LBE parsing. Axim2s completes the parsing of the packet header, the packet starting position: keep_start_site and the keep length keep_len. Mwr_ctrl completes the data packet alignment and TLP packet encapsulation based on the output information of the above two modules, as shown below: Figure 8 shown.

[0119] The read data mover mainly splits the read descriptor output by the AXI read analysis and the preset max_read_req_size to obtain several TLP packet read requests (4K, including max_read_req_size and RCB boundary), and performs tag management at the same time, and finally parses, caches, and outputs the CplD from the PCIe module to the AXI read data port. The read data mover mainly consists of five parts: Mrd_ctrl (read control management), Rx_cpld (return packet analysis), Mem_cpld (data caching and processing), Axis2m (interface conversion) and Tx_mrd (transmission management). Mrd_ctrl completes descriptor splitting management, Tag management and recycling. Rx_cpld completes CplD analysis and data alignment. Mem_cpld completes data caching, tag disorder processing and data packet splicing. Axis2m completes the mapping of data packets to the AXI read data channel interface. Tx_mrd completes the encapsulation of read descriptor information into Mrd TLP packets, as shown below: Fig. 9 shown.

[0120] The interrupt management module supports traditional interrupts INTX and MSI (Message Signal Interrupt). The interrupt type can be defined in the header file and the corresponding module can be automatically generated. MSI supports 32-bit and 64-bit addresses and supports up to 32 interrupts. MSI interrupts can be in the form of standardized TLP packets or directly connected to the interrupt management interface of the PCIe module.

[0121] In this embodiment, a PCIe-AXI bridge controller is designed based on a programmable logic device FPGA as hardware implementation. The design is completely implemented in RTL, which is convenient for porting to various platforms; the design block diagram is shown in the figure. Fig.10As shown. Among them, the RC end can automatically / manually configure the EP bar space starting address and MSI interrupt configuration register, support dual-channel AXI address 64bit, arbitrary data bit width configuration (integer multiples of 32), and the MPS / MRRS of RC and EP are automatically configured according to the maximum value supported by each (128-4096). It only needs to modify the peripheral matching interface to adapt to various FPGA platforms. Various address conversion parameterization controls can be flexibly modified through the internal APB bus; the overall design is flexible and efficient. Based on the PCIe-AXI bridge controller, the AXI interface communication between the RC end and the EP end based on the PCIe protocol can be realized. The RC end AXI MASTER can read and write the storage space corresponding to the BAR address of the EP end, and the EP end AXIMASTER reads and writes the local storage space of the RC end with large data volume in the form of DMA. The present invention completely adopts RTL design, does not introduce any third-party chips, and is easy to transplant on various platforms. The present invention realizes chip interconnection based on the PCIe protocol, and the internal bus adopts the standardized AXI protocol, which has strong versatility; greatly simplifies the system architecture, while ensuring high bandwidth and low latency.

[0122] A computing architecture provided by an embodiment of the present invention is introduced below. The computing architecture described below can be referenced to other embodiments described in this document.

[0123] An embodiment of the present invention discloses a computing architecture, including: a root device and a slave device; the root device and the slave device communicate based on the bridge system described in any one of the above embodiments.

[0124] In this example, the bridge system includes: a root device bridge controller and a slave device bridge controller; the root device bridge controller and the slave device bridge controller communicate with each other through a target bus standard.

[0125] The root device bridge controller includes: a target bus configuration module, a request management module and a first address management module; the target bus configuration module is used to configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs; the request management module is used to respond to the first request packet sent by the slave device bridge controller; the first address management module is used to convert the first request packet from the object bus standard to the target bus standard;

[0126] Among them, the slave device bridge controller includes: a request parsing module, a second address management module, a data mover and an interrupt management module; the request parsing module is used to: parse the second request packet sent by the root device bridge controller; the second address management module is used to: convert the second request packet from the target bus standard to the object bus standard; the data mover is used to implement direct memory access according to the parsing result of the second request packet; the interrupt management module is used to manage the interrupt signal between the root device bridge controller and the root device bridge controller through the target bus standard.

[0127] In one embodiment, the target bus configuration module includes: a slave device configuration unit, which is used to perform base address configuration, register configuration and interrupt configuration on the slave device; and a root device configuration unit, which is used to perform base address configuration and register configuration on the root device.

[0128] In one implementation, the slave device configuration unit is used to: after writing all 1s to the base address register in the slave device, read the register value from the base address register, invert the read register value and increment it by one to obtain the bus space size corresponding to the base address register.

[0129] In one embodiment, the first address management module includes: a first root conversion unit, used to convert a request based on the object bus standard into a request based on the object bus standard based on LITE; a second root conversion unit, used to convert a request based on the object bus standard based on LITE into a transaction layer data packet based on the target bus standard.

[0130] In one embodiment, the request management module includes: an interrupt request management unit for storing interrupt requests using registers; a write request management unit for calculating a corresponding write address according to a write request and completing a write operation according to the write address; and a read request management unit for processing a read request.

[0131] In one embodiment, the write request management unit includes: an address calculation subunit, used to calculate the write address based on the write request starting address, data length and first information group in the write request; a write length calculation subunit, used to calculate the bus address length based on the write address; and a write control subunit, used to complete the corresponding write operation based on the bus address length.

[0132] In one embodiment, the read request management unit includes: a cache subunit, used to cache the read request as a first-in-first-out queue; a parsing subunit, used to parse the read request to obtain read address information; an address subunit, used to parse the read address information to obtain an address resolution result; and a read control subunit, used to complete a corresponding read operation according to the address resolution result.

[0133] In one embodiment, the second address management module includes: a first slave conversion unit, used to parse and convert transaction layer data packets based on the target bus standard; a second slave conversion unit, used to convert transaction layer data packets based on the target bus standard; and a third slave conversion module, used to implement conversion from an internal bus to an object bus standard.

[0134] In one embodiment, the request parsing module includes: a write operation parsing unit, used to complete a corresponding write operation according to a write descriptor obtained by parsing a write address; and a read operation parsing unit, used to complete a corresponding read operation according to a read descriptor obtained by parsing a read address.

[0135] In one implementation, the write operation parsing unit is specifically used to: detect whether the write address is legal; if legal, calculate the write start address and the data bit width alignment address, and concatenate the write start address and the data bit width alignment address to obtain a write descriptor.

[0136] In one implementation, the read operation parsing unit is specifically used to: detect whether the read address is legal, if legal, parse the read address to obtain a read descriptor, and complete the corresponding read operation according to the read descriptor.

[0137] In one embodiment, the data mover includes: a write mover for encapsulating write data into a transaction layer data packet based on a target bus standard; and a read mover for outputting read data to a read data interface based on an object bus standard.

[0138] In one embodiment, the write mover includes: a write descriptor processing unit for processing write descriptor information of write data; a packet processing unit for processing write request packet information; and a write encapsulation unit for encapsulating a transaction layer data packet based on the target bus standard according to the processing results of the descriptor information and the processing results of the request packet information.

[0139] In one embodiment, the read mover includes: a read descriptor processing unit for processing read descriptor information of read data; a data parsing and alignment unit for completing parsing and alignment of read data; a read cache unit for caching data; a mapping unit for completing mapping of data packets to a read data interface based on an object bus standard; and a read encapsulation unit for completing encapsulation of read data.

[0140] Among them, for more specific working processes of each module and unit in this embodiment, reference can be made to the corresponding contents disclosed in the aforementioned embodiments, which will not be repeated here.

[0141] It can be seen that the bridge system of this embodiment is divided into two parts: the root device bridge controller and the slave device bridge controller. The two controllers communicate using the target bus standard. The address configuration of the two controllers can be achieved without the help of a host processor. The communication process does not require the participation of an external CPU, which reduces the complexity of chip configuration and communication. While ensuring high-speed data transmission, the system architecture is streamlined and optimized, the overall design is more flexible, the compatibility is strong, and the communication efficiency is higher.

[0142] An electronic device provided by an embodiment of the present invention is introduced below, and the electronic device described below can be referenced to other embodiments described herein. The electronic device described in this embodiment can be any functional module described in any of the above embodiments.

[0143] An embodiment of the present invention discloses an electronic device, including:

[0144] Memory, used to store computer programs;

[0145] The processor is used to execute the computer program to implement the method functions implemented by any functional module described in any of the above embodiments.

[0146] A nonvolatile storage medium provided in an embodiment of the present invention is introduced below. The nonvolatile storage medium described below and other embodiments described herein may be cross-referenced.

[0147] A non-volatile storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the method functions implemented by any functional module described in the above embodiments. The non-volatile storage medium is a computer-readable non-volatile storage medium, which, as a carrier for storing resources, may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon include an operating system, a computer program and data, etc., and the storage method may be temporary storage or permanent storage.

[0148] A computer program product provided by an embodiment of the present invention is introduced below. The computer program product described below can be referenced to other embodiments described in this document.

[0149] A computer program product includes a computer program / instruction, which, when executed by a processor, implements the method functions implemented by any functional module described in the foregoing embodiments.

[0150] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0151] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of non-volatile storage medium known in the art.

[0152] Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A bridging system, characterized in that: include: A root device bridge controller and a slave device bridge controller; The root device bridge controller and the slave device bridge controller communicate via a target bus standard; Wherein, the root device bridge controller includes: a target bus configuration module, a request management module and a first address management module; The target bus configuration module is used to: configure the slave device to which the slave device bridge controller belongs and the root device to which the root device bridge controller belongs; The request management module is used to: respond to the first request packet sent by the slave device bridge controller; The first address management module is used to: convert the first request packet from the object bus standard to the target bus standard; Wherein, the slave device bridge controller includes: a request parsing module, a second address management module, a data mover and an interrupt management module; The request parsing module is used to: parse the second request packet sent by the root device bridge controller; The second address management module is used to: convert the second request packet from the target bus standard to the object bus standard; The data mover is used to implement direct memory access according to the parsing result of the second request packet; The interrupt management module is used to manage the interrupt signal between the root device bridge controller and the target bus standard.

2. The bridging system according to claim 1, characterized in that: The target bus configuration module comprises: A slave device configuration unit, used for performing base address configuration, register configuration and interrupt configuration on the slave device; The root device configuration unit is used to perform base address configuration and register configuration on the root device.

3. The bridging system according to claim 2, characterized in that: The slave device configuration unit is used to: after writing all 1s to the base address register in the slave device, read the register value from the base address register, invert the read register value and increment it by one to obtain the bus space size corresponding to the base address register.

4. The bridging system according to claim 1, characterized in that: The first address management module includes: A first root conversion unit, configured to convert a request based on the object bus standard into a request based on the object bus standard of LITE; The second root conversion unit is used to convert a request based on the LITE object bus standard into a transaction layer data packet based on the target bus standard.

5. The bridging system according to claim 1, characterized in that: The request management module includes: An interrupt request management unit, used for storing interrupt requests using registers; A write request management unit, used to calculate a corresponding write address according to a write request, and complete a write operation according to the write address; The read request management unit is used to process the read request.

6. The bridging system according to claim 5, characterized in that: The write request management unit comprises: An address calculation subunit, configured to calculate the write address according to a write request start address, a data length and a first information group in the write request; A write length calculation subunit, used to calculate the bus address length according to the write address; The write control subunit is used to complete the corresponding write operation according to the bus address length.

7. The bridging system according to claim 5, characterized in that: The read request management unit comprises: A cache subunit, for caching read requests as a first-in-first-out queue; A parsing subunit, used for parsing a read request to obtain read address information; An address subunit, used for parsing the read address information to obtain an address parsing result; The read control subunit is used to complete the corresponding read operation according to the address resolution result.

8. The bridging system according to claim 1, characterized in that: The second address management module includes: A first slave conversion unit, configured to parse and convert a transaction layer data packet based on a target bus standard; A second slave conversion unit is used for converting and obtaining a transaction layer data packet based on a target bus standard; The third slave conversion module is used to realize the conversion from the internal bus to the object bus standard.

9. The bridging system according to claim 1, characterized in that: The request parsing module includes: A write operation parsing unit, used to complete a corresponding write operation according to a write descriptor obtained by parsing a write address; The read operation parsing unit is used to complete the corresponding read operation according to the read descriptor obtained by parsing the read address.

10. The bridging system according to claim 9, characterized in that: The write operation parsing unit is specifically used to: detect whether the write address is legal; if legal, calculate the write start address and the data bit width alignment address, and concatenate the write start address and the data bit width alignment address to obtain the write descriptor.

11. The bridging system according to claim 9, characterized in that: The read operation parsing unit is specifically used to detect whether the read address is legal, and if legal, parse the read address to obtain a read descriptor, and complete the corresponding read operation according to the read descriptor.

12. The bridging system according to claim 1, characterized in that: The data mover comprises: A write mover, used to encapsulate write data into a transaction layer data packet based on the target bus standard; The read shifter is used for outputting the read data to the read data interface based on the object bus standard.

13. The bridging system according to claim 12, characterized in that: The write mover comprises: A write descriptor processing unit, used for processing write descriptor information of write data; A packet processing unit, used for processing write request packet information; The write encapsulation unit is used to encapsulate a transaction layer data packet based on the target bus standard according to the processing result of the descriptor information and the processing result of the request packet information.

14. The bridging system according to claim 12, characterized in that: The read mover comprises: A read descriptor processing unit, used for processing read descriptor information of read data; Data parsing and alignment unit, used to complete the parsing and alignment of read data; A read cache unit, used to cache data; A mapping unit, used to complete the mapping of data packets to a read data interface based on the object bus standard; The read encapsulation unit is used to complete the encapsulation of read data.

15. A computing architecture, characterized in that: include: A root device and a slave device; the root device and the slave device communicate based on the bridge system according to any one of claims 1 to 14.

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