Model Processing Method and Device for IP Core Used in Hardware-in-the-Loop Simulation

Abstract

An embodiment of the present application provides a method and device for model processing of an IP core for hardware-in-the-loop simulation. The method includes: encapsulating an algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defining the attributes of model variables in the algorithm description of the algorithm IP core, and dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; performing synthesis, placement, and routing on a top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and downloading the bitstream file to a target hardware platform to start running; the present application can effectively improve the simulation efficiency and accuracy.

Description

Technical Field

[0001] This application relates to the field of simulation tests, and specifically relates to a method and device for processing models of IP cores for hardware-in-the-loop simulation. Background Art

[0002] In current electronic design automation (EDA) and embedded system development, field-programmable gate arrays (FPGAs) have become the first choice for various high-performance computing and real-time processing applications due to their high flexibility and reconfigurability. However, with the continuous increase in application requirements and the improvement of algorithm complexity, how to efficiently perform hardware-in-the-loop simulation of FPGAs has become an important technical challenge. Although certain progress has been made in FPGA hardware-in-the-loop simulation in the prior art, there are still many deficiencies in aspects such as model processing, resource mapping, simulation efficiency, and flexibility.

[0003] First of all, existing FPGA simulation methods usually rely on manually writing hardware description language (HDL) codes, such as Verilog or VHDL. This method not only has a long development cycle but also requires high professional knowledge of developers. Developers need to have a detailed understanding of the FPGA hardware architecture and design process to write efficient and accurate simulation codes. For complex algorithm models, the process of manually writing HDL codes is not only cumbersome but also error-prone, resulting in deviations between simulation results and actual operation results. In addition, existing FPGA simulation methods have significant deficiencies in terms of encapsulation and reusability. Many algorithm models have similar logical structures in different application scenarios, but due to the lack of effective modularization and encapsulation mechanisms, developers need to write and debug simulation codes separately for each specific application scenario. This not only increases the development workload but also is not conducive to the reuse and maintenance of algorithm models.

[0004] Secondly, existing FPGA simulation methods have deficiencies in the processing and management of model variables. The simulation models of FPGAs usually contain a large number of variables, which may include input / output ports, dynamically adjustable parameters, and special signals such as clock reset. When dealing with these variables, existing methods often lack effective classification and management mechanisms, resulting in complex relationships between variables and making it difficult to maintain and debug. In addition, existing methods also have deficiencies in variable mapping and resource management. The allocation and management of FPGA hardware resources are the key to achieving efficient simulation, but existing methods usually rely on developers to manually configure and optimize. This manual configuration is not only inefficient but also difficult to ensure the optimization of resource utilization. Especially when facing complex algorithm models and diverse hardware resources, how to effectively perform resource mapping and management is a problem that existing simulation methods are difficult to solve.

[0005] In terms of the generation and execution of simulation results, the existing technologies mainly rely on static design and offline simulation. To a certain extent, this traditional method can meet the simulation requirements of simple algorithm models. However, for complex algorithm models with high real-time requirements, static design and offline simulation are obviously difficult to meet the needs. Real-time simulation not only requires the algorithm model to run efficiently on the FPGA, but also requires the simulation results to be fed back and adjusted in a timely manner. The deficiencies of the existing methods in this regard lead to unsatisfactory real-time simulation effects and are difficult to meet the needs of practical applications. In addition, the existing FPGA simulation tools and platforms also have deficiencies in terms of integration and usability. Although some EDA tools provide the basic functions of FPGA simulation, in actual use, the integration and usability of these tools still need to be improved. Developers need to switch between different tools, manually adjust and optimize the simulation process, which increases the complexity and workload of development. Especially when facing multiple heterogeneous platforms and complex algorithm models, the lack of effective integrated and automated simulation tools seriously affects the efficiency and effect of FPGA simulation.

[0006] In addition, the existing FPGA simulation methods also have deficiencies in dynamic adjustment and real-time optimization. In actual applications, the requirements for algorithm models and hardware resources often change dynamically, and fixed simulation strategies are difficult to cope with these changes. The existing methods lack effective dynamic adjustment and real-time optimization mechanisms, resulting in a lack of flexibility and adaptability in the simulation process and being difficult to meet the requirements of complex application scenarios. Especially when facing high-performance computing and real-time processing applications, how to achieve dynamic adjustment and optimization of the simulation process is an urgent problem to be solved by the existing technologies.

[0007] In summary, there are still many deficiencies and challenges in the existing FPGA hardware-in-the-loop simulation methods in terms of model processing, resource mapping, simulation efficiency, and tool integration. Facing the increasingly complex application requirements and algorithm models, there is an urgent need for a more efficient, flexible, and easy-to-use FPGA simulation method to improve simulation efficiency and accuracy and promote the further development of FPGA design and applications. Summary of the Invention

[0008] In view of the problems in the existing technologies, the present application provides a method and device for model processing of an IP core for hardware-in-the-loop simulation, which can effectively improve simulation efficiency and accuracy.

[0009] To solve at least one of the above problems, the present application provides the following technical solutions:

[0010] In a first aspect, the present application provides a method for model processing of an IP core for hardware-in-the-loop simulation, including:

[0011] Encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0012] Obtain the hardware resource description information of the programmable array logic device. Based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, use the model-driven method to establish the mapping relationship between the model variables and the hardware resource description information, and dynamically generate the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0013] Perform synthesis, placement, and routing on the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0014] Further, encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device and defining the attributes of model variables in the algorithm description of the algorithm IP core includes:

[0015] Construct the algorithm model to be simulated in a preset modeling tool, and convert the algorithm model into an algorithm IP core that can run on the programmable array logic device through a programmable array logic device design tool;

[0016] Define the attribute content for each model variable in the description file of the algorithm IP core, where the attribute content includes at least one of variable name, port direction, data type, and initial value.

[0017] Further, dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals includes:

[0018] Divide the model variables into two categories: input / output ports and parameters. Among them, the input / output ports are directly bound to the physical input / output channels of the hardware of the programmable array logic device for real-time data exchange;

[0019] Divide the model variables of the parameter type into two categories: dynamically adjustable parameters and clock reset special signals. Among them, the dynamically adjustable parameters are dynamically adjusted and mapped to the CPU register space through software.

[0020] Further, for the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, a mapping relationship between the model variables and the hardware resource description information is established by using a model-driven method, including:

[0021] Extracting the detailed information of the model variables from the description file of the constructed algorithm IP core, and obtaining the resource description information of the target programmable array logic device hardware platform;

[0022] Using a model-driven method to establish an automatic mapping between the model variables and the hardware resources, where the model variables of the input / output port type are mapped to the corresponding hardware physical channels, the model variables of the dynamically adjustable parameter type are mapped to the register space accessible by the CPU, and the clock reset special information is mapped to the corresponding clock reset resource area.

[0023] Further, generating the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship includes:

[0024] Generating a configurable description corresponding to the project of the programmable array logic device according to the mapping relationship between the model variables and the hardware resources;

[0025] Obtaining the corresponding configurable top-level design file through the preset design tool of the programmable array logic device.

[0026] Further, performing synthesis, placement, and routing on the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, including:

[0027] Importing the top-level design file of the programmable array logic device into a preset design tool to convert it into a corresponding logic netlist;

[0028] Performing placement and routing process operations through the logic netlist to obtain a corresponding bitstream file.

[0029] Further, downloading the bitstream file to the target hardware platform to start running includes:

[0030] Transmitting the bitstream file to the hardware platform of the corresponding target programmable array logic device;

[0031] Starting the execution of the bitstream file on the hardware platform of the target programmable array logic device.

[0032] In a second aspect, the present application provides a model processing device for an IP core used in hardware-in-the-loop simulation, including:

[0033] The simulation model encapsulation module is used to encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0034] The mapping relationship construction module is used to obtain the hardware resource description information of the programmable array logic device, establish the mapping relationship between the model variables and the hardware resource description information by using the model-driven method based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0035] The file execution module is used to perform comprehensive layout and wiring on the top-level design file through the preset design tool of the programmable array logic device, generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0036] In a third aspect, the present application provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the steps of the model processing method of the IP core for hardware-in-the-loop simulation described above are implemented.

[0037] In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the model processing method of the IP core for hardware-in-the-loop simulation described above are implemented.

[0038] In a fifth aspect, the present application provides a computer program product, including a computer program / instructions. When the computer program / instructions are executed by a processor, the steps of the model processing method of the IP core for hardware-in-the-loop simulation described above are implemented.

[0039] As can be seen from the above technical solutions, the present application provides a model processing method and device for an IP core for hardware-in-the-loop simulation. By encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defining the attributes of model variables in the algorithm description of the algorithm IP core, and dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; performing comprehensive layout and wiring on the top-level design file through the preset design tool of the programmable array logic device, generating a corresponding bitstream file that can be directly run on the programmable array logic device, and downloading the bitstream file to the target hardware platform to start running, the simulation efficiency and accuracy can be effectively improved. Description of the Drawings

[0040] To more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0042] Figure 2 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0043] Figure 3 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0044] Figure 4 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0045] Figure 5 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0046] Figure 6 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0047] Figure 7 One of the flow diagrams of the model processing method for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0048] Figure 8 The structural diagram of the model processing device for the IP core used in the semi-physical simulation in the embodiments of the present application;

[0049] Figure 9 The structural diagram of the electronic device in the embodiments of the present application.

[0050] Reference numerals:

[0051] Electronic device 9600, central processing unit 9100, memory 9140, communication module 9110, input unit 9120, audio processor 9130, display 9160, power supply 9170, buffer memory 9141, application / function storage unit 9142, data storage unit 9143, driver program storage unit 9144, antenna 9111, speaker 9131, microphone 9132. Detailed implementation manners

[0052] To make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Apparently, the described embodiments are some but not all of the embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the scope of protection of the present application.

[0053] In the technical solutions of the present application, the acquisition, storage, use, processing, etc. of data all comply with the relevant provisions of national laws and regulations.

[0054] Considering the problems existing in the prior art, the present application provides a model processing method and device for an IP core for hardware-in-the-loop simulation. By encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defining the attributes of model variables in the algorithm description of the algorithm IP core, and dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; through the preset design tool of the programmable array logic device, the top-level design file is comprehensively laid out and routed to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and the bitstream file is downloaded to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0055] To effectively improve the simulation efficiency and accuracy, the present application provides an embodiment of a model processing method for an IP core for hardware-in-the-loop simulation. Refer to Figure 1 , the model processing method for the IP core for hardware-in-the-loop simulation specifically includes the following contents:

[0056] Step S101: Encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0057] Optionally, in this embodiment, in step S101, the system first encapsulates the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device (FPGA). The specific technical process includes the following steps: First, the designer uses a hardware description language (such as VHDL, Verilog) or a high-level synthesis tool (such as HLS) to convert the algorithm model into a hardware-implementable description. Next, the designer defines the attributes of the model variables in the algorithm description and divides these variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals. The input / output ports are used for data transmission, the dynamically adjustable parameters are used to adjust the algorithm behavior at runtime, and the clock reset special signals are used to control the timing and state reset of the IP core. After completing these steps, the designer synthesizes and verifies the algorithm description to ensure that it can be correctly mapped to the resources of the FPGA, and finally generates a reusable algorithm IP core.

[0058] In terms of the technical principle, step S101 utilizes the modeling ability of the hardware description language and the flexible configuration characteristics of the FPGA. The hardware description language allows the designer to define the behavior and interface of the algorithm in a structured manner, and through the synthesis tool, these high-level descriptions are transformed into low-level logic circuits. Defining the attributes and classification of the model variables is to clarify the input-output relationship and adjustable parameters of the algorithm, which helps to improve the flexibility and reusability of the IP core. The setting of the clock reset special signal is to ensure the timing and state control of the IP core in different operating environments, and to ensure its stability and reliability.

[0059] In terms of the technical problems solved, step S101 mainly solves the problem of converting the algorithm model into a hardware implementation. The algorithm model usually exists in the form of high-level mathematical or behavioral descriptions, while the FPGA implementation requires low-level logic circuit representations. Through the hardware description language and the synthesis tool, the system can transform the high-level algorithm model into a low-level hardware representation. In addition, by defining and classifying the model variables, the system can clarify the interface and parameter settings of the algorithm, enhancing the flexibility and reusability of the IP core. The setting of the clock reset special signal solves the problem of timing and state control of the IP core in different operating environments, ensuring its stability and reliability.

[0060] In terms of the technical effects achieved, through step S101, the system can generate an efficient, flexible, and reusable algorithm IP core. The algorithm IP core not only refines the hardware implementation of the algorithm model but also enhances its adaptability and adjustability through clear interfaces and parameter settings. The setting of the clock reset special signal ensures the stability and reliability of the IP core in different operating environments. Through efficient hardware description and synthesis technologies, the design efficiency and reliability are improved, laying a solid foundation for subsequent FPGA implementation and system integration.

[0061] For example, assume a team is developing a filtering algorithm for digital signal processing. In step S101, the team first describes the filtering algorithm as a hardware-implementable module using VHDL. In this description, they define dynamically adjustable parameters such as data input ports, data output ports, filtering coefficients, as well as clock and reset signals. The data input port is used to transmit the signal data to be processed, and the data output port is used to output the processed signal. The filtering coefficients, as dynamically adjustable parameters, allow the characteristics of the filter to be adjusted during runtime, while the clock and reset signals are used to control the timing and state reset of the module. After completing these definitions, the team uses a synthesis tool to convert the VHDL description into an FPGA-implementable logic circuit and conducts simulation and verification to ensure the correct implementation of the filtering algorithm in hardware. Finally, the team generates a reusable filtering algorithm IP core that can be reused in different projects and the filtering coefficients and other parameters can be adjusted as needed.

[0062] In summary, through step S101, the system can convert a high-level algorithm model into a low-level hardware description and generate an efficient, flexible, and reusable algorithm IP core. This process not only improves the design efficiency and reliability but also provides a solid foundation for FPGA implementation and system integration. Through clear interfaces and parameter settings, the algorithm IP core can adapt to different application requirements, enhancing the flexibility and scalability of the system. The setting of the clock reset special signals ensures the stability and reliability of the IP core in different operating environments, providing strong support for the efficient operation and performance optimization of the system.

[0063] Step S102: Obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device using a model-driven method, and dynamically generate an engineering-configurable top-level design file for the programmable array logic device according to the established mapping relationship;

[0064] Optionally, in this embodiment, in step S102, the system obtains the hardware resource description information of the Field-Programmable Gate Array (FPGA), and based on the model variables of the algorithm IP core and this hardware resource description information, uses the model-driven method to establish the mapping relationship between the two. The specific technical process includes the following links: First, the system obtains the hardware resource description information from the FPGA's resource management tool or document, and this information usually includes the detailed specifications and available quantities of resources such as logic units, memory blocks, DSP blocks, I / O pins, etc. Then, the system analyzes the model variables of the algorithm IP core, and these variables have been clearly classified as input / output ports, dynamically adjustable parameters, and clock reset special signals in step S101. Based on this information, the system uses the model-driven method to establish the mapping relationship between the model variables and the FPGA hardware resources, ensuring that each model variable can be effectively allocated to the specific hardware resources of the FPGA. Finally, the system dynamically generates the project configurable top-level design file of the FPGA according to the established mapping relationship, and this file is used to guide the final configuration and implementation of the FPGA.

[0065] In terms of technical principles, step S102 utilizes the technologies of Model-Driven Engineering (MDE) and Hardware Description Language (HDL). The model-driven engineering method can effectively map the abstract algorithm model to the specific hardware resources through high-level model descriptions and automated model transformations. The hardware description language is used to generate the specific top-level design file, which describes all the resources and connection information required for FPGA configuration. Through the model-driven method, the system can automatically convert the high-level description of the algorithm IP core into a specific hardware implementation, reducing manual intervention and errors, and improving the design efficiency and accuracy.

[0066] In terms of the technical problems solved, step S102 mainly solves the problem of the effective mapping between the model variables of the algorithm IP core and the FPGA hardware resources. The hardware resources of the FPGA are limited and complex, and how to efficiently map the model variables of the algorithm IP core to these resources is a key problem that must be solved in the design process. By obtaining the hardware resource description information, the system can comprehensively understand the resource status of the FPGA; through the model-driven method, the system can automatically establish the mapping relationship between the model variables and the hardware resources, ensuring that the algorithm IP core can efficiently utilize the resources of the FPGA. In addition, dynamically generating the top-level design file further ensures the flexibility and adjustability of the design, and can quickly adapt to different application requirements and hardware platforms.

[0067] In terms of the achieved technical effects, through step S102, the system can efficiently and accurately establish the mapping relationship between the algorithm IP core model variables and the FPGA hardware resources, and dynamically generate an engineering configurable top-level design file according to this mapping relationship. This not only ensures that the algorithm IP core can make full use of the FPGA hardware resources, improving the resource utilization rate and system performance, but also reduces the manual intervention and errors in the design process through an automated model-driven method, improving the design efficiency and reliability. The dynamically generated top-level design file can quickly adapt to different application requirements and hardware platforms, enhancing the flexibility and scalability of the system.

[0068] For example, assume a team is developing an algorithm IP core for image processing. The team first obtains the FPGA hardware resource description information from the FPGA's resource management tool, including available logic units, memory blocks, DSP blocks, and I / O pins, etc. Next, the team analyzes the model variables of the algorithm IP core, such as the input / output ports of image data, filter parameters, clock, and reset signals, etc. Based on this information, the team uses the model-driven method to establish the mapping relationship between the model variables and the FPGA hardware resources. For example, map the input port of image data to specific I / O pins, map the filter parameters to programmable memory blocks, map the clock and reset signals to the global clock network, etc. After completing the establishment of the mapping relationship, the system dynamically generates the top-level design file of the FPGA according to this mapping relationship, which details all the resource allocation and connection information. Finally, the team uses this top-level design file to configure and implement the FPGA to ensure that the image processing algorithm can run efficiently on the FPGA.

[0069] In summary, through step S102, the system can efficiently and accurately establish the mapping relationship between the algorithm IP core model variables and the FPGA hardware resources, and dynamically generate an engineering configurable top-level design file. This process not only improves the design efficiency and accuracy, but also ensures that the algorithm IP core can make full use of the FPGA hardware resources, improving the system performance and resource utilization rate. Through the automated model-driven method, the manual intervention and errors are reduced, further improving the reliability and flexibility of the design. The dynamically generated top-level design file can quickly adapt to different application requirements and hardware platforms, providing strong support for the efficient operation and performance optimization of the system.

[0070] Step S103: Synthesize, place, and route the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0071] Optionally, in this embodiment, in step S103, the system performs synthesis, placement, and routing on the previously generated top-level design file through a preset design tool of a Field-Programmable Gate Array (FPGA), and finally generates a bitstream file that can be directly run on the FPGA. The specific technical process includes the following steps: First, the designer imports the top-level design file into the design tool of the FPGA. These tools usually include synthesis tools, placement and routing tools, and bitstream generation tools. The synthesis tool first processes the top-level design file, converts the high-level hardware description into a low-level logic gate circuit, and performs resource allocation and optimization. Next, the placement and routing tool, based on the synthesis result, specifically places the hardware resources such as logic units, registers, and I / O pins on the FPGA chip and determines the connection paths between the various units. Finally, the bitstream generation tool generates a bitstream file for configuring the FPGA according to the placement and routing result. The generated bitstream file contains all the information about the FPGA configuration and can be directly downloaded to the target hardware platform to start running.

[0072] In terms of technical principles, step S103 utilizes the synthesis, placement, and routing algorithms of the FPGA design tool. These algorithms optimize the hardware description to ensure the efficient implementation of the design on the FPGA. The synthesis algorithm converts the high-level hardware description into a low-level logic circuit and performs resource allocation and optimization to improve the efficiency and performance of the design. The placement algorithm is responsible for allocating the positions of the various logic units on the FPGA chip to ensure the reasonable utilization of resources and minimize latency. The routing algorithm determines the connection paths between the various logic units to ensure the reliability and speed of signal transmission. Finally, the bitstream generation algorithm integrates all this information into a bitstream file for configuring the FPGA.

[0073] In terms of the technical problems solved, step S103 mainly solves the problem of converting from the top-level design file to a runnable bitstream file. Although the top-level design file contains all the information of the design, it still needs to be converted into a specific hardware implementation through synthesis, placement, and routing algorithms. Through the synthesis tool, the system can optimize the high-level design description into a low-level logic circuit and perform resource allocation. The placement and routing tool ensures the reasonable distribution of logic units and connection paths, optimizing the performance and resource utilization of the design. Finally, the bitstream generation tool integrates all this information into a bitstream file to ensure that the design can run correctly on the FPGA.

[0074] In terms of the achieved technical effects, through step S103, the system can generate an efficient and reliable bitstream file and download it to the target hardware platform for operation. First, through the optimization of the synthesis tool, the design can be efficiently implemented on the FPGA, improving the performance and resource utilization rate of the system. The placement and routing tool ensures the reasonable distribution of logic units and connection paths, further optimizing the performance and reliability of the design. The finally generated bitstream file contains all the information for FPGA configuration and can directly run on the hardware platform, ensuring the correct implementation and stable operation of the design. Through the automated processing of these tools, manual intervention and errors in the design process are greatly reduced, improving the design efficiency and reliability.

[0075] For example, assume a team is developing a real-time video processing system. In step S103, they first import the previously generated top-level design file into the FPGA design tool. The synthesis tool processes the top-level design file, converts the high-level design description into a specific logic circuit, and performs optimization. Next, the placement and routing tool allocates the positions of logic units on the FPGA chip and determines the connection paths between various units to ensure the reliability and speed of signal transmission. Finally, the bitstream generation tool generates a bitstream file based on the placement and routing results, which contains all the information about FPGA configuration. The team downloads the generated bitstream file to the target hardware platform and starts the video processing system to ensure that the system can process video data in real time and meet the performance requirements.

[0076] In summary, through step S103, the system can efficiently and accurately convert the top-level design file into a runnable bitstream file and download it to the target hardware platform for operation. This process not only improves the design efficiency and accuracy but also ensures the efficient implementation and stable operation of the design on the FPGA. Through the automated processing of the synthesis, placement, and routing tools, manual intervention and errors in the design process are greatly reduced, further improving the reliability and performance of the design. The finally generated bitstream file can quickly adapt to different application requirements and hardware platforms, providing strong support for the efficient operation and performance optimization of the system.

[0077] As can be seen from the above description, the model processing method of the IP core for hardware-in-the-loop simulation provided by the embodiments of the present application can encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; perform synthesis, placement, and routing on the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0078] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation of the present application, referring to Figure 2 , the following specific content may further be included:

[0079] Step S201: Construct an algorithm model to be simulated in a preset modeling tool, and convert the algorithm model into an algorithm IP core that can run on a programmable array logic device through a programmable array logic device design tool;

[0080] Step S202: Define attribute content for each model variable in the description file of the algorithm IP core, where the attribute content includes at least one of variable name, port direction, data type, and initial value.

[0081] Optionally, in this embodiment, in step S201, the system constructs an algorithm model to be simulated in a preset modeling tool, and converts the algorithm model into an algorithm IP core that can run on an FPGA through a programmable array logic device (FPGA) design tool. The specific technical process includes the following links: First, the designer uses a graphical interface or programming language in the modeling tool to construct an algorithm model to be simulated. This model can include various signal processing, control logic, or data processing algorithms. The construction of the model usually needs to consider factors such as input / output, timing constraints, and resource requirements. Next, the designer exports the constructed algorithm model and converts it into hardware description language (HDL) code through the FPGA design tool. This step involves the synthesis and optimization of the model, converting the high-level algorithm description into a low-level logic circuit to adapt to the hardware architecture of the FPGA. Finally, the generated HDL code is encapsulated as an algorithm IP core for subsequent design and simulation.

[0082] In terms of the technical principle, step S201 utilizes the technologies of Model-Driven Design (MDD) and Hardware Description Language (HDL). The model-driven design method can intuitively express complex algorithmic logic and data streams through high-level abstract models. FPGA design tools then convert these high-level models into low-level hardware descriptions, and through synthesis and optimization, generate logic circuits that conform to the FPGA hardware architecture. Hardware description languages (such as VHDL or Verilog) are used to describe these logic circuits so that they can be implemented on the FPGA. Through this method, designers can quickly and accurately convert algorithm models into runnable hardware IP cores.

[0083] In terms of the technical problems solved, step S201 mainly solves the problem of converting from a high-level algorithm model to a low-level hardware implementation. Although constructing a high-level algorithm model is intuitive and easy to understand, how to efficiently convert it into a hardware implementation on the FPGA is a challenge. By using preset modeling tools and FPGA design tools, the system can automatically perform model conversion and optimization, reducing manual intervention and errors. In addition, the generated algorithm IP core encapsulates the specific hardware implementation details, making subsequent design and simulation more convenient.

[0084] In terms of the technical effects achieved, through step S201, the system can quickly and accurately convert a high-level algorithm model into an algorithm IP core that can run on the FPGA. First, through the graphical interface or programming language of the modeling tool, designers can intuitively construct complex algorithm models, improving the design efficiency. Then, through the synthesis and optimization of the FPGA design tool, the system can automatically convert the high-level model into a low-level hardware description, improving the accuracy and performance of the design. The finally generated algorithm IP core encapsulates the specific hardware implementation details, facilitating subsequent design, simulation, and verification, and ensuring the efficient implementation and stable operation of the system.

[0085] For example, assume a team is developing an algorithm for audio signal processing. In step S201, they first construct an audio signal processing algorithm model in the modeling tool, including modules such as filters, amplifiers, and equalizers. Next, the team exports the constructed algorithm model and, through the FPGA design tool, converts it into HDL code. The HDL code undergoes synthesis and optimization to generate logic circuits that conform to the FPGA architecture. Finally, these logic circuits are encapsulated as an algorithm IP core for subsequent design and simulation. Through this method, the team can quickly and accurately convert the audio signal processing algorithm model into a hardware implementation that can run on the FPGA, ensuring the efficient operation and performance optimization of the system.

[0086] In step S202, the system defines the attribute content for each model variable in the description file of the algorithm IP core. The specific technical process of implementation includes the following aspects: First, the designer analyzes the model variables in the algorithm IP core to determine the attribute content of each variable. These attribute contents include variable name, port direction, data type, and initial value, etc. Then, the designer defines the attribute content for each model variable in the description file of the algorithm IP core in a preset format. The variable name is used to identify the variable, the port direction indicates whether the variable is an input or an output, the data type defines the data format of the variable, and the initial value specifies the initial state of the variable. Finally, the system generates a description file containing these attribute contents to ensure the correct implementation and operation of the algorithm IP core on the FPGA.

[0087] In terms of technical principles, step S202 utilizes the technologies of hardware description language (HDL) and modular design. The hardware description language is used to define the logic circuit and variable attributes of the algorithm IP core. By accurately describing the attribute content of each variable, it ensures the accuracy of the hardware implementation. Modular design decomposes the complex system into multiple modules, and each module independently defines attributes and functions, improving the maintainability and scalability of the design. Through this method, the system can automatically generate the variable attribute description file, reducing manual intervention and errors, and ensuring the efficient implementation of the design.

[0088] In terms of the technical problems solved, step S202 mainly solves the problem of defining the variable attributes of the algorithm IP core. The variable attributes in the algorithm IP core are crucial for the hardware implementation. How to accurately define these attributes is a key link in the design process. By defining the variable attribute content in the description file, the system can ensure the correct implementation and operation of each variable on the FPGA. In addition, the automatic generation of the description file reduces the complexity and errors of manual definition, improving the efficiency and accuracy of the design.

[0089] In terms of the technical effects achieved, through step S202, the system can accurately define the attribute content of the algorithm IP core variables, ensuring the correctness of the hardware implementation and the stability of the operation. First, by defining the attribute content such as variable name, port direction, data type, and initial value, the system can accurately describe the function and state of each variable, ensuring the accuracy of the design. Then, by automatically generating the description file, it reduces the complexity and errors of manual definition, improving the design efficiency and reliability. The finally generated description file ensures the correct implementation and operation of the algorithm IP core on the FPGA, providing strong support for the efficient implementation and performance optimization of the system.

[0090] For example, assume that a team is developing an algorithm IP core for image processing. In step S202, they first analyze the model variables in the algorithm IP core to determine the attribute content of each variable. Then, in the description file, the team defines the attribute content for each model variable according to a preset format. For example, the variable "pixel_data" is defined as an input port, with a data type of 8-bit unsigned integer and an initial value of 0; the variable "filter_coeff" is defined as a programmable parameter, with a data type of 32-bit floating point number and an initial value of 1.0. Through this method, the team can accurately define the attribute content of the algorithm IP core variables, ensuring the correctness of the hardware implementation and the stability of operation.

[0091] In summary, through steps S201 and S202, the system can efficiently and accurately convert a high-level algorithm model into an algorithm IP core that can run on an FPGA, and define the attribute content for each model variable. This process not only improves the design efficiency and accuracy, but also ensures the correctness of the hardware implementation and the stability of operation. Through the use of automated tools, manual intervention and errors are reduced, further improving the design efficiency and reliability. The generated algorithm IP core and description file provide strong support for the efficient implementation and performance optimization of the system.

[0092] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation in the present application, refer to Figure 3 , it may specifically include the following content:

[0093] Step S301: Divide the model variables into two categories: input / output ports and parameters. Among them, the input / output ports are directly bound to the physical input / output channels of the hardware of the programmable array logic device for real-time data exchange;

[0094] Step S302: Divide the model variables of the parameter type into two categories: dynamically adjustable parameters and clock reset special signals. Among them, the dynamically adjustable parameters are mapped to the CPU register space through software dynamic adjustment.

[0095] Optionally, in this embodiment, in step S301, the system divides the model variables into two categories: input / output ports and parameters, each with different functions. The specific technical process for implementation includes the following steps: First, the designer classifies all the variables in the model to determine which variables need to be used as input / output ports and which variables are used as parameters. The input / output port variables are directly bound to the hardware physical input / output channels of the FPGA for real-time data exchange. These ports usually include sensor inputs, control signal outputs, etc., ensuring that the system can communicate with external devices in real time. The parameter variables, on the other hand, are used to configure and control the internal behavior of the system, including various algorithm parameters and control parameters. Through this division, the system can effectively manage and use the model variables, improving the clarity and maintainability of the design.

[0096] In terms of the technical principle, step S301 utilizes the port mapping and parameterized design techniques in hardware design. The port mapping technique associates the input / output port variables in the design with the physical pins of the FPGA to achieve communication between the design and external hardware. The parameterized design technique, by defining flexible parameters, enables the design to be configured and adjusted according to different application requirements. The combination of these two techniques enables the design to not only achieve real-time data exchange but also flexibly adjust the internal behavior of the system, achieving an efficient and flexible design effect.

[0097] In terms of the technical problems solved, step S301 mainly solves the problems of model variable management and real-time data exchange. Without reasonable classification and management of model variables, the design complexity will increase, making it difficult to maintain and debug. By dividing the variables into two categories: input / output ports and parameters, the system can manage the variables more clearly, improving the readability and maintainability of the design. In addition, by binding the input / output ports to the physical channels of the FPGA, the system can achieve real-time data exchange with external devices, meeting various application requirements.

[0098] In terms of the technical effects achieved, through step S301, the system can effectively manage the model variables, achieving the efficiency and flexibility of the design. First, through reasonable variable division, the designer can clearly understand and manage each part of the system, improving the maintainability and scalability of the design. Then, through the port mapping technique, the system can achieve real-time data exchange with external devices, ensuring the real-time performance and reliability of the system. Finally, through the parameterized design technique, the system can flexibly adjust the internal parameters to meet different application requirements, improving the flexibility and adaptability of the design.

[0099] For example, assume that a team is developing a real-time image processing system. In step S301, they first classify the variables in the model. Variables such as image data input and processing result output are regarded as input / output ports and are bound to the physical pins of the FPGA to achieve real-time data exchange with the camera and the display. At the same time, variables such as filter coefficients and thresholds are used as parameters to configure the image processing algorithm. Through this division, the team can clearly manage the variables and improve the maintainability and real-time performance of the design.

[0100] In step S302, the system further divides the model variables of the parameter type into two categories: dynamically adjustable parameters and clock reset special signals. The specific technical process of implementation includes the following links: First, the designers analyze the parameter variables to determine which parameters need to be dynamically adjusted during operation and which are clock reset special signals. The dynamically adjustable parameters are adjusted dynamically by software. These parameters are usually mapped to the register space of the CPU, and the designers can modify these parameters in real time through the software interface to adjust the behavior of the system. The clock reset special signals are used to control the clock and reset logic of the system to ensure the stable operation of the system. Through this division, the system can flexibly adjust the operating parameters while ensuring the reliability of the clock and reset signals.

[0101] In terms of technical principles, step S302 utilizes the technologies of dynamic parameter adjustment and clock reset control. The dynamic parameter adjustment technology maps the parameters to the register space of the CPU through the software interface, enabling the designers to modify the parameters in real time and improving the flexibility of the system. The clock reset control technology ensures the reliability of the clock and reset signals of the system, preventing the system from becoming unstable or having errors during operation. Through the combination of these two technologies, the system can flexibly adjust the operating parameters on the premise of ensuring stable operation, achieving an efficient and reliable design effect.

[0102] In terms of the technical problems solved, step S302 mainly solves the problems of dynamic parameter adjustment and clock reset control. Parameters may need to be adjusted according to actual requirements during the design and operation processes. If they cannot be adjusted dynamically, it will lead to a decrease in the flexibility of the design. By mapping the dynamically adjustable parameters to the CPU register space, the system can modify the parameters in real time to meet different application requirements. In addition, the clock and reset signals are crucial for the stable operation of the system. By treating these signals as special signals, the system can ensure their reliability and stability.

[0103] In terms of the achieved technical effects, through step S302, the system can flexibly adjust the operating parameters while ensuring the reliability of the clock and reset signals. First, through the dynamic parameter adjustment technology, designers can modify the system parameters in real time, improving the flexibility and adaptability of the design. Then, through the clock reset control technology, the system can ensure the reliability of the clock and reset signals, preventing instability or errors during operation. Finally, through reasonable parameter partitioning and management, the system can operate efficiently and reliably, meet different application requirements, and improve the performance and stability of the design.

[0104] For example, assume a team is developing an adaptive filter system. In step S302, they first partition parameters such as filter coefficients into dynamically adjustable parameters, map them to the CPU register space through a software interface, and designers can modify these parameters in real time to adapt to different signal environments. At the same time, the system's clock signal and reset signal are treated as special signals to ensure the stable operation of the system. Through this partitioning, the team can flexibly adjust the filter parameters, improve the adaptability and performance of the system, and ensure the stability and reliability of the system.

[0105] In summary, through steps S301 and S302, the system can efficiently and reliably manage and use model variables, achieving the efficiency and flexibility of the design. Through reasonable variable partitioning and dynamic adjustment technology, the system can meet different application requirements, improve the performance and adaptability of the design. At the same time, by ensuring the reliability of the clock and reset signals, the system can operate stably, preventing instability or errors during operation. Finally, the generated design scheme provides strong support for the efficient implementation and performance optimization of the system.

[0106] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation in the present application, referring to Figure 4 , it may specifically include the following content:

[0107] Step S401: Extract the detailed information of the model variables from the description file of the constructed algorithm IP core, and obtain the resource description information of the target programmable array logic device hardware platform;

[0108] Step S402: Establish an automatic mapping between the model variables and the hardware resources by using the model-driven method, where the model variables of the input / output port type are mapped to the corresponding hardware physical channels, the model variables of the dynamically adjustable parameter type are mapped to the register space accessible by the CPU, and the clock reset special information is mapped to the corresponding clock reset resource area.

[0109] Optionally, in this embodiment, in step S401, the system extracts the detailed information of the model variables from the description file of the constructed algorithm IP core and obtains the resource description information of the target programmable array logic device hardware platform. The specific technical process includes the following links: First, the system parses the description file of the algorithm IP core, which usually uses a standard hardware description language (such as VHDL or Verilog) or a high-level description language (such as HLS). During the parsing process, the system extracts the detailed information of the model variables, including the type, name, bit width, etc. of the variables. Then, the system obtains the resource description information of the target FPGA hardware platform, which is usually provided by the FPGA manufacturer and includes the quantity, type, and distribution of the hardware resources. Through the above steps, the system can comprehensively understand the detailed information of the algorithm IP core and the target hardware platform, laying a foundation for the subsequent steps.

[0110] In terms of technical principles, step S401 utilizes the technologies of hardware description language parsing and hardware resource description. The hardware description language parsing technology is used to extract the model variable information in the algorithm IP core. By parsing the description file, the system can accurately obtain the type, name, and other attributes of the variables. The hardware resource description technology is used to obtain the resource information of the target FPGA platform. By reading the resource description file provided by the manufacturer, the system can understand the resource distribution and availability of the hardware platform. The combination of these two technologies enables the system to comprehensively master the detailed information of the algorithm and the hardware platform, laying a foundation for the subsequent automatic mapping.

[0111] In terms of the technical problems solved, step S401 mainly solves the problems of extracting the variable information of the algorithm IP core and obtaining the resources of the hardware platform. The algorithm IP core usually contains a large number of variables. Without automated parsing means, manually extracting this information will be very cumbersome and error-prone. By adopting the hardware description language parsing technology, the system can automatically extract the variable information, improving efficiency and accuracy. In addition, the resource information of the hardware platform is crucial for the mapping process. Without detailed resource descriptions, the mapping process cannot proceed. By obtaining the resource description information, the system can comprehensively master the resource situation of the hardware platform and provide support for automatic mapping.

[0112] In terms of the technical effects achieved, through step S401, the system can efficiently and accurately extract the variable information of the algorithm IP core and comprehensively understand the resource situation of the target hardware platform. First, through the automated hardware description language parsing technology, the system can efficiently extract the variable information, improving work efficiency and accuracy. Then, by obtaining the detailed hardware resource description information, the system can comprehensively understand the resource distribution and availability of the hardware platform and provide support for the subsequent mapping process. Finally, through the combination of these two links, the system can comprehensively master the detailed information of the algorithm and the hardware platform, laying a foundation for efficient automatic mapping.

[0113] For example, assume that a team is developing a real-time signal processing system. In step S401, they first parse the description file of the algorithm IP core to extract detailed information about variables such as input signals, output signals, and filter coefficients in the signal processing algorithm. Then, they obtain the resource description information of the target FPGA platform to understand the available logic units, storage resources, and I / O channels on the hardware platform. Through these steps, the team can comprehensively master the detailed information of the algorithm and the hardware platform, preparing for the subsequent mapping work.

[0114] In step S402, the system uses a model-driven method to establish an automatic mapping between model variables and hardware resources. The specific technical process includes the following links: First, the system establishes a mapping relationship between variables and resources based on the model variable and hardware resource information extracted in step S401. Model variables of input / output port types are mapped to corresponding hardware physical channels. Through this mapping, the system can achieve real-time data exchange with external devices. Model variables of parameter types that can be dynamically adjusted are mapped to the register space accessible by the CPU, and these parameters can be dynamically adjusted at runtime through a software interface. Special information such as clock reset is mapped to the corresponding clock reset resource area. Through this mapping, the system can ensure the reliability of clock and reset signals. Through the above steps, the system can achieve an automatic mapping between model variables and hardware resources, improving the efficiency and accuracy of the design.

[0115] In terms of technical principles, step S402 utilizes the model-driven method and automatic mapping technology. The model-driven method enables the design to automatically match hardware resources by establishing a mapping relationship between variables and resources, improving the design efficiency. The automatic mapping technology maps model variables to corresponding hardware resources through predefined rules and algorithms, ensuring the accuracy and efficiency of the mapping process. The combination of these two technologies enables the system to efficiently and accurately implement the mapping between model variables and hardware resources, improving the automation level and efficiency of the design.

[0116] In terms of the technical problems solved, step S402 mainly solves the problem of mapping between model variables and hardware resources. The matching of model variables and hardware resources is a key link in the design. Without automated mapping means, manual mapping would be very cumbersome and error-prone. By adopting the model-driven method and automatic mapping technology, the system can automatically establish a mapping relationship between variables and resources, improving the mapping efficiency and accuracy. In addition, through reasonable mapping rules and algorithms, the system can ensure the reliability and efficiency of the mapping process, meeting the design requirements.

[0117] In terms of the achieved technical effects, through step S402, the system can efficiently and accurately implement the mapping between model variables and hardware resources, improving the automation level and efficiency of the design. First, through the model-driven method, the system can automatically establish the mapping relationship between variables and resources, improving the design efficiency and accuracy. Then, through the automatic mapping technology, the system can efficiently and accurately map model variables to the corresponding hardware resources, improving the reliability and efficiency of the mapping. Finally, through the combination of these two links, the system can achieve the efficient mapping between model variables and hardware resources, improving the automation level and efficiency of the design.

[0118] For example, assume a team is developing an adaptive filter system. In step S402, they first adopt the model-driven method to establish the mapping relationship between variables such as filter coefficients, input signals, and output signals and hardware resources. The input signal and output signal are mapped to the physical I / O channels of the FPGA, the filter coefficients are mapped to the register space accessible by the CPU, and the clock signal and reset signal are mapped to the corresponding hardware resource areas. Through these steps, the team can efficiently and accurately implement the mapping between model variables and hardware resources, improving the real-time performance and flexibility of the system.

[0119] In summary, through steps S401 and S402, the system can efficiently and accurately extract the variable information of the algorithm IP core and implement the automatic mapping between model variables and hardware resources. Through reasonable technical means and processes, the system can improve the automation level and efficiency of the design, meet different application requirements, and improve the performance and adaptability of the design. Finally, the generated design scheme provides strong support for the efficient implementation and performance optimization of the system.

[0120] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation in the present application, referring to Figure 5 , it may specifically include the following content:

[0121] Step S501: Generate a configurable description of the corresponding programmable array logic device project according to the mapping relationship between the model variables and the hardware resources;

[0122] Step S502: Obtain the corresponding configurable top-level design file through the preset design tool of the programmable array logic device.

[0123] Optionally, in this embodiment, in step S501, the system generates a corresponding configurable description of the programmable array logic device project according to the mapping relationship between the model variables and the hardware resources. The specific technical process includes the following aspects: First, the system utilizes the mapping relationship between the model variables and the hardware resources established in the previous steps, which details the specific location and configuration of each model variable in the hardware resources. Then, the system generates a configurable description file for the programmable array logic device project according to these mapping relationships. These files usually adopt standard hardware description languages (such as VHDL or Verilog) or configuration script formats. The generated description files define in detail the implementation method of each model variable in the hardware, including the connection of input and output ports, the configuration of registers, the management of clock and reset signals, etc. Through the above steps, the system can generate a hardware configuration file for implementing the algorithm, laying a foundation for subsequent hardware design and implementation.

[0124] In terms of technical principles, step S501 utilizes the technologies of hardware description language generation and configuration file generation. The hardware description language generation technology automatically generates corresponding hardware description files by parsing the mapping relationship between the model variables and the hardware resources. These files detail all aspects of the hardware design, including logical connections, resource allocation, and signal management, etc. The configuration file generation technology generates configuration files that conform to specific formats and specifications through predefined templates and rules. The combination of these two technologies enables the system to generate configuration descriptions for hardware design efficiently and accurately, providing support for subsequent hardware implementation.

[0125] In terms of the technical problems solved, step S501 mainly solves the problems of the implementation of the mapping relationship between the model variables and the hardware resources and the generation of the hardware configuration file. The mapping relationship between the model variables and the hardware resources is the key to the design. Without automated generation means, manually writing hardware description files would be very cumbersome and error-prone. By adopting the hardware description language generation technology, the system can automatically generate corresponding hardware description files, improving efficiency and accuracy. In addition, through the configuration file generation technology, the system can generate configuration files that conform to specific formats and specifications, ensuring the correctness and consistency of the hardware design.

[0126] In terms of the technical effects achieved, through step S501, the system can generate a configuration description file for hardware design efficiently and accurately. First, through the automated hardware description language generation technology, the system can generate hardware description files efficiently and accurately, improving the design efficiency and accuracy. Then, through the configuration file generation technology, the system can generate configuration files that conform to specific formats and specifications, ensuring the correctness and consistency of the hardware design. Finally, through the combination of these two aspects, the system can generate a hardware configuration file for implementing the algorithm, laying a foundation for subsequent hardware design and implementation.

[0127] For example, assume that a team is developing an image processing system. In step S501, they first generate a hardware configuration description file for the image processing algorithm by using the mapping relationship between the model variables and hardware resources established in the previous steps. These files detail how the input image signal, output processing results, filter parameters, etc. are implemented in hardware. Through these steps, the team can generate a hardware configuration file for implementing the image processing algorithm, laying the foundation for subsequent hardware design and implementation.

[0128] In step S502, the system obtains the corresponding configurable top-level design file through the preset tools of the programmable array logic device. The specific technical process of implementation includes the following links: First, the system uses the preset tools of the programmable array logic device (such as Vivado from Xilinx or Quartus from Intel) to import the hardware configuration description file generated in step S501. These tools usually provide a graphical interface and an automated script interface, enabling convenient import and management of hardware configuration files. Then, the system uses the preset tools to generate the corresponding configurable top-level design files, which usually adopt a hardware description language or configuration script format and detail the structure and configuration of the entire hardware design. Through the above steps, the system can generate a top-level design file for hardware implementation, providing support for the final hardware implementation.

[0129] In terms of the technical principle, step S502 utilizes the technologies of hardware design tools and top-level design file generation. Hardware design tools, by providing a graphical interface and an automated script interface, enable users to conveniently import and manage hardware configuration files and generate the corresponding top-level design files. The top-level design file generation technology, by parsing the hardware configuration file, automatically generates a top-level design file that conforms to specific formats and specifications, detailing the structure and configuration of the hardware design. The combination of these two technologies enables the system to efficiently and accurately generate a top-level design file for hardware implementation, providing support for the final hardware implementation.

[0130] In terms of the technical problems solved, step S502 mainly solves the problems of hardware configuration file import and top-level design file generation. The import and management of hardware configuration files are key links in the design. Without automated tool support, manual import and management would be very cumbersome and error-prone. By adopting hardware design tools, the system can conveniently import and manage hardware configuration files, improving efficiency and accuracy. In addition, through the top-level design file generation technology, the system can generate a top-level design file that conforms to specific formats and specifications, ensuring the correctness and consistency of the hardware design.

[0131] In terms of the achieved technical effects, through step S502, the system can efficiently and accurately generate a top-level design file for hardware implementation. First, through the hardware design tool, the system can conveniently import and manage the hardware configuration file, improving the design efficiency and accuracy. Then, through the top-level design file generation technology, the system can generate a top-level design file that conforms to specific formats and specifications, ensuring the correctness and consistency of the hardware design. Finally, through the combination of these two links, the system can generate a top-level design file for implementing the algorithm, providing support for the final hardware implementation.

[0132] For example, assume a team is developing a wireless communication system. In step S502, they first use the preset tool of the programmable array logic device to import the hardware configuration description file generated in step S501. Then, they use the preset tool to generate the top-level design files of the wireless communication system, which define in detail the implementation methods of transmitting signals, receiving signals, signal processing algorithms, etc. in the hardware. Through these steps, the team can generate a top-level design file for implementing the wireless communication system, providing support for the final hardware implementation.

[0133] In summary, through steps S501 and S502, the system can efficiently and accurately generate the configuration description file and the top-level design file for hardware design and implementation. Through reasonable technical means and processes, the system can improve the automation degree and efficiency of the design, meet different application requirements, and improve the performance and adaptability of the design. Finally, the generated design scheme provides strong support for the efficient implementation and performance optimization of the system.

[0134] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation in the present application, referring to Figure 6 , it may specifically include the following content:

[0135] Step S601: Import the top-level design file of the programmable array logic device into a preset design tool and convert it into a corresponding logic netlist;

[0136] Step S602: Perform placement and routing process operations through the logic netlist to obtain a corresponding bitstream file.

[0137] Optionally, in this embodiment, in step S601, the system imports the top-level design file of the programmable array logic device into a preset design tool and converts it into a corresponding logic netlist. The specific technical process includes the following steps: First, the system selects a suitable preset design tool, such as Vivado from Xilinx or Quartus from Intel, which can support the conversion of the top-level design file into a logic netlist. Then, the top-level design files generated in the previous step are imported into the selected design tool. These files usually adopt a hardware description language (such as VHDL or Verilog) or a configuration script format. The design tool automatically generates the corresponding logic netlist by parsing the top-level design file. The logic netlist is an intermediate representation of the design, which details the logical structure and connection relationships of the circuit. Through the above steps, the system can generate a logic netlist for subsequent placement and routing, laying a foundation for hardware implementation.

[0138] In terms of technical principles, step S601 utilizes the technologies of hardware description language parsing and logic netlist generation. The hardware description language parsing technology extracts the logical structure and connection relationships of the circuit by parsing the top-level design file. The logic netlist generation technology then generates the corresponding logic netlist based on the parsing results, which details the logical structure and connection relationships of the circuit. The combination of these two technologies enables the system to efficiently and accurately generate a logic netlist for subsequent placement and routing, providing support for hardware implementation.

[0139] In terms of the technical problems solved, step S601 mainly solves the problem of converting the top-level design file into a logic netlist. The top-level design file is a high-level abstract representation of the hardware design. Without automated conversion means, manually generating a logic netlist would be very cumbersome and error-prone. By adopting the hardware description language parsing and logic netlist generation technologies, the system can automatically generate the corresponding logic netlist, improving efficiency and accuracy. In addition, through the preset design tool, the system can conveniently manage and convert the top-level design file, ensuring the smoothness and efficiency of the design process.

[0140] In terms of the technical effects achieved, through step S601, the system can efficiently and accurately generate a logic netlist for subsequent placement and routing. First, through the hardware description language parsing technology, the system can accurately extract the logical structure and connection relationships in the top-level design file, improving the accuracy of the design. Then, through the logic netlist generation technology, the system can generate a logic netlist that details the logical structure and connection relationships of the circuit, providing support for subsequent placement and routing. Finally, through the preset design tool, the system can conveniently manage and convert the top-level design file, improving the efficiency and smoothness of the design process.

[0141] For example, assume that a team is developing a signal processing system. In step S601, they first select Vivado from Xilinx as the preset design tool and import the top-level design file generated in the previous step into Vivado. By parsing the top-level design file, Vivado automatically generates the logic netlist of the signal processing system, which details the logical relationships among signal input, processing modules, and output. Through these steps, the team can generate the logic netlist for subsequent placement and routing, laying the foundation for the hardware implementation of the signal processing system.

[0142] In step S602, the system performs placement and routing process operations through the logic netlist to obtain the corresponding bitstream file. The specific technical processes involved include the following steps: First, the system uses a preset design tool (such as Vivado or Quartus) to import the logic netlist generated in step S601. These tools provide powerful placement and routing functions and can automatically perform placement and routing operations based on the logic netlist. Next, through the placement and routing algorithm, the system maps the logic cells in the logic netlist to specific hardware resources and optimizes the signal paths to improve performance and reduce latency. After placement and routing are completed, the system generates the corresponding bitstream file. The bitstream file is the final file for configuring programmable array logic devices and contains all the information required to implement the circuit function. Through the above steps, the system can generate the bitstream file for hardware implementation, providing support for the final hardware configuration.

[0143] In terms of technical principles, step S602 utilizes the placement and routing algorithm and bitstream generation technology. The placement and routing algorithm improves the performance of the design and reduces latency by optimizing the mapping of logic cells and signal paths. The bitstream generation technology generates the bitstream file containing all the circuit function information based on the placement and routing results. The combination of these two technologies enables the system to efficiently and accurately generate the bitstream file for hardware implementation, providing support for the final hardware configuration.

[0144] In terms of the technical problems solved, step S602 mainly solves the problems of logic netlist placement and routing and bitstream file generation. Placement and routing are key links in hardware design. Without the support of automated tools, manual placement and routing would be very cumbersome and error-prone. By adopting the placement and routing algorithm, the system can automatically perform placement and routing operations, improving efficiency and accuracy. In addition, through the bitstream generation technology, the system can generate the bitstream file containing all the circuit function information, ensuring the correctness and consistency of the hardware configuration.

[0145] In terms of the achieved technical effects, through step S602, the system can efficiently and accurately generate a bitstream file for hardware implementation. First, through the placement and routing algorithm, the system can optimize the mapping of logic units and signal paths, improve the performance of the design, and reduce latency. Then, through the bitstream generation technology, the system can generate a bitstream file containing all circuit function information to support hardware configuration. Finally, through the preset design tool, the system can conveniently manage and generate the bitstream file, improving the efficiency and smoothness of the design process.

[0146] For example, assume a team is developing an image processing system. In step S602, they first use Vivado to import the logic netlist generated in step S601. Vivado maps the logic units of the image processing system to specific hardware resources through the placement and routing algorithm and optimizes the signal paths. After the placement and routing are completed, Vivado generates a bitstream file for the image processing system, which contains all the information required to implement the image processing function. Through these steps, the team can generate a bitstream file for hardware implementation to support the final hardware configuration of the image processing system.

[0147] In summary, through steps S601 and S602, the system can efficiently and accurately generate a logic netlist and a bitstream file for hardware implementation. Through reasonable technical means and processes, the system can improve the automation degree and efficiency of the design, meet different application requirements, and improve the performance and adaptability of the design. Finally, the generated design solution provides strong support for the efficient implementation and performance optimization of the system.

[0148] In an embodiment of the model processing method of the IP core for hardware-in-the-loop simulation in the present application, referring to Figure 7 , it may specifically include the following content:

[0149] Step S701: Transmit the bitstream file to the hardware platform of the corresponding target programmable array logic device;

[0150] Step S702: Start the execution of the bitstream file on the hardware platform of the target programmable array logic device.

[0151] Optionally, in this embodiment, in step S701, the system transfers the bitstream file to the hardware platform of the corresponding target programmable array logic device. The specific technical process includes the following steps: First, the system needs to identify the type and interface of the target hardware platform, such as USB, JTAG or Ethernet interface, etc. Then, through the preset transmission protocol, the system transfers the bitstream file from a computer or other storage device to the target hardware platform. During the transmission process, the system needs to ensure the integrity and accuracy of the bitstream file and verify it through technical means such as checksums. After the transmission is completed, the bitstream file will be stored in the configuration memory of the target hardware platform and wait for subsequent execution operations.

[0152] In terms of technical principles, step S701 utilizes data transmission and verification technologies. The data transmission technology transfers the bitstream file from a computer or other storage device to the target hardware platform through the preset transmission protocol. The verification technology ensures the integrity and accuracy of the bitstream file during the transmission process through means such as checksums. The combination of these two technologies enables the system to efficiently and accurately transfer the bitstream file to the target hardware platform and provide support for hardware configuration.

[0153] In terms of the technical problems solved, step S701 mainly solves the problem of bitstream file transmission. The bitstream file is the key file for configuring the programmable array logic device. If an error occurs during the transmission process, it may lead to hardware configuration failure or abnormal functions. By adopting data transmission and verification technologies, the system can ensure the integrity and accuracy of the bitstream file during the transmission process, improving the reliability and stability of the transmission. In addition, through the preset transmission protocol, the system can adapt to different hardware platforms and interfaces to ensure that the bitstream file can be successfully transferred to the target hardware platform.

[0154] In terms of the technical effects achieved, through step S701, the system can efficiently and accurately transfer the bitstream file to the target hardware platform. First, through the data transmission technology, the system can adapt to the requirements of different hardware platforms and interfaces to ensure that the bitstream file can be successfully transferred. Then, through the verification technology, the system can ensure the integrity and accuracy of the bitstream file during the transmission process, improving the reliability and stability of the transmission. Finally, through the preset transmission protocol, the system can efficiently manage and transfer the bitstream file to provide support for hardware configuration.

[0155] For example, assume a team is developing an embedded control system. In step S701, they first identify the type and interface of the target hardware platform and determine to transfer the bitstream file through the JTAG interface. The system transfers the bitstream file from the computer to the target hardware platform through a preset JTAG transfer protocol. During the transfer process, the system ensures the integrity and accuracy of the bitstream file through checksum technology and finally stores the bitstream file in the configuration memory of the target hardware platform to prepare for subsequent execution operations.

[0156] In step S702, the system starts the execution of the bitstream file on the hardware platform of the target programmable array logic device. The specific technical process includes the following links: First, the system sends a start command to the target hardware platform through a control interface (such as JTAG or SPI) to trigger the loading and execution of the bitstream file. After receiving the start command, the target hardware platform loads the bitstream file stored in the configuration memory into the programmable array logic device to complete the hardware configuration. After the configuration is completed, the target hardware platform will start working according to the logical structure and functions defined in the bitstream file to implement the designed hardware functions.

[0157] In terms of technical principles, step S702 utilizes hardware configuration and start control technologies. The hardware configuration technology configures the programmable array logic device into the designed logical structure and functions by loading the bitstream file. The start control technology triggers the loading and execution of the bitstream file by sending a start command through the control interface. The combination of these two technologies enables the system to efficiently and accurately start the execution of the bitstream file on the target hardware platform and implement the designed hardware functions.

[0158] In terms of the technical problems solved, step S702 mainly solves the problems of bitstream file loading and execution. The bitstream file contains all the information for implementing the circuit functions. If errors occur during the loading and execution processes, it may lead to hardware configuration failure or abnormal functions. By adopting hardware configuration and start control technologies, the system can ensure the correctness and consistency of the bitstream file during the loading and execution processes, improving the reliability and stability of the hardware configuration. In addition, through the control interface, the system can conveniently manage and control the startup process of the hardware platform to ensure the smooth execution of the bitstream file.

[0159] In terms of the achieved technical effects, through step S702, the system can efficiently and accurately start the execution of the bitstream file on the target hardware platform. First, through the hardware configuration technology, the system can accurately load the logical structure and functions in the bitstream file into the programmable array logic device to achieve hardware configuration. Then, through the startup control technology, the system can conveniently manage and control the startup process of the hardware platform to ensure the smooth execution of the bitstream file. Finally, through the control interface, the system can efficiently manage and start the hardware configuration, improving the efficiency and stability of the hardware implementation.

[0160] For example, assume a team is developing a communication system. In step S702, they send a startup command to the target hardware platform through the JTAG interface to trigger the loading and execution of the bitstream file. After receiving the startup command, the target hardware platform loads the bitstream file stored in the configuration memory into the programmable array logic device to complete the hardware configuration. After the configuration is completed, the communication system starts to work according to the logical structure and functions defined in the bitstream file to achieve signal processing and transmission functions. Through these steps, the team can efficiently and accurately start the execution of the bitstream file on the target hardware platform, providing support for the implementation of the communication system.

[0161] In summary, through steps S701 and S702, the system can efficiently and accurately transfer the bitstream file to the target hardware platform and start the execution of the bitstream file on the hardware platform. Through reasonable technical means and processes, the system can improve the automation degree and efficiency of hardware configuration, meet different application requirements, and improve the performance and adaptability of the hardware implementation. Finally, the generated design solution provides strong support for the efficient implementation and performance optimization of the system.

[0162] In order to effectively improve the simulation efficiency and accuracy, an embodiment of a model processing device for an IP core for hardware-in-the-loop simulation is provided in the present application, which is used to implement all or part of the content of the model processing method for the IP core for hardware-in-the-loop simulation. Refer to Figure 8 The model processing device for the IP core for hardware-in-the-loop simulation specifically includes the following content:

[0163] The simulation model encapsulation module 10 is used to encapsulate the algorithm model to be simulated into a reusable algorithm IP core of the programmable array logic device, define the attributes of the model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0164] The mapping relationship construction module 20 is configured to obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the model variables and the hardware resource description information by using a model-driven method based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0165] The file execution module 30 is configured to perform synthesis, placement, and routing on the top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to a target hardware platform to start running.

[0166] As can be seen from the above description, the model processing device for the IP core for hardware-in-the-loop simulation provided by the embodiments of the present application can encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; perform synthesis, placement, and routing on the top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to a target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0167] From a hardware perspective, in order to effectively improve the simulation efficiency and accuracy, the embodiments of the present application provide an electronic device for implementing all or part of the content in the model processing method for the IP core for hardware-in-the-loop simulation. The electronic device specifically includes the following content:

[0168] A processor, a memory, a communication interface, and a bus; wherein, the processor, the memory, and the communication interface complete communication with each other through the bus; the communication interface is used to implement information transmission between the model processing device for the IP core for hardware-in-the-loop simulation and related devices such as a core business system, a user terminal, and a related database. The logic controller can be a desktop computer, a tablet computer, a mobile terminal, etc., and this embodiment is not limited thereto. In this embodiment, the logic controller can be implemented with reference to the embodiments of the model processing method for the IP core for hardware-in-the-loop simulation and the embodiments of the model processing device for the IP core for hardware-in-the-loop simulation, and the content is incorporated herein, and the repeated parts will not be described again.

[0169] It can be understood that the user terminal may include a smart phone, a tablet electronic device, a network set-top box, a portable computer, a desktop computer, a personal digital assistant (PDA), a vehicle-mounted device, a smart wearable device, etc. Among them, the smart wearable device may include smart glasses, a smart watch, a smart bracelet, etc.

[0170] In practical applications, part of the model processing method of the IP core for hardware-in-the-loop simulation can be executed on the electronic device side as described above, or all operations can be completed in the client device. Specifically, it can be selected according to the processing capacity of the client device and the limitations of the user usage scenario, etc. This application does not make any limitations in this regard. If all operations are completed in the client device, the client device may further include a processor.

[0171] The above-mentioned client device may have a communication module (i.e., a communication unit), and can be communicatively connected to a remote server to realize data transmission with the server. The server may include a server on the task scheduling center side, and in other implementation scenarios, it may also include a server of an intermediate platform, such as a server of a third-party server platform communicatively linked to the task scheduling center server. The server may include a single computer device, or may include a server cluster composed of multiple servers, or a server structure of a distributed device.

[0172] Figure 9 It is a schematic block diagram of the system composition of the electronic device 9600 according to an embodiment of the present application. As Figure 9 shown, the electronic device 9600 may include a central processing unit 9100 and a memory 9140; the memory 9140 is coupled to the central processing unit 9100. It should be noted that this Figure 9 is exemplary; other types of structures can also be used to supplement or replace this structure to implement telecommunication functions or other functions.

[0173] In one embodiment, the function of the model processing method of the IP core for hardware-in-the-loop simulation can be integrated into the central processing unit 9100. Among them, the central processing unit 9100 may be configured to perform the following controls:

[0174] Step S101: Encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0175] Step S102: Obtain the hardware resource description information of the programmable array logic device. Based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, use the model-driven method to establish the mapping relationship between the model variables and the hardware resource description information, and dynamically generate the project-configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0176] Step S103: Through the preset design tool of the programmable array logic device, perform synthesis, placement, and routing on the top-level design file to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0177] As can be seen from the above description, for the electronic device provided in the embodiment of the present application, by encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defining the attributes of the model variables in the algorithm description of the algorithm IP core, and dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; through the preset design tool of the programmable array logic device, perform synthesis, placement, and routing on the top-level design file to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0178] In another implementation, the model processing device of the IP core for hardware-in-the-loop simulation can be separately configured from the central processing unit 9100. For example, the model processing device of the IP core for hardware-in-the-loop simulation can be configured as a chip connected to the central processing unit 9100, and the function of the model processing method of the IP core for hardware-in-the-loop simulation can be realized through the control of the central processing unit.

[0179] As Figure 9 shown, the electronic device 9600 may further include: a communication module 9110, an input unit 9120, an audio processor 9130, a display 9160, and a power supply 9170. It should be noted that the electronic device 9600 does not necessarily have to include all the components shown in Figure 9 ; in addition, the electronic device 9600 may further include components not shown in Figure 9 , and reference can be made to the prior art.

[0180] As Figure 9 shown, the central processing unit 9100 is sometimes also referred to as a controller or an operation control, and may include a microprocessor or other processor devices and / or logic devices. The central processing unit 9100 receives inputs and controls the operations of the various components of the electronic device 9600.

[0181] Among them, the memory 9140 can be, for example, one or more of a buffer, a flash memory, a hard drive, a removable medium, a volatile memory, a non-volatile memory, or other suitable devices. It can store the above information related to failures, and can also store a program for executing relevant information. And the central processing unit 9100 can execute the program stored in the memory 9140 to achieve information storage or processing, etc.

[0182] The input unit 9120 provides an input to the central processing unit 9100. The input unit 9120 is, for example, a key or a touch input device. The power supply 9170 is used to supply power to the electronic device 9600. The display 9160 is used to display display objects such as images and texts. The display can be, for example, an LCD display, but is not limited thereto.

[0183] The memory 9140 can be a solid-state memory. For example, it can be a read-only memory (ROM), a random access memory (RAM), a SIM card, etc. It can also be a memory that stores information even when power is off, can be selectively erased, and has more data. An example of such a memory is sometimes referred to as an EPROM, etc. The memory 9140 can also be some other type of device. The memory 9140 includes a buffer memory 9141 (sometimes referred to as a buffer). The memory 9140 can include an application / function storage unit 9142, which is used to store application programs and function programs or the processes for operating the electronic device 9600 through the central processing unit 9100.

[0184] The memory 9140 can also include a data storage unit 9143, which is used to store data, such as contacts, digital data, pictures, sounds, and / or any other data used by the electronic device. The driver storage unit 9144 of the memory 9140 can include various drivers of the electronic device for communication functions and / or for executing other functions of the electronic device (such as a messaging application, an address book application, etc.).

[0185] The communication module 9110 is a transmitter / receiver that transmits and receives signals via the antenna 9111. The communication module 9110 (transmitter / receiver) is coupled to the central processing unit 9100 to provide an input signal and receive an output signal, which can be the same as in the case of a conventional mobile communication terminal.

[0186] Based on different communication technologies, in the same electronic device, multiple communication modules 9110 can be provided, such as a cellular network module, a Bluetooth module, and / or a wireless local area network module, etc. The communication module 9110 (transmitter / receiver) is also coupled to a speaker 9131 and a microphone 9132 via an audio processor 9130 to provide an audio output via the speaker 9131 and receive an audio input from the microphone 9132, thereby implementing normal telecommunication functions. The audio processor 9130 may include any suitable buffer, decoder, amplifier, etc. Additionally, the audio processor 9130 is also coupled to a central processor 9100, enabling recording on the device through the microphone 9132 and playing the sound stored on the device through the speaker 9131.

[0187] Embodiments of the present application also provide a computer-readable storage medium capable of implementing all steps in the model processing method for an IP core for hardware-in-the-loop simulation where the execution subject in the above embodiments is a server or a client. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, it implements all steps in the model processing method for an IP core for hardware-in-the-loop simulation where the execution subject in the above embodiments is a server or a client. For example, when the processor executes the computer program, the following steps are implemented:

[0188] Step S101: Package the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0189] Step S102: Obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the model variables of the algorithm IP core and the hardware resource description information based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device by using a model-driven method, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0190] Step S103: Synthesize, place, and route the top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to a target hardware platform to start running.

[0191] As can be seen from the above description, the computer-readable storage medium provided by the embodiments of the present application encapsulates the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defines the attributes of model variables in the algorithm description of the algorithm IP core, and divides the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; the top-level design file is synthesized, placed, and routed through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and the bitstream file is downloaded to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0192] The embodiments of the present application also provide a computer program product that can implement all steps in the model processing method of the IP core for hardware-in-the-loop simulation whose execution subject in the above embodiments is a server or a client. When the computer program / instructions are executed by a processor, the steps of the model processing method of the IP core for hardware-in-the-loop simulation are implemented. For example, the computer program / instructions implement the following steps:

[0193] Step S101: Encapsulate the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, define the attributes of model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals;

[0194] Step S102: Obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the model variables and the hardware resource description information by using a model-driven method based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generate an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship;

[0195] Step S103: Synthesize, place, and route the top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

[0196] As can be seen from the above description, the computer program product provided by the embodiments of the present application encapsulates the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defines the attributes of model variables in the algorithm description of the algorithm IP core, and divides the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; the top-level design file is synthesized, placed, and routed through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and the bitstream file is downloaded to the target hardware platform to start running, thereby effectively improving the simulation efficiency and accuracy.

[0197] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, apparatus, or computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0198] The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (apparatus), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one or more of the processes Figure 1 or multiple processes and / or blocks

[0199] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one or more of the processes Figure 1 or multiple processes and / or blocks

[0200] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, so that the instructions executed on the computer or other programmable device provide means for implementing the functions specified in Figure 1Steps of one or more processes and / or blocks Figure 1 Steps of functions specified in one or more blocks.

[0201] Specific embodiments are used in the present invention to illustrate the principles and implementation manners of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those of ordinary skill in the art, according to the idea of the present invention, there will be changes in the specific implementation manners and application scopes. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A model processing method for an IP core used in hardware-in-the-loop simulation, characterized in that The method includes: Encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device, defining the attributes of model variables in the algorithm description of the algorithm IP core, and dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; Obtaining the hardware resource description information of the programmable array logic device, establishing a mapping relationship between the model variables and the hardware resource description information by using a model-driven method based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device, and dynamically generating an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship; Performing comprehensive placement and routing on the top-level design file through a preset design tool of the programmable array logic device to generate a corresponding bitstream file that can be directly run on the programmable array logic device, and downloading the bitstream file to a target hardware platform to start running.

2. The model processing method of the IP core for semi-physical simulation according to claim 1, wherein, The encapsulating the algorithm model to be simulated into an algorithm IP core of a reusable programmable array logic device and defining the attributes of model variables in the algorithm description of the algorithm IP core includes: Constructing an algorithm model to be simulated in a preset modeling tool, and converting the algorithm model into an algorithm IP core that can run on a programmable array logic device through a programmable array logic device-related tool; Defining attribute content for each model variable in the description file of the algorithm IP core, where the attribute content includes at least one of variable name, port direction, data type, and initial value.

3. The model processing method of the IP core for hardware-in-the-loop simulation according to claim 1, wherein The dividing the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals includes: Dividing the model variables into two categories: input / output ports and parameters, where the input / output ports are directly bound to the physical input / output channels of the hardware of the programmable array logic device for real-time data exchange; Dividing the model variables of the parameter type into two categories: dynamically adjustable parameters and clock reset special signals, where the dynamically adjustable parameters are mapped to the CPU register space through software dynamic adjustment.

4. The model processing method for the IP core used in hardware-in-the-loop simulation according to claim 1, wherein The establishing a mapping relationship between the model variables and the hardware resource description information by using a model-driven method based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device includes: Extracting the detailed information of the model variables from the description file of the constructed algorithm IP core, and obtaining the resource description information of the target programmable array logic device hardware platform; Establishing an automatic mapping between the model variables and the hardware resources by using a model-driven method, where the model variables of the input / output port type are mapped to the corresponding hardware physical channels, the model variables of the dynamically adjustable parameter type are mapped to the register space accessible by the CPU, and the clock reset special information is mapped to the corresponding clock reset resource area.

5. The model processing method of the IP core for hardware-in-the-loop simulation according to claim 1, wherein The dynamically generating an engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship includes: Generate a corresponding configurable description of the programmable array logic device project according to the mapping relationship between the model variables and the hardware resources; Obtain a corresponding configurable top-level design file through a preset design tool for the programmable array logic device.

6. The model processing method of the IP core for hardware-in-the-loop simulation according to claim 1, wherein Comprehensively place and route the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can run directly on the programmable array logic device, including: Import the top-level design file of the programmable array logic device into a preset design tool to convert it into a corresponding logic netlist; Perform placement and routing process operations through the logic netlist to obtain a corresponding bitstream file.

7. The model processing method of the IP core for hardware-in-the-loop simulation according to claim 1, wherein Download the bitstream file to the target hardware platform to start running, including: Transmit the bitstream file to the hardware platform of the corresponding target programmable array logic device; Start the execution of the bitstream file on the hardware platform of the target programmable array logic device.

8. A model processing device for an IP core used in hardware-in-the-loop simulation, characterized in that The device includes: A simulation model encapsulation module, which is used to encapsulate the algorithm model to be simulated into a reusable algorithm IP core of the programmable array logic device, define the attributes of the model variables in the algorithm description of the algorithm IP core, and divide the model variables into three categories: input / output ports, dynamically adjustable parameters, and clock reset special signals; A mapping relationship construction module, which is used to obtain the hardware resource description information of the programmable array logic device, establish a mapping relationship between the model variables and the hardware resource description information based on the model variables of the algorithm IP core and the hardware resource description information of the programmable array logic device by using the model-driven method, and dynamically generate the engineering configurable top-level design file of the programmable array logic device according to the established mapping relationship; A file execution module, which is used to comprehensively place and route the top-level design file through the preset design tool of the programmable array logic device to generate a corresponding bitstream file that can run directly on the programmable array logic device, and download the bitstream file to the target hardware platform to start running.

9. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the model processing method of the IP core for hardware-in-the-loop simulation according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the model processing method of the IP core for hardware-in-the-loop simulation according to any one of claims 1 to 7.

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