A PCB multi-layer copper laying design system based on region division

Abstract

The application relates to the technical field of PCB design, in particular to a PCB multi-layer copper laying design system based on region division, which comprises a processor and a memory storing a computer program; when the computer program is executed by the processor, the following steps are realized: determining a copper laying level set corresponding to each drawing region, determining copper laying related parameters corresponding to each copper laying level, generating a copper laying result of a target PCB according to N drawing regions, copper laying levels corresponding to the N drawing regions respectively, and copper laying related parameters corresponding to each copper laying level respectively; the drawing region is determined first, and then the copper laying level corresponding to the drawing region is set, so that the drawing region can be directly applied to multiple target levels during copper laying design, repeated design is avoided, and when the copper laying region is adjusted, the drawing region can be directly adjusted, and modification based on layers is not needed, so that the design efficiency of the PCB multi-layer copper laying is improved.

Description

A PCB Multilayer Copper Laying Design System Based on Region Division Technical Field

[0001] This invention relates to the field of PCB design technology, and in particular to a multilayer copper plating design system for PCBs based on region division. Background Technology

[0002] In the scenario of copper pour design for multi-layer PCBs, existing technologies usually require separate copper pour design for each layer. However, PCB design may require the same copper pour design for different layers of the multi-layer PCB based on power routing and other requirements.

[0003] Because the existing technology uses a method of designing copper pours separately for each layer, when the same copper pour design is used in different layers, redundant and repetitive design is introduced. In addition, it is necessary to ensure that the copper pour design is consistent across different layers. Furthermore, when the copper pour design needs to be modified or adjusted, the existing technology also needs to be processed layer by layer, which results in low adjustment efficiency.

[0004] Therefore, how to improve the design efficiency of multi-layer copper plating on PCBs has become an urgent problem to be solved. Summary of the Invention

[0005] To address the aforementioned technical problems, the technical solution adopted by this invention is as follows:

[0006] A multi-layer copper pour design system for PCB boards based on region partitioning, the system comprising: N drawing regions {a1, a2, ..., a...} applied to the target PCB board. n , ..., a N}, processor and memory storing computer programs, wherein, a n The nth drawing region applied to the target PCB board, where n is an integer in the range [1, N], is an integer applied to the target PCB board. The target PCB board contains K target layers, and each target layer contains the layout information of the target PCB board in that target layer. When the computer program is executed by the processor, the following steps are implemented:

[0007] S101, iterate through n and determine a. n The corresponding copper pour layer set B n Among them, B n ={b 1 n b 2 n , ..., b m(n) n , ..., b M (n) n}, b m(n)n For a n The corresponding m(n)th copper pour level, where m(n) is an integer in the range [1, M(n)], and M(n) is the B... n The number of copper pour layers included, B n The maximum value of all copper pour layers is less than or equal to K.

[0008] S102, determine b m(n) n The corresponding copper pour-related parameters, wherein the copper pour-related parameters are based on the target level corresponding to the m(n)th copper pour layer, a n The layout information of the target PCB board within the range and a n Sure.

[0009] S103, based on N drawing areas and their corresponding copper pouring levels, and the copper pouring related parameters corresponding to each copper pouring level, generate the copper pouring result of the target PCB board.

[0010] Compared with the prior art, the present invention has significant advantages. Through the above technical solution, the PCB multilayer copper pour design system based on region division provided by the present invention achieves considerable technological progress and practicality, and has broad industrial application value. It has at least the following advantages:

[0011] This invention provides a multilayer copper pour design system for PCB boards based on region partitioning. The system includes N drawing regions {a1, a2, ..., a...} applied to the target PCB board. n , ..., a N}, processor and memory storing computer programs, wherein, a n For the nth drawing area applied to the target PCB board, where n is an integer in the range [1, N], the target PCB board contains K target layers, and each target layer contains the layout information of the target PCB board in that target layer. When the computer program is executed by the processor, the following steps are implemented: S101, traverse n, determine a n The corresponding copper pour layer set B n Among them, B n ={b 1 n b 2 n , ..., b m(n) n , ..., b M(n) n}, b m(n) n For a nThe corresponding m(n)th copper pour level, where m(n) is an integer in the range [1, M(n)], and M(n) is the B... n The number of copper pour layers included, B n The maximum value of all copper pour layers is less than or equal to K, S102, determine b. m(n) n The corresponding copper pour-related parameters, wherein the copper pour-related parameters are based on the target level corresponding to the m(n)th copper pour layer, a n The layout information of the target PCB board within the range and a n S103: Based on the N drawing areas and their corresponding copper pouring levels, and the copper pouring related parameters corresponding to each copper pouring level, generate the copper pouring result of the target PCB board.

[0012] As can be seen, by first determining the drawing area and then setting the corresponding copper pour layer for the drawing area, the drawing area can be directly applied to multiple target layers during copper pour design, avoiding repetitive design. Moreover, when adjusting the copper pour area, the drawing area can be adjusted directly without modifying it layer by layer, thereby improving the design efficiency of multi-layer copper pours on PCBs. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a flowchart illustrating the execution of a computer program by a processor in a PCB multilayer copper plating design system based on region partitioning, according to an embodiment of the present invention. Detailed Implementation

[0015] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0016] This embodiment provides a multi-layer copper pour design system for PCB boards based on region partitioning. The system includes N drawing regions {a1, a2, ..., a...} applied to the target PCB board. n , ..., a N}, processor and memory storing computer programs, wherein, a nThis refers to the nth drawing area applied to the target PCB board, where n is an integer in the range [1, N]. The target PCB board contains K target layers, and each target layer contains the layout information of the target PCB board in that target layer. Referring to Figure 1, it is a flowchart illustrating the execution of a computer program by a processor in a PCB board multilayer copper pour design system based on region partitioning according to an embodiment of the present invention. When the computer program is executed by the processor, the following steps are implemented:

[0017] S101, iterate through n and determine a. n The corresponding copper pour layer set B n Among them, B n ={b 1 n b 2 n , ..., b m(n) n , ..., b M (n) n}, b m(n) n For a n The corresponding m(n)th copper pour level, where m(n) is an integer in the range [1, M(n)], and M(n) is the B... n The number of copper pour layers included, B n The maximum value of all copper pour layers is less than or equal to K;

[0018] S102, determine b m(n) n The corresponding copper pour-related parameters, wherein the copper pour-related parameters are based on the target level corresponding to the m(n)th copper pour layer, a n The layout information of the target PCB board within the range and a n Sure;

[0019] S103, based on N drawing areas and their corresponding copper pouring levels, and the copper pouring related parameters corresponding to each copper pouring level, generate the copper pouring result of the target PCB board.

[0020] The drawing area can refer to the area designed as a copper pour, and the copper pour level can refer to the target level to be referenced by the corresponding drawing area. Since a drawing area can be applied to multiple target levels, a drawing area corresponds to a set of copper pour levels. The set of copper pour levels can include at least one copper pour level, and each copper pour level has a corresponding target level.

[0021] Copper pouring parameters can be used to instruct the generation of copper pouring results so that the copper pouring results conform to the copper pouring rules determined by the copper pouring parameters.

[0022] Specifically, this embodiment can use multiple drawing areas for copper pour design. Correspondingly, a target layer can include multiple drawing areas. Compared with the existing copper pour design method, which requires drawing each area on the target layer one by one, this greatly improves the efficiency of PCB multilayer copper pour.

[0023] In one specific implementation, the target PCB board includes digital and / or analog areas, and the layout information includes at least the devices on the target PCB board in the corresponding target layer;

[0024] When the target PCB board includes a digital area or an analog area, the drawing area satisfies a first constraint condition, which includes a coverage constraint condition that all devices are within the drawing area.

[0025] The target PCB board includes either a digital area or an analog area. It may mean that the target PCB board only includes one of the digital or analog areas. In this case, the drawing area should be determined based on the distribution information of the components. It should be noted that, under normal circumstances, the drawing area is drawn by engineers. In addition to meeting the first restriction condition mentioned above, it also needs to meet electrical standards and other constraints.

[0026] In one specific implementation, when the target PCB board includes a digital area and an analog area, the drawing area satisfies a second constraint condition. The second constraint condition includes the coverage constraint condition and the spacing constraint condition between the drawing area corresponding to the digital area and the drawing area corresponding to the analog area.

[0027] When the target PCB board includes both digital and analog areas, additional spacing constraints need to be added between the drawing areas corresponding to the digital areas and the drawing areas corresponding to the analog areas to avoid noise interference.

[0028] Specifically, when calculating the distance between the drawing area corresponding to the digital area and the drawing area corresponding to the analog area, the distance between each contour point of the drawing area corresponding to the digital area and each contour point of the drawing area corresponding to the analog area can be calculated, and the minimum distance can be used as the distance between the drawing area corresponding to the digital area and the drawing area corresponding to the analog area.

[0029] In one specific implementation, the determination of a n The corresponding copper pour layer set B n ,include:

[0030] For any target level, if a n Corresponding to the wiring, vias, and devices included in the target layer, the target layer is determined to be a. nThe corresponding first reference level;

[0031] Traverse all target levels to obtain a n The corresponding first reference levels;

[0032] By a n All corresponding first reference levels form a n The corresponding copper pour layer set B n .

[0033] Among them, a n Corresponding to the wiring, vias, and devices contained in the target layer, it can refer to a n It can be applied to target levels. Typically, when designing the drawing area, engineers can determine which target levels the drawing area will be applied to.

[0034] In one specific implementation, the determination of a n The corresponding copper pour layer set B n It also includes:

[0035] For any target level, the relevant levels of the target level are determined based on the wiring and devices that meet the preset requirements contained in the target level.

[0036] If a n Corresponding to the wiring and devices that meet the preset requirements contained in the target level, the relevant level is determined to be a. n The corresponding second reference level;

[0037] Traverse all target levels to obtain a n The corresponding second reference levels;

[0038] Accordingly, the statement by a n All corresponding first reference levels form a n The corresponding copper pour layer set B n ,include:

[0039] By a n The corresponding first reference level and all second reference levels form a n The corresponding copper pour layer set B n .

[0040] Among them, the preset requirements can refer to shielding requirements. For example, when a target layer contains a crystal oscillator device, it is usually necessary to carry out copper pour design for each target layer in order to dissipate heat or shield the signal. Then all other target layers are regarded as related layers of this target layer.

[0041] For example, when there is a shielding requirement for the wiring in a target layer, copper pouring is required in the target layer above and below the target layer to achieve the shielding effect. Therefore, the target layer above and below the target layer are regarded as the relevant layers of the target layer.

[0042] In one specific implementation, the layout information includes at least the wiring, vias, and through-holes of the target PCB board in the corresponding target layer;

[0043] The copper pouring related parameters are based on the target level corresponding to the m(n)th copper pouring layer, where a n The layout information of the target PCB board within the range and a n Determined, including:

[0044] According to the target level a n The wiring of the target PCB board within the range, determining the wiring and a n The first reference spacing value;

[0045] According to the target level a n The vias of the target PCB board within the specified range are determined to be related to a. n The second reference spacing value, and the via and a n The first connection method;

[0046] According to the target level a n The through holes of the target PCB board within the specified range are determined to be related to a. n The third reference spacing value, and the through hole and a n The second connection method;

[0047] The first reference spacing value, the second reference spacing value, the third reference spacing value, the first connection method, and the second connection method are used as the copper pouring related parameters.

[0048] The first reference spacing value can be used to constrain the spacing between the wiring and the drawing area, the second reference spacing value can be used to constrain the spacing between the via and the drawing area, and the third reference spacing value can be used to constrain the spacing between the through hole and the drawing area. The above copper pouring related parameters can be set by the implementer or automatically set using default values.

[0049] Specifically, in this embodiment, copper pouring related parameters can be set based on the target layer. In this case, all copper pouring areas of the same target layer will apply the same copper pouring related parameters. Alternatively, copper pouring related parameters can be set based on the copper pouring area. In this case, different copper pouring areas of the same target layer can apply different copper pouring related parameters.

[0050] In one specific implementation, both the first connection method and the second connection method belong to a set of connection methods, and the set of connection methods includes at least a cross connection method and a full connection method.

[0051] The set of connection methods can also include plum blossom connection methods, teardrop connection methods, etc.

[0052] In one specific implementation, when the computer program is executed by the processor, after step S103, the following steps are further performed:

[0053] S104, Simulate the copper pouring results of the target PCB board to obtain the simulation optimization parameters corresponding to each copper pouring layer;

[0054] S105, for any copper pouring layer, update the copper pouring related parameters corresponding to the copper pouring layer using the simulation optimization parameters corresponding to the copper pouring layer;

[0055] S106, return to steps S103 to S104 until the simulation optimization parameters corresponding to each copper pour layer meet the preset conditions.

[0056] Among them, the simulation optimization parameters correspond to the copper pouring related parameters. The simulation optimization parameters can be regarded as the optimized values ​​of the copper pouring related parameters obtained after simulation processing. At this time, the simulation optimization parameters corresponding to the copper pouring layer are used to update the copper pouring related parameters corresponding to the copper pouring layer, and simulation iteration can be performed directly, which effectively improves the simulation efficiency of PCB multilayer copper pouring design.

[0057] Specifically, the preset condition may refer to the simulation optimization parameters being the same as the copper pouring related parameters. In one embodiment, the preset condition may refer to the difference between the simulation optimization parameters and the copper pouring related parameters being less than or equal to the error constraint.

[0058] In this embodiment, the drawing area is determined first, and then the copper pouring layer corresponding to the drawing area is set. This allows the drawing area to be directly applied to multiple target layers during copper pouring design, avoiding repetitive design. Moreover, when adjusting the copper pouring area, the drawing area can be adjusted directly without modifying the layer as an object, thereby improving the design efficiency of multi-layer copper pouring on PCB boards.

[0059] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A PCB multilayer copper plating design system based on region partitioning, characterized in that, The system includes: N drawing regions {a1, a2, ..., a...} applied to the target PCB board. n , ..., a N }, processor and memory storing computer programs, wherein, a n For the nth drawing area applied to the target PCB board, where n is an integer in the range [1, N], the target PCB board contains K target layers, and each target layer contains the layout information of the target PCB board in that target layer. When the computer program is executed by the processor, the following steps are implemented: S101, traverse n, determine a n The corresponding copper pour layer set B n Among them, B n ={b 1 n b 2 n , ..., b m(n) n , ..., b M(n) n }, b m (n) n For a n The corresponding m(n)th copper pour level, where m(n) is an integer in the range [1, M(n)], and M(n) is the B n The number of copper pour layers included, B n The maximum value of all copper pour layers is less than or equal to K; S102, determine b m(n) n The corresponding copper pour-related parameters, wherein the copper pour-related parameters are based on the target level corresponding to the m(n)th copper pour layer, in terms of a n The layout information of the target PCB board within the range and a n S103: Based on the N drawing areas and their corresponding copper pouring levels, and the copper pouring related parameters corresponding to each copper pouring level, generate the copper pouring result of the target PCB board.

2. The PCB multilayer copper plating design system based on region partitioning according to claim 1, characterized in that, The target PCB board includes a digital area and / or an analog area, and the layout information includes at least the devices on the target PCB board in the corresponding target layer; when the target PCB board includes a digital area or an analog area, the drawing area satisfies a first constraint condition, which includes a coverage constraint condition that all devices are within the drawing area.

3. The PCB multilayer copper plating design system based on region partitioning according to claim 2, characterized in that, When the target PCB board includes digital and analog areas, the drawing area satisfies the second constraint condition. The second constraint condition includes the coverage constraint condition and the spacing constraint condition between the drawing area corresponding to the digital area and the drawing area corresponding to the analog area.

4. The PCB multilayer copper plating design system based on region partitioning according to claim 1, characterized in that, The layout information includes at least the wiring, vias, and through-holes of the target PCB board in the corresponding target layer; the copper pouring related parameters are based on a in the target layer corresponding to the m(n)th copper pouring layer. n The layout information of the target PCB board within the range and a n Determining includes: based on a in the target level n The wiring of the target PCB board within the range, determining the wiring and a n The first reference spacing value; based on a in the target level n The vias of the target PCB board within the specified range are determined to be related to a. n The second reference spacing value, and the via and a n The first connection method; based on a in the target level n The through holes of the target PCB board within the specified range are determined to be related to a. n The third reference spacing value, and the through hole and a n The second connection method; using the first reference spacing value, the second reference spacing value, the third reference spacing value, the first connection method, and the second connection method as the copper pouring related parameters.

5. The PCB multilayer copper plating design system based on region partitioning according to claim 4, characterized in that, Both the first connection method and the second connection method belong to a set of connection methods, which includes at least a cross connection method and a full connection method.

6. The PCB multilayer copper plating design system based on region partitioning according to claim 1, characterized in that, When the computer program is executed by the processor, after step S103, the following steps are also implemented: S104, the copper pouring result of the target PCB board is simulated to obtain the simulation optimization parameters corresponding to each copper pouring layer; S105, for any copper pouring layer, the copper pouring related parameters corresponding to the copper pouring layer are updated using the simulation optimization parameters corresponding to the copper pouring layer; S106, the execution of steps S103 to S104 is returned until the simulation optimization parameters corresponding to each copper pouring layer meet the preset conditions.

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