High-voltage ldo overshoot protection circuit

Abstract

The application relates to the technical field of integrated circuits, in particular to a high-voltage LDO overshoot protection circuit. The high-voltage LDO overshoot protection circuit comprises a resistor R1 for limiting branch current, a resistor R2 and a capacitor C1 for filtering output V voltage ripple, a capacitor C2 for stabilizing the voltage of an IPD node, a diode D1 for protecting the MN4 gate from breakdown, a MOS tube MN1 and a MOS tube MP1 for constituting an overshoot detection circuit, when an overshoot voltage is detected, the MOS tube is turned on, a MOS tube MN2 and a MOS tube MN3 for constituting an N-type current mirror to start working and copy the left-side current to the right-side circuit, a high-voltage MOS tube MN4 for being a high-voltage resistant device and playing a voltage resistance role, a MOS tube MP2, a MOS tube MP3 and a MOS tube MP4 for constituting a P-type current mirror to copy the right-side circuit current after the right-side circuit is turned on, pull up the voltage of PGATE1 and PGATE2 nodes and close the power tube of the LDO, so that the effect of overshoot protection is achieved, and the safety and robustness of the circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and more specifically to a high-voltage LDO overshoot protection circuit. Background Technology

[0002] Power management modules are a crucial component of electronic power systems. Any electronic product, even large power electronic devices, cannot function properly without a stable power supply. For example, the voltages provided by generators, transformers, and batteries are inherently unstable and fluctuate under different environmental and operating conditions. The role of a voltage regulator is to transform rippled and noisy voltages into precise, stable, and load-independent voltages. Due to their advantages such as low noise and fast response to load changes, LDO (Linear Voltage Regulator) devices are playing an increasingly important role in analog and mixed-signal chips.

[0003] like Figure 1 As shown, a traditional LDO circuit structure consists of several parts, including a bandgap reference (BGR), an error amplifier (EA), a power transistor (MP), a feedback network, a load capacitor (CL), and a load resistor (RL). Its basic working principle is that the difference between the output voltage sampled by the feedback network and the reference voltage of the bandgap reference module (BGR) is amplified by the error amplifier (EA) to output a value that controls the gate voltage of the power transistor (MP). By controlling the voltage difference between the gate and source of the power transistor (MP), the output voltage is controlled, thus achieving a stable output voltage. However, in LDOs with small external compensation capacitors or no external compensation capacitors, during the change from heavy load to light load, the current of the power transistor jumps from a large current to a small current, leading to an excessively high output voltage and severe overshoot. This excessively high output voltage may cause irreversible damage or destruction to the connected load, resulting in a decrease in the stability and lifespan of the entire circuit, and even various safety risks. Therefore, this invention proposes a high-voltage LDO overshoot protection circuit, solving the problem of output voltage overshoot in existing LDOs during load or power supply transitions, and improving the safety and robustness of the LDO circuit. Summary of the Invention

[0004] In order to overcome the impact of LDO output voltage overshoot on the circuit in the prior art, this invention patent proposes a high-voltage LDO overshoot protection circuit.

[0005] A high-voltage LDO overshoot protection circuit includes: a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a diode D1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, and ports VLDO, V, IPD, G, PGATE1, PGATE2, and HV.

[0006] Port VLDO is connected to the left end of the first resistor R1, and the right end of the first resistor R1 is connected to the source of the first PMOS transistor MP1, the negative terminal of the diode D1, and the gate of the fourth NMOS transistor MN4. Port V is connected to the left end of the second resistor R2, and the right end of the second resistor R2 is connected to the gate of the first PMOS transistor MP1 and the upper end of the first capacitor C1. The gate of the first NMOS transistor MN1 is directly connected to port V, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1.

[0007] Port IPD is connected to the source of the first NMOS transistor MN1, the upper end of the second capacitor C2, the positive terminal of the diode D1, the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2, and the gate of the third NMOS transistor MN3; Port G is connected to the lower end of the first capacitor C1, the lower end of the second capacitor C2, the source of the second NMOS transistor MN2, and the source of the third NMOS transistor MN3.

[0008] The drain of the third MOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4. The drain of the fourth NMOS transistor MN4 is connected to the drain of the second PMOS transistor MP2, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, and the gate of the fourth PMOS transistor MP4. Port PGATE1 is connected to the drain of the third PMOS transistor MP3, and port PGATE2 is connected to the drain of the fourth PMOS transistor MP4. Port HV is connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, and the source of the fourth PMOS transistor MP4.

[0009] Furthermore, port VLDO is an input signal port used to receive the voltage signal output by the LDO; port V is a power signal port used to provide a 5V low voltage; port IPD is an input signal port used to provide pull-down current; port G is a power signal port used to provide a 0V ground potential; port HV is a power signal port used to provide a 25V high voltage; and ports PGATE1 and PGATE2 are output signal ports used for output.

[0010] Furthermore, the fourth NMOS transistor MN4 is a 40V high-voltage LDMOS device; the diode D1 is a Zener diode device.

[0011] The beneficial effect of this invention is that when the LDO has an overshoot, the protection circuit will sample and detect the voltage value. When the voltage exceeds the threshold set by the protection circuit, the protection circuit will output a shutdown signal to turn off the power transistor of the LDO circuit, preventing the voltage from continuing to overshoot and thus playing the role of the protection circuit.

[0012] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0013] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0014] Figure 1 This is a schematic diagram of a typical traditional LDO structure;

[0015] Figure 2 This invention relates to an LDO overshoot protection circuit.

[0016] Figure 3 This invention relates to an LDO circuit with an overshoot protection module.

[0017] Figure 4 for Figure 3 Simulation results of the circuit shown. Detailed Implementation

[0018] See attached document Figure 2 As shown, a high-voltage LDO overshoot protection circuit includes a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2, a diode D1, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4.

[0019] VLDO is the LDO output voltage signal, which is directly connected to the source of the first PMOS transistor MP1, the negative terminal of diode D1, and the gate of the fourth NMOS transistor MN4 through the first resistor R1. V is a low voltage signal, which is connected to the gate of the first PMOS transistor MP1 and the upper end of the first capacitor C1 through the second resistor R2. The gate of the first NMOS transistor MN1 is directly connected to the low voltage signal V, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1.

[0020] IPD is the pull-down current signal, which is directly connected to the source of the first NMOS transistor MN1, the upper end of the second capacitor C2, the positive terminal of the diode D1, the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2, and the gate of the third NMOS transistor MN3. G is the ground potential signal, which is directly connected to the lower end of the first capacitor C1, the lower end of the second capacitor C2, the source of the second NMOS transistor MN2, and the source of the third NMOS transistor MN3.

[0021] The drain of the third MOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4. The drain of the fourth NMOS transistor MN4 is connected to the drain and gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, and the gate of the fourth PMOS transistor MP4. PGATE1 is the first output signal, connected to the drain of the third PMOS transistor MP3. PGATE2 is the second signal, connected to the drain of the fourth PMOS transistor MP4. HV is the high voltage signal, connected to the sources of the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4.

[0022] The first PMOS transistor MP1 acts as a switch to determine if the VLDO voltage is overshooting; the first NMOS transistor MN1 acts as a protection device to limit the drain voltage of the second NMOS transistor MN2; the first resistor R1 is a current-limiting resistor to limit the current in the left branch; the second resistor and the first capacitor C1 form an RC filter to filter noise on the low-voltage signal V; the second capacitor C2 is a Zener capacitor to stabilize the drain voltage of the second NMOS transistor D; the diode D1 is a Zener diode to protect the gate of the fourth NMOS transistor MN4; the first NMOS transistor MN4 is a voltage withstand device to withstand high voltage; the second NMOS transistor MN2 and the third NMOS transistor MN3 form an N-type current mirror, and the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 form a P-type current mirror to replicate the current.

[0023] Under normal conditions, the gate-source voltage VGS of the first PMOS transistor MP1 is less than VTH, so the first PMOS transistor MP1 is in the off state and no current flows through the left branch. The gate voltage of the second NMOS transistor MN2 is pulled low by the IPD signal, so the second NMOS transistor MN2 is not conducting. The N-type current mirror formed by the second NMOS transistor MN2 and the third NMOS transistor MN3 is not working. No current flows through the right branch of the third NMOS transistor MN3, so the entire circuit is in the off state.

[0024] When the VLDO voltage signal overshoots and rises, it causes the VGS voltage of the first PMOS transistor MP1 to increase. When it increases to a certain level, the first PMOS transistor MP1 turns on, and the first NMOS transistor MN1 turns on. At this time, current flows through the left circuit. When the current is greater than the IPD current signal, the gate voltage of the second NMOS transistor MN2 is pulled high, and the second NMOS transistor MN2 turns on. The second NMOS transistor MN2 and the third NMOS transistor MN3 form an N-type current mirror and start working. The third NMOS transistor MN3 replicates the current of the second NMOS transistor MN2. The fourth NMOS transistor MN4 turns on, and the gate of the second PMOS transistor MP2 is pulled low, and the second PMOS transistor MP2 turns on. The second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 form a P-type current mirror and start working. The third PMOS transistor MP3 and the fourth PMOS transistor MP4 replicate the current of the second PMOS transistor MP2. The output terminals PGATE1 and PGATE2 output pull-up turn-off signals.

[0025] In special circumstances, the VLDO may have a very high overshoot voltage for a very short time. The first PMOS transistor MP1 and the first NMOS transistor MN1 may not have enough time to turn on, and the diode D1 will turn on to form a current path to ensure the normal operation of the circuit and prevent the gate of the fourth NMOS transistor M4 from being broken down due to the overshoot of the VLDO voltage.

[0026] To further illustrate the features and advantages of the patent, please refer to the appendix. Figure 3 As shown, an LDO circuit with an overshoot protection module is used to prevent the LDO output voltage from overshooting. The LDO circuit consists of several modules, including an error amplifier EA, a buffer, a power transistor M1, voltage divider feedback resistors R1 and R2, and an overshoot protection circuit LDO_clamp.

[0027] Among them, the first input terminal of the error amplifier EA is used to receive the VREF voltage signal, and the second input terminal of the error amplifier EA is used to receive the voltage feedback signal transmitted by the voltage divider feedback resistor; the first input terminal of the error amplifier EA is the positive input terminal, the second input terminal of the error amplifier EA is the negative input terminal, and the output of the error amplifier EA is AOUT; the power transistor M1 is a P-channel MOSFET, the first terminal of the power transistor M1 is the source, the second terminal of the power transistor M1 is the drain, and the control terminal GATE of the power transistor M1 is the gate; the overshoot protection circuit LDO_clamp has the first terminal HV, the second terminal V, the third terminal IPD, the fourth terminal PGATE1, and the fifth terminal PGATE2.

[0028] The VREF signal is a 1.2V reference voltage signal provided by the bandgap reference circuit. It is connected to the first input terminal of the error amplifier EA. The second input terminal of the error amplifier EA is connected to the feedback signal of the voltage divider feedback resistor. The output terminal AOUT of the error amplifier EA is connected to the input terminal of the buffer. The output terminal of the buffer is connected to the control terminal GATE of the power transistor M1. The first terminal of the power transistor M1 is connected to the 25V power supply voltage signal PVIN (VDD). The second terminal of the power transistor M1 is connected to the output VPPH. The overshoot protection circuit LDO_clamp has the first terminal connected to the 25V high voltage signal, the second terminal connected to the 5V low voltage signal, the third terminal connected to the 1uA pull-down current signal, the fourth terminal connected to the control terminal GATE of the power transistor M1, and the fifth terminal connected to the output terminal AOUT of the error amplifier EA.

[0029] When the LDO circuit is working normally, the VPPH output voltage is constant at 5.7V. If the external compensation capacitor is small or there is no external compensation capacitor, the power supply voltage PVIN will jump, which will cause the VPPH voltage to overshoot. When the VPPH exceeds the overshoot voltage threshold, the protection circuit starts to work. The output ports PGATE1 and PGATE2 output strong pull-up signals to pull the AOUT and GATE terminals up to PVIN. The power transistor M1 is turned off, so that the VPPH voltage drops and prevents it from overshooting.

[0030] The simulation results based on specific examples of the present invention are as follows, refer to... Figure 4 As shown, Figure 4 This is a simulation result of LDO output voltage overshoot triggering overshoot protection. When the power supply voltage PVIN jumps from 25V to 40V, it causes VPPH overshoot, reaching the overshoot protection threshold. To prevent overshoot, the protection circuit pulls up the voltage at the output terminal AOUT of the error amplifier EA and the control terminal GATE of the power transistor to the power supply voltage PVIN, thereby shutting down the power transistor M1 and causing the VPPH voltage to drop, achieving the protection purpose. Curve VPPH1 is the simulation result obtained without adding the overshoot protection circuit. The waveform clearly shows a large overshoot during the power supply voltage jump. Curve VPPH2 is the simulation result obtained with the overshoot protection circuit added. The waveform shows that the VPPH overshoot phenomenon has been suppressed, greatly improving the safety and robustness of the circuit.

[0031] The above description is merely a preferred embodiment of the present invention and does not limit the implementation and protection scope of the present invention. Those skilled in the art should realize that any equivalent substitutions and obvious changes made based on the description and illustrations of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-voltage LDO overshoot protection circuit, characterized in that, include: First resistor R1, second resistor R2, first capacitor C1, second capacitor C2, diode D1, first NMOS transistor MN1, second NMOS transistor MN2, third NMOS transistor MN3, fourth NMOS transistor MN4, first PMOS transistor MP1, second PMOS transistor MP2, third PMOS transistor MP3, fourth PMOS transistor MP4, port VLDO, port V, port IPD, port G, port PGATE1, port PGATE2, port HV; The port VLDO is connected to the first resistor R1, and the first resistor R1 is connected to the source of the first PMOS transistor MP1, the negative terminal of the diode D1, and the gate of the fourth NMOS transistor MN4. The port V is connected to the second resistor R2, the second resistor R2 is connected to the gate of the first PMOS transistor MP1 and the first capacitor C1, the gate of the first NMOS transistor MN1 is connected to the port V, and the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1. The port IPD is connected to the source of the first NMOS transistor MN1, the second capacitor C2, the positive terminal of the diode D1, the drain of the second NMOS transistor MN2, the gate of the second NMOS transistor MN2, and the gate of the third NMOS transistor MN3. The port G is connected to the first capacitor C1, the second capacitor C2, the source of the second NMOS transistor MN2, and the source of the third NMOS transistor MN3. The drain of the third NMOS transistor MN3 is connected to the source of the fourth NMOS transistor MN4, and the drain of the fourth NMOS transistor MN4 is connected to the drain of the second PMOS transistor MP2, the gate of the second PMOS transistor MP2, the gate of the third PMOS transistor MP3, and the gate of the fourth PMOS transistor MP4. The port PGATE1 is connected to the drain of the third PMOS transistor MP3, and the port PGATE2 is connected to the drain of the fourth PMOS transistor MP4. The port HV is connected to the source of the second PMOS transistor MP2, the source of the third PMOS transistor MP3, and the source of the fourth PMOS transistor MP4. The VLDO port is an input signal port used to receive the voltage signal output by the LDO. Port V is a power signal port used to provide a 5V low voltage; The IPD port is an input signal port used to provide pull-down current; Port G is a power signal port used to provide 0V ground potential; The HV port is a power signal port used to provide a 25V high voltage; Ports PGATE1 and PGATE2 are output signal ports used for output.

2. The high-voltage LDO overshoot protection circuit according to claim 1, characterized in that, The fourth NMOS transistor MN4 is a 40V high-voltage LDMOS device.

3. The high-voltage LDO overshoot protection circuit according to claim 1, characterized in that, The diode D1 is a Zener diode device.

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