A control circuit and memory

Abstract

An embodiment of the present disclosure provides a control circuit and a memory, which includes: a signal sampling circuit, used to sample and process a write command signal according to a first clock signal to obtain a first output signal; a delay shift circuit, used to sample and shift the first output signal according to a first control signal and a first clock signal to obtain a second output signal; a shift selection circuit, used to generate a first intermediate signal according to the first clock signal and the second output signal, generate a second intermediate signal according to the second clock signal and the second output signal, and select the first intermediate signal, the second intermediate signal and the inverted first output signal according to the second control signal to obtain a third output signal; and a command adjustment circuit, used to perform pulse width adjustment processing according to the first output signal and the third output signal to generate a target command signal, so as to meet the resistance switching timing requirements of the terminal resistor and improve the memory performance.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a control circuit and a memory. Background Art

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speeds when manufacturing and using computers and other devices. To achieve faster data transmission speeds, a series of devices such as memories that can transmit data at double the data rate (DDR) have emerged.

[0003] In dynamic random access memory (DRAM) chips, the on-die termination (ODT) function requires that the switching of the terminal resistor's resistance follow certain timing requirements. The pulse width of the output signal in the ODT circuit must meet a certain offset compared to the pulse width of the input signal, otherwise the memory's ODT function will be affected. Summary of the Invention

[0004] Embodiments of the present disclosure provide a control circuit and a memory.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] In a first aspect, an embodiment of the present disclosure provides a control circuit, the control circuit including a signal sampling circuit, a delay shift circuit, a shift selection circuit, and a command adjustment circuit, wherein:

[0007] a signal sampling circuit, configured to receive a write command signal and a first clock signal, and sample the write command signal according to the first clock signal to obtain a first output signal;

[0008] a delay shift circuit, configured to receive a first output signal, a first clock signal, and a first control signal, and perform sampling and shift processing on the first output signal according to the first control signal and the first clock signal to obtain a second output signal; wherein a shift length between the second output signal and the first output signal is correlated with the first control signal;

[0009] a shift selection circuit configured to receive the first output signal, the second output signal, the first clock signal, the second clock signal, and the second control signal; sample the second output signal according to the first clock signal to obtain a first intermediate signal; sample the second output signal according to the second clock signal to obtain a second intermediate signal; and select the first intermediate signal, the second intermediate signal, and the inverted first output signal according to the second control signal to obtain a third output signal;

[0010] a command adjustment circuit, configured to receive the first output signal and the third output signal, perform pulse width adjustment processing according to the first output signal and the third output signal, and generate a target command signal;

[0011] Among them, the clock periods of the first clock signal and the second clock signal are both twice the preset clock period, and the phase difference between the first clock signal and the second clock signal is 180 degrees; the pulse width of the target command signal is widened by A times the preset clock period compared to the pulse width of the write command signal, and the first control signal and the second control signal are generated based on A, where A is an integer greater than or equal to 0.

[0012] In some embodiments, the control circuit further includes a clock frequency dividing circuit, wherein:

[0013] a clock frequency dividing circuit, configured to receive an initial clock signal, perform frequency division processing on the initial clock signal, and generate a first clock signal and a second clock signal;

[0014] The clock period of the initial clock signal is a preset clock period.

[0015] In some embodiments, the pulse width of the write command signal is equal to B times the preset clock period; wherein B is equal to 0.5 times the burst length BL of the data.

[0016] In some embodiments, B is equal to any one of the following values: 4, 8, 16.

[0017] In some embodiments, A is equal to any one of the following values: 0, 1, 2, 3, 4, 5, 6, 7, 8.

[0018] In some embodiments, the signal sampling circuit includes a first trigger, wherein:

[0019] The clock end of the first trigger is used to receive a first clock signal, the input end of the first trigger is used to receive a write command signal, and the first output end of the first trigger is used to output a first output signal; wherein, the first output end of the first trigger is used to reflect the value of the input end of the first trigger after being sampled by the first clock signal.

[0020] In some embodiments, the delay shift circuit includes M delay units, where M is an integer greater than 0, wherein:

[0021] The delay shift circuit is used to receive a first control signal, determine a target number of delay units among M delay units according to the first control signal, and sample and shift the first output signal through the target number of delay units to obtain a second output signal.

[0022] In some embodiments, the first control signal includes M sub-control signals, a j-th delay unit corresponds to the j-th sub-control signal, and the j-th delay unit includes a j-th delay sub-unit and a j-th selection unit, wherein:

[0023] When M is equal to 1, the clock terminal of the first delay subunit is used to receive the first clock signal, the input terminal of the first delay subunit is used to receive the first output signal, the first input terminal of the first selection unit is used to receive the first output signal, the first output terminal of the first delay subunit is connected to the second input terminal of the first selection unit, the control terminal of the first selection unit is used to receive the first sub-control signal, and the output terminal of the first selection unit is used to output the second output signal;

[0024] When M is greater than 1 and j is greater than 1, the clock terminal of the jth delay subunit is used to receive the first clock signal, the input terminal of the jth delay subunit is used to receive the j-1th selection result signal, the first output terminal of the jth delay subunit is connected to the second input terminal of the jth selection unit, and is used to output the jth delay result signal; the first input terminal of the jth selection unit is used to receive the first output signal, the control terminal of the jth selection unit is used to receive the jth sub-control signal, and the output terminal of the jth selection unit is used to output the jth selection result signal;

[0025] Wherein, j is an integer greater than 1 and less than or equal to M; and when j is equal to 1, the input end of the first delay subunit is used to receive the first output signal, and the output end of the first selection unit is used to output the first selection result signal; when j is equal to M, the output end of the Mth selection unit is used to output the second output signal.

[0026] In some embodiments, the jth delay subunit is configured to receive the j-1th selection result signal and the first clock signal, and perform sampling processing on the j-1th selection result signal according to the first clock signal to obtain the jth delayed result signal;

[0027] The jth selection unit is configured to receive the jth sub-control signal, and select one between the jth delayed result signal and the first output signal according to the jth sub-control signal to output as the jth selection result signal.

[0028] In some embodiments, the jth delay subunit includes a second flip-flop, wherein:

[0029] The clock end of the second trigger is used to receive the first clock signal, the input end of the second trigger is used to receive the j-1th selection result signal, and the first output end of the second trigger is used to output the jth delayed result signal; wherein, the first output end of the second trigger is used to reflect the value of the input end of the second trigger after being sampled by the first clock signal.

[0030] In some embodiments, the shift selection circuit includes a shift subcircuit, an inversion subcircuit, and a selection subcircuit, wherein:

[0031] a shift subcircuit, configured to receive the second output signal, the first clock signal, and the second clock signal, sample the second output signal according to the first clock signal to obtain a first intermediate signal, and sample the second output signal according to the second clock signal to obtain a second intermediate signal;

[0032] an inverting sub-circuit, configured to receive the first output signal, perform inversion processing on the first output signal, and obtain a third intermediate signal;

[0033] The selection subcircuit is configured to receive the first intermediate signal, the second intermediate signal, the third intermediate signal, and the second control signal, select the first intermediate signal, the second intermediate signal, and the third intermediate signal according to the second control signal, and output a third output signal.

[0034] In some embodiments, the shift subcircuit includes a third flip-flop and a fourth flip-flop, wherein:

[0035] The input terminals of the third flip-flop and the fourth flip-flop are both used to receive the second output signal, the clock terminal of the third flip-flop is used to receive the first clock signal, and the first output terminal of the third flip-flop is used to output the first intermediate signal; the clock terminal of the fourth flip-flop is used to receive the second clock signal, and the first output terminal of the fourth flip-flop is used to output the second intermediate signal;

[0036] Among them, the first output end of the third trigger is used to reflect the value of the input end of the third trigger after being sampled by the first clock signal; the first output end of the fourth trigger is used to reflect the value of the input end of the fourth trigger after being sampled by the second clock signal.

[0037] In some embodiments, the second control signal includes a first sub-control signal and a second sub-control signal, and the selection sub-circuit includes a first selection sub-circuit and a second selection sub-circuit, wherein:

[0038] a first selection sub-circuit, configured to receive the first intermediate signal and the second intermediate signal, and select one of the first intermediate signal and the second intermediate signal according to the first sub-control signal to output as a fourth intermediate signal;

[0039] a second selection sub-circuit, configured to receive the third intermediate signal and the fourth intermediate signal, and select one of the third intermediate signal and the fourth intermediate signal as a third output signal according to the second sub-control signal;

[0040] Among them, the first input end of the first selection subcircuit is used to receive the first intermediate signal, the second input end of the first selection subcircuit is used to receive the second intermediate signal, the control end of the first selection subcircuit is used to receive the first sub-control signal, and the output end of the first selection subcircuit is connected to the second input end of the second selection subcircuit for outputting the fourth intermediate signal; the first input end of the second selection subcircuit is used to receive the third intermediate signal, the control end of the second selection subcircuit is used to receive the second sub-control signal, and the output end of the second selection subcircuit is used to output the third output signal.

[0041] In some embodiments, the command adjustment circuit includes an SR latch, a first NOT gate, and a first NOR gate, and the SR latch includes a first NAND gate and a second NAND gate, wherein:

[0042] The input end of the first NOT gate is connected to the first input end of the first NAND gate for receiving the third output signal; the output end of the first NOT gate is used to output the first command signal;

[0043] The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminal of the second NAND gate is used to receive the first output signal, and the output terminal of the second NAND gate serves as the output terminal of the SR latch to output the second command signal;

[0044] The first input terminal of the first NOR gate is connected to the output terminal of the second NAND gate for receiving the second command signal; the second input terminal of the first NOR gate is connected to the output terminal of the first NOT gate for receiving the first command signal; the output terminal of the first NOR gate is used to output the target command signal;

[0045] The first command signal is delayed by A times of the preset clock cycle compared to the second command signal.

[0046] In a second aspect, an embodiment of the present disclosure provides a memory, which at least includes the control circuit as described in any one of the first aspects.

[0047] The present disclosure provides a control circuit and a memory, the control circuit comprising a signal sampling circuit, a delay shift circuit, a shift selection circuit, and a command adjustment circuit. The signal sampling circuit is configured to sample a write command signal according to a first clock signal to obtain a first output signal; the delay shift circuit is configured to sample and shift the first output signal according to a first control signal and a first clock signal to obtain a second output signal, wherein the shift length between the second output signal and the first output signal is associated with the first control signal; the shift selection circuit is configured to sample the second output signal according to the first clock signal to obtain a first intermediate signal; the second output signal is configured to sample the second output signal according to a second clock signal to obtain a second intermediate signal; and the first intermediate signal, the second intermediate signal, and the inverted first output signal are selected according to a second control signal to obtain a third output signal; and the command adjustment circuit is configured to perform pulse width adjustment processing based on the first output signal and the third output signal to generate a target command signal. The clock periods of the first clock signal and the second clock signal are both twice the preset clock period, and the phase difference between the first clock signal and the second clock signal is 180 degrees. The pulse width of the target command signal is widened by A times the preset clock period compared to the pulse width of the write command signal, where A is an integer greater than or equal to 0. Thus, because the write command signal includes burst length BL information, the pulse width of the target command signal generated by the command adjustment circuit is widened by A times the preset clock period compared to the pulse width of the write command signal. At the same time, the first control signal and the second control signal can also indicate the size of the compensation amount, and the first control signal and the second control signal are generated based on A. Thus, the pulse width of the write command signal can be adjusted according to different BLs and different compensation amounts, so that the target command signal after pulse width adjustment can meet the resistance switching timing requirements of the terminal resistor. In this way, not only can signal conflicts during transmission be avoided, but also energy loss and reflection of the signal during transmission can be reduced, thereby improving signal integrity and thereby improving memory performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Schematic diagram of the structure of an ODT functional circuit;

[0049] Figure 2 A signal timing diagram of an ODT function;

[0050] Figure 3 A detailed structural diagram of a control circuit Figure 1 ;

[0051] Figure 4 A signal timing diagram of a control circuit Figure 1 ;

[0052] Figure 5 A signal timing diagram of a control circuit Figure 2 ;

[0053] Figure 6 A detailed structural diagram of a control circuit Figure 2 ;

[0054] Figure 7 A signal timing diagram of a control circuit Figure 3 ;

[0055] Figure 8 A signal timing diagram of a control circuit Figure 4 ;

[0056] Figure 9 A schematic diagram of the structure of a control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0057] Figure 10 A schematic diagram of the structure of a control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0058] Figure 11 A schematic diagram of the structure of a signal sampling circuit provided in an embodiment of the present disclosure;

[0059] Figure 12 A schematic diagram of the structure of a delay shift circuit provided in an embodiment of the present disclosure Figure 1 ;

[0060] Figure 13 A schematic diagram of the structure of a delay shift circuit provided in an embodiment of the present disclosure Figure 2 ;

[0061] Figure 14 A schematic diagram of the structure of a shift selection circuit provided in an embodiment of the present disclosure;

[0062] Figure 15 A schematic diagram of the structure of a command adjustment circuit provided in an embodiment of the present disclosure;

[0063] Figure 16 A detailed structural diagram of a control circuit provided in an embodiment of the present disclosure;

[0064] Figure 17 A signal timing diagram of a control circuit provided in an embodiment of the present disclosure Figure 1 ;

[0065] Figure 18 A signal timing diagram of a control circuit provided in an embodiment of the present disclosure Figure 2 ;

[0066] Figure 19 A flow chart of a control method provided in an embodiment of the present disclosure;

[0067] Figure 20 A schematic diagram of the composition structure of a memory provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0068] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It should be understood that the specific embodiments described herein are only used to explain the relevant applications and are not intended to limit the relevant applications. It should also be noted that for ease of description, only the portions relevant to the relevant applications are shown in the drawings.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0070] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0071] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0072] Before further explaining the embodiments of the present disclosure in detail, the nouns and terms involved in the embodiments of the present disclosure are explained first. The nouns and terms involved in the embodiments of the present disclosure are subject to the following interpretations:

[0073] Dynamic Random Access Memory (DRAM);

[0074] Double Data Rate (DDR);

[0075] The third generation of double data rate (Double Data Rate 3, DDR3);

[0076] Fourth-generation double data rate (Double Data Rate 4, DDR4);

[0077] Fifth-generation double data rate (DDR5);

[0078] On Die Termination (ODT);

[0079] Termination resistance / terminal resistance (RTT);

[0080] Mode Register (MR);

[0081] Command (CMD);

[0082] Data (DQ);

[0083] Preset clock cycle (tck);

[0084] Write (WR);

[0085] Column address strobe write delay (CAS Write Latency, CWL);

[0086] Burst Length (BL);

[0087] D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF);

[0088] Set / Reset Latch (SR latch);

[0089] NAND Gate (NAND);

[0090] NOR Gate (NOR);

[0091] Central Processing Unit (CPU);

[0092] Mode Register Setting (MRS).

[0093] With the rapid development of semiconductor technology, signal transmission rates are increasing, leading to increasingly prominent signal integrity issues. To improve data signal integrity during high-speed signal transmission, DDR3, DDR4, and DDR5 designs incorporate dedicated ODT resistors. These resistors are used to impedance-match transmission lines, minimizing reflections and energy loss during transmission, thereby ensuring signal integrity at the receiving end.

[0094] Taking DDR5 DRAM as an example, DDR5 DRAM supports ODT function, which can adjust the terminal resistance (also called "termination resistance") of each device's DQ, DQS_t / c, DM_n and TDQS_t / c ports through ODT pin control, write commands or mode register setting default resistance values. In addition, the purpose of the ODT function is to reduce reflections and effectively improve the signal integrity on the memory interface by independently controlling the terminal resistance of all or any DRAM by the controller. Figure 1 As shown, it shows a structural diagram of an ODT functional circuit provided by the related art. Figure 1 In the example, the ODT functional circuit may include at least a switch S1, a terminal resistor RTT, and a power supply VDDQ. One end of the switch S1 is connected to one end of the terminal resistor RTT, the other end of the terminal resistor RTT is connected to the power supply VDDQ, and the other end of the switch S1 is connected to other circuits, as well as the DQ, DQS, DM, and TDQS ports. It should be noted that DQS can be a pair of differential data strobe signals DQS_t and DQS_c, and TDQS can be a pair of differential data strobe signals TDQS_t and TDQS_c.

[0095] in addition, Figure 1 Switch S1 in the MCU is controlled by the ODT control logic. The ODT control logic includes the external ODT pin input, mode register configuration, and other control information. The RTT value is controlled by the configuration information in the mode register. Furthermore, if RTT_NOM is disabled in self-refresh mode or the mode register configuration, the ODT pin control is ignored.

[0096] For example, Figure 2 FIG1 shows a signal timing diagram of an ODT function, specifically a control timing diagram of the ODT function during a write operation in DDR5. Figure 2As shown, when DDR5 receives a command (CMD), it needs to transmit the command to the DQ end to control the change in the resistance of RTT. When DDR5 receives a write command, the resistance of RTT needs to switch from RTT_PARK to RTT_WR. That is to say, when the resistance of RTT is in the RTT_PARK stage, the DQ end does not receive data. When the write command is transmitted to the DQ end, the resistance of RTT switches to the RTT_WR stage, and the DQ end receives and writes data. That is, before the DQ end receives data, when the RTT resistance switches from RTT_PARK to RTT_WR, it is necessary to wait for tODTLon_WR preset clock cycles after the write command, where tODTLon_WR = CWL + ODTLon_WR_offset, where ODTLon_WR_offset is the adjustment value for the tODTLon_WR parameter issued by the controller. After the DQ end receives data, when the RTT resistance switches from RTT_WR to RTT_PARK again, it is necessary to wait for tODTLoff_WR preset clock cycles after the write command, where tODTLoff_WR = CWL + BL / 2 + ODTLoff_WR_offset, where ODTLoff_WR_offset is the adjustment value for the tODTLoff_WR parameter issued by the controller. Furthermore, the RTT resistance switching does not occur immediately but takes time to change. The RTT resistance switching time is represented by tADC. Here, the maximum and minimum values ​​of tADC can be set, represented as: tADC.Max and tADC.Min, respectively.

[0097] It is understandable that when DDR5 receives a write command, if you want to control the resistance change of RTT, you need to convert the write command into an internal ODT command to control the resistance change of RTT, such as Figure 2As shown, the data width is equal to the burst length (Burst Length, BL). When writing data, since there is data on both the rising and falling edges of the clock signal within a preset clock cycle, that is, there are two data within a preset clock cycle, the pulse width (i.e., pulse width) of the ODT command must be at least equal to BL / 2 times the preset clock cycle, that is, ODT CMD width1 = BL / 2. In addition, before the DQ end receives data, the RTT resistance value needs to be switched from RTT_PARK to RTT_WR. After the DQ end finishes receiving data, the RTT resistance value needs to be switched from RTT_WR to RTT_PARK. In other words, in the actual process, the pulse width of the ODT command requires an additional compensation amount (Offset) to meet the timing requirements when the RTT resistance value switches, that is, ODT CMD width2 = BL / 2 + Offset, where Offset = ODTLoff_WR_offset - ODTLon_WR_offset. Here, Offset is determined based on the instruction issued by the CPU and is used to further widen the pulse width of the ODT command.

[0098] Furthermore, Table 1 shows the relevant provisions of ODTLon_WR_offset and ODTLoff_WR_offset in DDR5. The values ​​of ODTLon_WR_offset and ODTLoff_WR_offset can be set according to the mode register, where the value of ODTLon_WR_offset can be set to -4, -3, -2, -1, 0, 1, or 2 preset clock cycles, and the value of ODTLoff_WR_offset can be set to 4, 3, 2, 1, 0, -1, or -2 preset clock cycles. Because it needs to comply with the relevant provisions of the DDR5 standard, as shown in Table 1, when ODTLon_WR_offset and ODTLoff_WR_offset are set to different values, the ODT function will be in valid mode or invalid mode, so 0≤ODTLoff_WR_offset-ODTLon_WR_offset≤8 is required; that is, when 0≤ODTLoff_WR_offset-ODTLon_WR_offset≤8, the width of the ODT command, that is, the value of ODT CMD width can be between BL / 2 and BL / 2+8.

[0099] It's understandable that the above content is the relevant provisions for the ODT function in the DDR5 technical specifications. Simply put, the RTT resistance value can be switched, but the switching must follow certain timing requirements. Due to non-ideal delay time on the transmission line, there are timing deviations, which can cause abnormal RTT resistance switching. This can cause signal reflections during the reception process, resulting in energy loss and even signal conflicts, reducing memory performance.

[0100] Table 1

[0101]

[0102] See also Figure 3 , which shows a detailed structural diagram of a control circuit Figure 1 .like Figure 3 As shown, the control circuit 10 may include a trigger 101, a trigger 102, a selection unit 103, a trigger 104, a selection unit 105, a trigger 106, a selection unit 107, a trigger 108, a trigger 109, a selection unit 110, a NOT gate 111, a selection unit 112 and an SR latch 113. The SR latch 113 includes a NAND gate C1 and a NAND gate C2. The specific connection relationship is as follows: Figure 3 shown.

[0103] exist Figure 3 In the embodiment, the clock ends of triggers 101, 102, 104, 106 and 108 are all used to receive the first clock signal QCLK, the clock end of trigger 109 is used to receive the second clock signal QBCLK, the input end of trigger 101 is used to receive the write command signal CMD_I, the control end of selection unit 103 is used to receive the first control signal SEL[4], the control end of selection unit 105 is used to receive the first control signal SEL[3], the control end of selection unit 107 is used to receive the first control signal SEL[2], the control end of selection unit 110 is used to receive the first control signal SEL[1], the control end of selection unit 112 is used to receive the first control signal SEL[0], the first input end of SR latch 113 is used to receive the first command signal CMD_shift, the second input end of SR latch 113 is used to receive the second command signal CMD_delay, and the output end of SR latch 113 is used to output the target command signal CMD_O. Among them, the first clock signal QCLK and the second clock signal QBCLK are clock signals obtained by dividing the initial clock signal CLK. The clock periods of the first clock signal QCLK and the second clock signal QBCLK are both twice the clock period of the initial clock signal CLK. The clock period of the initial clock signal CLK is a preset clock period, which can be represented by tck.

[0104] based on Figure 3 In the control circuit 10 shown, taking SEL[4]=1, SEL[3]=0, SEL[2]=0, SEL[1]=1 and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[10010] , the first command signal CMD_shift can be shifted by 6tck compared to the second command signal CMD_delay; when the pulse width CMD_width of the write command signal CMD_I is CMD_width=4tck, the pulse width of the target command signal CMD_O is 6tck, and the corresponding signal timing can be as follows Figure 4 shown.

[0105] based on Figure 3 The control circuit 10 shown takes SEL[4]=1, SEL[3]=1, SEL[2]=1, SEL[1]=1 and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[11110] , the first command signal CMD_shift can be shifted by 2tck compared to the second command signal CMD_delay; when BL is selected as 8, the pulse width CMD_width of the write command signal CMD_I is CMD_width=4tck=2T, and the pulse width widening compensation amount Offset of the write command signal CMD_I is Offset=2tck=1T. At this time, CMD_width>Offset, and the control circuit 10 using the SR latch 113 fails and cannot work normally. The corresponding signal timing can be seen in Figure 5 .like Figure 5 As shown in the figure, when CMD_width>Offset, the first command signal CMD_shift is shifted by 2tck compared to the second command signal CMD_delay, but the target command signal CMD_O is not in a high level state within the dotted box and is not widened within the dotted box. At this time, the pulse width of the target command signal CMD_O is consistent with the pulse width of the write command signal CMD_I, resulting in the pulse width of the target command signal CMD_O not being widened, thereby failing to ensure that it can cover the entire DQ data writing process. Here, 1T=2tck can represent the clock period of the first clock signal QCLK and the second clock signal QBCLK.

[0106] See also Figure 6 , which shows a detailed structural diagram of a control circuit Figure 2 .like Figure 6 As shown, the control circuit 20 may include a trigger 201, a trigger 202, a selection unit 203, a trigger 204, a selection unit 205, a trigger 206, a selection unit 207, a trigger 208, a trigger 209, a selection unit 210, a NOT gate 211, a selection unit 212 and a NAND gate 213; the specific connection relationship is as follows Figure 6 As shown. Figure 6Among them, the clock terminals of flip-flops 201, 202, 204, 206 and 208 are all used to receive the first clock signal QCLK, the clock terminal of flip-flop 209 is used to receive the second clock signal QBCLK, the input terminal of flip-flop 201 is used to receive the write command signal CMD_I, the control terminal of selection unit 203 is used to receive the first control signal SEL[4], the control terminal of selection unit 205 is used to receive the first control signal SEL[3], the control terminal of selection unit 207 is used to receive the first control signal SEL[2], the control terminal of selection unit 210 is used to receive the first control signal SEL[1], the control terminal of selection unit 212 is used to receive the first control signal SEL[0], the first input terminal of NAND gate 213 is used to receive the first command signal CMD_shift, the second input terminal of NAND gate 213 is used to receive the second command signal CMD_delay, and the output terminal of NAND gate 213 is used to output the target command signal CMD_O. Among them, the first clock signal QCLK and the second clock signal QBCLK are clock signals obtained by frequency dividing the initial clock signal CLK. The clock periods of the first clock signal QCLK and the second clock signal QBCLK are both twice the clock period of the initial clock signal CLK, and the clock period of the initial clock signal CLK can be represented by tck.

[0107] Based on Figure 6 the control circuit 20 shown, taking SEL[4]=1, SEL[3]=1, SEL[2]=1, SEL[1]=1 and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[11110] , the first command signal CMD_shift can be shifted by 2tck compared to the second command signal CMD_delay; when the pulse width CMD_width of the write command signal CMD_I is 4tck, at this time the pulse width of the target command signal CMD_O is 6tck, and the corresponding signal timing can be as Figure 7 shown.

[0108] Based on Figure 6 the control circuit 20 shown, taking SEL[4]=1, SEL[3]=0, SEL[2]=0, SEL[1]=1 and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[10010] , the first command signal CMD_shift can be shifted by 6tck compared to the second command signal CMD_delay; when BL is selected as 8, the pulse width CMD_width of the write command signal CMD_I is 4tck = 2T, the pulse width broadening compensation amount Offset of the write command signal CMD_I is 6tck = 3T, at this time CMD_width < Offset, and the control circuit 20 of the NAND gate 213 fails and cannot work properly, and the corresponding signal timing can be referred to Figure 8 As shown in Figure 8 , when CMD_width < Offset, the first command signal CMD_shift is shifted by 6 tck compared to the second command signal CMD_delay. However, the target command signal CMD_O is not always at a high level within the dashed box, resulting in an interruption of the pulse of the target command signal CMD_O, thus failing to ensure that the entire process of writing DQ data can be covered.

[0109] In summary, when the control circuit 10 uses an SR latch to widen the pulse width of the write command signal, in the case of BL = 8, CMD_width = 4 tck, and Offset = ODTLoff_WR_offset - ODTLon_WR_offset = 2 tck, that is, when CMD width > Offset, the control circuit 10 using the SR latch will fail; and when the control circuit 20 uses a NAND gate to widen the pulse width of the write command signal, in the case of BL = 8, CMD_width = 4 tck, and Offset = ODTLoff_WR_offset - ODTLon_WR_offset = 6 tck, that is, when CMD width < Offset, the control circuit 20 using the NAND gate fails. That is to say, in different cases, the control circuits using the SR latch and the NAND gate will both fail, thus affecting the ODT function of the memory.

[0110] Based on this, an embodiment of the present disclosure provides a control circuit. Since the write command signal includes BL information, the pulse width of the target command signal generated by the command adjustment circuit is widened by A times the preset clock period compared to the pulse width of the write command signal. At the same time, the first control signal and the second control signal can also indicate the magnitude of the compensation amount, and the first control signal and the second control signal are generated according to A. Thus, it is possible to adjust the pulse width of the write command signal according to different BLs and different compensation amounts, so that the target command signal with the adjusted pulse width can meet the timing requirements of the terminal resistance value switching; in this way, not only can signal conflicts during transmission be avoided, but also the energy loss and reflection of signals during transmission can be reduced, improving signal integrity and further improving the performance of the memory.

[0111] In an embodiment of the present disclosure, refer to Figure 9 , which shows a schematic structural composition of a control circuit provided by an embodiment of the present disclosure Figure 1 As shown in Figure 9 , the control circuit 30 may include a signal sampling circuit 31, a delay shift circuit 32, a shift selection circuit 33, and a command adjustment circuit 34, where:

[0112] The signal sampling circuit 31 is configured to receive a write command signal and a first clock signal, and sample the write command signal according to the first clock signal to obtain a first output signal;

[0113] a delay shift circuit 32 configured to receive the first output signal, the first clock signal, and the first control signal, and to sample and shift the first output signal according to the first control signal and the first clock signal to obtain a second output signal; wherein a shift length between the second output signal and the first output signal is associated with the first control signal;

[0114] The shift selection circuit 33 is configured to receive the first output signal, the second output signal, the first clock signal, the second clock signal, and the second control signal; sample the second output signal according to the first clock signal to obtain a first intermediate signal; sample the second output signal according to the second clock signal to obtain a second intermediate signal; and select the first intermediate signal, the second intermediate signal, and the inverted first output signal according to the second control signal to obtain a third output signal;

[0115] The command adjustment circuit 34 is configured to receive the first output signal and the third output signal, perform pulse width adjustment processing according to the first output signal and the third output signal, and generate a target command signal.

[0116] Among them, the clock periods of the first clock signal and the second clock signal are both twice the preset clock period, and the phase difference between the first clock signal and the second clock signal is 180 degrees; the pulse width of the target command signal is widened by A times the preset clock period compared to the pulse width of the write command signal, and the first control signal and the second control signal are generated based on A, where A is an integer greater than or equal to 0.

[0117] It should be noted that in the embodiment of the present disclosure, the control circuit 30 can be applied to a memory. The memory can be, for example, a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), etc., and is not specifically limited here.

[0118] It should also be noted that in the embodiment of the present disclosure, the control circuit 30 is specifically a circuit for generating an ODT command, which can support the ODT function introduced in DDR5. In addition, the write command signal here includes BL information, that is, the pulse width of the write command signal is associated with BL.

[0119] It should also be noted that in the disclosed embodiments, the pulse width of the target command signal, which is wider than the write command signal, is correlated with the compensation amount. That is, by adjusting the pulse width of the write command signal based on different BL values ​​and compensation amounts, target command signals with different pulse widths can be generated to reduce DQ pin reflections when receiving DQ data.

[0120] It should also be noted that in the embodiment of the present disclosure, the first output signal is shifted by the delay shift circuit 32 and the shift selection circuit 33, wherein the delay shift circuit 32 receives the first control signal and the shift selection circuit 33 receives the second control signal. The first control signal and the second control signal indicate the size of the compensation amount, so the first control signal and the second control signal are generated based on A.

[0121] It should also be noted that, in the embodiment of the present disclosure, the preset clock period can be represented by tck, and the clock periods of the first clock signal and the second clock signal can be represented by 2tck.

[0122] Furthermore, in some embodiments, Figure 9 Based on the control circuit 30 shown, see Figure 10 , the control circuit 30 may further include a clock frequency dividing circuit 35, wherein:

[0123] The clock frequency dividing circuit 35 is configured to receive an initial clock signal, perform frequency division processing on the initial clock signal, and generate a first clock signal and a second clock signal;

[0124] The clock period of the initial clock signal is a preset clock period.

[0125] It should be noted that, in the embodiment of the present disclosure, the first clock signal can be represented by QCLK, the second clock signal can be represented by QBCLK, and the first clock signal and the second clock signal are in antiphase to each other.

[0126] It should also be noted that in the embodiment of the present disclosure, the frequency of the initial clock signal is twice the frequency of the first clock signal and the second clock signal. In other words, when the clock period of the initial clock signal is the preset clock period, the clock periods of the first clock signal and the second clock signal are both twice the preset clock period.

[0127] In some embodiments, the pulse width of the write command signal is equal to B times the preset clock period; wherein B is equal to 0.5 times the burst length BL of the data.

[0128] It should be noted that in the embodiment of the present disclosure, the write command signal can have different pulse widths, so the control circuit 30 can implement pulse width stretching for write command signals with different pulse widths. Specifically, the pulse width of the write command signal can be equal to BL / 2 preset clock cycles, that is, the pulse width of the write command signal is (BL / 2)tck.

[0129] It should also be noted that in the embodiment of the present disclosure, in order to match the terminal resistance of the DQ end with the resistance on the data path when receiving data at the DQ end, the width of the ODT command needs to match the width of the data at the DQ end, that is, BL, where BL can be determined by the mode register. Here, B = BL / 2, because within a preset clock cycle, DDR can have data on both the rising and falling edges of the clock signal when writing data, that is, there are two data in one preset clock cycle; if a preset clock cycle is 1tck, then the pulse width of the write command signal is (BL / 2)tck. In this way, in order to keep consistent with the unit of the compensation amount, the width of the data can be converted into a multiple of the preset clock cycle to represent it.

[0130] Specifically, in some embodiments, B can be equal to any one of the following values: 4, 8, 16.

[0131] It should be noted that in the embodiment of the present disclosure, the control circuit 30 can support one of BL8, BL16, BL32, etc. Here, BL8 means that BL is equal to 8, BL16 means that BL is equal to 16, and BL32 means that BL is equal to 32. Because B = BL / 2, when BL is equal to 8, 16, or 32, B can be 4, 8, or 16. Accordingly, for different BLs, the ODT command needs to support different pulse widths so that the resistance switching of the terminal resistor can be controlled according to the final generated ODT pulse.

[0132] In some embodiments, A can be equal to any of the following values: 0, 1, 2, 3, 4, 5, 6, 7, 8.

[0133] It should be noted that in the embodiment of the present disclosure, the control circuit 30 can support a compensation amount of 0 to 8 tck, that is, the pulse width of the target command signal can be widened by 0, 1, 2, 3, 4, 5, 6, 7 or 8 times the preset clock cycle compared to the pulse width of the write command signal. Therefore, the control circuit 30 can also realize widening the pulse width of the write command signal according to different compensation amounts.

[0134] It should also be noted that in the disclosed embodiment, to ensure that DQ pin reflections are reduced when receiving DQ data, the control circuit 30 can further widen the pulse width of the ODT command based on the offset required by the CPU to generate the final ODT pulse at the DQ pin. Here, the pulse width of the write command signal is (BL / 2)tck, and the pulse width difference between the target command signal and the write command signal can be expressed as Offset, Offset = ODTLoff_WR_offset - ODTLon_WR_offset.

[0135] In addition, in the embodiment of the present disclosure, for the target command signal, the pulse width of the target command signal is (BL / 2+Offset), that is, the pulse width of the target command signal is not only related to the value of BL, but also related to the Offset, so that the reflection of the DQ pin can be greatly reduced when the DQ data is finally received.

[0136] Furthermore, in some embodiments, for the signal sampling circuit 31, see Figure 11 , the signal sampling circuit 31 may include a first trigger DFF1, wherein:

[0137] The clock end of the first trigger DFF1 is used to receive a first clock signal, the input end of the first trigger DFF1 is used to receive a write command signal, and the first output end of the first trigger DFF1 is used to output a first output signal; wherein, the first output end of the first trigger DFF1 is used to reflect the value of the input end of the first trigger DFF1 after being sampled by the first clock signal.

[0138] It should be noted that in the disclosed embodiment, the first flip-flop DFF1 may be a D-type flip-flop. A D-type flip-flop is an information storage device with a memory function and two stable states. It is the most basic logic unit for various sequential circuits and an important unit circuit in digital logic circuits. The D-type flip-flop has two stable states, "0" and "1," and can flip from one stable state to the other under the influence of a signal received from a clock terminal.

[0139] It should also be noted that, in the embodiment of the present disclosure, the first flip-flop DFF1 may include a clock terminal (CK), an input terminal (D), a first output terminal (Q), and a second output terminal (Q). In addition, a set terminal (SET) and a reset terminal (RST) may also be included, but they are not shown in the figure.

[0140] Furthermore, in some embodiments, for the delay shift circuit 32, see Figure 12, the delay shift circuit 32 may include M delay units, where M is an integer greater than 0, wherein:

[0141] The delay shift circuit 32 is used to receive a first control signal, determine a target number of delay units among the M delay units according to the first control signal, and sample and shift the first output signal through the target number of delay units to obtain a second output signal.

[0142] It should be noted that, in the embodiment of the present disclosure, the first control signal is not a single signal, but represents a group of signals, which can be represented by Sel[1:M], specifically Sel[1], Sel[2], ..., Sel[M]. Figure 12 , delay unit 1 receives Sel[1],…, delay unit 2 receives Sel[2], and delay unit M receives Sel[M].

[0143] It should also be noted that in the embodiment of the present disclosure, there is an association between the target number of delay units and the first control signal. Specifically, the first control signal can determine how many delay units are used to sample and shift the first output signal to obtain the second output signal.

[0144] In some embodiments, the first control signal may include M sub-control signals, a j-th delay unit and a j-th sub-control signal have a corresponding relationship, and the j-th delay unit includes a j-th delay sub-unit and a j-th selection unit, wherein:

[0145] When M is equal to 1, the delay shift circuit 32 includes only one delay unit, and the connection relationship thereof is as follows: the clock terminal of the first delay sub-unit is used to receive the first clock signal, the input terminal of the first delay sub-unit is used to receive the first output signal, the first input terminal of the first selection unit is used to receive the first output signal, the first output terminal of the first delay sub-unit is connected to the second input terminal of the first selection unit, the control terminal of the first selection unit is used to receive the first sub-control signal, and the output terminal of the first selection unit is used to output the second output signal;

[0146] When M is greater than 1 and j is greater than 1, the delay shift circuit 32 includes at least two delay units, and their connection relationship is as follows: the clock terminal of the jth delay sub-unit is used to receive the first clock signal, the input terminal of the jth delay sub-unit is used to receive the j-1th selection result signal, the first output terminal of the jth delay sub-unit is connected to the second input terminal of the jth selection unit, and is used to output the jth delayed result signal; the first input terminal of the jth selection unit is used to receive the first output signal, the control terminal of the jth selection unit is used to receive the jth sub-control signal, and the output terminal of the jth selection unit is used to output the jth selection result signal; wherein j is an integer greater than 1 and less than or equal to M;

[0147] And, when j is equal to 1, the clock end of the first delay sub-unit is used to receive the first clock signal, the input end of the first delay sub-unit is used to receive the first output signal, and the first output end of the first delay sub-unit is connected to the second input end of the first selection unit for outputting the first delayed result signal; the first input end of the first selection unit is used to receive the first output signal, the control end of the first selection unit is used to receive the first sub-control signal, and the output end of the first selection unit is used to output the first selection result signal.

[0148] In the embodiment of the present disclosure, when j is equal to M, the output end of the Mth selection unit is used to output the Mth selection result signal, that is, the second output signal.

[0149] It can be understood that when M is greater than 1, the delay shift circuit 32 includes a plurality of delay units, and the plurality of delay units are connected in sequence.

[0150] Furthermore, taking the jth delay unit as an example, in some embodiments, the jth delay sub-unit is configured to receive the j-1th selection result signal and the first clock signal, and sample the j-1th selection result signal according to the first clock signal to obtain the jth delayed result signal;

[0151] The jth selection unit is configured to receive the jth sub-control signal, and select one between the jth delayed result signal and the first output signal according to the jth sub-control signal to output as the jth selection result signal.

[0152] It should be noted that, see Figure 13, the M delay units can be respectively represented as D[1], D[2], ..., D[M], and the M sub-control signals can be respectively represented as Sel[1], Sel[2], ..., Sel[M]. For the M sub-control signals, when the level states of the M sub-control signals are different, the target number of selected delay units is also different. Exemplarily, when the j-th sub-control signal is in a first level state, the first output signal is selected from the j-th delayed result signal and the first output signal as the j-th selected result signal; and when the j-th sub-control signal is in a second level state, the j-th delayed result signal is selected from the j-th delayed result signal and the first output signal as the j-th selected result signal.

[0153] For the j-th sub-control signal, the first level state may be a high level state, such as logic 1; the second level state may be a low level state, such as logic 0, but this is not specifically limited.

[0154] It is understood that in the disclosed embodiments, the target number is associated with the first control signal. Specifically, the first control signal represents a control code that determines how many delay units are used to delay the first output signal. Different control codes result in different target numbers of delay units.

[0155] It can also be understood that in the first control signal, if the level value of the jth sub-control signal is the first value, then it is determined that the level values ​​of other sub-control signals except the jth sub-control signal are all the second value; wherein the first value is different from the second value.

[0156] For example, assuming that the first value is set to logic 1 and the second value is set to logic 0, taking M=8 and the delay shift circuit 32 including eight delay units as an example, the first control signal includes eight sub-control signals, and the order of the first control signal is Sel<1:M>. At this time, the control code can be 0000 0001, 0000 0010, 0000 0100, 0000 1000, or 0001 0000, 0010 0000, 0100 0000, 1000 0000, etc. Here, if the control code is 0000 0100, it means that two delay units are determined, then the first output signal is selected from the sixth delay unit, and then the seventh delay unit and the eighth delay unit, a total of two delay units, are used as the target number of delay units, and the first output signal is sampled and shifted through these two delay units; if the control code is 0001 0000, it means that four delay units are determined, then the first output signal is selected from the fourth delay unit, and then the fifth delay unit to the eighth delay unit, a total of four delay units, are used as the target number of delay units, and the first output signal is sampled and shifted through these four delay units; if the control code is 1000 0000, it means that seven delay units are determined, then the first output signal is selected from the first delay unit, and then the second delay unit to the eighth delay unit, a total of seven delay units, are used as the target number of delay units, and the first output signal is sampled and shifted through these seven delay units.

[0157] In this way, for the first control signal, when the corresponding control codes are different, the target number of delay units is also different.

[0158] Furthermore, in some embodiments, Figure 13 As shown, the j-th delay sub-unit includes a second flip-flop DFF2, wherein:

[0159] When j is equal to 1, the clock terminal of the second flip-flop DFF2 is used to receive the first clock signal, the input terminal of the second flip-flop DFF2 is used to receive the first output signal, and the first output terminal of the second flip-flop DFF2 is used to output the first delayed result signal;

[0160] When j is greater than 1, the clock end of the second flip-flop DFF2 is used to receive the first clock signal, the input end of the second flip-flop DFF2 is used to receive the j-1th selection result signal, and the first output end of the second flip-flop DFF2 is used to output the jth delayed result signal.

[0161] The first output terminal of the second flip-flop DFF2 is used to reflect the value of the input terminal of the second flip-flop DFF2 after being sampled by the first clock signal.

[0162] It should be noted that, in the embodiment of the present disclosure, the second flip-flop DFF2 may be a D-type flip-flop.

[0163] Further, in some embodiments, for the shift selection circuit 33, see Figure 14 , the shift selection circuit 33 may include a shift sub-circuit 331, an inversion sub-circuit 332 and a selection sub-circuit 333, wherein:

[0164] a shift subcircuit 331 configured to receive the second output signal, the first clock signal, and the second clock signal, sample the second output signal according to the first clock signal to obtain a first intermediate signal, and sample the second output signal according to the second clock signal to obtain a second intermediate signal;

[0165] an inverting sub-circuit 332, configured to receive the first output signal, and invert the first output signal to obtain a third intermediate signal;

[0166] The selection subcircuit 333 is configured to receive the first intermediate signal, the second intermediate signal, the third intermediate signal, and the second control signal, select the first intermediate signal, the second intermediate signal, and the third intermediate signal according to the second control signal, and output a third output signal.

[0167] It should be noted that in the embodiment of the present disclosure, the first intermediate signal and the second intermediate signal can be obtained by sampling the second output signal according to the first clock signal and the second clock signal respectively by the shift sub-circuit 331, and the phase difference between the first clock signal and the second clock signal is 180 degrees, and the first clock signal and the second clock signal differ by 1tck, so the compensation amount can be an odd number according to the different selections of the first intermediate signal and the second intermediate signal by the selection sub-circuit 333.

[0168] It can be understood that in some embodiments, the inversion sub-circuit 332 may be composed of an odd number of second NOT gates.

[0169] It should be noted that the inverting sub-circuit 332 can be composed of one second NOT gate, or three, or five, or seven second NOT gates connected in series, and this embodiment of the present disclosure does not specifically limit this. Figure 14 In the embodiment, the specific implementation of the present disclosure is described in detail by taking the inverting sub-circuit 332 consisting of a second NOT gate U1 as an example.

[0170] Furthermore, in some embodiments, for the shift subcircuit 331, as shown in FIG. Figure 14 As shown, the shift sub-circuit 331 includes a third flip-flop DFF3 and a fourth flip-flop DFF4, wherein:

[0171] The input terminals of the third flip-flop DFF3 and the fourth flip-flop DFF4 are both used to receive the second output signal, the clock terminal of the third flip-flop DFF3 is used to receive the first clock signal, and the first output terminal of the third flip-flop DFF3 is used to output the first intermediate signal; the clock terminal of the fourth flip-flop DFF4 is used to receive the second clock signal, and the first output terminal of the fourth flip-flop DFF4 is used to output the second intermediate signal;

[0172] Among them, the first output end of the third trigger DFF3 is used to reflect the value of the input end of the third trigger DFF3 after being sampled by the first clock signal; the first output end of the fourth trigger DFF4 is used to reflect the value of the input end of the fourth trigger DFF4 after being sampled by the second clock signal.

[0173] It should be noted that, in the embodiment of the present disclosure, the third flip-flop DFF3 and the fourth flip-flop DFF4 may be D-type flip-flops.

[0174] Furthermore, in some embodiments, for the selection sub-circuit 333, as shown in FIG. Figure 14 As shown, the second control signal includes a first sub-control signal and a second sub-control signal, and the selection sub-circuit 333 includes a first selection sub-circuit U2 and a second selection sub-circuit U3, wherein:

[0175] a first selection sub-circuit U2, configured to receive the first intermediate signal and the second intermediate signal, and select one of the first intermediate signal and the second intermediate signal according to the first sub-control signal to output as a fourth intermediate signal;

[0176] The second selection sub-circuit U3 is configured to receive the third intermediate signal and the fourth intermediate signal, and select one of the third intermediate signal and the fourth intermediate signal according to the second sub-control signal to output as a third output signal.

[0177] It should be noted that, in the embodiment of the present disclosure, the first input terminal of the first selection sub-circuit U2 is used to receive the first intermediate signal, the second input terminal of the first selection sub-circuit U2 is used to receive the second intermediate signal, the control terminal of the first selection sub-circuit U2 is used to receive the first sub-control signal, and the output terminal of the first selection sub-circuit U2 is connected to the second input terminal of the second selection sub-circuit U3 for outputting the fourth intermediate signal; the first input terminal of the second selection sub-circuit U3 is used to receive the third intermediate signal, the control terminal of the second selection sub-circuit U3 is used to receive the second sub-control signal, and the output terminal of the second selection sub-circuit U3 is used to output the third output signal.

[0178] It should also be noted that in the embodiment of the present disclosure, the first sub-control signal can be represented by Sel[e], and the second sub-control signal can be represented by Sel[f]. For the first sub-control signal and the second sub-control signal, if the level states of the first sub-control signal and the second sub-control signal are different, the signals selected and output by the selection sub-circuit 333 are also different.

[0179] Exemplarily, when the first sub-control signal is at a first level and the second sub-control signal is at a first level, the selection sub-circuit 333 selects the third intermediate signal to be output as the third output signal; when the first sub-control signal is at a first level and the second sub-control signal is at a second level, the selection sub-circuit 333 selects the first intermediate signal to be output as the third output signal; when the first sub-control signal is at a second level and the second sub-control signal is at a first level, the selection sub-circuit 333 selects the third intermediate signal to be output as the third output signal; when the first sub-control signal is at a second level and the second sub-control signal is at a second level, the selection sub-circuit 333 selects the second intermediate signal to be output as the third output signal;

[0180] For the first sub-control signal and the second sub-control signal, the first level state may be a high level state, such as logic 1; the second level state may be a low level state, such as logic 0, but this is not specifically limited.

[0181] In some embodiments, for the command adjustment circuit 34, see Figure 15 The command adjustment circuit 34 includes an SR latch 341, a first NOT gate 342, and a first NOR gate 343. The SR latch 341 includes a first NAND gate U4 and a second NAND gate U5, wherein:

[0182] The input end of the first NOT gate 342 is connected to the first input end of the first NAND gate U4 for receiving the third output signal; the output end of the first NOT gate 342 is used to output the first command signal;

[0183] The second input terminal of the first NAND gate U4 is connected to the output terminal of the second NAND gate U5, the first input terminal of the second NAND gate U5 is connected to the output terminal of the first NAND gate U4, the second input terminal of the second NAND gate U5 is used to receive the first output signal, and the output terminal of the second NAND gate U5 serves as the output terminal of the SR latch 341 for outputting the second command signal;

[0184] A first input terminal of the first NOR gate 343 is connected to the output terminal of the second NAND gate U5 for receiving the second command signal; a second input terminal of the first NOR gate 343 is connected to the output terminal of the first NOT gate 342 for receiving the first command signal; an output terminal of the first NOR gate 343 is used to output the target command signal;

[0185] The first command signal is delayed by A times of the preset clock cycle compared to the second command signal.

[0186] It should be noted that, in the embodiment of the present disclosure, the first command signal can be represented by CMD_shift, and the second command signal can be represented by CMD_delay.

[0187] It should also be noted that, in the embodiment of the present disclosure, the SR latch 341 can perform a latching process based on the first output signal and the third output signal to obtain a second command signal. Specifically, the first input terminal of the first NAND gate U4 serves as the first input terminal of the SR latch 341 for receiving the third output signal; the second input terminal of the second NAND gate U5 serves as the second input terminal of the SR latch 341 for receiving the first output signal; and the output terminal of the second NAND gate U5 serves as the output terminal of the SR latch 341 for outputting the second command signal.

[0188] It should also be noted that, in the embodiment of the present disclosure, the first command signal is first obtained through the first NOT gate 342, and the second command signal is obtained through the SR latch 341, and then the first command signal and the second command signal are subjected to a NOR logic operation through the first NOR gate 343 to obtain the target command signal, thereby enabling the command adjustment circuit 34 to perform pulse width adjustment processing on the first output signal, and when the first command signal is delayed by A times the preset clock period compared to the second command signal, the pulse width of the target command signal can be widened by A times the preset clock period compared to the pulse width of the write command signal.

[0189] An embodiment of the present disclosure provides a control circuit. Since the write command signal contains BL information, the pulse width of the target command signal generated by the command adjustment circuit is widened by A times the preset clock period compared to the pulse width of the write command signal. At the same time, the first control signal and the second control signal can also indicate the size of the compensation amount, and the first control signal and the second control signal are generated based on A, so that the pulse width of the write command signal can be adjusted according to different BLs and different compensation amounts, so that the target command signal after pulse width adjustment can meet the resistance switching timing requirements of the terminal resistor; in this way, not only can signal conflicts during transmission be avoided, but also energy loss and reflection of the signal during transmission can be reduced, thereby improving signal integrity and thus improving memory performance.

[0190] In another embodiment of the present disclosure, based on the control circuit 30 in the aforementioned embodiment, the control circuit 30 is further refined. Figure 16 Detailed structural diagram of a control circuit provided by an embodiment of the present disclosure. Figure 16As shown, the control circuit 30 may include a trigger 401, a trigger 402, a selection unit 403, a trigger 404, a selection unit 405, a trigger 406, a selection unit 407, a trigger 408, a trigger 409, a selection unit 410, a second NOT gate 411, a selection unit 412, an SR latch 413, a first NOT gate 414 and a first NOR gate 415, and the SR latch 413 includes a first NAND gate E1 and a second NAND gate E2. Specifically, the signal sampling circuit is composed of a trigger 401; the delay shift circuit is composed of three delay units, wherein the first delay unit is composed of a trigger 402 and a selection unit 403, the second delay unit is composed of a trigger 404 and a selection unit 405, and the third delay unit is composed of a trigger 406 and a selection unit 407; the shift selection circuit is composed of a trigger 408, a trigger 409, a selection unit 410, a second NOT gate 411, and a selection unit 412; the command adjustment circuit is composed of an SR latch 413, a first NOT gate 414, and a first NOR gate 415. For details on the specific connection relationship, see Figure 16 .

[0191] It should be noted that in the embodiment of the present disclosure, the write command signal can be represented by CMD_I, the first clock signal can be represented by QCLK, the second clock signal can be represented by QBCLK, the first output signal can be represented by Q1, the third output signal can be represented by Q3, the first command signal can be represented by CMD_shift, the second command signal can be represented by CMD_delay, the target command signal can be represented by CMD_O, the first sub-control signal can be represented by Sel[1], and the second sub-control signal can be represented by Sel[0].

[0192] It should also be noted that, in the embodiment of the present disclosure, the first control signal includes Sel[4], Sel[3], and Sel[2]. In the delay shift circuit, the first delay unit receives the first sub-control signal Sel[4], the second delay unit receives the second sub-control signal Sel[3], and the third delay unit receives the third sub-control signal Sel[2].

[0193] based on Figure 16The control circuit 30 shown, taking SEL[4]=1, SEL[3]=1, SEL[2]=1, SEL[1]=1, and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[11110] , the first command signal CMD_shift can be shifted by 2tck compared to the second command signal CMD_delay; when BL is selected as 8, the pulse width CMD_width of the write command signal CMD_I is 4tck = 2T, and the pulse width broadening compensation amount Offset of the write command signal CMD_I is 2tck = 1T. At this time, CMD_width > Offset, and the corresponding signal timing can be seen in Figure 17 . As Figure 17 shown, when CMD_width > Offset, the third output signal Q3 is shifted by 2tck compared to the first output signal Q1, and the first command signal CMD_shift is shifted by 2tck compared to the second command signal CMD_delay. As a result, the pulse width of the target command signal CMD_O is broadened by 2tck compared to the pulse width of the write command signal CMD_I, and the pulse width of the target command signal CMD_O is 6tck.

[0194] Based on Figure 16 the control circuit 30 shown, taking SEL[4]=1, SEL[3]=0, SEL[2]=0, SEL[1]=1, and SEL[0]=0 as an example, that is, when the value of the first control signal is Sel

[10010] , the first command signal CMD_shift can be shifted by 6tck compared to the second command signal CMD_delay; when BL is selected as 8, the pulse width CMD_width of the write command signal CMD_I is 4tck = 2T, and the pulse width broadening compensation amount Offset of the write command signal CMD_I is 6tck = 3T. At this time, CMD_width < Offset, and the corresponding signal timing can be seen in Figure 18 . As Figure 18 shown, when CMD_width < Offset, the third output signal Q3 is shifted by 6tck compared to the first output signal Q1, and the first command signal CMD_shift is shifted by 6tck compared to the second command signal CMD_delay. As a result, the pulse width of the target command signal CMD_O is broadened by 6tck compared to the pulse width of the write command signal CMD_I, and the pulse width of the target command signal CMD_O is 10tck.

[0195] This embodiment provides a control circuit that supports data burst lengths such as BL8, BL16, and BL32, as well as compensation amounts ranging from 0 to 8 tck. Here, an SR latch and a NOR gate are used to adjust the pulse width of the write command signal based on different BL values ​​and compensation amounts, thereby generating target command signals with different pulse widths. This covers the entire DQ data write process, reduces DQ pin reflections when receiving DQ data, improves signal integrity, and thus enhances memory performance.

[0196] In another embodiment of the present disclosure, see Figure 19 , which shows a flow chart of a control method provided by an embodiment of the present disclosure. Figure 19 As shown, the method may include:

[0197] S501 : Receive a write command signal and a first clock signal through a signal sampling circuit, sample the write command signal according to the first clock signal, and obtain a first output signal.

[0198] S502: Receive the first output signal, the first clock signal, and the first control signal through the delay shift circuit, and sample and shift the first output signal according to the first control signal and the first clock signal to obtain a second output signal.

[0199] S503. Receive the first output signal, the second output signal, the first clock signal, the second clock signal, and the second control signal through a shift selection circuit, sample the second output signal according to the first clock signal to obtain a first intermediate signal; sample the second output signal according to the second clock signal to obtain a second intermediate signal; and select the first intermediate signal, the second intermediate signal, and the inverted first output signal according to the second control signal to obtain a third output signal.

[0200] S504 : Receive the first output signal and the third output signal through the command adjustment circuit, perform pulse width adjustment processing according to the first output signal and the third output signal, and generate a target command signal.

[0201] In an embodiment of the present disclosure, the shift length between the second output signal and the first output signal is associated with the first control signal; the clock periods of the first clock signal and the second clock signal are both twice the preset clock period, and the phase difference between the first clock signal and the second clock signal is 180 degrees; the pulse width of the target command signal is widened by A times the preset clock period compared to the pulse width of the write command signal, and the first control signal and the second control signal are generated based on A, where A is an integer greater than or equal to 0.

[0202] In the embodiment of the present disclosure, the control method is applied to the control circuit 30 in the aforementioned embodiment. For details not disclosed in the embodiment of the present disclosure, please refer to the description of the aforementioned embodiment for understanding.

[0203] This embodiment provides a control method, specifically a control method for generating an ODT command. Because the write command signal includes BL information, the pulse width of the target command signal generated by the command adjustment circuit is widened by A times the preset clock cycle compared to the pulse width of the write command signal. At the same time, the first control signal and the second control signal can also indicate the size of the compensation amount, and the first control signal and the second control signal are generated based on A. This allows the pulse width of the write command signal to be adjusted according to different BLs and different compensation amounts, so that the target command signal after pulse width adjustment can meet the resistance switching timing requirements of the terminal resistor. In this way, not only can signal conflicts during transmission be avoided, but also energy loss and reflection of the signal during transmission can be reduced, thereby improving signal integrity and thereby improving memory performance.

[0204] In another embodiment of the present disclosure, see Figure 20 , which shows a schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure. Figure 20 As shown, the memory 60 may include the control circuit 30 described in any one of the aforementioned embodiments.

[0205] In some embodiments, the memory 60 may include a DRAM chip. The DRAM chip may conform not only to memory specifications such as DDR, DDR2, DDR3, DDR4, DDR5, and DDR6, but also to memory specifications such as LPDDR, LPDDR2, LPDDR3, LPDDR4, LPDDR5, and LPDDR6, which are not specifically limited herein.

[0206] In the embodiment of the present disclosure, for the memory 60, since the write command signal contains BL information, the pulse width of the target command signal generated by the command adjustment circuit is widened by A times the preset clock period compared to the pulse width of the write command signal. At the same time, the first control signal and the second control signal can also indicate the size of the compensation amount, and the first control signal and the second control signal are generated based on A, so that the pulse width of the write command signal can be adjusted according to different BLs and different compensation amounts, so that the target command signal after pulse width adjustment can meet the resistance switching timing requirements of the terminal resistor; in this way, not only can signal conflicts during transmission be avoided, but also energy loss and reflection of the signal during transmission can be reduced, thereby improving signal integrity and thus improving memory performance.

[0207] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure.

[0208] It should be noted that, in this disclosure, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0209] The serial numbers of the above-mentioned embodiments of the present disclosure are for description only and do not represent the advantages or disadvantages of the embodiments.

[0210] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0211] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0212] The features disclosed in several method or device embodiments provided in this disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0213] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A control circuit, characterized in that: The control circuit includes a signal sampling circuit, a delay shift circuit, a shift selection circuit and a command adjustment circuit, wherein: The signal sampling circuit is configured to receive a write command signal and a first clock signal, and sample the write command signal according to the first clock signal to obtain a first output signal; The delay shift circuit is configured to receive the first output signal, the first clock signal, and a first control signal, and perform sampling and shift processing on the first output signal according to the first control signal and the first clock signal to obtain a second output signal; wherein a shift length between the second output signal and the first output signal is associated with the first control signal; the shift selection circuit is configured to receive the first output signal, the second output signal, the first clock signal, the second clock signal, and the second control signal; sample the second output signal according to the first clock signal to obtain a first intermediate signal; sample the second output signal according to the second clock signal to obtain a second intermediate signal; and select the first intermediate signal, the second intermediate signal, and the inverted first output signal according to the second control signal to obtain a third output signal; The command adjustment circuit is configured to receive the first output signal and the third output signal, perform pulse width adjustment processing according to the first output signal and the third output signal, and generate a target command signal; Among them, the clock periods of the first clock signal and the second clock signal are both twice the preset clock period, and the phase difference between the first clock signal and the second clock signal is 180 degrees; the pulse width of the target command signal is widened by A times the preset clock period compared to the pulse width of the write command signal, and the first control signal and the second control signal are generated based on A, where A is an integer greater than or equal to 0.

2. The control circuit according to claim 1, wherein: The control circuit further includes a clock frequency dividing circuit, wherein: The clock frequency dividing circuit is configured to receive an initial clock signal, perform frequency division processing on the initial clock signal, and generate the first clock signal and the second clock signal; Wherein, the clock period of the initial clock signal is the preset clock period.

3. The control circuit according to claim 1, wherein: The pulse width of the write command signal is equal to B times the preset clock period; wherein B is equal to 0.5 times the burst length BL of the data.

4. The control circuit according to claim 3, characterized in that: The B is equal to any one of the following values: 4, 8, 16.

5. The control circuit according to claim 1, wherein: A is equal to any of the following values: 0, 1, 2, 3, 4, 5, 6, 7, 8.

6. The control circuit according to claim 1, wherein: The signal sampling circuit includes a first trigger, wherein: The clock end of the first trigger is used to receive the first clock signal, the input end of the first trigger is used to receive the write command signal, and the first output end of the first trigger is used to output the first output signal; wherein, the first output end of the first trigger is used to reflect the value of the input end of the first trigger after being sampled by the first clock signal.

7. The control circuit according to claim 1, wherein: The delay shift circuit includes M delay units, where M is an integer greater than 0, wherein: The delay shift circuit is used to receive the first control signal, determine a target number of delay units among the M delay units according to the first control signal, and sample and shift the first output signal through the target number of delay units to obtain the second output signal.

8. The control circuit according to claim 7, characterized in that: The first control signal includes M sub-control signals, the j-th delay unit has a corresponding relationship with the j-th sub-control signal, and the j-th delay unit includes a j-th delay sub-unit and a j-th selection unit, wherein: When M is equal to 1, the clock terminal of the first delay subunit is used to receive the first clock signal, the input terminal of the first delay subunit is used to receive the first output signal, the first input terminal of the first selection unit is used to receive the first output signal, the first output terminal of the first delay subunit is connected to the second input terminal of the first selection unit, the control terminal of the first selection unit is used to receive the first sub-control signal, and the output terminal of the first selection unit is used to output the second output signal; When M is greater than 1 and j is greater than 1, the clock end of the jth delay subunit is used to receive the first clock signal, the input end of the jth delay subunit is used to receive the j-1th selection result signal, the first output end of the jth delay subunit is connected to the second input end of the jth selection unit, and is used to output the jth delay result signal; the first input end of the jth selection unit is used to receive the first output signal, the control end of the jth selection unit is used to receive the jth sub-control signal, and the output end of the jth selection unit is used to output the jth selection result signal; Wherein, j is an integer greater than 1 and less than or equal to M; and when j is equal to 1, the input end of the first delay subunit is used to receive the first output signal, and the output end of the first selection unit is used to output the first selection result signal; when j is equal to M, the output end of the Mth selection unit is used to output the second output signal.

9. The control circuit according to claim 8, characterized in that: the j-th delay subunit is configured to receive the j-1-th selection result signal and the first clock signal, and perform sampling processing on the j-1-th selection result signal according to the first clock signal to obtain the j-th delayed result signal; The j-th selection unit is configured to receive the j-th sub-control signal, and select one between the j-th delayed result signal and the first output signal according to the j-th sub-control signal to output as the j-th selection result signal.

10. The control circuit according to claim 9, characterized in that: The j-th delay sub-unit includes a second trigger, wherein: The clock end of the second trigger is used to receive the first clock signal, the input end of the second trigger is used to receive the j-1th selection result signal, and the first output end of the second trigger is used to output the jth delayed result signal; wherein, the first output end of the second trigger is used to reflect the value of the input end of the second trigger after being sampled by the first clock signal.

11. The control circuit according to claim 1, wherein: The shift selection circuit includes a shift subcircuit, an inversion subcircuit and a selection subcircuit, wherein: the shift subcircuit is configured to receive the second output signal, the first clock signal, and the second clock signal, sample the second output signal according to the first clock signal to obtain the first intermediate signal; and sample the second output signal according to the second clock signal to obtain the second intermediate signal; The inverting sub-circuit is configured to receive the first output signal and perform inversion processing on the first output signal to obtain a third intermediate signal; The selection subcircuit is configured to receive the first intermediate signal, the second intermediate signal, the third intermediate signal, and the second control signal, select the first intermediate signal, the second intermediate signal, and the third intermediate signal according to the second control signal, and output the third output signal.

12. The control circuit according to claim 11, characterized in that: The shift subcircuit includes a third trigger and a fourth trigger, wherein: The input terminals of the third flip-flop and the fourth flip-flop are both used to receive the second output signal, the clock terminal of the third flip-flop is used to receive the first clock signal, and the first output terminal of the third flip-flop is used to output the first intermediate signal; the clock terminal of the fourth flip-flop is used to receive the second clock signal, and the first output terminal of the fourth flip-flop is used to output the second intermediate signal; Among them, the first output end of the third trigger is used to reflect the value of the input end of the third trigger after being sampled by the first clock signal; the first output end of the fourth trigger is used to reflect the value of the input end of the fourth trigger after being sampled by the second clock signal.

13. The control circuit according to claim 11, wherein: The second control signal includes a first sub-control signal and a second sub-control signal, and the selection sub-circuit includes a first selection sub-circuit and a second selection sub-circuit, wherein: the first selection sub-circuit is configured to receive the first intermediate signal and the second intermediate signal, and select one of the first intermediate signal and the second intermediate signal according to the first sub-control signal to output as a fourth intermediate signal; the second selection sub-circuit is configured to receive the third intermediate signal and the fourth intermediate signal, and select one of the third intermediate signal and the fourth intermediate signal according to the second sub-control signal to output as the third output signal; The first input terminal of the first selection subcircuit is used to receive the first intermediate signal, the second input terminal of the first selection subcircuit is used to receive the second intermediate signal, the control terminal of the first selection subcircuit is used to receive the first sub-control signal, and the output terminal of the first selection subcircuit is connected to the second input terminal of the second selection subcircuit for outputting the fourth intermediate signal; the first input terminal of the second selection subcircuit is used to receive the third intermediate signal, the control terminal of the second selection subcircuit is used to receive the second sub-control signal, and the output terminal of the second selection subcircuit is used to output the third output signal.

14. The control circuit according to claim 1, wherein: The command adjustment circuit includes an SR latch, a first NOT gate and a first NOR gate, and the SR latch includes a first NAND gate and a second NAND gate, wherein: The input end of the first NOT gate is connected to the first input end of the first NAND gate for receiving the third output signal; the output end of the first NOT gate is used to output the first command signal; The second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminal of the second NAND gate is used to receive the first output signal, and the output terminal of the second NAND gate serves as the output terminal of the SR latch to output a second command signal; The first input terminal of the first NOR gate is connected to the output terminal of the second NAND gate for receiving the second command signal; the second input terminal of the first NOR gate is connected to the output terminal of the first NOT gate for receiving the first command signal; the output terminal of the first NOR gate is used to output the target command signal; The first command signal is delayed by A times the preset clock period compared to the second command signal.

15. A memory, characterized in that: The memory includes the control circuit according to any one of claims 1 to 14.

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