Timing measurement methods

Abstract

The embodiment of the present disclosure provides a timing measurement method. The timing measurement method is used to measure the timing between a target signal to be tested and a target reference signal of the target signal to be tested on an input buffer of a system to be tested. The method includes: obtaining the on-chip delay of the target signal to be tested and the target reference signal in the system to be tested respectively; obtaining the package delay of the target signal to be tested and the target reference signal on the system to be tested respectively; generating a filter characteristic curve based on the on-chip delay and the package delay, so as to measure the timing between the target signal to be tested and the target reference signal according to the filter characteristic curve. The measurement method of the embodiment of the present disclosure can improve the accuracy of the timing between the target signal to be tested and its target reference signal, and improve the accuracy of problem analysis.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor testing technology, and in particular to a timing measurement method. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. When reading and writing data to DRAM, a control chip is required to send and receive control signals.

[0003] However, with the continuous development of semiconductor technology, delay circuits are now added to DRAM and control chips, which can add different delays to the input or output signal and the reference signal of the signal. At the same time, due to the delays in the packaging of DRAM and control chips, the timing relationship between the signal and the reference signal cannot be directly and accurately measured by the oscilloscope due to these delays, resulting in low analysis accuracy.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to a person of ordinary skill in the art. Summary of the Invention

[0005] The embodiments of the present disclosure provide a method for timing measurement, which can improve the accuracy of the timing between a target signal to be measured and its target reference signal, and improve the accuracy of problem analysis.

[0006] An embodiment of the present disclosure provides a timing measurement method for measuring the timing between a target signal to be tested and a target reference signal of the target signal to be tested on an input buffer of a system to be tested. The method includes: obtaining on-chip delays of the target signal to be tested and the target reference signal in the system to be tested, respectively; obtaining package delays of the target signal to be tested and the target reference signal in the system to be tested, respectively; and generating a filter characteristic curve based on the on-chip delays and the package delays to measure the timing between the target signal to be tested and the target reference signal based on the filter characteristic curve.

[0007] In some embodiments, the system under test also includes a memory interface; wherein, respectively obtaining the on-chip delays of the target signal under test and the target reference signal in the system under test includes: obtaining a training log of the memory interface on the system under test; respectively obtaining the on-chip delays of the target signal under test and the target reference signal from the training log; wherein, when the target signal under test and the target reference signal are respectively connected to the first probe and the second probe of the oscilloscope, the system under test is turned on and the training log of the memory interface is saved.

[0008] In some embodiments, obtaining the on-chip delays of the target test signal and the target reference signal respectively from the training log includes: obtaining a test delay value of the target test signal and a reference delay value of the target reference signal from the training log; and obtaining the on-chip delay based on the test delay value and the reference delay value.

[0009] In some embodiments, obtaining the on-chip delay according to the delay value to be measured and the reference delay value includes: obtaining the width of the target signal to be measured and the number of steps of each width; obtaining the on-chip delay of the target signal to be measured according to the width, the number of steps of the width, and the delay value to be measured; obtaining the on-chip delay of the target reference signal according to the width, the number of steps of the width, and the reference delay value.

[0010] In some embodiments, obtaining the width of the target signal to be tested includes: obtaining an operating rate of the memory interface; and obtaining the width of the target signal to be tested according to the operating rate.

[0011] In some embodiments, generating a filter characteristic curve based on the on-chip delay and the package delay includes: obtaining an on-chip delay difference between the target signal to be tested and the target reference signal based on the on-chip delay of the target signal to be tested and the on-chip delay of the target reference signal; obtaining a package delay difference between the target signal to be tested and the target reference signal based on the package delay of the target signal to be tested and the package delay of the target reference signal; and obtaining the filter characteristic curve based on the on-chip delay difference and the package delay difference.

[0012] In some embodiments, the amplitude-frequency response of the filter characteristic curve is a preset constant, and the phase difference of the filter characteristic curve is the sum of the on-chip delay difference and the package delay difference.

[0013] In some embodiments, before respectively obtaining the on-chip delay of the target signal to be tested and the target reference signal in the system to be tested, it also includes: judging whether the measurement results obtained by an oscilloscope on the target signal to be tested and the target reference signal comply with a preset timing; if so, using the measurement results as the timing between the target signal to be tested and the target reference signal; if not, obtaining the on-chip delay or the package delay of the target signal to be tested and the target reference signal respectively.

[0014] In some embodiments, the target signal to be tested and the target reference signal are used to write data into the dynamic random access memory; or, the target signal to be tested and the target reference signal are used to read data from the dynamic random access memory.

[0015] In some embodiments, the target signal to be tested is DQ, and the target reference signal is DQS; or, the target signal to be tested is CA, and the target reference signal is CLK.

[0016] As can be seen from the above technical solutions, the timing measurement method of the embodiment of the present disclosure has at least one of the following advantages and positive effects:

[0017] In the embodiment of the present disclosure, by respectively obtaining the on-chip delay and package delay of the target signal to be measured and the target reference signal in the system to be measured, and then obtaining a filter characteristic curve through the on-chip delay and package delay, the oscilloscope can accurately measure the timing between the target signal to be measured and the target reference signal according to the filter characteristic curve, so that the timing relationship between the target signal to be measured and the target reference signal is more consistent with the operating conditions of the actual circuit, meets the requirements of setup time and hold time, and improves the accuracy of problem analysis. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0019] Figure 1 A flowchart of a timing measurement method according to some embodiments of the present disclosure;

[0020] Figure 2 A schematic diagram of the timing between a target signal under test and a target reference signal measured by an oscilloscope when on-chip delay and package delay are not obtained according to some embodiments of the present disclosure;

[0021] Figure 3 A block diagram of a system to be tested according to some embodiments of the present disclosure;

[0022] Figure 4 A schematic diagram of a filter characteristic curve according to some embodiments of the present disclosure;

[0023] Figure 5 A schematic diagram of the timing between a target signal to be measured and a target reference signal measured by an oscilloscope when obtaining on-chip delay and package delay according to some embodiments of the present disclosure;

[0024] Figure 6 Another flow chart of a timing measurement method according to some embodiments of the present disclosure;

[0025] Figure 7 A block diagram of a measurement system illustrating some embodiments of the present disclosure;

[0026] Figure 8 is a structural diagram of a computer device shown in some embodiments of the present disclosure;

[0027] Figure 9 A schematic diagram of a computer-readable storage medium is shown for disclosing some embodiments.

[0028] Description of reference numerals:

[0029] 300, system under test; 301, central processing unit; 3011, first input buffer; 3012, memory interface; 302, dynamic random access memory; 3021, second input buffer; 700, measurement system; 701, oscilloscope; 7011, first probe; 7012, second probe; 702, timing measurement device. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus detailed descriptions thereof will be omitted.

[0031] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure and in which different exemplary structures that can implement various aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0032] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0033] In addition, in the description of the present disclosure, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0034] With the continuous development of semiconductor technology, delay circuits are now added to DRAM and control chips. These circuits can add different delays to the input or output signal and the reference signal of the signal. In addition, since both DRAM and control chips are packaged, there are also delays in the package. Due to these delays, the timing relationship between the signal and the reference signal cannot be directly and accurately measured by an oscilloscope, resulting in low analysis accuracy.

[0035] For example, when the signal is a DQ (data) signal, its reference signal is the DQS (Data Strobe, source synchronous clock) signal. When reading data, the timing relationship between DQ and DQS must still meet the basic setup time and hold time. Therefore, the expected waveform timing relationship is that the rising and falling edges of DQS are in the middle of the DQ signal eye diagram. When writing data, the expected waveform timing relationship is also that the rising and falling edges of DQS are in the middle of the DQ eye diagram.

[0036] Due to the different delays added to the input and output DQ / DQS, plus the package delay, the relative timing relationship of DQ / DQS finally measured on the oscilloscope is not accurate, that is, it does not achieve the expected timing relationship. Figure 2As shown in the figure, when writing data, the rising edge of DQS measured by the oscilloscope is not located in the middle of the DQ eye diagram, but is offset. Figure 2 The setup time margin of the DQ signal is very large compared to the DQS signal, which cannot meet the hold time requirement.

[0037] Based on this, Figure 1 As shown, the embodiment of the present disclosure provides a timing measurement method. Figure 1 The method provided in the embodiment can be executed by any electronic device, or by a controller included in the electronic device. The electronic device may be, for example, ATE (Automatic Test Equipment), but the present disclosure is not limited thereto. The method is used to measure the timing between a target test signal at an input buffer of a system under test 300 and a target reference signal of the target test signal. The method may include the following steps S110 to S130.

[0038] S110 : Obtaining on-chip delays of the target signal under test and the target reference signal within the system under test 300 .

[0039] In some embodiments, the target signal to be measured may be a DQ signal. DQ is a data signal. The target reference signal for DQ is DQS. DQS is used to distinguish each data transmission cycle, facilitating accurate data reception by the receiver. DQ uses DQS as a reference.

[0040] In other embodiments, the target signal to be tested may be a CA (Command Address) signal, and its target reference signal is a CLK (Clock) signal. CLK has a fixed period and is independent of operation, and CA uses CLK as a reference.

[0041] like Figure 3 As shown, the system under test 300 may include a control chip, such as a CPU (Central Processing Unit) 301, and a memory chip, such as a DRAM (Dynamic Random Access Memory) 302. DRAM may include different types, such as DDR (Double Data Rate), such as DDR3, DDR4, and DDR5; and LPDDR (Low Power Double Data Rate SDRAM), such as LPDDR4 and LPDDR5.

[0042] In some embodiments, as Figure 3As shown, the system under test 300 includes a central processing unit 301 and a dynamic random access memory 302; wherein, the on-chip delay is the delay within the central processing unit 301 or the dynamic random access memory 302; the package delay is the delay caused by the packaging of the central processing unit 301 or the dynamic random access memory 302.

[0043] In-chip delay can be understood as a delay circuit within the chip that adds delay to different signals, i.e., different signals have delays. In other words, the in-chip delay refers to the signal delay caused by the in-chip delay circuit. The in-chip delay can be generated in the control chip or memory chip of the system under test 300.

[0044] In some embodiments, as Figure 3 As shown, the system under test 300 further includes a memory interface 3012. Wherein, obtaining the on-chip delay of the target signal under test and the target reference signal in the system under test 300 in S110 may include: obtaining a training log of the memory interface 3012 on the system under test 300. Obtaining the on-chip delay of the target signal under test and the target reference signal from the training log. Wherein, as Figure 7 As shown, when the target test signal and the target reference signal are connected to the first probe 7011 and the second probe 7012 of the oscilloscope 701 respectively, the system under test 300 is turned on and the training log of the memory interface 3012 is saved.

[0045] Specifically, if Figure 3 As shown, the memory interface 3012 can be an interface of DRAM, DDR or LPDDR. The memory interface 3012 is set in a control chip, such as a CPU, to facilitate signal transmission with a memory chip (such as DDR).

[0046] like Figure 7 As shown, the oscilloscope 701 has a first probe 7011 and a second probe 7012 for connecting different signals. The target test signal is connected to the first probe 7011 of the oscilloscope 701, and the target reference signal is connected to the second probe 7012 of the oscilloscope 701. The system to be tested 300 is turned on, and the memory interface 3012 of the system to be tested 300 is trained to obtain a training log, record and save the training log. The on-chip delay of the target signal to be tested and the target reference signal is recorded in the training log. Therefore, through the training log, the on-chip delay of the two signals can be accurately recorded, so that the on-chip delay that cannot be obtained by measurement can be displayed. Then the on-chip delay of the target signal to be tested and the target reference signal are obtained from the training log respectively.

[0047] In some embodiments, obtaining the on-chip delays of the target test signal and the target reference signal respectively from the training log includes: obtaining a test delay value of the target test signal and a reference delay value of the target reference signal from the training log; and obtaining the on-chip delay based on the test delay value and the reference delay value.

[0048] For example, if the target test signal is a DQ signal and the target reference signal is a DQS signal, the on-chip delay value of the DQ signal (i.e., the test delay value) is obtained from the training log, and the on-chip delay value of the DQS signal (i.e., the reference delay value) is also obtained. For example, if the DQ delay is 24 steps and the DQS delay is 14 steps, then the DQ test delay value is 24 and the DQS reference delay value is 14. These two delay values ​​can be used to obtain the on-chip delay.

[0049] In some embodiments, the on-chip delay is obtained according to the delay value to be measured and the reference delay value, including: obtaining the width of the target signal to be measured and the number of steps of each width; obtaining the on-chip delay of the target signal to be measured according to the width, the number of steps of the width and the delay value to be measured, and obtaining the on-chip delay of the target reference signal according to the width, the number of steps of the width and the reference delay value.

[0050] Specifically, the width of the target signal to be measured can also be referred to as a unit interval (UI). The width UI can be obtained by the operating rate of the memory interface 3012. Each UI width includes different step sizes. For example, the width of the DQ signal is 64 steps, that is, the number of width steps is 64. The UI can be 234.4 ps. The on-chip delay can be obtained by the above data. The on-chip delay can be obtained by the following calculation relationship (1).

[0051] T=D*1 / S*U (1)

[0052] Wherein, in the above formula (1), T represents the on-chip delay; D represents the delay value, that is, the delay value to be measured or the reference delay value; S represents the number of steps of the width of the target signal to be measured; and U represents the width of the target signal to be measured.

[0053] Taking the above values ​​as an example, the on-chip delay of the target signal under test is: 24*(1 / 64)*234.4=87.9 ps. The on-chip delay of the target reference signal is: 14*(1 / 64)*234.4=51.28 ps.

[0054] Of course, there is not only one set of values ​​mentioned above. When the control chip is different, the above values ​​can vary. In one embodiment, the delay of DQ is 32 steps, and the delay of DQS is 21 steps. Then the measured delay value of DQ is 32, and the reference delay value of DQS is 21. The width of the DQ signal is 128 steps, and the UI can be 312.5ps. Through calculation, it can be concluded that the on-chip delay of the target signal to be measured is: 32*(1 / 128)*312.5=78.13ps. The on-chip delay of the target reference signal is: 21*(1 / 128)*312.5=51.27ps. The above values ​​are only for illustration, and there can be other values. The calculation formula is the same, so they will not be repeated here.

[0055] In some embodiments, as Figure 3 As shown, obtaining the width of the target signal to be tested includes: obtaining the operating rate of the memory interface 3012; and obtaining the width of the target signal to be tested according to the operating rate.

[0056] Specifically, the width of the target signal to be measured can be obtained by calculating the following relationship (2).

[0057] U=1 / R (2)

[0058] In the above formula, U represents the width of the target signal to be measured, and R represents the operating rate of the memory interface 3012.

[0059] Specifically, the operating rates of different memory interfaces 3012 are different. For example, if the operating rate of the LPDDR4 interface is 4266Mbps, then according to the above calculation relationship, the width of the target signal to be tested can be obtained as 1 / 4266=234.4ps. For another example, if the operating rate of the DDR4 interface is 3200Mbps, then the width of the target signal to be tested can be obtained as 1 / 3200=312.5ps. Although different interfaces have different operating rates, the algorithm for obtaining the width of the target signal to be tested is the same. The two widths obtained are the widths in the corresponding embodiments above, so through the above calculation, the on-chip delay can be obtained.

[0060] S120: Obtaining the package delays of the target signal under test and the target reference signal on the system under test 300 respectively.

[0061] Specifically, the package delays of the target test signal and the target reference signal can be directly queried from a database, such as a chip data sheet. This query reveals that for the LPDDR4 chip in the above embodiment, the package delay of the target test signal is 22 ps, and the package delay of the target reference signal is 25.67 ps.

[0062] S130: Generate a filter characteristic curve according to the on-chip delay and the package delay, so as to measure the timing between the target signal to be measured and the target reference signal according to the filter characteristic curve.

[0063] In some embodiments, generating a filter characteristic curve based on the on-chip delay and the package delay may include: obtaining the on-chip delay difference between the target signal to be tested and the target reference signal based on the on-chip delay of the target signal to be tested and the on-chip delay of the target reference signal; obtaining the package delay difference between the target signal to be tested and the target reference signal based on the package delay of the target signal to be tested and the package delay of the target reference signal; and obtaining the filter characteristic curve based on the on-chip delay difference and the package delay difference. Figure 4 , shows the filter characteristic curve.

[0064] Specifically, still taking the numerical values ​​in the above example, the on-chip delay of the target test signal is 87.9 ps, and the on-chip delay of the target reference signal is 51.28 ps. Then, the on-chip delay difference between the target test signal and the target reference signal is 87.9 ps-51.28 ps=36.62 ps.

[0065] The package delay of the target signal to be measured is 22 ps, the package delay of the target reference signal is 25.67 ps, and the package delay difference between the target signal to be measured and the target reference signal is 22-25.67=-3.67 ps.

[0066] In some embodiments, the sum of the on-chip delay difference and the package delay difference is obtained, and the sum is used as the phase difference of the filter characteristic curve, that is, 36.62ps-3.67ps=32.96ps. Figure 4 As shown, the amplitude-frequency response of the generated filter characteristic curve is a preset constant, for example, the preset constant can be 1, that is, Figure 4 The phase difference of the filter characteristic curve is the sum of the on-chip delay difference and the package delay difference, which is 32.96ps. Figure 4 In the figure, the broken line at the bottom represents the phase difference of the filter characteristic curve.

[0067] By obtaining the filter characteristic curve, such as Figure 7 As shown, by adding the characteristic curve to the test probe of the target signal to be measured in the oscilloscope 701 software, the timing of the target signal to be measured and the target reference signal can be directly displayed in the oscilloscope 701, as shown in FIG. Figure 5As shown in the figure, the rising and falling edges of the DQS signal are located in the middle of the DQ signal's eye diagram, ensuring that the timing relationship between the target test signal and the target reference signal meets the setup and hold time requirements. In other words, when writing data, the rising and falling edges of the DQS signal are located in the middle of the DQ signal's eye diagram, making the timing relationship between the target test signal and the target reference signal more consistent with actual circuit operation, thereby improving the accuracy of problem analysis.

[0068] In some embodiments, the filter characteristic curve may be formed by simulation tools such as HSpice, LTSpice, and Matlab. Those skilled in the art may select one based on actual conditions, and no special limitation is made here.

[0069] In some embodiments, as Figure 6 As shown, before obtaining the intra-chip delays of the target signal under test and the target reference signal in the system under test 300 , the following steps S610 to S630 are also included.

[0070] S610: After measuring the target signal to be measured and the target reference signal using the oscilloscope 701 , determine whether the measurement results conform to a preset timing sequence; if so, proceed to S620 ; if not, proceed to S630 .

[0071] S620: Using the measurement result as the timing between the target signal to be measured and the target reference signal.

[0072] 630 : Obtain the on-chip delay of the target signal under test and the target reference signal in the system under test 300 or obtain the package delay of the target signal under test and the target reference signal on the system under test 300 .

[0073] That is to say, before obtaining the measured delay value of the target measured signal and the reference delay value of the target reference signal from the training log, the target measured signal and the target reference signal can be connected to the oscilloscope 701, and the timing of the target measured signal and the target reference signal can be measured using the oscilloscope 701. If the measurement result shows that it meets the preset timing, it means that the timing relationship between the target measured signal and the target reference signal meets the requirements of the setup time and hold time, and there is no need to obtain the on-chip delay from the training log. If the measurement result shows that it does not meet the preset timing, such as Figure 2 As shown, the rising edge of DQS measured by oscilloscope 701 is not located in the middle of the DQ eye diagram, but is offset. The setup time margin of the DQ signal relative to the DQS signal in the figure is very large and cannot meet the hold time requirement. At this time, it is necessary to obtain the on-chip delay from the training log and then continue to perform the following steps until the filter characteristic curve is obtained.

[0074] The preset timing can be understood as follows: taking DQ and DQS when reading data as an example, the preset timing can be understood as the rising and falling edges of DQS being located in the middle of the DQ eye diagram. Taking DQ and DQS when writing data as an example, the preset timing can be understood as the rising and falling edges of DQS also being located in the middle of the DQ eye diagram. That is, under this preset timing, the timing relationship between the target test signal and the target reference signal meets the setup time and hold time requirements.

[0075] After obtaining the filter characteristic curve, add the filter characteristic curve to the test probe of the target test signal of the oscilloscope 701 software to measure the timing between the target test signal and the target reference signal. Figure 5 As shown in the figure, by adding the filter characteristic curve, it can be seen that when writing data, the rising and falling edges of the DQS signal are located in the middle of the DQ signal's eye diagram. In other words, the timing of the DQ and DQS signals meets the setup and hold time requirements. Therefore, on-chip delay and package delay can be characterized by external signals, making the timing relationship between the target test signal and the target reference signal more consistent with the actual circuit operation, improving the accuracy of problem analysis.

[0076] In some embodiments, as Figure 3 As shown, the input buffer is located in the central processing unit 301 (CPU) or the dynamic random access memory 302 (DRAM). Specifically, the location of the input buffer is determined based on the signal transmission and reception of read and write data. When input buffers are required in both the CPU and the DRAM, the minimum number of input buffers is two: a first input buffer 3011 and a second input buffer. In one embodiment, the first input buffer 3011 is located in the CPU, and the second input buffer is located in the DRAM.

[0077] In some embodiments, the target signal to be tested and the target reference signal are used to write data into the dynamic random access memory 302 ; or, the target signal to be tested and the target reference signal are used to read data from the dynamic random access memory 302 .

[0078] Regardless of reading data or writing data, the embodiments of the present disclosure can improve the accuracy of problem analysis.

[0079] To sum up, in the embodiments of the present disclosure, the on-chip delay and package delay of the target signal to be tested and the target reference signal in the system to be tested 300 can be accurately obtained respectively, that is, the on-chip delay and package delay can be characterized by external signals, and the filter characteristic curve is obtained through the on-chip delay and package delay. According to the filter characteristic curve, the oscilloscope 701 can accurately measure the timing between the target signal to be tested and the target reference signal, so that the timing relationship between the target signal to be tested and the target reference signal is more consistent with the operating conditions of the actual circuit, meets the requirements of setup time and hold time, and improves the accuracy of problem analysis.

[0080] like Figure 7 As shown, the embodiment of the present disclosure further provides a measurement system 700 , including an oscilloscope 701 and a timing measurement device 702 .

[0081] The oscilloscope 701 includes a first probe 7011 and a second probe 7012 . The first probe 7011 is used to connect to the target test signal on the input buffer of the system under test 300 . The second probe 7012 is used to connect to the target reference signal of the target test signal on the input buffer.

[0082] The timing measurement device 702 is used to respectively obtain the on-chip delay of the target signal to be tested and the target reference signal in the system to be tested 300, and respectively obtain the package delay of the target signal to be tested and the target reference signal on the system to be tested 300, and generate a filter characteristic curve based on the on-chip delay and the package delay, and add the filter characteristic curve to the first probe 7011.

[0083] The oscilloscope 701 is further configured to measure the timing between the target signal to be measured and the target reference signal through the first probe 7011 and the second probe 7012 .

[0084] In some embodiments, as Figure 3 and Figure 7 As shown, the timing measurement device 702 is further configured to obtain a training log of the memory interface 3012 on the system under test 300; and to obtain the intra-chip delays of the target test signal and the target reference signal from the training log. When the target test signal and the target reference signal are connected to the first probe 7011 and the second probe 7012 of the oscilloscope 701, respectively, the system under test 300 is turned on and the training log of the memory interface 3012 is saved.

[0085] In some embodiments, the timing measurement device 702 is further configured to obtain a test delay value of a target test signal and a reference delay value of a target reference signal from a training log; and obtain an intra-chip delay based on the test delay value and the reference delay value.

[0086] In some embodiments, the timing measurement device 702 is also used to obtain the width of the target signal to be tested and the number of steps of each width; obtain the on-chip delay of the target signal to be tested based on the width, the number of steps of the width and the delay value to be tested; and obtain the on-chip delay of the target reference signal based on the width, the number of steps of the width, and the reference delay value.

[0087] In some embodiments, as Figure 3 and Figure 7 As shown, the timing measurement device 702 is further used to obtain the operating rate of the memory interface 3012; and obtain the width of the target signal to be measured according to the operating rate.

[0088] In some embodiments, the timing measurement device 702 is further used to obtain an on-chip delay difference between the target signal to be measured and the target reference signal based on the on-chip delay of the target signal to be measured and the on-chip delay of the target reference signal; obtain an encapsulation delay difference between the target signal to be measured and the target reference signal based on the encapsulation delay of the target signal to be measured and the encapsulation delay of the target reference signal; and obtain a filter characteristic curve based on the on-chip delay difference and the encapsulation delay difference.

[0089] In some embodiments, the oscilloscope 701 is further configured to measure the target test signal and the target reference signal and obtain measurement results. The timing measurement device 702 is further configured to determine whether the measurement results conform to a preset timing sequence. If so, the measurement results are used as the timing sequence between the target test signal and the target reference signal. If not, the on-chip delay of the target test signal and the target reference signal within the system under test 300 is obtained.

[0090] The present disclosure also provides a computer device. Figure 8 As shown, the computer device in the embodiment of the present disclosure may include one or more processors 801 and memory 802. The processor 801 and the memory 802, as shown in FIG. Figure 8 As shown, the processor 801 and memory 802 are connected via a bus 803. In an exemplary embodiment, the computer device may further include an input / output interface 804, which is connected to the processor 801 and memory 802 via the bus 803. The memory 802 is used to store computer programs, which include program instructions. The input / output interface 804 is used to receive and output data, such as for data exchange between a host computer and the computer device, or for data exchange between virtual machines in the host computer. The processor 801 is used to execute the program instructions stored in the memory 802.

[0091] In which, the processor 801 can perform the following operations: respectively obtain the on-chip delay of the target signal to be tested and the target reference signal in the system to be tested 300; respectively obtain the package delay of the target signal to be tested and the target reference signal on the system to be tested 300; generate a filter characteristic curve according to the on-chip delay and the package delay, so as to measure the timing between the target signal to be tested and the target reference signal according to the filter characteristic curve.

[0092] In some feasible implementations, the processor 801 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc.

[0093] The memory 802 may include a read-only memory and a random access memory, and provides instructions and data to the processor 801 and the input / output interface 804. A portion of the memory 802 may also include a non-volatile random access memory. For example, the memory 802 may also store device type information.

[0094] In a specific implementation, the computer device can execute the implementation methods provided by the various steps in any of the above method embodiments through its built-in functional modules. For details, please refer to the implementation methods provided by the various steps in the figure shown in the above method embodiments, which will not be repeated here.

[0095] The embodiment of the present disclosure provides a computer device, including a processor 801, an input / output interface 804, and a memory 802. The processor 801 obtains a computer program in the memory 802 to execute each step of the method shown in any of the above embodiments.

[0096] The present disclosure also provides a computer-readable storage medium 900. Figure 9 As shown, the computer-readable storage medium 900 stores a computer program, which is suitable for the processor 801 to load and execute the timing measurement method provided by each step in any of the above embodiments. For details, please refer to the implementation method provided by each step in any of the above embodiments, which will not be repeated here.

[0097] In addition, the description of the beneficial effects of using the same method will not be repeated. For technical details not disclosed in the embodiment of the computer-readable storage medium 900 involved in the present disclosure, please refer to the description of the method embodiment of the present disclosure. As an example, the computer program can be deployed to be executed on a computer device, or on multiple computer devices located in one location, or on multiple computer devices distributed in multiple locations and interconnected by a communication network.

[0098] The computer-readable storage medium 900 can be the measurement system 700 provided in any of the aforementioned embodiments or the internal storage unit of the computer device, such as the hard disk or memory of the computer device. The computer-readable storage medium 900 can also be an external storage device of the computer device, such as a plug-in hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the computer device. Further, the computer-readable storage medium 900 can also include both the internal storage unit of the computer device and an external storage device. The computer-readable storage medium 900 is used to store the computer program and other programs and data required by the computer device. The computer-readable storage medium 900 can also be used to temporarily store data that has been output or is about to be output.

[0099] The embodiments of the present disclosure also provide a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium 900. A processor of a computer device reads the computer instructions from the computer-readable storage medium 900, and the processor executes the computer instructions, so that the computer device performs the method provided in any of the optional embodiments described above.

[0100] In summary, the measurement system 700, computer device, and computer-readable storage medium of the embodiment of the present disclosure can accurately obtain the on-chip delay and package delay of the target signal to be measured and the target reference signal in the system to be measured 300, that is, the on-chip delay and package delay can be characterized by external signals, and a filter characteristic curve is obtained through the on-chip delay and package delay. According to the filter characteristic curve, the oscilloscope 701 can accurately measure the timing between the target signal to be measured and the target reference signal, so that the timing relationship between the target signal to be measured and the target reference signal is more consistent with the operating conditions of the actual circuit, meets the requirements of setup time and hold time, and improves the accuracy of problem analysis.

[0101] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and executed in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments of this specification illustrate the best mode known for implementing the present disclosure and will enable those skilled in the art to utilize the present disclosure.

Claims

1. A timing measurement method, characterized in that: The method is used to measure the timing between a target signal to be tested and a target reference signal of the target signal to be tested on an input buffer of a system to be tested, and the method comprises: respectively obtaining on-chip delays of the target signal under test and the target reference signal within the system under test; respectively obtaining the package delays of the target signal under test and the target reference signal on the system under test; generating a filter characteristic curve according to the on-chip delay and the package delay, so as to measure the timing between the target signal to be measured and the target reference signal according to the filter characteristic curve; Generating a filter characteristic curve according to the on-chip delay and the package delay, comprising: Obtaining an intra-chip delay difference between the target signal to be measured and the target reference signal according to the intra-chip delay of the target signal to be measured and the intra-chip delay of the target reference signal; Obtaining a package delay difference between the target signal to be measured and the target reference signal according to the package delay of the target signal to be measured and the package delay of the target reference signal; The filter characteristic curve is obtained according to the on-chip delay difference and the package delay difference.

2. The method according to claim 1, characterized in that The system under test further includes a memory interface; wherein obtaining the on-chip delays of the target signal under test and the target reference signal within the system under test respectively comprises: Obtaining a training log of the memory interface on the system under test; Obtaining on-chip delays of the target signal to be tested and the target reference signal respectively from the training log; When the target signal to be tested and the target reference signal are connected to a first probe and a second probe of an oscilloscope respectively, the system to be tested is turned on and a training log of the memory interface is saved.

3. The method according to claim 2, characterized in that Obtaining the on-chip delays of the target signal to be tested and the target reference signal from the training log respectively, including: Obtaining a test delay value of the target test signal and a reference delay value of the target reference signal from the training log; The on-chip delay is obtained according to the delay value to be measured and the reference delay value.

4. The method according to claim 3, characterized in that Obtaining the on-chip delay according to the delay value to be measured and the reference delay value, including: Obtaining the width of the target signal to be measured and the number of steps of each width; Obtain the on-chip delay of the target signal to be measured according to the width, the number of steps of the width, and the delay value to be measured; An intra-chip delay of the target reference signal is obtained according to the width, the number of steps of the width, and the reference delay value.

5. The method according to claim 4, characterized in that Obtaining the width of the target signal to be measured includes: Obtaining an operating rate of the memory interface; According to the operating rate, the width of the target signal to be measured is obtained.

6. The method according to claim 1, characterized in that The amplitude-frequency response of the filter characteristic curve is a preset constant, and the phase difference of the filter characteristic curve is the sum of the on-chip delay difference and the package delay difference.

7. The method according to any one of claims 1 to 5, characterized in that Before respectively obtaining the on-chip delay of the target signal to be tested and the target reference signal in the system to be tested, the method further includes: Based on the measurement results obtained by the oscilloscope on the target signal to be tested and the target reference signal, it is determined whether the measurement results comply with the preset timing; if so, the measurement results are used as the timing between the target signal to be tested and the target reference signal; if not, the on-chip delay or the package delay of the target signal to be tested and the target reference signal are obtained respectively.

8. The method according to any one of claims 1 to 5, characterized in that The target signal to be tested and the target reference signal are used to write data into a dynamic random access memory; or, The target signal to be tested and the target reference signal are used to read data from the dynamic random access memory.

9. The method according to any one of claims 1 to 5, characterized in that The target signal to be tested is a data signal DQ, and the target reference signal is a source synchronous clock signal DQS; or The target signal to be tested is a command address signal CA, and the target reference signal is a clock signal CLK.

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