Semiconductor structure and method of manufacturing the same

Abstract

The application provides a semiconductor structure and a preparation method thereof, relates to the technical field of semiconductors, and aims to solve the technical problem of large contact resistance between the source / drain and the channel of a transistor. The preparation method is characterized in that: an IGZO layer is formed on part of the main surface of the first sub-source and the first sub-drain, the IGZO layer covers the area between the first sub-source and the first sub-drain, then a gate is formed on the IGZO layer, the first sub-source and the first sub-drain are respectively located on the opposite sides of the gate, and the second sub-source and the second sub-drain are respectively formed on at least part of the main surface of the IGZO layer on the opposite sides of the gate, the second sub-source and the first sub-source are located on the same side and connected with the first sub-source to jointly form a source, and the second sub-drain and the first sub-drain are located on the same side and connected with the first sub-drain to jointly form a drain, so that the contact area of the source and the drain with the IGZO layer is increased, the contact resistance is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Thin Film Transistor (TFT) is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) manufactured using thin film technology.

[0003] In the related technology, the semiconductor structure includes a substrate and a transistor located on the substrate. The transistor includes a source, a drain and a gate. The gate is located on the substrate. A channel is arranged below the gate. The channel material is usually made of semiconductor material. A gate oxide layer is arranged between the gate and the channel. The source and drain are respectively located on both sides of the gate and are in ohmic contact with the channel. The contact resistance of the source and drain in ohmic contact with the channel will have a great impact on the performance of the transistor and the entire semiconductor device.

[0004] However, with the continuous development of semiconductor technology, the size of semiconductor devices continues to shrink, and the contact resistance between the source / drain and the channel of the transistor is getting larger and larger, resulting in the technical problem of poor performance of the semiconductor device. Summary of the Invention

[0005] In view of the above problems, embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can reduce the contact resistance between the source / drain and the channel of a transistor, thereby improving the performance of the semiconductor device.

[0006] In order to achieve the above objectives, the embodiments of the present application provide the following technical solutions:

[0007] A first aspect of an embodiment of the present application provides a method for preparing a semiconductor structure, comprising:

[0008] Providing a substrate, on which a first sub-source electrode and a first sub-drain electrode spaced apart are formed;

[0009] forming an IGZO layer on a portion of the main surface of the first sub-source electrode and the first sub-drain electrode, wherein the IGZO layer covers a region between the first sub-source electrode and the first sub-drain electrode;

[0010] forming a gate above the IGZO layer, wherein the first sub-source electrode and the first sub-drain electrode are respectively located on opposite sides of the gate;

[0011] A second sub-source electrode and a second sub-drain electrode are respectively formed on at least part of the main surface of the IGZO layer on opposite sides of the gate, wherein the second sub-source electrode and the first sub-source electrode are located on the same side and connected to the first sub-source electrode to jointly form a source electrode; and the second sub-drain electrode and the first sub-drain electrode are located on the same side and connected to the first sub-drain electrode to jointly form a drain electrode;

[0012] The source, the drain, the gate and the IGZO layer together form an IGZO transistor.

[0013] In some optional implementations, before forming the IGZO layer on a portion of the surface of the first sub-source electrode and the first sub-drain electrode, the method further includes:

[0014] A first isolation structure is formed between the first sub-source and the first sub-drain, and a main surface of the first isolation structure is flush with a main surface of the first sub-source and a main surface of the first sub-drain, respectively.

[0015] In some optional embodiments, the step of forming an IGZO layer on a portion of the surface of the first sub-source electrode and the first sub-drain electrode, wherein the IGZO layer covers the area between the first sub-source electrode and the first sub-drain electrode, includes:

[0016] forming an IGZO layer on a main surface of the first isolation structure, and on a portion of a main surface of the first sub-source electrode and the first sub-drain electrode;

[0017] The IGZO layer is symmetrically arranged about the central axis of the first isolation structure.

[0018] In some optional embodiments, the step of forming the first sub-source and the first sub-drain spaced apart from each other on the substrate includes:

[0019] forming a dielectric layer on the substrate;

[0020] forming a first electrode layer on the dielectric layer;

[0021] forming a patterned first mask layer on the first electrode layer;

[0022] Using the patterned first mask layer as a mask, a portion of the first electrode layer is removed to form a channel exposing the dielectric layer on the first electrode layer, and the first electrode layer retained on both sides of the channel is formed into a first sub-source and a first sub-drain respectively.

[0023] In some optional embodiments, the step of forming a first isolation structure between the first sub-source and the first sub-drain includes:

[0024] forming an isolation layer in the channel, wherein the isolation layer covers major surfaces of the first sub-source electrode and the first sub-drain electrode;

[0025] The isolation layer on the main surfaces of the first sub-source and the first sub-drain is removed, and the isolation layer in the channel is retained, with the main surface of the retained isolation layer flush with the main surfaces of the first sub-source and the first sub-drain.

[0026] In some optional embodiments, the step of forming a second sub-source electrode and a second sub-drain electrode on at least a portion of the main surface of the IGZO layer on opposite sides of the gate includes:

[0027] forming a second electrode layer on a main surface of the gate, a main surface of the exposed IGZO layer, and main surfaces of the exposed first sub-source and first sub-drain electrodes;

[0028] The second electrode layer on the main surface of the gate and part of the second electrode layer on both sides of the gate are removed; the main surface of the retained second electrode layer is lower than the main surface of the gate, and the second electrode layer retained on both sides of the gate are respectively formed into a second sub-source and a second sub-drain.

[0029] In some optional implementations, before forming a gate on the IGZO layer, the method further includes:

[0030] forming a gate dielectric layer on the IGZO layer;

[0031] Wherein, the sidewall of the gate dielectric layer is flush with the sidewall of the gate.

[0032] In some optional implementations, after forming a gate on the IGZO layer, the method further includes:

[0033] A gate insulating layer is formed on the sidewalls of the gate electrode and the gate dielectric layer, and the gate insulating layer covers the sidewalls of the gate electrode and the gate dielectric layer.

[0034] A second aspect of an embodiment of the present application provides a semiconductor structure, including:

[0035] substrate;

[0036] An IGZO transistor is provided on the substrate, wherein the IGZO transistor includes a gate, a source, a drain and an IGZO layer;

[0037] The gate is arranged on the substrate, the source and the drain are respectively located on both sides of the gate, and the IGZO layer is located between the substrate and the gate. In the direction perpendicular to the main surface of the substrate, the projection of the IGZO layer overlaps with the projection of the source and the drain respectively, wherein the source at least partially covers the upper and lower surfaces and side walls of the IGZO layer close to the source side, and the drain at least partially covers the upper and lower surfaces and side walls of the IGZO layer close to the drain side.

[0038] In some optional embodiments, the source electrode includes a first sub-source electrode and a second sub-source electrode, the first sub-source electrode is located between the substrate and the IGZO layer, the second sub-source electrode is located above the IGZO layer, and an end of the second sub-source electrode away from the gate is connected to the first sub-source electrode;

[0039] The drain includes a first sub-drain and a second sub-drain, the second sub-drain is located between the substrate and the IGZO layer, the second sub-drain is located above the IGZO layer, and one end of the second sub-drain away from the gate is connected to the first sub-drain.

[0040] In some optional embodiments, a first isolation structure is further arranged between the first sub-source and the first sub-drain, and the main surfaces of the first isolation structure are flush with the main surfaces of the first sub-source and the first sub-drain, respectively. The IGZO layer is located on the main surface of the first isolation structure, and both sides of the IGZO layer extend to the main surfaces of the first sub-source and the first sub-drain, respectively.

[0041] In some optional embodiments, a dielectric layer is further provided between the first sub-source electrode and the first sub-drain electrode and the substrate respectively.

[0042] In some optional embodiments, the IGZO transistor further includes a gate dielectric layer and a gate insulating layer, the gate dielectric layer is disposed between the IGZO layer and the gate, and the gate insulating layer covers the sidewalls of the gate dielectric layer and the gate, respectively.

[0043] In some optional embodiments, the semiconductor structure includes at least two IGZO transistor units disposed on the substrate, and a second isolation structure is disposed between two adjacent IGZO transistor units;

[0044] Each of the IGZO transistor units includes two IGZO transistors, the two IGZO transistors are stacked in a vertical direction, and the two IGZO transistors are signal-connected.

[0045] In some optional embodiments, the semiconductor structure further includes a contact plug; the two IGZO transistors include a first IGZO transistor and a second IGZO transistor, the second IGZO transistor is located above the first IGZO transistor, and the gate of the second IGZO transistor is signal-connected to the source of the first IGZO transistor through the contact plug.

[0046] In some optional embodiments, the second IGZO transistor and the first IGZO transistor are staggered so that the gate of the second IGZO transistor is located directly above the source of the first IGZO transistor connected to its signal.

[0047] In some optional embodiments, the semiconductor structure includes at least two IGZO transistors, at least two IGZO transistors are stacked along the thickness direction of the substrate, and an insulating structure is provided between two adjacent IGZO transistors, and the two adjacent IGZO transistors are insulated and connected by the insulating structure.

[0048] In the preparation method of the semiconductor structure provided in the embodiment of the present application, an IGZO layer is formed on a portion of the main surface of the first sub-source and the first sub-drain, and the IGZO layer covers the area between the first sub-source and the first sub-drain, and then a gate is formed above the IGZO layer, the first sub-source and the first sub-drain are respectively located on opposite sides of the gate, and a second sub-source and a second sub-drain are respectively formed on at least a portion of the main surface of the IGZO layer on opposite sides of the gate, the second sub-source and the first sub-source are located on the same side and are connected to the first sub-source to jointly form a source, and the second sub-drain and the first sub-drain are located on the same side and are connected to the first sub-drain to jointly form a drain. In this way, the contact area between the source and the drain and the IGZO layer, respectively, can be increased, thereby reducing the contact resistance between the source and the drain and the IGZO layer, respectively, and thereby improving the performance of the semiconductor device.

[0049] The semiconductor structure provided in the embodiment of the present application has the same beneficial effects as the above-mentioned embodiment, which will not be described in detail here.

[0050] In addition to the technical problems solved by the embodiments of the present application, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that can be solved by the semiconductor structure and the preparation method thereof provided by the embodiments of the present application, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0053] Figure 2 A schematic cross-sectional view of a substrate provided in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0054] Figure 3 A cross-sectional schematic diagram of forming a dielectric layer and a first electrode layer on a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0055] Figure 4 A schematic cross-sectional view of forming a first sub-source electrode and a first sub-drain electrode in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0056] Figure 5 A cross-sectional schematic diagram of forming an isolation layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0057] Figure 6 A schematic cross-sectional view of forming a first isolation structure in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0058] Figure 7 A cross-sectional schematic diagram of forming an IGZO layer on a first isolation structure in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0059] Figure 8 A schematic cross-sectional view of forming a gate dielectric layer and a gate on an IGZO layer in a method for preparing a semiconductor structure provided in an embodiment of the present application;

[0060] Figure 9 A cross-sectional schematic diagram of forming a gate insulating layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0061] Figure 10 A schematic cross-sectional view of forming a second electrode layer in the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0062] Figure 11 A schematic cross-sectional view of an IGZO transistor formed by the method for preparing a semiconductor structure provided in an embodiment of the present application;

[0063] Figure 12A schematic diagram of an application scenario of the semiconductor structure provided in an embodiment of the present application;

[0064] Figure 13 A schematic diagram of another application scenario of the semiconductor structure provided in an embodiment of the present application.

[0065] Reference numerals:

[0066] 100- semiconductor structure; 10- substrate;

[0067] 20-IGZO transistor; 20a-first IGZO transistor;

[0068] 20b-second IGZO transistor; 21-source;

[0069] 211 - first sub-source electrode; 212 - second sub-source electrode;

[0070] 213 - first electrode layer; 214 - channel;

[0071] 22-drain; 221-first sub-drain;

[0072] 222-second sub-drain; 223-second electrode layer;

[0073] 23-IGZO layer; 24-gate;

[0074] 25-gate dielectric layer; 26-gate insulating layer;

[0075] 30-isolation layer; 31-first isolation structure;

[0076] 40-dielectric layer; 50-IGZO transistor unit;

[0077] 60-second isolation structure; 70-contact plug;

[0078] 80-Insulation structure. DETAILED DESCRIPTION

[0079] In the related art, a semiconductor structure includes a substrate and a transistor located on the substrate. The transistor includes a source, a drain, and a gate. The gate is located on the substrate. A channel is provided below the gate. The channel material is usually made of a semiconductor material. A gate oxide layer is provided between the gate and the channel. The source and drain are respectively located on both sides of the gate and are in ohmic contact with the channel. That is, the sidewalls of the source and drain facing the channel are respectively in contact with the two ends of the channel to form ohmic contacts. The contact resistance of the source and drain in ohmic contact with the channel will have a significant impact on the performance of the transistor and the entire semiconductor device. For example, the smaller the contact resistance, the better the performance of the semiconductor device. However, with the continuous development of semiconductor technology, the size of semiconductor devices continues to shrink. The smaller the contact area between the source / drain of the transistor and the channel, the greater the contact resistance, which leads to the technical problem of poor performance of the semiconductor device.

[0080] In order to solve the above problems, an embodiment of the present application provides a semiconductor structure and a preparation method thereof. In the preparation method of the semiconductor structure, an IGZO layer is formed on a portion of the main surface of the first sub-source and the first sub-drain, and the IGZO layer covers the area between the first sub-source and the first sub-drain, and then a gate is formed above the IGZO layer. The first sub-source and the first sub-drain are respectively located on opposite sides of the gate, and a second sub-source and a second sub-drain are respectively formed on at least a portion of the main surface of the IGZO layer on opposite sides of the gate. The second sub-source and the first sub-source are located on the same side and are connected to the first sub-source to jointly form a source. The second sub-drain and the first sub-drain are located on the same side and are connected to the first sub-drain to jointly form a drain. In this way, the contact area between the source and the drain and the IGZO layer, respectively, can be increased, thereby reducing the contact resistance between the source and the drain and the IGZO layer, respectively, and thereby improving the performance of the semiconductor device.

[0081] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0082] Figure 1 A schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 2 A schematic cross-sectional view of a substrate provided in the method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 3 A cross-sectional schematic diagram of forming a dielectric layer and a first electrode layer on a substrate in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 4A schematic cross-sectional view of forming a first sub-source electrode and a first sub-drain electrode in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 5 A cross-sectional schematic diagram of forming an isolation layer in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 6 A schematic cross-sectional view of forming a first isolation structure in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 7 A cross-sectional schematic diagram of forming an IGZO layer on a first isolation structure in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 8 A schematic cross-sectional view of forming a gate dielectric layer and a gate on an IGZO layer in a method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 9 A cross-sectional schematic diagram of forming a gate insulating layer in the method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 10 A schematic cross-sectional view of forming a second electrode layer in the method for preparing a semiconductor structure provided in an embodiment of the present application; Figure 11 A schematic cross-sectional view of an IGZO transistor formed by the method for preparing a semiconductor structure provided in an embodiment of the present application.

[0083] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, which is mainly used to prepare a semiconductor structure. The semiconductor structure includes a substrate and an IGZO transistor located on the substrate. The IGZO transistor can be prepared by the preparation method provided by the embodiment of the present application.

[0084] It should be noted that Indium Gallium Zinc Oxide (IGZO) is a new type of semiconductor material with higher electron mobility than amorphous silicon (α-Si) and can be used as a channel material in thin film transistors.

[0085] Indium gallium zinc oxide (IGZO) includes indium oxide (In2O3), gallium oxide (Ga2O3) and zinc oxide (ZnO), wherein the composition ratio of indium oxide (In2O3), gallium oxide (Ga2O3) and zinc oxide (ZnO) may include but is not limited to 1:1:1. By using IGZO as the trench material of the thin film transistor, the carrier mobility can be higher. For example, the carrier mobility of IGZO is about 10 to 30 cm 2 / V-sec, therefore, less IGZO material can meet the requirements, making the size of the thin film transistor smaller and the semiconductor device thinner and lighter; in addition, the preparation process temperature is lower than the requirement of single crystal silicon. For example, it can be prepared at a temperature of less than 300°C and has good bending performance, so that it can be used with different devices or structures.

[0086] In the present application, IGZO material is used as the channel layer material of the thin film transistor to form an IGZO transistor. Below, the preparation method of the semiconductor structure including the IGZO transistor will be described in detail with reference to the accompanying drawings.

[0087] Please refer to Figure 1 As shown, the method for preparing a semiconductor structure provided in an embodiment of the present application specifically includes:

[0088] Step S101: providing a substrate, on which a first sub-source electrode and a first sub-drain electrode spaced apart are formed.

[0089] Please combine Figure 2 As shown, the substrate 10 serves as a supporting structure of the semiconductor structure 100 and can provide a supporting basis or process basis for the devices or structural layers on the substrate 10. The material constituting the substrate 10 may include any one or more of silicon, germanium, silicon germanium, silicon carbide, silicon on insulator, and germanium on insulator; or, the material constituting the substrate 10 may also be other materials known to those skilled in the art. In the embodiment of the present application, at least a portion of the substrate 10 is a silicon substrate, and the silicon material may be single crystal silicon. Exemplarily, the substrate 10 may be prepared by chemical vapor deposition (CVD).

[0090] In some optional implementations, please combine Figure 3 As shown, after providing the substrate 10, the process further includes: forming a dielectric layer 40 on the substrate 10. Exemplarily, the dielectric layer 40 is deposited on the main surface of the substrate 10 by an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, or a chemical vapor deposition (CVD) process, wherein the material of the dielectric layer 40 includes but is not limited to an insulating material such as silicon dioxide (SiO2), so that the substrate 10 is electrically isolated by the dielectric layer 40.

[0091] It should be noted that the main surface of the substrate 10 is the surface where the devices subsequently prepared on the substrate 10 are located. Figure 2 and Figure 3 In the embodiment, the main surface of the substrate 10 is the upper surface of the substrate 10 .

[0092] In some optional implementations, after forming the dielectric layer 40 on the substrate 10 , the method further includes: forming a first electrode layer 213 on the dielectric layer 40 .

[0093] Combine Figure 3As shown, illustratively, a first electrode layer 213 can be formed on the surface of the dielectric layer 40 by a deposition process on the upper surface of the dielectric layer 40. For example, a conductive material such as aluminum or gold is deposited on the upper surface of the dielectric layer 40 by an atomic layer deposition process, a physical vapor deposition process, or a chemical vapor deposition process. The conductive material deposited on the dielectric layer 40 forms the first electrode layer 213.

[0094] In some optional implementations, after forming the first electrode layer 213 on the dielectric layer 40 , the method further includes: forming a patterned first mask layer on the first electrode layer 213 .

[0095] The first mask layer may be a photoresist layer, which is patterned by exposure, development or etching. For example, the patterned first mask layer exposes the region corresponding to the gate 24 of the IGZO transistor 20 to be formed in a subsequent process.

[0096] Then, the patterned first mask layer is used as a mask to remove the first electrode layer 213 corresponding to the exposed area of ​​the first mask layer, so as to form a channel 214 exposing the dielectric layer 40 on the first electrode layer 213, and the first electrode layer 213 remaining on both sides of the channel 214 is formed into a first sub-source 211 and a first sub-drain 221, respectively. Figure 4 As shown in .

[0097] Exemplarily, the patterned first mask layer is used as a mask, and the first electrode layer 213 exposed by the first mask layer is etched by wet etching or dry etching to form a channel 214 on the first electrode layer 213 that exposes the upper surface of the dielectric layer 40, so that the first electrode layer 213 remaining on both sides of the channel 214 is respectively formed into a first sub-source electrode 211 and a first sub-drain electrode 221;

[0098] After the first sub-source electrode 211 and the first sub-drain electrode 221 are formed, a cleaning solution or a cleaning gas may be used to remove the first mask layer on the first electrode layer 213 .

[0099] In some optional embodiments, after forming the first sub-source electrode 211 and the first sub-drain electrode 221 on the dielectric layer 40 and forming the channel 214 between the first sub-source electrode 211 and the first sub-drain electrode 221 , the method further includes:

[0100] A first isolation structure 31 is formed between the first sub-source electrode 211 and the first sub-drain electrode 221 , and a main surface of the first isolation structure 31 is flush with a main surface of the first sub-source electrode 211 and a main surface of the first sub-drain electrode 221 , respectively.

[0101] Specific, combined Figure 5As shown, insulating isolation materials such as silicon dioxide can be deposited in the channel 214 and on the main surfaces (e.g., upper surfaces) of the first sub-source 211 and the first sub-drain 221 by atomic layer deposition, physical vapor deposition, or chemical vapor deposition processes to form an isolation layer 30 that fills the channel 214 and covers the main surfaces of the first sub-source 211 and the first sub-drain 221.

[0102] Please combine Figure 5 and Figure 6 As shown, after forming the isolation layer 30 that fills the channel 214 and covers the main surfaces of the first sub-source electrode 211 and the first sub-drain electrode 221, the isolation layer 30 on the main surfaces of the first sub-source electrode 211 and the first sub-drain electrode 221 can be removed by a chemical mechanical polishing (CMP) process, and the isolation layer 30 in the channel 214 is retained. The main surfaces of the isolation layer 30 retained in the channel 214 are flush with the main surfaces of the first sub-source electrode 211 and the first sub-drain electrode 221, respectively, as shown in FIG. Figure 6 As shown in .

[0103] Step S102 : forming an IGZO layer on a portion of the main surface of the first sub-source electrode and the first sub-drain electrode, and the IGZO layer covers the area between the first sub-source electrode and the first sub-drain electrode.

[0104] It can be understood that the IGZO layer 23 is formed on part of the main surface of the first sub-drain 221 and the first sub-source 211, and the IGZO layer 23 covers the area between the first sub-source 211 and the first sub-drain 221. That is, the IGZO layer 23 is located above the substrate 10 in the area between the first sub-source 211 and the first sub-drain 221, and in the thickness direction of the substrate 10, the projection of the IGZO layer 23 on the substrate 10 partially overlaps with the projection of the first sub-source 211 and the first sub-drain 221 on the substrate 10, respectively. In this way, the IGZO layer 23 can serve as the channel layer of the subsequently formed IGZO transistor 20, which can increase the contact area between the first sub-source 211 and the first sub-drain 221 and the IGZO layer 23.

[0105] For details, please combine Figure 7As shown, after the first isolation structure 31 is formed in the channel 214 between the first sub-source 211 and the first sub-drain 221, an IGZO material is deposited on the main surfaces of the first sub-source 211, the first isolation structure 31 and the first sub-drain 221 by atomic layer deposition, physical vapor deposition or chemical vapor deposition to form an IGZO layer 23, that is, the IGZO layer 23 is located above the first isolation structure 31; then, a second mask layer is formed on the main surface of the IGZO layer 23. For example, the second mask layer The second mask layer is a photoresist layer, and the photoresist layer is patterned by exposure, development or etching to form a mask pattern, so that the IGZO layer 23 is etched according to the mask pattern, retaining the IGZO layer 23 on the first isolation structure 31, and retaining the IGZO layer 23 on the main surface of the first sub-source 211 and the first sub-drain 221 close to one end of the first isolation structure 31, and the IGZO layer 23 retained on the main surface of the first sub-source 211 and the first sub-drain 221 is symmetrical about the central axis of the first isolation structure 31.

[0106] It can be understood that, in the thickness direction along the substrate 10, the projection of the IGZO layer 23 overlaps with the projection parts of the first sub-source 211 and the first sub-drain 221, respectively, thereby increasing the contact area between the IGZO layer 23 and the first sub-source 211 and the first sub-drain 221, so as to reduce the contact resistance when the IGZO layer 23 is in ohmic contact with the first sub-source 211 and the first sub-drain 221.

[0107] It should be noted that in order to further increase the contact area between the IGZO layer 23 and the first sub-source 211 and the first sub-drain 221, the area where the projection of the IGZO layer 23 overlaps with the projection of the first sub-source 211 and the first sub-drain 221 should be as large as possible. The specific design can be adaptively adjusted according to actual needs and is not limited here.

[0108] Step S103: forming a gate on the IGZO layer, with a first sub-source electrode and a first sub-drain electrode located on opposite sides of the gate.

[0109] Please combine Figure 8 As shown, after the IGZO layer 23 is formed on the first isolation structure 31 and before the gate 24 is formed on the IGZO layer 23 , the process further includes: forming a gate dielectric layer 25 on the IGZO layer 23 .

[0110] The gate dielectric layer 25 may include one or more layers. When the gate dielectric layer 25 includes multiple layers, the multiple layers of gate dielectric layer 25 may be stacked along the thickness direction of the substrate 10. Furthermore, the material of the gate dielectric layer 25 may include silicon oxide, silicon dioxide, or a high-K dielectric material. For example, high-K materials used in the gate dielectric layer 25 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high-K material is used, the gate 24 dielectric layer 40 may be annealed to improve its quality.

[0111] Please continue to combine Figure 8 As shown, after a gate dielectric layer 25 is formed on the IGZO layer 23, a conductive material is deposited on the gate dielectric layer 25 by, for example, a physical vapor deposition (PVD) process to form a gate 24, wherein the gate 24 may also be a conductive metal layer, or the gate 24 may be composed of two or more conductive metal layers stacked together.

[0112] For P-type transistors, metal materials that can be used for gate 24 include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). The P-type metal layer will be able to form the gate 24 of the P-type transistor with a work function between about 4.9 eV and about 5.2 eV. For N-type transistors, metal materials that can be used for gate 24 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). The N-type metal layer will be able to form the gate 24 of the N-type transistor with a work function between about 3.9 eV and about 4.2 eV.

[0113] Of course, the gate 24 includes but is not limited to the above-mentioned conductive materials. For example, the gate 24 is a multi-layer structure, and the gate 24 includes a polysilicon layer, a titanium nitride layer, a metal tungsten layer, etc. stacked in sequence from bottom to top. The specific configuration can be adaptively adjusted according to actual needs and is not limited here.

[0114] In addition, the gate 24 can be formed by a self-alignment process. After the gate 24 is formed by the self-alignment process, the gate dielectric layer 25 can be patterned according to the gate 24 to remove part of the gate dielectric layer 25 so that the sidewall of the gate dielectric layer 25 is flush with the sidewall of the gate 24.

[0115] Please combine Figure 9As shown, after the gate 24 is formed on the IGZO layer 23, that is, after the gate 24 is formed on the upper surface of the gate dielectric layer 25, the following further includes: forming a gate insulating layer 26 on the sidewalls of the gate 24 and the gate dielectric layer 25. The gate insulating layer 26 covers the sidewalls of the gate 24 and the gate dielectric layer 25, so as to electrically isolate the gate 24 from other external structures through the gate insulating layer 26. The gate insulating layer 26 may include, but is not limited to, an insulating material such as silicon oxide, silicon dioxide, or silicon nitride.

[0116] In addition, the gate insulation layer 26 can be a stacked structure of one layer or multiple layers. When the gate insulation layer 26 is a multi-layer structure, the multiple layers of gate insulation layer 26 are stacked in sequence along the side walls close to the gate dielectric layer 25 and the gate 24 toward the side walls away from the gate dielectric layer 25 and the gate 24 to improve the electrical isolation of the gate 24.

[0117] Step S104: forming a second sub-source and a second sub-source on at least part of the main surface of the IGZO layer on opposite sides of the gate, respectively, the second sub-source and the first sub-source are located on the same side and are connected to the first sub-source to jointly form a source; the second sub-drain and the first sub-drain are located on the same side and are connected to the first sub-drain to jointly form a drain; wherein the source, the drain, the gate and the IGZO layer jointly form an IGZO transistor.

[0118] For details, please combine Figure 10 As shown, after the gate insulating layer 26 is formed on the side walls of the gate 24 and the gate dielectric layer 25, a conductive material can be deposited on the main surfaces of the gate 24, the exposed IGZO layer 23, the exposed first sub-source 211 and the first sub-drain 221 through a PVD process, a CVD process, etc. to form a second electrode layer 223; that is, the second electrode layer 223 covers the surface of the gate 24, the surface of the IGZO layer 23 exposed on both sides of the gate 24, the surface of the first sub-drain 221 and the first sub-source 211, wherein the material of the second electrode layer 223 may include but is not limited to conductive materials such as aluminum.

[0119] After the second electrode layer 223 is formed, the second electrode layer 223 on the main surface (e.g., the upper surface) of the gate 24 and part of the second electrode layer 223 on both sides of the gate 24 can be removed by CMP or etching process. The main surface of the retained second electrode layer 223 is lower than the main surface of the gate 24. It can be understood that the retained second electrode layer 223 covers at least part of the main surface of the IGZO on both sides of the gate 24 and covers the exposed main surfaces of the first sub-source 211 and the first sub-drain 221. The second electrode layers 223 retained on both sides of the gate 24 are respectively formed into the second sub-source 212 and the second sub-drain 222, as shown in FIG. Figure 11 shown.

[0120] It should be noted that, along the thickness direction of the substrate 10, the projections of the second sub-source 212 and the second sub-drain 222 on the substrate 10 partially overlap with the projections of the IGZO layer 23 on the substrate 10, thereby increasing the contact areas between the second sub-source 212 and the second sub-drain 222 and the IGZO layer 23.

[0121] Please combine Figure 11 As shown in the figure, the second sub-source 212 and the first sub-source 211 are located on the same side of the gate 24, and the second sub-source 212 is connected to the first sub-source 211, and the first sub-source 211 and the second sub-source 212 together form the source 21 of the transistor; the second sub-drain 222 and the first sub-drain 221 are located on the same side of the gate 24, and the second sub-drain 222 is connected to the first sub-drain 221, and the first sub-drain 221 and the second sub-drain 222 together form the drain 22 of the transistor, and the source 21, the drain 22, the gate 24 and the IGZO layer 23 together form the IGZO transistor 20.

[0122] In the above scheme, an IGZO layer 23 is formed on a portion of the main surface of the first sub-source electrode 211 and the first sub-drain electrode 221, and the IGZO layer 23 covers the area between the first sub-source electrode 211 and the first sub-drain electrode 221, and then a gate electrode 24 is formed on the IGZO layer 23, the first sub-source electrode 211 and the first sub-drain electrode 221 are respectively located on opposite sides of the gate electrode 24, and a second sub-source electrode 212 and a second sub-drain electrode 222 are respectively formed on at least a portion of the main surface of the IGZO layer 23 on opposite sides of the gate electrode 24, the second sub-source electrode 212 and the first sub-source electrode 211 are located on the same side and are connected to the first sub-source electrode 211 to jointly form the source electrode 21, and the second sub-drain electrode 222 and the first sub-drain electrode 221 are located on opposite sides of the gate electrode 24. On the same side and connected to the first sub-drain 221 to jointly form the drain 22, so that the IGZO layer 23 is arranged between the source 21 and the drain 22, and the two ends of the IGZO layer 23 are respectively embedded in the source 21 and the drain 22, that is, the source 21 is arranged around the surface of one end of the IGZO layer 23, and the drain 22 is arranged around the surface of the other end of the IGZO layer 23, so that the upper and lower surfaces and side walls of the two ends of the IGZO layer 23 are respectively in contact with the source 21 and the drain 22, thereby increasing the contact area between the source 21 and the drain 22 and the IGZO layer 23, and then reducing the contact resistance between the source 21 and the drain 22 and the IGZO layer 23, thereby improving the performance of the semiconductor device.

[0123] It should be noted that in the embodiment of the present application, IGZO material is used as the channel material of the channel layer of the IGZO transistor 20. Since the carrier mobility of IGZO is 20 to 50 times that of polysilicon, it is beneficial to improve the carrier mobility between the source 21 and the drain 22 in the IGZO transistor 20, thereby helping to reduce the leakage current of the semiconductor structure 100 during operation, thereby reducing the power consumption of the semiconductor structure 100 and improving the working efficiency of the semiconductor structure 100; in addition, the IGZO material can be prepared and formed in a low-temperature preparation process, for example, it can be prepared at a temperature of 300°C or below, thereby reducing the conditions of the preparation process.

[0124] In a second aspect, an embodiment of the present application further provides a semiconductor structure 100 . The semiconductor structure 100 provided by the embodiment of the present application is prepared using the preparation method provided by the above embodiment.

[0125] Please refer to Figure 11 As shown, the semiconductor structure 100 provided in an embodiment of the present application includes: a substrate 10 and an IGZO transistor 20, the IGZO transistor 20 is arranged on the substrate 10, the IGZO transistor 20 includes a gate 24, a source 21, a drain 22 and an IGZO layer 23, the gate 24 is arranged on the substrate 10, the source 21 and the drain 22 are respectively located on both sides of the gate 24, the IGZO layer 23 is located between the substrate 10 and the gate 24, and in the direction perpendicular to the main surface of the substrate 10, the projection of the IGZO layer 23 partially overlaps with the projection of the source 21 and the drain 22, respectively, wherein the source 21 at least partially covers the upper and lower surfaces and side walls of the IGZO layer 23 close to the source 21 side, and the drain 22 at least partially covers the upper and lower surfaces and side walls of the IGZO layer 23 close to the drain 22 side.

[0126] In the above scheme, the IGZO layer 23 serves as the channel layer of the IGZO transistor 20, and the source 21 and the drain 22 arranged on both sides of the gate 24 are arranged in a direction perpendicular to the main surface of the substrate 10 (that is, along the thickness direction of the substrate 10). The projection of the IGZO layer 23 overlaps with the projection of the source 21 and the drain 22, that is, the IGZO layer 23 is arranged between the source 21 and the drain 22, and the two ends of the IGZO layer 23 are respectively embedded in the source 21 and the drain 22, that is, the source 21 is arranged around the surface of one end of the IGZO layer 23, and the drain 22 is arranged around the IGZO layer 23. The surface of the other end of the ZO layer 23 is set to increase the contact area between the source 21 and the drain 22 and the IGZO layer 23 respectively, so that the source 21 covers the upper and lower surfaces and side walls of the IGZO layer 23 close to the source 21, and the drain 22 covers the upper and lower surfaces and side walls of the IGZO layer 23 close to the drain 22. In this way, the contact area of ​​the ohmic contact between the IGZO layer 23 and the source 21 and the drain 22 can be increased, thereby reducing the contact resistance of the ohmic contact between the IGZO layer 23 and the source 21 and the drain 22, thereby improving the performance of the semiconductor structure 100.

[0127] It can be understood that the substrate 10 serves as a supporting component of the semiconductor structure 100 , and is used to support other components or devices disposed thereon.

[0128] In addition, the IGZO transistor 20 also includes a gate dielectric layer 25 and a gate insulating layer 26, wherein the gate dielectric layer 25 is arranged between the IGZO layer 23 and the gate 24, wherein the gate dielectric layer 25 can be a stacked structure of one layer or multiple layers; when the gate dielectric layer 25 is a multi-layer structure, the gate dielectric layer 25 is stacked in sequence along the thickness direction of the substrate 10, for example, the gate dielectric layer 25 includes a silicon oxide layer, a silicon dioxide layer, a silicon nitride layer, etc. stacked in sequence; the gate insulating layer 26 covers the sidewalls of the gate dielectric layer 25 and the gate 24 to electrically isolate the gate 24 through the gate insulating layer 26, wherein the gate insulating layer 26 can also be a stacked structure of one layer or multiple layers, wherein when the gate insulating layer 26 is multi-layer, the multiple layers of gate insulating layers 26 are stacked in sequence from the sidewall of the gate 24 toward the direction away from the sidewall of the gate 24 to improve the electrical isolation of the gate 24 through the multi-layer gate insulating layer 26.

[0129] In some optional embodiments, the source 21 includes a first sub-source 211 and a second sub-source 212, the first sub-source 211 is located between the substrate 10 and the IGZO layer 23, and the second sub-source 212 is located above the IGZO layer 23, that is, the first sub-source 211 and the second sub-source 212 are located on the same side of the gate 24, and one end of the IGZO layer 23 is located between the first sub-source 211 and the second sub-source 212, and the end of the second sub-source 212 away from the gate 24 is connected to the first sub-source 211, so that the first sub-source 211 and the second sub-source 212 together form the source 21 of the IGZO transistor 20, thereby increasing the contact area between the source 21 and the IGZO layer 23 and reducing the contact resistance between the source 21 and the IGZO layer 23.

[0130] In addition, the drain 22 includes a first sub-drain 221 and a second sub-drain 222, the second sub-drain 222 is located between the substrate 10 and the IGZO layer 23, and the second sub-drain 222 is located above the IGZO layer 23, that is, the first sub-drain 221 and the second sub-drain 222 are located on the same side of the gate 24, and the end of the IGZO layer 23 away from the source 21 is located between the second sub-drain 222 and the first sub-drain 221, and the end of the second sub-drain 222 away from the gate 24 is connected to the first sub-drain 221, so that the first sub-drain 221 and the second sub-drain 222 are jointly formed into the drain 22, so as to increase the contact area between the drain 22 and the IGZO layer 23 and reduce the contact resistance between the drain 22 and the IGZO layer 23.

[0131] In the above scheme, one end of the IGZO layer 23 is covered by the first sub-source 211 and the second sub-source 212, and the other end of the IGZO layer 23 is covered by the first sub-drain 221 and the second sub-drain 222. In this way, in addition to being connected to the end face of the IGZO layer 23, the source 21 and the drain 22 are also in contact with the upper and lower surface parts of the IGZO layer 23, thereby increasing the contact area between the source 21 and the drain 22 and the IGZO layer 23, thereby reducing the contact resistance when the source 21 and the drain 22 are in ohmic contact with the IGZO layer 23, thereby improving the electrical performance of the semiconductor device.

[0132] Please continue to refer to Figure 11 As shown, a first isolation structure 31 is further provided between the first sub-source electrode 211 and the first sub-drain electrode 221. The main surfaces of the first isolation structure 31 are flush with the main surfaces of the first sub-source electrode 211 and the first sub-drain electrode 221, respectively. The IGZO layer 23 is located on the main surface of the first isolation structure 31, and both sides of the IGZO layer 23 extend to the main surfaces of the first sub-source electrode 211 and the first sub-drain electrode 221, respectively, so as to electrically isolate the IGZO layer 23 through the first isolation structure 31. The first isolation structure 31 includes, but is not limited to, a silicon dioxide structure.

[0133] In addition, a dielectric layer 40 is provided between the first sub-source 211 and the first sub-drain 221 and the substrate 10, respectively, to electrically isolate the first source 21 and the first drain 22 through the dielectric layer 40. The material of the dielectric layer 40 includes but is not limited to insulating materials such as silicon dioxide.

[0134] like Figure 11 As shown in the figure, the dielectric layer 40 is arranged on the upper surface of the substrate 10, the first sub-source 211, the first isolation structure 31 and the first sub-drain 221 are all located on the dielectric layer 40, the second sub-source 212 is located above the first sub-source 211 and is connected to the first sub-source 211, the second sub-drain 222 is located above the second sub-drain 222 and is connected to the first sub-drain 221, and the upper surfaces of the second sub-drain 222 and the second sub-source 212 are both lower than the upper surface of the gate 24.

[0135] In some optional embodiments, the semiconductor structure 100 provided in the embodiment of the present application includes an IGZO transistor 20 and may also include a capacitor, a word line, and a bit line, wherein the gate 24 of the IGZO transistor 20 is connected to the word line (Wordline, referred to as WL), the drain 22 is connected to the bit line, and the source 21 is connected to the capacitor. The voltage signal on the word line can control the opening or closing of the transistor, and then read the data information stored in the capacitor through the bit line, or write the data information into the capacitor for storage through the bit line. The word line is connected to the word line driver (Word line driver) through a contact structure (Local interconnect contact, referred to as LICON) located in the peripheral area of ​​the memory cell, so that the word line driver can input a voltage signal into the word line.

[0136] Since the IGZO material can be grown on any desired surface, the IGZO transistor 20 using the IGZO material as the channel layer of the transistor can also be applied in the 3D semiconductor structure 100 .

[0137] In some optional implementations, please refer to Figure 12 As shown, the semiconductor structure 100 includes at least two IGZO transistor units 50 arranged on a substrate 10, and a second isolation structure 60 is arranged between two adjacent IGZO transistor units 50, wherein the material of the second isolation structure 60 may include but is not limited to insulating materials such as silicon oxide and silicon dioxide; each IGZO transistor unit 50 includes two IGZO transistors 20, the two IGZO transistors 20 are stacked in a vertical direction, and the signals between the two IGZO transistors 20 are connected.

[0138] It can be understood that an IGZO transistor unit 50 includes two IGZO transistors 20, and the two IGZO transistors 20 form a dual-transistor capacitor-free storage unit (2Transistor0Capacitor, abbreviated as 2T0C). In the semiconductor structure 100 provided in the embodiment of the present application, no capacitor is set, but an IGZO transistor 20 is used instead of the capacitor to store data information.

[0139] Please refer to Figure 12 As shown, the semiconductor structure 100 further includes a contact plug 70, wherein the material of the contact plug 70 includes, but is not limited to, a conductive material such as metal tungsten. In addition, two IGZO transistors 20 include a first IGZO transistor 20a and a second IGZO transistor 20b, wherein the second IGZO transistor 20b is located above the first IGZO transistor 20a, and the gate 24 of the second IGZO transistor 20b is signal-connected to the source 21 of the first IGZO transistor 20a via the contact plug 70. Exemplarily, the first IGZO transistor 20a may be a write transistor, and the second IGZO transistor 20b may be a read transistor. When a voltage is applied to the gate 24 of the first IGZO transistor 20a to turn on the first IGZO transistor, the source 21 of the first IGZO transistor 20a is signal-connected to the gate 24 of the second IGZO transistor 20b via the contact plug 70, so that data information is written into the gate 24 of the second IGZO transistor 20b for storage. In other words, the gate 24 of the second IGZO transistor 20b acts as a capacitor.

[0140] In some optional embodiments, the second IGZO transistor 20b and the first IGZO transistor 20a are staggered so that the gate 24 in the second IGZO transistor 20b is located directly above the source 21 in the first IGZO transistor 20a connected to its signal. In this way, the density of the semiconductor structure 100 can be increased, and the length of the contact plug 70 connecting the source 21 of the first IGZO transistor 20a and the gate 24 of the second IGZO transistor 20b can be shortened, thereby improving the efficiency of signal transmission. At the same time, the layout density of each device in the semiconductor structure 100 can be increased, thereby reducing the overall size of the semiconductor structure 100.

[0141] In some other optional implementations, please refer to Figure 13As shown, the semiconductor structure 100 provided in an embodiment of the present application includes at least two IGZO transistors 20, which are stacked along the thickness direction of the substrate 10. An insulating structure 80 is provided between two adjacent IGZO transistors 20, and the two adjacent IGZO transistors 20 are insulated and connected by the insulating structure 80. The material of the insulating structure 80 includes, but is not limited to, insulating materials such as silicon oxide and silicon dioxide.

[0142] It is understandable that in Figure 13 In the embodiment, at least two IGZO transistors 20 are stacked in the thickness direction of the substrate 10, and each IGZO transistor 20 exists independently as a transistor, and any two adjacent IGZO transistors 20 are electrically isolated by an insulating structure 80. In this way, by stacking at least two IGZO transistors 20 in and out, the layout density of the semiconductor structure 100 can be improved, thereby reducing the overall size of the semiconductor structure 100.

[0143] In the semiconductor structure and preparation method provided in the embodiments of the present application, an IGZO layer is formed on a portion of the main surface of the first sub-source and the first sub-drain, and the IGZO layer covers the area between the first sub-source and the first sub-drain. Then, a gate is formed on the IGZO layer, and the first sub-source and the first sub-drain are respectively located on opposite sides of the gate. A second sub-source and a second sub-drain are respectively formed on at least a portion of the main surface of the IGZO layer on opposite sides of the gate. The second sub-source and the first sub-source are located on the same side and connected to the first sub-source to jointly form a source. The second sub-drain and the first sub-drain are located on the same side and connected to the first sub-drain to jointly form a drain. In this way, the two ends of the IGZO layer are respectively embedded in the source and the drain, so that the upper and lower surfaces and sidewalls of the two ends of the IGZO layer are respectively in contact with the source and the drain, thereby increasing the contact area between the source and the drain and the IGZO layer, thereby reducing the contact resistance between the source and the drain and the IGZO layer, and improving the performance of the semiconductor device.

[0144] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0145] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0146] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, on which a first sub-source electrode and a first sub-drain electrode spaced apart are formed; forming an IGZO layer on a portion of the main surface of the first sub-source electrode and the first sub-drain electrode, wherein the IGZO layer covers a region between the first sub-source electrode and the first sub-drain electrode; forming a gate above the IGZO layer, wherein the first sub-source electrode and the first sub-drain electrode are respectively located on opposite sides of the gate; A second sub-source electrode and a second sub-drain electrode are respectively formed on at least part of the main surface of the IGZO layer on opposite sides of the gate, wherein the second sub-source electrode and the first sub-source electrode are located on the same side and connected to the first sub-source electrode to jointly form a source electrode; and the second sub-drain electrode and the first sub-drain electrode are located on the same side and connected to the first sub-drain electrode to jointly form a drain electrode; The source, the drain, the gate and the IGZO layer together form an IGZO transistor.

2. The method for preparing a semiconductor structure according to claim 1, wherein: Before forming the IGZO layer on a portion of the surface of the first sub-source electrode and the first sub-drain electrode, the method further includes: A first isolation structure is formed between the first sub-source and the first sub-drain, and a main surface of the first isolation structure is flush with a main surface of the first sub-source and a main surface of the first sub-drain, respectively.

3. The method for preparing a semiconductor structure according to claim 2, wherein: The step of forming an IGZO layer on a portion of the surface of the first sub-source electrode and the first sub-drain electrode, wherein the IGZO layer covers the area between the first sub-source electrode and the first sub-drain electrode, comprises: forming an IGZO layer on a main surface of the first isolation structure, and on a portion of a main surface of the first sub-source electrode and the first sub-drain electrode; The IGZO layer is symmetrically arranged about the central axis of the first isolation structure.

4. The method for preparing a semiconductor structure according to claim 2, wherein: The step of forming a first sub-source electrode and a first sub-drain electrode spaced apart from each other on the substrate includes: forming a dielectric layer on the substrate; forming a first electrode layer on the dielectric layer; forming a patterned first mask layer on the first electrode layer; Using the patterned first mask layer as a mask, a portion of the first electrode layer is removed to form a channel exposing the dielectric layer on the first electrode layer, and the first electrode layer remaining on both sides of the channel is formed into a first sub-source and a first sub-drain respectively.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The step of forming a first isolation structure between the first sub-source and the first sub-drain includes: forming an isolation layer in the channel, wherein the isolation layer covers major surfaces of the first sub-source electrode and the first sub-drain electrode; The isolation layer on the main surfaces of the first sub-source and the first sub-drain is removed, and the isolation layer in the channel is retained, with the main surface of the retained isolation layer flush with the main surfaces of the first sub-source and the first sub-drain.

6. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: The step of forming a second sub-source electrode and a second sub-drain electrode on at least a portion of the main surface of the IGZO layer on opposite sides of the gate respectively includes: forming a second electrode layer on a main surface of the gate, a main surface of the exposed IGZO layer, and main surfaces of the exposed first sub-source and first sub-drain electrodes; The second electrode layer on the main surface of the gate and part of the second electrode layer on both sides of the gate are removed; the main surface of the retained second electrode layer is lower than the main surface of the gate, and the second electrode layer retained on both sides of the gate are respectively formed into a second sub-source and a second sub-drain.

7. The method for preparing a semiconductor structure according to any one of claims 1 to 3, characterized in that: Before forming a gate on the IGZO layer, the method further includes: forming a gate dielectric layer on the IGZO layer; Wherein, the sidewall of the gate dielectric layer is flush with the sidewall of the gate.

8. The method for preparing a semiconductor structure according to claim 7, wherein: After forming a gate on the IGZO layer, the method further includes: A gate insulating layer is formed on the sidewalls of the gate electrode and the gate dielectric layer, and the gate insulating layer covers the sidewalls of the gate electrode and the gate dielectric layer.

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