Embedded stacking packaging method and packaging structure

Abstract

The present invention relates to the technical field of stacked packaging structures, and provides an embedded stacked packaging method and packaging structure, including: S1: preparing a first ceramic substrate and covering the upper surface of the first ceramic substrate with a first upper conductive metal layer; S2: forming a first solder layer on the first upper conductive metal layer; S31: covering the lower surface of the second ceramic substrate with a second lower conductive metal layer; the first lower chip is embedded in a first hole on the second ceramic substrate; S4: forming a second solder layer on the upper surface of the first lower chip; S5: integrating and fixing the first lower chip, the second ceramic substrate and the first ceramic substrate through heat treatment; S61: forming a third solder layer; S7: injecting a first insulating solder into the gap between the first lower chip and the second ceramic substrate; S8: covering the third lower conductive metal layer; S9: integrating and fixing the predetermined substrate with the conductive hole with the second ceramic substrate through heat treatment.

Description

Technical Field

[0001] The present invention belongs to the technical field of stacked packaging structures, and more particularly, relates to an embedded stacked packaging method and a packaging structure. Background Art

[0002] Existing power half-bridge module packages are self-contained modules that integrate power devices, a package substrate, power terminals, and a heat sink. They are widely used in aerospace, automotive electronics, energy storage, and other applications requiring control and regulation of high-power electronic equipment. Chip-to-chip electrical connections within existing power module packages are typically made via wire bonding. The substrate and chip are connected by soldering the chip's bottom pads to the substrate's top surface. Wire bonding also connects the chip's surface electrodes to the substrate and power terminals. The overall power circuit exists on a flat substrate, forming a two-dimensional power circuit.

[0003] 1. The wire bonding structure requires a large package space, which is not conducive to the miniaturization of power modules. Furthermore, thermal stress can easily cause fatigue failure of the bonding wires, leading to increased resistance and loss at the contact points within the module through the wire bonds, ultimately causing chip overheating and damage.

[0004] 2. The current loop inside the power module exists in a two-dimensional plane, which makes the overall power loop longer and introduces greater parasitic inductance, which may introduce larger voltage fluctuations, current oscillations and increased energy loss, reducing the stability of the system.

[0005] 3. Traditional power module packaging is usually made of plastic or metal materials. The heat transfer speed between the materials is slow, resulting in high thermal resistance and poor heat dissipation effect, which cannot meet the heat dissipation requirements of high-power devices. Secondly, the heat dissipation area of ​​traditional packaging is limited and cannot effectively dissipate heat.

[0006] 4. Traditional power modules will introduce a large common-mode capacitor (capacitance between the output port and the ground). The common-mode capacitor creates a high-frequency noise signal path between the output port and the ground. The high-frequency noise will enter the system through this path, generating common-mode noise. Common-mode noise may cause performance degradation and increased errors. Summary of the Invention

[0007] The object of the present invention is to provide an embedded stacking packaging method to solve the technical problems in the prior art that chip packaging occupies too much external space and the packaging is not firm.

[0008] To achieve the above-mentioned purpose, the present invention adopts a technical solution of providing an embedded stacking packaging method, comprising:

[0009] S1: preparing a first ceramic substrate and covering the upper surface of the first ceramic substrate with a first upper conductive metal layer;

[0010] S2: forming a first solder layer on the first upper conductive metal layer;

[0011] S3: includes: S31 or S32; S31: preparing a second ceramic substrate and a first lower chip; wherein the lower surface of the second ceramic substrate is covered with a second lower conductive metal layer, and the upper surface of the second ceramic substrate is covered with a second upper conductive metal layer; the second lower conductive metal layer is laid on the first solder layer; the first lower chip is embedded in the first hole on the second ceramic substrate; S32: preparing the first lower chip;

[0012] S4: forming a second solder layer on the upper surface of the first lower chip;

[0013] S5: laying a first lower low expansion coefficient conductive metal gasket on the second solder layer; integrating and fixing the first lower chip, the second ceramic substrate, and the first ceramic substrate through heat treatment;

[0014] S6: including: S61 or S62; S61: when performing S31, forming a third solder layer on the upper surface of the second upper conductive metal layer and the upper surface of the first lower low expansion coefficient conductive metal pad; S62: when performing S32, forming a third solder layer on the upper surface of the first lower low expansion coefficient conductive metal pad;

[0015] S7: injecting a first insulating solder into the gap between the first lower chip and the second ceramic substrate;

[0016] S8: preparing a predetermined substrate having a conductive hole and covering the lower surface of the predetermined substrate having the conductive hole with a third lower conductive metal layer;

[0017] S9: placing the third lower conductive metal layer on the third solder layer, the third lower conductive metal layer being electrically connected to the first upper conductive metal layer through the first lower chip; integrating and fixing the predetermined substrate with the conductive hole and the second ceramic substrate through heat treatment.

[0018] Further, S10: a third upper conductive metal layer is covered on the upper surface of the predetermined substrate having the conductive hole; a conductive hole is opened on the predetermined substrate having the conductive hole, and a conductor is filled in the conductive hole; the third upper conductive metal layer is electrically connected to the third lower conductive metal layer through the conductor;

[0019] S11: forming a fourth solder layer on the third upper conductive metal layer;

[0020] S12: Preparing a fourth ceramic substrate and a first upper chip; wherein the lower surface of the fourth ceramic substrate is covered with a fourth lower conductive metal layer, and the upper surface of the fourth ceramic substrate is covered with a fourth upper conductive metal layer; the fourth lower conductive metal layer is laid on the fourth solder layer; and the first upper chip is embedded in the second hole on the fourth ceramic substrate;

[0021] S13: forming a fifth solder layer on the upper surface of the first upper chip;

[0022] S14: laying a first upper low expansion coefficient conductive metal gasket on the fifth solder layer; integrating and fixing the first upper chip, the predetermined substrate having the conductive hole, and the fourth ceramic substrate through heat treatment;

[0023] S15: forming a sixth solder layer on the upper surface of the fourth upper conductive metal layer and the upper surface of the first upper low expansion coefficient conductive metal pad;

[0024] S16: injecting a second insulating solder into the gap between the first upper chip and the fourth ceramic substrate;

[0025] S17: preparing a fifth ceramic substrate and covering the lower surface of the fifth ceramic substrate with a fifth lower conductive metal layer;

[0026] S18: placing the fifth lower conductive metal layer on the sixth solder layer; integrating and fixing the fourth ceramic substrate and the fifth ceramic substrate through heat treatment; and electrically connecting the fifth lower conductive metal layer to the third upper conductive metal layer through the first upper chip.

[0027] The present invention also provides an embedded stacked package structure, comprising:

[0028] a first ceramic substrate; and a first upper conductive metal layer covering an upper surface of the first ceramic substrate;

[0029] a first solder layer; the first solder layer is formed on the first upper conductive metal layer;

[0030] a second ceramic substrate;

[0031] A first lower chip; wherein the lower surface of the second ceramic substrate is covered with a second lower conductive metal layer, and the upper surface of the second ceramic substrate is covered with a second upper conductive metal layer; the second lower conductive metal layer is laid on the first solder layer; and the first lower chip is embedded in the first hole on the second ceramic substrate;

[0032] a second solder layer; the second solder layer is formed on the upper surface of the first lower chip;

[0033] A first lower low expansion coefficient conductive metal gasket; the first lower low expansion coefficient conductive metal gasket is laid on the second solder layer; the first lower chip, the second ceramic substrate and the first ceramic substrate are integrated and fixed by heat treatment;

[0034] a third solder layer; the third solder layer is formed on the upper surface of the second upper conductive metal layer and the upper surface of the first lower low expansion coefficient conductive metal pad;

[0035] A first insulating solder is filled in the gap between the first lower chip and the second ceramic substrate;

[0036] A predetermined substrate having a conductive hole; the lower surface of the predetermined substrate having a conductive hole is covered with a third lower conductive metal layer; the third lower conductive metal layer is attached to the third solder layer, and the third lower conductive metal layer is electrically connected to the first upper conductive metal layer through the first lower chip; the predetermined substrate having a conductive hole is integrated and fixed with the second ceramic substrate by heat treatment.

[0037] Furthermore, it also includes:

[0038] a third upper conductive metal layer; the third upper conductive metal layer covers the upper surface of the predetermined substrate having the conductive hole; a conductive hole is opened on the predetermined substrate having the conductive hole, and the conductive hole is filled with a conductor; the third upper conductive metal layer is electrically connected to the third lower conductive metal layer through the conductor;

[0039] a fourth solder layer; the fourth solder layer being formed on the third upper conductive metal layer;

[0040] a fourth ceramic substrate;

[0041] A first upper chip; wherein the lower surface of the fourth ceramic substrate is covered with a fourth lower conductive metal layer, and the upper surface of the fourth ceramic substrate is covered with a fourth upper conductive metal layer; the fourth lower conductive metal layer is laid on the fourth solder layer; and the first upper chip is embedded in the second hole on the fourth ceramic substrate;

[0042] a fifth solder layer; the fifth solder layer is formed on the upper surface of the first upper chip;

[0043] A first upper low-expansion coefficient conductive metal gasket is provided; the first upper low-expansion coefficient conductive metal gasket is laid on the fifth solder layer; the first upper chip, the predetermined substrate having the conductive hole, and the fourth ceramic substrate are integrated and fixed by heat treatment;

[0044] a sixth solder layer; the sixth solder layer is formed on the upper surface of the fourth upper conductive metal layer and the upper surface of the first upper low expansion coefficient conductive metal pad; a second insulating solder is injected into the gap between the first upper chip and the fourth ceramic substrate;

[0045] A fifth ceramic substrate; the lower surface of the fifth ceramic substrate is covered with a fifth lower conductive metal layer; the fifth lower conductive metal layer is attached to the sixth solder layer; the fourth ceramic substrate and the fifth ceramic substrate are integrated and fixed by heat treatment; the fifth lower conductive metal layer is electrically connected to the third upper conductive metal layer through the first upper chip.

[0046] Furthermore, it also includes: a second lower chip and a second upper chip; the second lower chip is embedded in the third hole on the second ceramic substrate; the upper surface of the second lower chip is covered with a seventh solder layer, and the seventh solder layer is covered with a second lower low-expansion coefficient conductive metal gasket; the third solder layer covers the upper surface of the second lower low-expansion coefficient conductive metal gasket; the third lower conductive metal layer is electrically connected to the first upper conductive metal layer through the second lower chip; the second upper chip is embedded in the fourth hole on the fourth ceramic substrate; the upper surface of the second upper chip is covered with an eighth solder layer, and the eighth solder layer is covered with the second upper low-expansion coefficient conductive metal gasket; the sixth solder layer covers the upper surface of the second upper low-expansion coefficient conductive metal gasket; the fifth lower conductive metal layer is electrically connected to the third upper conductive metal layer through the second upper chip;

[0047] The first lower chip is a MOS transistor, the second lower chip is a diode, the first upper chip is a MOS transistor, and the second upper chip is a diode;

[0048] The first upper conductive metal layer includes: a first circuit and a second circuit; the first circuit is electrically connected to the source of the first lower chip, the first circuit is electrically connected to the anode of the second lower chip; the second circuit is connected to the gate of the first lower chip;

[0049] The third upper conductive metal layer serves as an output electrode;

[0050] The third circuit is electrically connected to the drain of the first lower chip, and the third lower conductive metal layer is electrically connected to the cathode of the second lower chip;

[0051] The current in the first upper conductive metal layer can reach the third upper conductive metal layer through the second lower chip; the current in the first upper conductive metal layer can reach the third upper conductive metal layer through the first lower chip after passing through the source electrode of the first lower chip;

[0052] The third upper conductive metal layer includes: a third circuit and a fourth circuit; the third circuit is electrically connected to the source of the first upper chip, and the third circuit is electrically connected to the anode of the second upper chip; the fourth circuit is connected to the gate of the first upper chip;

[0053] The fifth lower conductive metal layer is electrically connected to the drain of the first upper chip, and the fifth lower conductive metal layer is electrically connected to the cathode of the second upper chip;

[0054] The fifth lower conductive metal layer is electrically connected to the positive electrode of the power supply, and the first circuit is electrically connected to the negative electrode of the power supply.

[0055] The beneficial effects of the embedded stacking packaging method provided by the present invention are as follows: compared with the prior art, in the embedded stacking packaging method provided by the present invention, the upper surface of the first ceramic substrate is covered with a first upper conductive metal layer; the lower surface of the second ceramic substrate is covered with a second lower conductive metal layer; the first solder layer is covered on the first upper conductive metal layer; the second lower conductive metal layer is covered on the first solder layer; there is a first solder layer between the second lower conductive metal layer and the first upper conductive metal layer, and the first solder layer can fix the first upper conductive metal layer and the second lower conductive metal layer after heating, and the first upper conductive metal layer and the second lower conductive metal layer can be conductively connected through the first solder layer; a first hole is opened on the second ceramic substrate, and a first lower chip is embedded in the first hole; the upper surface of the first lower chip is covered with the second solder layer, and the second solder layer is covered with a first lower low expansion coefficient conductive metal layer. The first lower chip is packaged in the first hole, which reduces the package size and is more secure; the third lower conductive metal layer can be electrically connected to the first lower chip through the first lower conductive metal gasket and the first upper conductive metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0057] Figure 1 A schematic diagram of the coordination of the first ceramic substrate, the first lower conductive metal layer, and the first upper conductive metal layer provided in an embodiment of the present invention;

[0058] Figure 2 A schematic diagram of the coordination of a first ceramic substrate and a second ceramic substrate provided in an embodiment of the present invention;

[0059] Figure 3 A schematic diagram of the coordination of the first ceramic substrate, the second ceramic substrate, the first lower chip, and the second lower chip provided in an embodiment of the present invention;

[0060] Figure 4 A schematic diagram of the coordination of a first ceramic substrate, a second ceramic substrate, a first lower chip, a second lower chip, and a predetermined substrate with conductive holes provided in an embodiment of the present invention;

[0061] Figure 5 A schematic diagram of the coordination of a first ceramic substrate, a second ceramic substrate, a first lower chip, a second lower chip, a predetermined substrate having conductive holes, a fourth ceramic substrate, a first upper chip, and a second upper chip provided in an embodiment of the present invention;

[0062] Figure 6 A schematic diagram of the coordination of a first ceramic substrate, a second ceramic substrate, a first lower chip, a second lower chip, a predetermined substrate having conductive holes, a fourth ceramic substrate, a first upper chip, a second upper chip, and a fifth ceramic substrate provided in an embodiment of the present invention;

[0063] Figure 7 Provides a process for an embedded stacking packaging method according to an embodiment of the present invention Figure 1 ;

[0064] Figure 8 Provides a process for an embedded stacking packaging method according to an embodiment of the present invention Figure 2 ;

[0065] Figure 9 Provides a process for an embedded stacking packaging method according to an embodiment of the present invention Figure 3 ;

[0066] Figure 10 Schematic diagram of the coordination of a first ceramic substrate, a first lower chip, a second lower chip, a predetermined substrate with conductive holes, a first upper chip, a second upper chip, and a fifth ceramic substrate provided in an embodiment of the present invention.

[0067] Among them, the reference numerals in the figures are:

[0068] 11-first ceramic substrate; 12-first lower conductive metal layer; 13-first upper conductive metal layer; 21-second ceramic substrate; 22-second lower conductive metal layer; 23-second upper conductive metal layer; 24-first hole; 25-third hole; 31-predetermined substrate; 32-third lower conductive metal layer; 33-third upper conductive metal layer; 41-fourth ceramic substrate; 42-fourth lower conductive metal layer; 43-fourth upper conductive metal layer; 51-fifth ceramic substrate; 52-fifth lower conductive metal layer; 53-fifth upper conductive metal layer; 61-first solder layer; 62-third solder layer; 63-fourth solder layer; 64-sixth solder layer; 711-first lower core chip; 712-second solder layer; 713-first lower low-expansion coefficient conductive metal gasket; 721-first upper chip; 722-fifth solder layer; 723-first upper low-expansion coefficient conductive metal gasket; 731-second lower chip; 732-seventh solder layer; 733-second lower low-expansion coefficient conductive metal gasket; 741-second upper chip; 742-eighth solder layer; 743-second upper low-expansion coefficient conductive metal gasket; 81-first insulating solder; 82-second insulating solder; 83-third insulating solder; 84-fourth insulating solder; 91-conductor; 92-first gap; 93-second gap; 94-third gap; 95-fourth gap. DETAILED DESCRIPTION

[0069] It should be noted that the specific embodiments are only used to explain the present invention and are not used to limit the present invention.

[0070] It should be noted that, in the description of the embodiments of this application, unless otherwise specified, " / " represents the meaning of "or". For example, A / B can represent A or B. "And / or" in this article is only a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural.

[0071] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” or “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element. When an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element.

[0072] It should be noted that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they should not be understood as limiting the present invention.

[0073] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, features specified as "first" or "second" may explicitly or implicitly include one or more of such features.

[0074] It should be noted that the term "plurality" means two or more, unless otherwise clearly defined.

[0075] Please also refer to Figures 1 to 8 , the embedded stacking packaging method provided by the present invention is now described. The embedded stacking packaging method includes: S1: preparing a first ceramic substrate 11 and covering the upper surface of the first ceramic substrate 11 with a first upper conductive metal layer 13; S2: forming a first solder layer 61 on the first upper conductive metal layer 13; S31: preparing a second ceramic substrate 21 and a first lower chip 711; wherein, the lower surface of the second ceramic substrate 21 is covered with a second lower conductive metal layer 22, and the upper surface of the second ceramic substrate 21 is covered with a second upper conductive metal layer 23; the second lower conductive metal layer 22 is laid on the first solder layer 61; the first lower chip 711 is embedded in the first hole 24 on the second ceramic substrate 21; S4: forming a second solder layer 712 on the upper surface of the first lower chip 711; S5: laying a first lower low expansion coefficient conductive metal gasket 713 on the second solder layer 712; the first lower chip 711 and the second ceramic substrate 21 are heat treated. The substrate 21 and the first ceramic substrate 11 are integrated and fixed; S61: a third solder layer 62 is formed on the upper surface of the second upper conductive metal layer 23 and the upper surface of the first lower low expansion coefficient conductive metal gasket 713; S7: a first insulating solder 81 is injected into the gap between the first lower chip 711 and the second ceramic substrate 21 ("the gap between the first lower chip 711 and the second ceramic substrate 21", i.e., the first gap 92); S8: a predetermined substrate 31 with a conductive hole is prepared and the lower surface of the predetermined substrate 31 with a conductive hole is covered with a third lower conductive metal layer 32; S9: the third lower conductive metal layer 32 is placed on the third solder layer 62, and the third lower conductive metal layer 32 is electrically connected to the first upper conductive metal layer 13 through the first lower chip 711; the predetermined substrate 31 with a conductive hole is integrated and fixed to the second ceramic substrate 21 by heat treatment.

[0076] In this way, the upper surface of the first ceramic substrate 11 is covered with the first upper conductive metal layer 13; the lower surface of the second ceramic substrate 21 is covered with the second lower conductive metal layer 22; the first solder layer 61 is covered on the first upper conductive metal layer 13; the second lower conductive metal layer 22 is covered on the first solder layer 61; there is a first solder layer 61 between the second lower conductive metal layer 22 and the first upper conductive metal layer 13, and the first solder layer 61 can fix the first upper conductive metal layer 13 and the second lower conductive metal layer 22 after heating, and the first upper conductive metal layer 13 and the second lower conductive metal layer 22 can be conductively connected through the first solder layer 61; a first hole 24 is opened on the second ceramic substrate 21, and a first lower chip 711 is embedded in the first hole 24; the upper surface of the first lower chip 711 is covered with a second solder layer 712, and the second solder layer 712 is covered with a first lower low expansion coefficient conductive metal gasket 713, and the second solder layer 712 can fix the first lower low expansion coefficient conductive metal gasket after heating The first lower low expansion coefficient conductive metal gasket 713 and the first lower chip 711, the first lower low expansion coefficient conductive metal gasket 713 can be conductively connected to the first lower chip 711 through the second solder layer 712; the first lower low expansion coefficient conductive metal gasket 713 and the second upper conductive metal layer 23 are covered with a third solder layer 62; the third lower conductive metal layer 32 of the predetermined substrate 31 with a conductive hole is attached to the third solder layer 62, and the third solder layer 62 can fix the third lower conductive metal layer 32 and the first lower low expansion coefficient conductive metal gasket 713 after heating, and the third lower conductive metal layer 32 can be conductively connected to the first lower low expansion coefficient conductive metal gasket 713 through the third solder layer 62; that is, the first lower chip 711 is encapsulated in the first hole 24, which reduces the package size and is more secure; the third lower conductive metal layer 32 can be electrically connected through the first lower low expansion coefficient conductive metal gasket 713, the first lower chip 711, and the first upper conductive metal layer 13 in sequence.

[0077] Please also refer to Figures 9 and 10The embedded stack packaging method provided by the present invention is now described. The embedded stack packaging method includes: S1: preparing a first ceramic substrate 11 and covering the upper surface of the first ceramic substrate 11 with a first upper conductive metal layer 13; S2: forming a first solder layer 61 on the first upper conductive metal layer 13; S32: preparing a first lower chip 711; S4: forming a second solder layer 712 on the upper surface of the first lower chip 711; S5: laying a first lower low expansion coefficient conductive metal gasket 713 on the second solder layer 712; and heat-treating the first lower chip 711, the second ceramic substrate 21, and the first ceramic substrate 11. The third lower conductive metal layer 32 is electrically connected to the first upper conductive metal layer 13 through the first lower chip 711; the predetermined substrate 31 with the conductive hole is integrated and fixed by heat treatment.

[0078] In one embodiment, the first insulating solder 81 is any one of the following materials: glass-filled insulating solder, PTFE solder, mineral-filled insulating solder, polyimide (PI) solder, or phenolic resin solder. In one embodiment, the first insulating solder 81 can be applied by any one of the following methods: screen printing, scraper, electrophoresis, spin coating, pressure injection, or pre-forming.

[0079] In one embodiment, the second insulating solder 82 is any one of the following materials: glass-filled insulating solder, PTFE solder, mineral-filled insulating solder, polyimide (PI) solder, or phenolic resin solder. In one embodiment, the second insulating solder 82 can be applied by any one of the following methods: screen printing, scraper, electrophoresis, spin coating, pressure injection, or preforming.

[0080] In one embodiment, the third insulating solder 83 is any one of the following materials: glass-filled insulating solder, PTFE solder, mineral-filled insulating solder, polyimide (PI) solder, or phenolic resin solder. In one embodiment, the third insulating solder 83 can be applied by any one of the following methods: screen printing, scraper, electrophoresis, spin coating, pressure injection, or preforming.

[0081] In one embodiment, the fourth insulating solder 84 is any one of the following materials: glass-filled insulating solder, PTFE solder, mineral-filled insulating solder, polyimide (PI) solder, or phenolic resin solder. In one embodiment, the fourth insulating solder 84 can be applied by any one of the following methods: screen printing, scraper, electrophoresis, spin coating, pressure injection, or preforming.

[0082] In one embodiment, the “low expansion coefficient conductive metal gasket” is a copper gasket.

[0083] In one embodiment, the first lower low-expansion coefficient conductive metal gasket 713 is a copper gasket. In one embodiment, the first upper low-expansion coefficient conductive metal gasket 723 is a copper gasket. In one embodiment, the second lower low-expansion coefficient conductive metal gasket 733 is a copper gasket. In one embodiment, the second upper low-expansion coefficient conductive metal gasket 743 is a copper gasket.

[0084] In one embodiment, the “conductive metal layer” is a copper layer.

[0085] In one embodiment, the first lower conductive metal layer 12 is a copper layer. In one embodiment, the first upper conductive metal layer 13 is a copper layer. In one embodiment, the second lower conductive metal layer 22 is a copper layer. In one embodiment, the second upper conductive metal layer 23 is a copper layer. In one embodiment, the third lower conductive metal layer 32 is a copper layer. In one embodiment, the third upper conductive metal layer 33 is a copper layer. In one embodiment, the fourth lower conductive metal layer 42 is a copper layer. In one embodiment, the fourth upper conductive metal layer 43 is a copper layer. In one embodiment, the fifth lower conductive metal layer 52 is a copper layer. In one embodiment, the fifth upper conductive metal layer 53 is a copper layer.

[0086] In one embodiment, the predetermined substrate 31 having the conductive hole is a third ceramic substrate.

[0087] In one embodiment, the first solder layer 61 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the second solder layer 712 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the third solder layer 62 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the fourth solder layer 63 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the fifth solder layer 722 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the sixth solder layer 64 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the seventh solder layer 732 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides). In one embodiment, the eighth solder layer 742 can refer to tin powder (tin powder can be melted after heating to weld objects on both sides).

[0088] In one embodiment, the first hole 24 passes through the first ceramic substrate 11 . In one embodiment, the first hole 24 passes through the first lower conductive metal layer 12 . In one embodiment, the first hole 24 passes through the first upper conductive metal layer 13 .

[0089] In one embodiment, the first ceramic substrate 11, the first upper conductive metal layer 13, the first solder layer 61, the second lower conductive metal layer 22, the second ceramic substrate 21, the second upper conductive metal layer 23, the third solder layer 62, the third lower conductive metal layer 32, the predetermined substrate 31 with conductive holes, and the third upper conductive metal layer 33 are stacked in sequence from top to bottom.

[0090] In addition, the present invention embeds the power chip into the ceramic substrate, and then stacks and connects the chip through the circuit layer of the ceramic substrate. Since the structure of the present invention does not require the use of wire bonding electrical connection methods, there is no need to consider the excessive loss and chip overheating caused by fatigue failure of the wires at high temperatures. Secondly, since the chips are connected in a stacked manner, the length of the entire current loop is greatly reduced, the parasitic inductance is extremely low, the introduced voltage fluctuations are small, the energy loss and current oscillations are also smaller, and the stability of the system is increased. Due to the use of an embedded structure, the heat dissipation path of the chip is increased, and a high thermal conductivity ceramic substrate is used, the upper and lower outermost substrates can be integrated with a heat sink, which greatly improves the heat dissipation performance of the entire system. Since the output end of the power module of the structure of the present invention is shielded by the upper DC+ and lower DC- ends, there is almost no common-mode capacitance, which makes it easy to deal with the common-mode noise problem.

[0091] Further, see Figures 1 to 8As a specific embodiment of the embedded stack packaging method provided by the present invention, S10: the upper surface of the predetermined substrate 31 having a conductive hole is covered with a third upper conductive metal layer 33; the predetermined substrate 31 having a conductive hole is provided with a conductive hole, and the conductive hole is filled with a conductor 91; the third upper conductive metal layer 33 is electrically connected to the third lower conductive metal layer 32 through the conductor 91; S11: a fourth solder layer 63 is formed on the third upper conductive metal layer 33; S12: a fourth ceramic substrate 41 and a first upper chip 721 are prepared; wherein, the lower surface of the fourth ceramic substrate 41 is covered with a fourth lower conductive metal layer 42, and the upper surface of the fourth ceramic substrate 41 is covered with a fourth upper conductive metal layer 43; the fourth lower conductive metal layer 42 is laid on the fourth solder layer 63; the first upper chip 721 is embedded in the second hole on the fourth ceramic substrate 41;

[0092] S13: forming a fifth solder layer 722 on the upper surface of the first upper chip 721; S14: laying a first upper low-expansion coefficient conductive metal pad 723 on the fifth solder layer 722; integrating and fixing the first upper chip 721, the predetermined substrate 31 with the conductive hole, and the fourth ceramic substrate 41 by heat treatment; S15: forming a sixth solder layer 64 on the upper surface of the fourth upper conductive metal layer 43 and the upper surface of the first upper low-expansion coefficient conductive metal pad 723; S16: injecting the second insulating solder 82 into the first upper chip 721 and In the gap between the fourth ceramic substrate 41 ("the gap between the first upper chip 721 and the fourth ceramic substrate 41", i.e., the second gap 93); S17: prepare the fifth ceramic substrate 51 and cover the lower surface of the fifth ceramic substrate 51 with the fifth lower conductive metal layer 52; S18: place the fifth lower conductive metal layer 52 on the sixth solder layer 64; integrate and fix the fourth ceramic substrate 41 and the fifth ceramic substrate 51 through heat treatment; the fifth lower conductive metal layer 52 is electrically connected to the third upper conductive metal layer 33 through the first upper chip 721.

[0093] In this way, the upper surface of the predetermined substrate 31 with a conductive hole is covered with a third upper conductive metal layer 33; a conductive hole is opened on the predetermined substrate 31 with a conductive hole, and the conductive hole is filled with a conductor 91, and the third upper conductive metal layer 33 is connected to the third lower conductive metal layer 32 by a wire through the conductor 91; the lower surface of the fourth ceramic substrate 41 is covered with a fourth lower conductive metal layer 42, and a fourth solder layer 63 is provided between the fourth lower conductive metal layer 42 and the third upper conductive metal layer 33. After heating, the fourth solder layer 63 can fix the third upper conductive metal layer 33 and the fourth lower conductive metal layer 42, and the third upper conductive metal layer 33 and the fourth lower conductive metal layer 42 can be conductively connected through the fourth solder layer 63; a second hole is opened on the fourth ceramic substrate 41, and a first upper chip 721 is embedded in the second hole; the upper surface of the first upper chip 721 is covered with a fifth solder layer 722, and the fifth solder layer 722 is covered with a first upper low expansion coefficient conductive metal gasket 723, and the fifth solder layer 722 is heated. After heating, the first upper low-expansion coefficient conductive metal gasket 723 and the first upper chip 721 can be fixed, and the first upper low-expansion coefficient conductive metal gasket 723 and the first upper chip 721 can be conductively connected through the fifth solder layer 722; the sixth solder layer 64 is covered on the first upper low-expansion coefficient conductive metal gasket 723 and the fourth upper conductive metal layer 43; the fifth lower conductive metal layer 52 of the fifth ceramic substrate 51 is attached to the sixth solder layer 64, and the sixth solder layer 64 can be fixed to the fifth lower conductive metal layer 52 and the first upper low-expansion coefficient conductive metal gasket 723 after heating, and the fifth lower conductive metal layer 52 and the first upper low-expansion coefficient conductive metal gasket 723 can be conductively connected through the sixth solder layer 64; that is, the first upper chip 721 is encapsulated in the second hole, which reduces the package size and is more secure; the fifth lower conductive metal layer 52 can be electrically connected through the first upper low-expansion coefficient conductive metal gasket 723, the first upper chip 721, and the third upper conductive metal layer 33 in sequence.

[0094] In one embodiment, the second hole penetrates the fourth ceramic substrate 41. In one embodiment, the second hole penetrates the fourth lower conductive metal layer 42. In one embodiment, the second hole penetrates the fourth upper conductive metal layer 43.

[0095] In one embodiment, the conductive hole is processed by any one of laser drilling, mechanical drilling, jetting, and etching.

[0096] In one embodiment, the electrical conductor is a copper pillar.

[0097] In one embodiment, the copper pillars are formed by any one of electroplating, chemical vapor deposition, magnetron sputtering, and chemical plating.

[0098] Further, see Figures 1 to 8As a specific embodiment of the embedded stack packaging method provided by the present invention, the first solder layer 61, the second solder layer 712, the third solder layer 62, the fourth solder layer 63, and the fifth solder layer 722 can respectively adopt any one of a variety of solder coating and transfer methods; the various solder coating and transfer methods include: dispensing, screen printing, inkjet printing, steel mesh printing, and spraying.

[0099] Further, see Figures 1 to 8 As a specific embodiment of the embedded stack packaging method provided by the present invention, the first solder layer 61, the second solder layer 712, the third solder layer 62, the fourth solder layer 63, and the fifth solder layer 722 can respectively adopt any one of a variety of solder materials; the various solder materials include: nanometal solder, gold-tin solder, lead-tin solder, copper-tin solder, and tin-silver-copper solder.

[0100] Further, see Figures 1 to 8 As a specific embodiment of the embedded stack packaging method provided by the present invention, the first ceramic substrate 11, the second ceramic substrate 21, the predetermined substrate 31 with conductive holes, the fourth ceramic substrate 41, and the fifth ceramic substrate 51 can respectively adopt any one of a variety of ceramic materials; the various ceramic materials include: ALN, Al2O3, and SI3N4.

[0101] Further, see Figures 1 to 8 As a specific embodiment of the embedded stack packaging method provided by the present invention, it also includes: a first lower conductive metal layer 12 laid on the bottom of the first ceramic substrate 11 and used for heat dissipation, and a fifth upper conductive metal layer 53 laid on the top of the fifth ceramic substrate 51 and used for heat dissipation.

[0102] Further, see Figures 1 to 8As a specific embodiment of the embedded stack packaging method provided by the present invention, step S6 further includes: a second lower chip 731; the second lower chip 731 is embedded in the third hole 25 on the second ceramic substrate 21; the upper surface of the second lower chip 731 is covered with a seventh solder layer 732, and the seventh solder layer 732 is covered with a second lower low expansion coefficient conductive metal gasket 733; the third solder layer 62 covers the upper surface of the second lower low expansion coefficient conductive metal gasket 733; the third lower conductive metal layer 32 is connected to the second lower chip 731 through the second lower chip 731. The first upper conductive metal layer 13 is electrically connected. Step S15 further includes: a second upper chip 741; the second upper chip 741 is embedded in the fourth hole of the fourth ceramic substrate 41; the upper surface of the second upper chip 741 is covered with an eighth solder layer 742, and the eighth solder layer 742 is covered with a second upper low-expansion coefficient conductive metal pad 743; the sixth solder layer 64 covers the upper surface of the second upper low-expansion coefficient conductive metal pad 743; the fifth lower conductive metal layer 52 is electrically connected to the third upper conductive metal layer 33 through the second upper chip 741. In this way, the fifth lower conductive metal layer 52 is electrically connected to the third upper conductive metal layer 33 in sequence through the eighth solder layer 742, the second upper low-expansion coefficient conductive metal pad 743, the second upper chip 741, and the third upper conductive metal layer 33; and the third lower conductive metal layer 32 is electrically connected to the first upper conductive metal layer 13 in sequence through the seventh solder layer 732, the second lower low-expansion coefficient conductive metal pad 733, the second lower chip 731, and the first upper conductive metal layer 13.

[0103] In one embodiment, the third insulating solder 83 is injected between the second lower chip 731 and the inner wall of the third hole 25 .

[0104] In one embodiment, the fourth insulating solder 84 is injected between the second upper chip 741 and the inner wall of the fourth hole.

[0105] Further, see Figures 1 to 8As a specific embodiment of the embedded stack packaging method provided by the present invention, the first lower chip 711 is a MOS tube, the second lower chip 731 is a diode, the first upper chip 721 is a MOS tube, and the second upper chip 741 is a diode; the first upper conductive metal layer 13 includes: a first circuit and a second circuit; the first circuit is electrically connected to the source of the first lower chip 711, and the first circuit is electrically connected to the anode of the second lower chip 731; the second circuit is connected to the gate of the first lower chip 711; the third upper conductive metal layer 33 includes: a third circuit, a fourth circuit; the The three circuits are electrically connected to the source of the first upper chip 721, the third circuit is electrically connected to the anode of the second upper chip 741; the third circuit is electrically connected to the cathode of the second lower chip 731; the fourth circuit is connected to the gate of the first upper chip 721; the third circuit is electrically connected to the drain of the first lower chip 711; the fifth lower conductive metal layer 52 is electrically connected to the drain of the first upper chip 721, and the fifth lower conductive metal layer 52 is electrically connected to the cathode of the second upper chip 741; the fifth lower conductive metal layer 52 is electrically connected to the positive pole of the power supply, and the first circuit is electrically connected to the negative pole of the power supply. In this way, the source of the first lower chip 711 is electrically connected to the first circuit on the first upper conductive metal layer 13, an electrode of the second lower chip 731 is electrically connected to the first circuit, and the gate of the first lower chip 711 is electrically connected to the second circuit on the first upper conductive metal layer 13; the drain of the first lower chip 711 is electrically connected to the third circuit; the source of the first upper chip 721 is electrically connected to the third circuit on the third upper conductive metal layer 33, an electrode of the second upper chip 741 is electrically connected to the third circuit, and the gate of the first upper chip 721 is electrically connected to the fourth circuit on the third upper conductive metal layer 33; the current of the fifth lower conductive metal layer 52 can reach the third upper conductive metal layer 33 through the second upper chip 741, and the current of the fifth lower conductive metal layer 52 can pass through the drain of the first upper chip 721 and then pass through the first upper chip 721 and reach the third upper conductive metal layer 33.

[0106] In one embodiment, the second lower low expansion coefficient conductive metal gasket 733 and the second upper low expansion coefficient conductive metal gasket 743 can be made of any one of the following materials: Mo, W, CuNi.

[0107] In one embodiment, the third circuit is electrically connected to the drain of the first lower chip 711 through the first lower low thermal expansion coefficient conductive metal pad 713 .

[0108] In one embodiment, the third circuit is electrically connected to the second lower chip 731 through the second lower low thermal expansion coefficient conductive metal pad 733 .

[0109] In one embodiment, the fifth lower conductive metal layer 52 is electrically connected to the drain of the first upper chip 721 through the first upper low expansion coefficient conductive metal pad 723 .

[0110] In one embodiment, the fifth lower conductive metal layer 52 is electrically connected to the second upper chip 741 through the second upper low expansion coefficient conductive metal pad 743 .

[0111] In one embodiment, the fifth lower conductive metal layer 52 is electrically connected to the positive electrode of the power supply, and the first circuit is electrically connected to the negative electrode of the power supply. In this way, the positive electrode DC+ and the negative electrode DC- of the power supply can play a shielding role for the chip in the middle.

[0112] See also Figure 9 , the embedded stacked package structure can also be compared with the Figure 6 different.

[0113] See also Figures 1 to 8 The present invention also provides an embedded stacked package structure, comprising: a first ceramic substrate 11, a first solder layer 61, a second ceramic substrate 21, a first lower chip 711, a second solder layer 712, a first lower low expansion coefficient conductive metal gasket 713, a third solder layer 62, a first insulating solder 81, and a predetermined substrate 31 with a conductive hole; the first upper conductive metal layer 13 is covered on the upper surface of the first ceramic substrate 11; the first solder layer 61 is formed on the first upper conductive metal layer 13; wherein the lower surface of the second ceramic substrate 21 is covered with the second lower conductive metal layer 22, and the upper surface of the second ceramic substrate 21 is covered with the second upper conductive metal layer 23; the second lower conductive metal layer 22 is laid on the first solder layer 61; the first lower chip 711 is embedded in the first hole 24 on the second ceramic substrate 21; the second solder layer 712 is formed on the upper surface of the first lower chip 711; the first lower low expansion coefficient conductive metal gasket 713 is formed on the upper surface of the first lower chip 711; the first upper conductive metal layer 13 is covered on the upper surface of the first ceramic substrate 11; the first upper conductive metal layer 13 is covered on the upper surface of the first ceramic substrate 11; the first upper conductive metal layer 13 is covered on the lower surface of the second ceramic substrate 11; the second upper conductive metal layer 23 is covered on the upper surface of the second ceramic substrate 11; the second lower conductive metal layer 22 is laid on the first solder layer 61; the first lower chip 711 is embedded in the first hole 24 on the second ceramic substrate 21; the second solder layer 712 is formed on the upper surface of the first lower chip 711; the first lower low expansion coefficient conductive metal gasket 713 is formed on the upper surface of the first lower chip 711; the first upper conductive metal layer 13 is covered on the upper surface of the first ceramic substrate 1 Several conductive metal gaskets 713 are laid on the second solder layer 712; the first lower chip 711, the second ceramic substrate 21 and the first ceramic substrate 11 are integrated and fixed by heat treatment; the third solder layer 62 is formed on the upper surface of the second upper conductive metal layer 23 and the upper surface of the first lower low expansion coefficient conductive metal gasket 713; the first insulating solder 81 is filled in the gap between the first lower chip 711 and the second ceramic substrate 21 ("the gap between the first lower chip 711 and the second ceramic substrate 21", i.e., the third gap 94); the lower surface of the predetermined substrate 31 with conductive holes is covered with the third lower conductive metal layer 32; the third lower conductive metal layer 32 is placed on the third solder layer 62, and the third lower conductive metal layer 32 is electrically connected to the first upper conductive metal layer 13 through the first lower chip 711; the predetermined substrate 31 with conductive holes is integrated and fixed with the second ceramic substrate 21 by heat treatment.

[0114] In this way, the upper surface of the first ceramic substrate 11 is covered with the first upper conductive metal layer 13; the lower surface of the second ceramic substrate 21 is covered with the second lower conductive metal layer 22; the first solder layer 61 is covered on the first upper conductive metal layer 13; the second lower conductive metal layer 22 is covered on the first solder layer 61; there is a first solder layer 61 between the second lower conductive metal layer 22 and the first upper conductive metal layer 13, and the first solder layer 61 can fix the first upper conductive metal layer 13 and the second lower conductive metal layer 22 after heating, and the first upper conductive metal layer 13 and the second lower conductive metal layer 22 can be conductively connected through the first solder layer 61; a first hole 24 is opened on the second ceramic substrate 21, and a first lower chip 711 is embedded in the first hole 24; the upper surface of the first lower chip 711 is covered with a second solder layer 712, and the second solder layer 712 is covered with a first lower low expansion coefficient conductive metal gasket 713, and the second solder layer 712 can fix the first lower low expansion coefficient conductive metal gasket after heating The first lower low expansion coefficient conductive metal gasket 713 and the first lower chip 711, the first lower low expansion coefficient conductive metal gasket 713 can be conductively connected to the first lower chip 711 through the second solder layer 712; the first lower low expansion coefficient conductive metal gasket 713 and the second upper conductive metal layer 23 are covered with a third solder layer 62; the third lower conductive metal layer 32 of the predetermined substrate 31 with a conductive hole is attached to the third solder layer 62, and the third solder layer 62 can fix the third lower conductive metal layer 32 and the first lower low expansion coefficient conductive metal gasket 713 after heating, and the third lower conductive metal layer 32 can be conductively connected to the first lower low expansion coefficient conductive metal gasket 713 through the third solder layer 62; that is, the first lower chip 711 is encapsulated in the first hole 24, which reduces the package size and is more secure; the third lower conductive metal layer 32 can be electrically connected through the first lower low expansion coefficient conductive metal gasket 713, the first lower chip 711, and the first upper conductive metal layer 13 in sequence.

[0115] Further, see Figures 1 to 8, as a specific embodiment of the embedded stack packaging method provided by the present invention, it also includes: a third upper conductive metal layer 33, a fourth solder layer 63, a fourth ceramic substrate 41, a first upper chip 721, a fifth solder layer 722, a first upper low expansion coefficient conductive metal gasket 723, a sixth solder layer 64, and a fifth ceramic substrate 51; the third upper conductive metal layer 33 covers the upper surface of the predetermined substrate 31 with a conductive hole; a conductive hole is opened on the predetermined substrate 31 with a conductive hole, and the conductive hole is filled with a conductor 91; the third upper conductive metal layer 33 is electrically connected to the third lower conductive metal layer 32 through the conductor 91; the fourth solder layer 63 is formed on the third upper conductive metal layer 33; wherein the lower surface of the fourth ceramic substrate 41 is covered with the fourth lower conductive metal layer 42, and the upper surface of the fourth ceramic substrate 41 is covered with the fourth upper conductive metal layer 43; the fourth lower conductive metal layer 42 is laid on the fourth solder layer 63; the first upper chip 721 is embedded in the second hole; a fifth solder layer 722 is formed on the upper surface of the first upper chip 721; a first upper low expansion coefficient conductive metal gasket 723 is laid on the fifth solder layer 722; the first upper chip 721, the predetermined substrate 31 with the conductive hole and the fourth ceramic substrate 41 are integrated and fixed by heat treatment; a sixth solder layer 64 is formed on the upper surface of the fourth upper conductive metal layer 43 and the upper surface of the first upper low expansion coefficient conductive metal gasket 723; a second insulating solder 82 is injected into the gap between the first upper chip 721 and the fourth ceramic substrate 41 ("the gap between the first upper chip 721 and the fourth ceramic substrate 41", i.e., the fourth gap 95); the lower surface of the fifth ceramic substrate 51 is covered with a fifth lower conductive metal layer 52; the fifth lower conductive metal layer 52 is attached to the sixth solder layer 64; the fourth ceramic substrate 41 and the fifth ceramic substrate 51 are integrated and fixed by heat treatment; the fifth lower conductive metal layer 52 is electrically connected to the third upper conductive metal layer 33 through the first upper chip 721.

[0116] In this way, the upper surface of the predetermined substrate 31 with a conductive hole is covered with a third upper conductive metal layer 33; a conductive hole is opened on the predetermined substrate 31 with a conductive hole, and the conductive hole is filled with a conductor 91, and the third upper conductive metal layer 33 is connected to the third lower conductive metal layer 32 by a wire through the conductor 91; the lower surface of the fourth ceramic substrate 41 is covered with a fourth lower conductive metal layer 42, and a fourth solder layer 63 is provided between the fourth lower conductive metal layer 42 and the third upper conductive metal layer 33. After heating, the fourth solder layer 63 can fix the third upper conductive metal layer 33 and the fourth lower conductive metal layer 42, and the third upper conductive metal layer 33 and the fourth lower conductive metal layer 42 can be conductively connected through the fourth solder layer 63; a second hole is opened on the fourth ceramic substrate 41, and a first upper chip 721 is embedded in the second hole; the upper surface of the first upper chip 721 is covered with a fifth solder layer 722, and the fifth solder layer 722 is covered with a first upper low expansion coefficient conductive metal gasket 723, and the fifth solder layer 722 is heated. After heating, the first upper low-expansion coefficient conductive metal gasket 723 and the first upper chip 721 can be fixed, and the first upper low-expansion coefficient conductive metal gasket 723 and the first upper chip 721 can be conductively connected through the fifth solder layer 722; the sixth solder layer 64 is covered on the first upper low-expansion coefficient conductive metal gasket 723 and the fourth upper conductive metal layer 43; the fifth lower conductive metal layer 52 of the fifth ceramic substrate 51 is attached to the sixth solder layer 64, and the sixth solder layer 64 can be fixed to the fifth lower conductive metal layer 52 and the first upper low-expansion coefficient conductive metal gasket 723 after heating, and the fifth lower conductive metal layer 52 and the first upper low-expansion coefficient conductive metal gasket 723 can be conductively connected through the sixth solder layer 64; that is, the first upper chip 721 is encapsulated in the second hole, which reduces the package size and is more secure; the fifth lower conductive metal layer 52 can be electrically connected through the first upper low-expansion coefficient conductive metal gasket 723, the first upper chip 721, and the third upper conductive metal layer 33 in sequence.

[0117] Further, see Figures 1 to 8As a specific embodiment of the embedded stack packaging method provided by the present invention, it also includes: a second lower chip 731; the second lower chip 731 is embedded in the third hole 25 on the second ceramic substrate 21; the upper surface of the second lower chip 731 is covered with a seventh solder layer 732, and the seventh solder layer 732 is covered with a second lower low expansion coefficient conductive metal gasket 733; the third solder layer 62 covers the upper surface of the second lower low expansion coefficient conductive metal gasket 733; the third lower conductive metal layer 32 is electrically connected to the first upper conductive metal layer 13 through the second lower chip 731; the second upper chip 741 is embedded in the fourth ceramic substrate 41 The upper fourth hole; the upper surface of the second upper chip 741 is covered with an eighth solder layer 742, and the eighth solder layer 742 is covered with a second upper low expansion coefficient conductive metal gasket 743; the sixth solder layer 64 covers the upper surface of the second upper low expansion coefficient conductive metal gasket 743; the fifth lower conductive metal layer 52 is electrically connected to the third upper conductive metal layer 33 through the second upper chip 741; the first lower chip 711 is a MOS tube, the second lower chip 731 is a diode, the first upper chip 721 is a MOS tube, and the second upper chip 741 is a diode; the first upper conductive metal layer 13 includes: a first circuit and a second circuit; the first circuit and the first circuit are electrically connected The source of the lower chip 711 is electrically connected, the first circuit is electrically connected to the anode of the second lower chip 731; the second circuit is connected to the gate of the first lower chip 711; the third upper conductive metal layer 33 includes: a third circuit, a fourth circuit; the third circuit is electrically connected to the source of the first upper chip 721, the third circuit is electrically connected to the anode of the second upper chip 741; the third circuit is electrically connected to the cathode of the second lower chip 731; the fourth circuit is connected to the gate of the first upper chip 721; the third upper conductive metal layer 33 serves as an output electrode; the third circuit is electrically connected to the drain of the first lower chip 711, the third lower conductive metal layer 32 is electrically connected to the second The cathode of the lower chip 731 is electrically connected; the current of the first upper conductive metal layer 13 can reach the third upper conductive metal layer 33 through the second lower chip 731; the current of the first upper conductive metal layer 13 can pass through the source of the first lower chip 711 and then pass through the first lower chip 711 and reach the third upper conductive metal layer 33; the third circuit is electrically connected to the drain of the first lower chip 711; the fifth lower conductive metal layer 52 is electrically connected to the drain of the first upper chip 721, and the fifth lower conductive metal layer 52 is electrically connected to the cathode of the second upper chip 741; the fifth lower conductive metal layer 52 is electrically connected to the positive pole of the power supply, and the first circuit is electrically connected to the negative pole of the power supply.In this way, the source of the first lower chip 711 is electrically connected to the first circuit on the first upper conductive metal layer 13, an electrode of the second lower chip 731 is electrically connected to the first circuit, and the gate of the first lower chip 711 is electrically connected to the second circuit on the first upper conductive metal layer 13; the drain of the first lower chip 711 is electrically connected to the third circuit; the source of the first upper chip 721 is electrically connected to the third circuit on the third upper conductive metal layer 33, an electrode of the second upper chip 741 is electrically connected to the third circuit, and the gate of the first upper chip 721 is electrically connected to the fourth circuit on the third upper conductive metal layer 33; the current of the fifth lower conductive metal layer 52 can reach the third upper conductive metal layer 33 through the second upper chip 741, and the current of the fifth lower conductive metal layer 52 can pass through the drain of the first upper chip 721 and then pass through the first upper chip 721 and reach the third upper conductive metal layer 33.

[0118] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and substitutions can be made without departing from the technical principles of the present invention. These improvements and substitutions should also be regarded as the scope of protection of the present invention.

Claims

1. An embedded stacking packaging method, characterized in that: include: S1: preparing a first ceramic substrate and covering the upper surface of the first ceramic substrate with a first upper conductive metal layer; S2: forming a first solder layer on the first upper conductive metal layer; S3: comprising: preparing a second ceramic substrate and a first lower chip; wherein the lower surface of the second ceramic substrate is covered with a second lower conductive metal layer, and the upper surface of the second ceramic substrate is covered with a second upper conductive metal layer; the second lower conductive metal layer is laid on the first solder layer; and the first lower chip is embedded in the first hole on the second ceramic substrate; S4: forming a second solder layer on the upper surface of the first lower chip; S5: laying a first lower low expansion coefficient conductive metal gasket on the second solder layer; integrating and fixing the first lower chip, the second ceramic substrate, and the first ceramic substrate through heat treatment; S6: comprising: forming a third solder layer on the upper surface of the second upper conductive metal layer and the upper surface of the first lower low expansion coefficient conductive metal pad; S7: injecting a first insulating solder into the gap between the first lower chip and the second ceramic substrate; S8: preparing a predetermined substrate having a conductive hole and covering the lower surface of the predetermined substrate having the conductive hole with a third lower conductive metal layer; S9: placing the third lower conductive metal layer on the third solder layer, the third lower conductive metal layer being electrically connected to the first upper conductive metal layer through the first lower chip; integrating and fixing the predetermined substrate with the conductive hole and the second ceramic substrate through heat treatment.

2. The embedded stack packaging method according to claim 1, wherein: S10: Covering the upper surface of the predetermined substrate with the conductive hole with a third upper conductive metal layer; the predetermined substrate with the conductive hole has a conductive hole formed thereon, and the conductive hole is filled with a conductor; The third upper conductive metal layer is electrically connected to the third lower conductive metal layer through the conductor; S11: forming a fourth solder layer on the third upper conductive metal layer; S12: Preparing a fourth ceramic substrate and a first upper chip; wherein the lower surface of the fourth ceramic substrate is covered with a fourth lower conductive metal layer, and the upper surface of the fourth ceramic substrate is covered with a fourth upper conductive metal layer; the fourth lower conductive metal layer is laid on the fourth solder layer; and the first upper chip is embedded in the second hole on the fourth ceramic substrate; S13: forming a fifth solder layer on the upper surface of the first upper chip; S14: laying a first upper low expansion coefficient conductive metal gasket on the fifth solder layer; integrating and fixing the first upper chip, the predetermined substrate having the conductive hole, and the fourth ceramic substrate through heat treatment; S15: forming a sixth solder layer on the upper surface of the fourth upper conductive metal layer and the upper surface of the first upper low expansion coefficient conductive metal pad; S16: injecting a second insulating solder into the gap between the first upper chip and the fourth ceramic substrate; S17: preparing a fifth ceramic substrate and covering the lower surface of the fifth ceramic substrate with a fifth lower conductive metal layer; S18: placing the fifth lower conductive metal layer on the sixth solder layer; integrating and fixing the fourth ceramic substrate and the fifth ceramic substrate through heat treatment; and electrically connecting the fifth lower conductive metal layer to the third upper conductive metal layer through the first upper chip.

3. The embedded stack packaging method according to claim 2, wherein: Any one of the conductive metal layers is processed by any one of the following processes: DBC, DPC, AMB, HTCC, LTCC; Any one of the conductive metal layers is made of any one of the following materials: Mo-Mn, W, Mo, W-Cu, Cu, Ag, Al; The conductive holes on the predetermined substrate having the conductive holes are filled by any one of the following methods: electroplating, chemical plating, molten copper filling, and vacuum plating; The predetermined substrate with conductive holes is made of any one of the following materials: ceramic substrate, ABF substrate, pi substrate; The first solder layer, the second solder layer, the third solder layer, the fourth solder layer, and the fifth solder layer are respectively formed by any one of a plurality of solder coating and transfer methods; The plurality of solder coating transfer methods include: dispensing, screen printing, inkjet printing, steel screen printing, spraying; and / or The first solder layer, the second solder layer, the third solder layer, the fourth solder layer, and the fifth solder layer are respectively made of any one of a plurality of solder materials; the plurality of solder materials include: nano metal solder, gold-tin solder, lead-tin solder, copper-tin solder, and tin-silver-copper solder.

4. The embedded stack packaging method according to claim 2, wherein: The first ceramic substrate, the second ceramic substrate, the predetermined substrate with the conductive hole, the fourth ceramic substrate, and the fifth ceramic substrate are respectively made of any one of a plurality of ceramic materials; the plurality of ceramic materials include: ALN, Al2O3, and SI3N4.

5. The embedded stack packaging method according to claim 2, wherein: Also includes: A first lower conductive metal layer is laid on the bottom of the first ceramic substrate and used for heat dissipation, and a fifth upper conductive metal layer is laid on the top of the fifth ceramic substrate and used for heat dissipation.

6. The embedded stack packaging method according to claim 2, wherein: Step S6 further includes: forming a second lower chip; embedding the second lower chip in the third hole of the second ceramic substrate; covering the upper surface of the second lower chip with a seventh solder layer, and covering the seventh solder layer with a second lower low expansion coefficient conductive metal gasket; covering the upper surface of the second lower low expansion coefficient conductive metal gasket with a third solder layer; and electrically connecting the third lower conductive metal layer to the first upper conductive metal layer through the second lower chip. The step S15 also includes: a second upper chip; the second upper chip is embedded in the fourth hole on the fourth ceramic substrate; the upper surface of the second upper chip is covered with an eighth solder layer, and the eighth solder layer is covered with a second upper low-expansion coefficient conductive metal gasket; the sixth solder layer covers the upper surface of the second upper low-expansion coefficient conductive metal gasket; the fifth lower conductive metal layer is electrically connected to the third upper conductive metal layer through the second upper chip.

7. The embedded stack packaging method according to claim 6, wherein: The first lower chip is a MOS transistor, the second lower chip is a diode, the first upper chip is a MOS transistor, and the second upper chip is a diode; The first upper conductive metal layer includes: a first circuit and a second circuit; the first circuit is electrically connected to the source of the first lower chip, and the first circuit is electrically connected to the anode of the second lower chip; the second circuit is connected to the gate of the first lower chip; the third upper conductive metal layer includes: a third circuit and a fourth circuit; the third circuit is electrically connected to the source of the first upper chip, and the third circuit is electrically connected to the anode of the second upper chip; the third circuit is electrically connected to the cathode of the second lower chip; the fourth circuit is connected to the gate of the first upper chip; the third circuit is electrically connected to the drain of the first lower chip; the fifth lower conductive metal layer is electrically connected to the drain of the first upper chip, and the fifth lower conductive metal layer is electrically connected to the cathode of the second upper chip; the fifth lower conductive metal layer is electrically connected to the positive pole of the power supply, and the first circuit is electrically connected to the negative pole of the power supply; And / or the second lower low expansion coefficient conductive metal gasket and the second upper low expansion coefficient conductive metal gasket are respectively made of any one of the following materials: Mo, W, CuNi.

8. Embedded stacked package structure, characterized in that: include: a first ceramic substrate; covering the upper surface of the first ceramic substrate with a first upper conductive metal layer; a first solder layer; the first solder layer is formed on the first upper conductive metal layer; a second ceramic substrate; A first lower chip; wherein the lower surface of the second ceramic substrate is covered with a second lower conductive metal layer, and the upper surface of the second ceramic substrate is covered with a second upper conductive metal layer; the second lower conductive metal layer is laid on the first solder layer; and the first lower chip is embedded in the first hole on the second ceramic substrate; a second solder layer; the second solder layer is formed on the upper surface of the first lower chip; a first lower low expansion coefficient conductive metal gasket; the first lower low expansion coefficient conductive metal gasket is laid on the second solder layer; the first lower chip, the second ceramic substrate and the first ceramic substrate are integrated and fixed by heat treatment; a third solder layer; the third solder layer being formed on an upper surface of the second upper conductive metal layer and an upper surface of the first lower low expansion coefficient conductive metal pad; A first insulating solder is filled in the gap between the first lower chip and the second ceramic substrate; A predetermined substrate having a conductive hole; the lower surface of the predetermined substrate having a conductive hole is covered with a third lower conductive metal layer; the third lower conductive metal layer is attached to the third solder layer, and the third lower conductive metal layer is electrically connected to the first upper conductive metal layer through the first lower chip; the predetermined substrate having a conductive hole is integrated and fixed with the second ceramic substrate by heat treatment.

9. The embedded stack package structure according to claim 8, wherein: Also includes: a third upper conductive metal layer; The third upper conductive metal layer covers the upper surface of the predetermined substrate having the conductive hole; The predetermined substrate with conductive holes is provided with conductive holes, and the conductive holes are filled with a conductor; The third upper conductive metal layer is electrically connected to the third lower conductive metal layer through the conductor; a fourth solder layer; the fourth solder layer being formed on the third upper conductive metal layer; a fourth ceramic substrate; A first upper chip; wherein the lower surface of the fourth ceramic substrate is covered with a fourth lower conductive metal layer, and the upper surface of the fourth ceramic substrate is covered with a fourth upper conductive metal layer; the fourth lower conductive metal layer is laid on the fourth solder layer; and the first upper chip is embedded in the second hole on the fourth ceramic substrate; a fifth solder layer; the fifth solder layer is formed on the upper surface of the first upper chip; A first upper low-expansion coefficient conductive metal gasket is provided; the first upper low-expansion coefficient conductive metal gasket is laid on the fifth solder layer; the first upper chip, the predetermined substrate having the conductive hole, and the fourth ceramic substrate are integrated and fixed by heat treatment; a sixth solder layer; the sixth solder layer is formed on the upper surface of the fourth upper conductive metal layer and the upper surface of the first upper low expansion coefficient conductive metal pad; a second insulating solder is injected into the gap between the first upper chip and the fourth ceramic substrate; A fifth ceramic substrate; the lower surface of the fifth ceramic substrate is covered with a fifth lower conductive metal layer; the fifth lower conductive metal layer is attached to the sixth solder layer; the fourth ceramic substrate and the fifth ceramic substrate are integrated and fixed by heat treatment; the fifth lower conductive metal layer is electrically connected to the third upper conductive metal layer through the first upper chip.

10. The embedded stack package structure according to claim 9, wherein: Also includes: a second lower chip and a second upper chip; the second lower chip is embedded in the third hole of the second ceramic substrate; the upper surface of the second lower chip is covered with a seventh solder layer, and the seventh solder layer is covered with a second lower low-expansion coefficient conductive metal gasket; the third solder layer covers the upper surface of the second lower low-expansion coefficient conductive metal gasket; The third lower conductive metal layer is electrically connected to the first upper conductive metal layer through the second lower chip; the second upper chip is embedded in the fourth hole of the fourth ceramic substrate; the upper surface of the second upper chip is covered with an eighth solder layer, and the eighth solder layer is covered with a second upper low-expansion coefficient conductive metal gasket; the sixth solder layer covers the upper surface of the second upper low-expansion coefficient conductive metal gasket; the fifth lower conductive metal layer is electrically connected to the third upper conductive metal layer through the second upper chip; the first lower chip is a MOS transistor, the second lower chip is a diode, the first upper chip is a MOS transistor, and the second upper chip is a diode; The first upper conductive metal layer includes: a first circuit and a second circuit; the first circuit is electrically connected to the source of the first lower chip, the first circuit is electrically connected to the anode of the second lower chip; the second circuit is connected to the gate of the first lower chip; the third upper conductive metal layer includes: a third circuit and a fourth circuit; the third circuit is electrically connected to the source of the first upper chip, the third circuit is electrically connected to the anode of the second upper chip; the fourth circuit is connected to the gate of the first upper chip; The third upper conductive metal layer serves as an output electrode; The third circuit is electrically connected to the drain of the first lower chip, and the third lower conductive metal layer is electrically connected to the cathode of the second lower chip; The current in the first upper conductive metal layer can reach the third upper conductive metal layer through the second lower chip; the current in the first upper conductive metal layer can reach the third upper conductive metal layer through the first lower chip after passing through the source electrode of the first lower chip; The fifth lower conductive metal layer is electrically connected to the drain of the first upper chip, and the fifth lower conductive metal layer is electrically connected to the cathode of the second upper chip; the fifth lower conductive metal layer is electrically connected to the positive electrode of the power supply, and the first circuit is electrically connected to the negative electrode of the power supply; The third lower conductive metal layer is electrically connected to the drain of the first lower chip, and the third lower conductive metal layer is electrically connected to the cathode of the second lower chip; the first upper conductive metal layer is electrically connected to the positive pole of the power supply, and the first circuit is electrically connected to the negative pole of the power supply.

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