A method for preparing TBC solar cells by laser crystallization

Abstract

The present invention relates to the field of solar cells, and discloses a method for preparing TBC solar cells by laser crystallization. The method of the present invention first generates a phosphorus diffusion layer, then deposits a boron-doped amorphous silicon layer, and then converts the boron-doped amorphous silicon into a boron-doped polycrystalline silicon layer by means of local laser crystallization, which can effectively improve the crystallization rate and reduce the contact resistance, thereby improving the battery performance. The method of the present invention can effectively avoid the serious internal expansion of phosphorus atoms during the high-temperature boron diffusion process of the conventional process, and provides another new path for the current TBC solar cell preparation process.

Description

Technical Field

[0001] The invention relates to the field of solar cells, and in particular to a method for preparing a TBC solar cell by laser crystallization. Background Art

[0002] At present, the high-temperature preparation process of TBC solar cells is generally to first deposit a p-poly-Si layer (p-region) on the back of the silicon wafer and then deposit n-poly-Si (n-region) again on this basis. For example, patent CN118136703A discloses a TBC back contact structure crystalline silicon solar cell and its preparation method, which first performs boron diffusion on the first polycrystalline silicon layer of the N-type silicon substrate that has completed the deposition process to form a P-type polycrystalline silicon layer (i.e., a boron diffusion layer), and then performs phosphorus diffusion on the second polycrystalline silicon layer of the N-type silicon substrate that has completed the deposition process to form an N-type polycrystalline silicon layer (i.e., a phosphorus diffusion layer). The main reason for the above-mentioned sequential process is that the temperature during the boron diffusion preparation process is relatively high (900~1050℃), while the temperature during the phosphorus diffusion preparation process is relatively low (800~900℃). If phosphorus diffusion is performed first and then boron diffusion, the phosphorus atoms in the first formed phosphorus diffusion layer will be excessively diffused into the interior of the silicon wafer substrate in the subsequent boron diffusion high temperature environment, thereby seriously affecting the battery. V oc value, reducing battery performance.

[0003] The method of first using boron diffusion to prepare p-poly-Si and then using phosphorus diffusion to prepare n-poly-Si ("boron first, phosphorus later" process) can reduce the risk of excessive diffusion of doped atoms into the silicon substrate due to excessive temperature compared to the "phosphorus first, boron later" process. However, the temperature required for the n-poly-Si deposition process is still relatively high, which will still have a significant impact on the properties of the p-poly-Si film. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an unconventional method for preparing a TBC solar cell by first generating a phosphorus diffusion layer (n-region) and then generating a boron-doped polysilicon layer (p-region). The present invention can realize the localized and rapid preparation of a boron-doped polysilicon layer with better performance by means of laser crystallization technology, and can effectively avoid the serious internal expansion of phosphorus atoms in conventional processes, thus providing a new path for the current high-temperature preparation process of TBC solar cells.

[0005] The specific technical solution of the present invention is: a method for preparing a TBC solar cell by laser crystallization, which specifically comprises the following steps:

[0006] S1. Double-sided polishing of silicon wafers.

[0007] S2. Deposit a tunnel oxide layer and an intrinsic polysilicon layer on the back side at one time.

[0008] The purpose of constructing the intrinsic polysilicon layer is to provide a basis for the subsequent phosphorus diffusion.

[0009] S3. Phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer are converted into a phosphorus diffusion layer and a PSG layer respectively.

[0010] S4. Laser patterning and grooving are used to remove the PSG layer in the boron-doped area (p-area) and the isolation area design area (the p-area and n-area on the back of the final finished battery are arranged in an interdigitated manner).

[0011] Ensure that the PSG layer in the laser patterned area is removed, paving the way for subsequent alkaline cleaning to remove the tunneling oxide layer and phosphorus diffusion layer at the bottom of the area.

[0012] S5. Alkaline cleaning to remove the various deposited layers (tunneling oxide layer, phosphorus diffusion layer) in the slotted area of ​​S4.

[0013] Under the corrosion of alkaline solution, the tunnel oxide layer and phosphorus diffusion layer in the S4 slot area are removed by corrosion, so that the back of the silicon wafer in this area is fully exposed. In the non-slot area, the bottom deposition layer is protected from corrosion and retained due to the protection of the PSG layer.

[0014] S6. Secondary deposition of a tunneling oxide layer, a boron-doped amorphous silicon layer, and a boron-doped mask layer on the back side.

[0015] Since the process temperature of depositing the boron-doped amorphous silicon layer by PECVD is relatively low, the risk of boron atoms diffusing into the phosphorus diffusion layer and causing it to invert can be effectively reduced during the process. In addition, the main purpose of establishing a boron-doped mask layer is: (1) During the subsequent laser crystallization process, the mask layer can serve as a buffer layer to prevent excessive laser energy from directly causing damage to the amorphous silicon layer; (2) During the laser crystallization process, the boron atoms inside the boron-doped mask layer can be further pushed into the boron-doped amorphous silicon layer, increasing its doping concentration, reducing the subsequent gold / semiconductor contact resistance, and improving the battery FF Numeric value.

[0016] S7, laser patterning once crystallizes the boron-doped amorphous silicon layer in the grooved area of ​​S4, so that the boron-doped amorphous silicon layer in the area is converted into a boron-doped polycrystalline silicon layer.

[0017] Since the crystallization rate of the boron-doped amorphous silicon layer is low, it will not only seriously affect the contact resistance between the subsequent gate line and the p-region, but also increase the parasitic absorption of the layer to affect the optical performance of the battery. To this end, the present invention selectively crystallizes the boron-doped amorphous silicon layer in the p-region design area to improve its crystallization rate. Due to the high energy of the laser, the treatment process will be accompanied by a rapid increase in the local temperature, which will increase the crystallization rate of this part. In addition, since the conventional tubular high-temperature boron diffusion process often takes a long time (≥5 h), and the laser crystallization process takes a shorter time, the process time can be further shortened and the preparation cost can be reduced; more importantly, the laser processing accuracy is high, and only the boron-doped amorphous silicon layer deposited in the preset boron-doped area is crystallized, while the boron-doped amorphous silicon layer deposited in the non-preset boron-doped area will not be affected, thereby avoiding the risk of laser high-temperature annealing causing the boron atoms at the bottom of the preset phosphorus diffusion area to diffuse into the phosphorus diffusion layer and invert it.

[0018] During the laser patterning primary crystallization process, the initial boron-doped mask layer will be simultaneously exposed to the high temperature of the laser, which can push these boron atoms into the bottom boron-doped polysilicon layer, increase its doping concentration, and improve the subsequent gold / semiconductor contact performance.

[0019] S8. Laser patterning of a preset gate line region of the secondary crystallized boron-doped polysilicon layer so that the boron-doped polysilicon layer in the region is converted into a high-concentration / high-crystallization boron-doped polysilicon layer.

[0020] In order to further reduce the contact resistance between the subsequent gate line and the boron-doped polysilicon layer, the present invention further adopts laser patterning to secondary crystallize the preset gate line area of ​​the boron-doped polysilicon layer, on the one hand, the crystallization rate of this part of the boron-doped polysilicon layer is further improved (the higher the crystallization rate of the polysilicon layer, the lower the subsequent gold / semi contact resistance); on the other hand, the boron atoms in the boron-doped mask layer are more effectively pushed to the polysilicon area of ​​the bottom preset gate line, so that the doping concentration is further increased, and the p-poly-Si is transformed into p + -poly-Si, reduce contact resistance and improve subsequent battery FF Numeric value.

[0021] S9, chain oxygen treatment.

[0022] During the laser crystallization process, the boron-doped mask layer will inevitably be partially damaged, which will cause the boron-doped polysilicon layer at the bottom of the damaged boron-doped mask layer to be affected by wet texturing in the subsequent wet texturing process, thereby reducing the performance of the entire battery. In order to repair the boron-doped mask layer damaged by laser crystallization, chain oxidation is used for repair treatment. After chain oxidation treatment, the laser-damaged position on the silicon wafer surface can be repaired to ensure that this part is not damaged during the subsequent alkaline cleaning and texturing process.

[0023] S10, laser patterning and grooving to remove the boron-doped mask layer in the phosphorus diffusion area and the isolation area design area.

[0024] Removing the boron-doped mask layer in the above region can pave the way for subsequent wet cleaning to remove the boron-doped polysilicon layer at the bottom of the region.

[0025] S11, removing the coating on the front and side surfaces of the silicon wafer.

[0026] S12, cleaning and texturing: Put the silicon wafer with the coating removed into an alkaline texturing tank for wet cleaning and integrated texturing. Since there is no coating on the front of the silicon wafer, an effective light-trapping velvet surface (i.e., pyramid velvet surface) can be formed during the texturing process; for the back of the silicon wafer, since the boron-doped mask layer at the bottom of the phosphorus diffusion area is removed during the S10 process, the boron-doped polysilicon layer can be effectively corroded and removed during the wet cleaning process until the PSG layer stops, so that the bottom phosphorus diffusion layer is not damaged; at the same time, the boron-doped mask layer in the isolation area design area is also removed by laser, and this part of the silicon substrate can be exposed and a pyramid velvet surface can be formed during the wet cleaning + texturing process. In addition, since the boron-doped mask layer in the p-region is not laser-processed, the bottom boron-doped polysilicon layer and the high-concentration / high-crystallization boron-doped polysilicon layer can still be protected from damage during the wet process. Finally, the residual PSG layer and boron-doped mask layer on the back of the silicon wafer can be removed by acid pickling.

[0027] S13, Double-sided coating: After double-sided coating, a passivation anti-reflection layer is generated on the front and back sides of the silicon wafer.

[0028] S14, screen printing, sintering, light injection, to produce TBC solar cells.

[0029] Preferably, in S3, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, and O2 flow rate 500~1000 sccm; then O2 is introduced for oxidation promotion, the temperature is 850~950℃, the promotion time is 20~60 min, and the O2 flow rate is 1000~10000 sccm, to generate a PSG layer with a thickness of 30~70 nm.

[0030] Preferably, in S6, the crystallization rate of the boron-doped amorphous silicon layer is 10-50%.

[0031] Preferably, in S6, the deposition conditions of the boron-doped amorphous silicon layer are: BH3 flow rate 1000~5000 sccm, SiH4 flow rate 2000~4000 sccm, H2 flow rate 5000~10000 sccm, temperature 400~600°C, time 5~20 min, working pressure 2000~5000 mTorr, and the thickness of the generated boron-doped amorphous silicon layer is 100~300 nm.

[0032] Preferably, in S6, the deposition conditions of the boron-doped mask layer are: BH3 flow rate 2000~10000 sccm, SiH4 flow rate 1000~5000 sccm, N2O flow rate 9000~11000 sccm, temperature 400~600°C, time 60~300 s, working pressure 1000~3000 mTorr, and the thickness of the boron-doped mask layer is 10~100 nm.

[0033] Since the process temperature of depositing boron-doped amorphous silicon by PECVD is relatively low, the risk of boron atoms diffusing into the phosphorus diffusion layer and causing it to be inverted can be effectively reduced during the process.

[0034] Preferably, in S7, the crystallization rate of the boron-doped polysilicon layer formed after the laser patterning and primary crystallization is 60-85%.

[0035] Preferably, in S7, the conditions for laser patterning primary crystallization are: laser wavelength 400-600 nm, pulse time 10-20 ns, frequency 10-20 KHz, power 1-10 W, time 1-20 s.

[0036] Preferably, in S8, the crystallization rate of the boron-doped polysilicon layer after laser secondary crystallization is 85-95%.

[0037] Preferably, in S8, the conditions for laser patterning secondary crystallization are: laser wavelength 400-600 nm, pulse time 50-100 ns, frequency 100-500 KHz, power 40-100 W, time 1-20 s.

[0038] Preferably, in S9, the chain oxidation treatment includes: turning the back side of the silicon wafer upside down and performing chain oxidation treatment; the chain oxidation belt speed is 3-4 m / min, the temperature is 750-800°C, and the oxygen flow rate is 100-300 L / min.

[0039] Compared with the prior art, the beneficial effects of the present invention are:

[0040] The method of the present invention first generates a phosphorus diffusion layer, then deposits a boron-doped amorphous silicon layer, and then transforms the boron-doped amorphous silicon into a boron-doped polysilicon layer by means of local laser crystallization, which can effectively improve the crystallization rate and reduce the contact resistance, thereby improving the battery performance. The method of the present invention can effectively avoid the serious internal expansion of phosphorus atoms during the high-temperature boron diffusion process of the conventional process, and provides another new path for the current TBC solar cell preparation process. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 Schematic diagram of the structure of the silicon wafer after double-sided polishing.

[0042] Figure 2 Schematic diagram of the structure of the silicon wafer after phosphorus diffusion.

[0043] Figure 3 Schematic diagram of the structure after laser patterning of PSG layer on silicon wafer + alkaline cleaning.

[0044] Figure 4 Schematic diagram of the structure after depositing a tunneling oxide layer, a boron-doped amorphous silicon layer, and a boron-doped mask layer on a silicon wafer.

[0045] Figure 5 This is a schematic diagram of the structure of the boron-doped layer in the S4 groove area after the silicon wafer is laser patterned and crystallized once.

[0046] Figure 6 This is the Raman spectrum of the boron-doped layer in the S4 groove area of ​​the silicon wafer after laser patterning and primary crystallization.

[0047] Figure 7 This is a schematic diagram of the structure after the gate line area is preset in the boron-doped layer of the S4 groove area of ​​the silicon wafer laser patterning secondary crystallization.

[0048] Figure 8 Schematic diagram of the structure after laser patterning of silicon wafers to remove the boron-doped mask layer in the phosphorus diffusion area and isolation area design area + cleaning and texturing.

[0049] Fig. 9 This is a schematic diagram of the structure of the finished TBC solar cell.

[0050] The reference numerals in the drawings are: N-type single crystal silicon wafer 1; tunneling oxide layer 2; phosphorus diffusion layer 3; PSG layer 4; boron-doped amorphous silicon layer 5; boron-doped mask layer 6; boron-doped polysilicon layer 7; high concentration / high crystallization boron-doped polysilicon layer 8; pyramid velvet surface 9; passivation anti-reflection layer 10; electrode layer 11. DETAILED DESCRIPTION

[0051] The present invention will be further described below in conjunction with the embodiments.

[0052] S1. Double-sided polishing of silicon wafers.

[0053] In some specific implementation cases, the double-sided polishing process includes: selecting an N-type single crystal silicon wafer 1 cut by diamond wire, with a thickness of 100-200 μm, placing it in an alkali polishing tank containing alkali solution, and double-sided polishing for 6-8 minutes at 75-85° C., with a polishing thickness of 3-7 μm and a thinning amount of 0.35-0.45 g, such as Figure 1 shown.

[0054] S2, depositing a tunnel oxide layer and an intrinsic polysilicon layer on the back surface at once. The purpose of constructing the intrinsic polysilicon layer is to provide a basis for subsequent phosphorus diffusion.

[0055] In some specific implementation cases, when depositing the tunnel oxide layer, the gas flow rate of O2 is 10000~80000 sccm, the reaction temperature is 400~800°C, the time is 200~1000 s, and the thickness of the tunnel oxide layer is 2~10 nm.

[0056] In some specific implementation cases, when depositing an intrinsic polysilicon layer on the tunnel oxide layer, the SiH4 gas flow rate is 300~2000 sccm, the reaction temperature is 500~700°C, the time is 2~4 h, the working gas pressure is 100~500mTorr, and the thickness of the intrinsic polysilicon layer is 100~300 nm.

[0057] S3, phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer are converted into a phosphorus diffusion layer 3 and a PSG layer 4 respectively, so that the surface of the silicon wafer is a tunneling oxide layer 2, a phosphorus diffusion layer 3 and a PSG layer 4 in sequence, such as Figure 2 shown.

[0058] In some specific implementation cases, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, and O2 flow rate 500~1000 sccm; then O2 is introduced for oxidation promotion, the temperature is 850~950℃, the promotion time is 20~60 min, and the O2 flow rate is 1000~10000 sccm, generating a PSG layer with a thickness of 30~70nm.

[0059] S4, laser patterning and grooving to remove the PSG layer in the boron doped area (p area) and the isolation area design area (the p area and n area on the back of the final finished battery are interdigitated). Ensure that the PSG layer in the laser patterning area is removed to pave the way for subsequent alkaline cleaning to remove the tunneling oxide layer and phosphorus diffusion layer at the bottom of the area.

[0060] In some specific implementation cases, picosecond laser is used for patterning grooving, and the conditions are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0061] S5, alkaline cleaning to remove the deposited layers (tunneling oxide layer 2, phosphorus diffusion layer 3) in the slotted area of ​​S4. Under the corrosion of the alkaline solution, the tunneling oxide layer 2 and phosphorus diffusion layer 3 in the slotted area of ​​S4 are corroded and removed, so that the back of the silicon wafer in this area is fully exposed. In the non-slotted area, due to the protection of the PSG layer 4, the bottom deposited layer can be protected from corrosion and retained, such as Figure 3 shown.

[0062] In some specific implementation cases, the alkaline cleaning conditions are: temperature of 75-85° C., time of 200-600 s, and corrosion depth of 1-5 μm.

[0063] S6, secondary deposition of tunnel oxide layer 2, boron-doped amorphous silicon layer 5, and boron-doped mask layer 6 on the back side, such as Figure 4 As shown. Since the process temperature of depositing the boron-doped amorphous silicon layer by PECVD is relatively low, the risk of boron atoms diffusing into the phosphorus diffusion layer and causing it to invert can be effectively reduced during the process. In addition, the main purposes of establishing a boron-doped mask layer are: (1) During the subsequent laser crystallization process, the mask layer can serve as a buffer layer to prevent excessive laser energy from directly causing damage to the amorphous silicon layer; (2) During the laser crystallization process, the boron atoms inside the boron-doped mask layer can be further pushed into the boron-doped amorphous silicon layer, thereby increasing the doping concentration, reducing the subsequent gold / semi contact resistance, and improving the battery FF Numeric value.

[0064] In some specific implementation cases, the deposition conditions of the tunnel oxide layer are: the reaction gas is N2O, the flow rate is 8000~50000 sccm, the temperature is 400~550°C, the time is 100~500 s, the working pressure is 1000~3000mTorr, and the thickness of the generated tunnel oxide layer is 2~10 nm.

[0065] In some specific implementation cases, the deposition conditions of the boron-doped amorphous silicon layer are: BH3 flow rate 1000~5000 sccm, SiH4 flow rate 2000~4000 sccm, H2 flow rate 5000~10000 sccm, temperature 400~600°C, time 5~20min, working pressure 2000~5000 mTorr, the thickness of the generated boron-doped amorphous silicon layer is 100~300 nm, and the crystallization rate is 10~50%.

[0066] In some specific implementation cases, the deposition conditions of the boron-doped mask layer are: BH3 flow rate 2000~10000 sccm, SiH4 flow rate 1000~5000 sccm, N2O flow rate 9000~11000 sccm, temperature 400~600°C, time 60~300 s, working pressure 1000~3000 mTorr, and the thickness of the boron-doped mask layer is 10~100 nm.

[0067] S7, laser patterning and crystallizing the boron-doped amorphous silicon layer in the grooved area of ​​S4, such as Figure 5 As shown, the boron-doped amorphous silicon layer in this region is converted into a boron-doped polysilicon layer 7. Figure 6 It can be seen that the Raman spectrum peak of amorphous silicon is located at 480 cm -1 The crystalline silicon peak is located at 510~520 cm-1 After laser crystallization, the main Raman peak changes from 480 cm -1 Move to 510~520 cm -1 .

[0068] Since the crystallization rate of the boron-doped amorphous silicon layer is low, it will not only seriously affect the contact resistance between the subsequent gate line and the p-region, but also increase the parasitic absorption of the layer to affect the optical performance of the battery. To this end, the present invention selectively crystallizes the boron-doped amorphous silicon layer in the p-region design area to improve its crystallization rate. Due to the high energy of the laser, the treatment process will be accompanied by a rapid increase in the local temperature, which will increase the crystallization rate of this part. In addition, since the conventional tubular high-temperature boron diffusion process often takes a long time (≥5 h), and the laser crystallization process takes a shorter time, the process time can be further shortened and the preparation cost can be reduced; more importantly, the laser processing accuracy is high, and only the boron-doped amorphous silicon layer deposited in the preset boron-doped area is crystallized, while the boron-doped amorphous silicon layer deposited in the non-preset boron-doped area will not be affected, thereby avoiding the risk of laser high-temperature annealing causing the boron atoms at the bottom of the preset phosphorus diffusion area to diffuse into the phosphorus diffusion layer and invert it. During the laser patterning primary crystallization process, the initial boron-doped mask layer will be simultaneously exposed to the high temperature of the laser, which can push these boron atoms into the bottom boron-doped polysilicon layer, increase its doping concentration, and improve the subsequent gold / semiconductor contact performance.

[0069] In some specific implementation cases, the conditions for laser patterning primary crystallization are: laser wavelength 400-600 nm, pulse time 10-20 ns, frequency 10-20 KHz, power 1-10 W, time 1-20 s. The crystallization rate of the boron-doped polysilicon layer formed after laser patterning primary crystallization is 60-85%.

[0070] S8, laser patterning the preset gate line area of ​​the secondary crystallized boron-doped polysilicon layer, so that the boron-doped polysilicon layer in the area is converted into a high-concentration / high-crystallization boron-doped polysilicon layer 8, such as Figure 7 In order to further reduce the contact resistance between the subsequent gate line and the boron-doped polysilicon layer, the present invention further adopts laser patterning to secondary crystallize the preset gate line area of ​​the boron-doped polysilicon layer, on the one hand, the crystallization rate of this part of the boron-doped polysilicon layer is further improved (the higher the crystallization rate of the polysilicon layer, the lower the subsequent gold / semi contact resistance); on the other hand, the boron atoms in the boron-doped mask layer are more effectively pushed to the polysilicon area of ​​the bottom preset gate line, so that the doping concentration is further increased, and the p-poly-Si is transformed into p + -poly-Si, reduce contact resistance and improve subsequent battery FF Numeric value.

[0071] In some specific implementation cases, the conditions for laser patterning secondary crystallization are: laser wavelength 400-600nm, pulse time 50-100ns, frequency 100-500KHz, power 40-100W, time 1-20s. The crystallization rate of the boron-doped polysilicon layer after laser secondary crystallization is 85-95%.

[0072] S9, chain oxidation treatment. During the laser crystallization process, the boron-doped mask layer will inevitably be partially damaged, which will cause the boron-doped polysilicon layer at the bottom of the damaged boron-doped mask layer to be affected by the wet texturing in the subsequent wet texturing process, thereby reducing the performance of the entire battery. In order to repair the boron-doped mask layer damaged by laser crystallization, chain oxidation is used for repair treatment. After chain oxidation treatment, the laser treatment damaged position on the silicon wafer surface can be repaired to ensure that this part is not damaged during the subsequent alkaline cleaning and texturing process.

[0073] In some specific implementation cases, the chain oxidation treatment includes: turning the back side of the silicon wafer upside down and performing chain oxidation treatment; the chain oxygen belt speed is 3~4 m / min, the temperature is 750~800℃, and the oxygen flow rate is 100~300 L / min.

[0074] S10, laser patterning and grooving to remove the boron-doped mask layer in the phosphorus diffusion area and the isolation area design area. Removing the boron-doped mask layer in the above area can pave the way for subsequent wet cleaning to remove the various deposition layers at the bottom of the area.

[0075] In some specific implementation cases, the conditions for laser patterning grooving are: laser wavelength 400~600 nm, frequency 500~700 KHz, marking speed 40000~50000 mm / s, power 10~50 W, and processing time 1~5 s.

[0076] S11, removing the coating on the front and side surfaces of the silicon wafer.

[0077] In some specific implementation cases, the silicon wafer is subjected to a chain machine (acid etching) to remove the coating on the front and side surfaces of the silicon wafer.

[0078] S12, cleaning and texturing: put the silicon wafer after the coating is removed into the alkaline texturing tank for wet cleaning and texturing integrated treatment. Figure 8As shown, since there is no coating layer on the front side of the silicon wafer, an effective light-trapping velvet surface (i.e., pyramid velvet surface 9) can be formed during the texturing process; for the back side of the silicon wafer, since the boron-doped mask layer at the bottom of the phosphorus diffusion area is removed during the S10 process, the boron-doped polysilicon layer can be effectively etched and removed during the wet cleaning process until the PSG layer stops, so that the bottom phosphorus diffusion layer is not damaged; at the same time, the boron-doped mask layer in the isolation area design area is also removed by laser, and this part of the silicon substrate can be exposed during the wet cleaning + texturing process to form a pyramid velvet surface 9. In addition, since the boron-doped mask layer in the p-region is not laser-processed, the bottom boron-doped polysilicon layer and the high-concentration / high-crystallization boron-doped polysilicon layer can still be protected from damage during the wet process. Finally, the residual PSG layer and boron-doped mask layer on the back side of the silicon wafer can be removed by pickling.

[0079] In some specific implementation cases, the silicon wafer after de-plating is placed in an alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein the temperature is maintained at 75-85°C for 6-12 minutes.

[0080] S13, double-sided coating: after double-sided coating, a passivation anti-reflection layer 10 is generated on the front and back sides of the silicon wafer.

[0081] S14, screen printing, sintering to form electrode layer 11, light injection, to obtain TBC solar cell, such as Fig. 9 shown.

[0082] Specific examples and comparative examples.

[0083] Example 1

[0084] S1. Double-sided polishing of silicon wafers: Select N-type single crystal silicon wafers 1 cut by diamond wire, with a thickness of 100-200 μm, put them into an alkaline polishing tank containing alkaline solution, and double-sided polish them at 75°C for 6 min. The polishing thickness is 4 μm, and the thinning amount is 0.42 g. Figure 1 shown.

[0085] S2, a tunnel oxide layer and an intrinsic polysilicon layer are deposited on the back at once. Specifically: when depositing the tunnel oxide layer, the gas flow rate of O2 is 40000 sccm, the reaction temperature is 600℃, the time is 600 s, and the thickness of the tunnel oxide layer is 3 nm. When depositing the intrinsic polysilicon layer on the tunnel oxide layer, the gas flow rate of SiH4 is 920 sccm, the reaction temperature is 550℃, the time is 3.3 h, the working gas pressure is 300 mTorr, and the thickness of the intrinsic polysilicon layer is about 290 nm.

[0086] S3, phosphorus diffusion, so that the inner layer and the surface layer of the intrinsic polysilicon layer are converted into a phosphorus diffusion layer 3 and a PSG layer 4 respectively, so that the surface of the silicon wafer is a tunneling oxide layer 2, a phosphorus diffusion layer 3 and a PSG layer 4 in sequence, such as Figure 2Specifically, the phosphorus diffusion conditions are as follows: phosphorus diffusion temperature 790°C, diffusion time 20 min, POCl3 carried by nitrogen with a flow rate of 1100 sccm, O2 flow rate 700 sccm; then O2 is introduced for oxidation advancement, the temperature is 890°C, the advancement time is 40 min, and the O2 flow rate is 3000 sccm, generating a PSG layer with a thickness of about 42 nm.

[0087] S4, laser patterning and grooving to remove the PSG layer in the boron doped area (p area) and the isolation area design area (the p area and n area on the back of the final finished battery are interdigitated). Specifically: picosecond laser patterning and grooving are performed under the following conditions: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 25 W, and processing time 2.7 s.

[0088] S5, alkaline cleaning to remove the deposited layers (tunneling oxide layer 2, phosphorus diffusion layer 3) in the S4 slot area. Specifically: the alkaline cleaning conditions are: temperature 75°C, time 400 s, and etching depth 3 μm. Under the corrosion of the alkaline solution, the tunneling oxide layer 2 and phosphorus diffusion layer 3 in the S4 slot area are corroded and removed, so that the back of the silicon wafer in this area is fully exposed. In the non-slot area, due to the protection of the PSG layer 4, its bottom deposited layer can be protected from corrosion and retained, such as Figure 3 shown.

[0089] S6, secondary deposition of tunnel oxide layer 2, boron-doped amorphous silicon layer 5, and boron-doped mask layer 6 on the back side, such as Figure 4 As shown. Specifically: the deposition conditions of the tunnel oxide layer are: the reaction gas is N2O, its flow rate is 20000 sccm, the temperature is 450℃, the time is 300 s, the working pressure is 1800 mTorr, and the thickness of the generated tunnel oxide layer is about 3 nm. The deposition conditions of the boron-doped amorphous silicon layer are: BH3 flow rate 2500 sccm, SiH4 flow rate 3000 sccm, H2 flow rate 8000 sccm, temperature 480℃, time 12min, working pressure 2700 mTorr, the thickness of the generated boron-doped amorphous silicon layer is about 290 nm, and the crystallization rate is 35%. The deposition conditions of the boron-doped mask layer are: BH3 flow rate 5000 sccm, SiH4 flow rate 1700 sccm, N2O flow rate 9500 sccm, temperature 520℃, time 120 s, working pressure 1600 mTorr, and the thickness of the boron-doped mask layer is about 50 nm.

[0090] S7, laser patterning and crystallizing the boron-doped amorphous silicon layer in the grooved area of ​​S4, such as Figure 5 As shown, the boron-doped amorphous silicon layer in this region is converted into a boron-doped polysilicon layer 7. Figure 6It can be seen that the Raman spectrum peak of amorphous silicon is located at 480 cm -1 The crystalline silicon peak is located at 520 cm -1 After laser crystallization, the main Raman peak changes from 480 cm -1 Move to 520 cm -1 Specifically, the conditions for the laser patterning primary crystallization are: laser wavelength 532 nm, pulse time 15 ns, frequency 12 KHz, power 8 W, time 5 s. The crystallization rate of the boron-doped polysilicon layer formed after the laser patterning primary crystallization is 82%.

[0091] S8, laser patterning the preset gate line area of ​​the secondary crystallized boron-doped polysilicon layer, so that the boron-doped polysilicon layer in the area is converted into a high-concentration / high-crystallization boron-doped polysilicon layer 8, such as Figure 7 Specifically, the conditions for laser patterning secondary crystallization are: laser wavelength 532 nm, pulse time 75 ns, frequency 300 KHz, power 80 W, time 12 s. The crystallization rate of the boron-doped polysilicon layer after laser secondary crystallization is 89%.

[0092] S9, chain oxidation treatment: turn the back of the silicon wafer upside down and perform chain oxidation treatment; the chain oxidation belt speed is 3.5 m / min, the temperature is 780℃, and the oxygen flow rate is 150 L / min.

[0093] S10, laser patterning and grooving to remove the boron-doped mask layer in the phosphorus diffusion area and the isolation area design area. Specifically, the conditions of the laser patterning and grooving are: laser wavelength 532 nm, frequency 600 KHz, marking speed 45000 mm / s, power 50 W, and processing time 3 s.

[0094] S11. Removing the coating on the front and side surfaces of the silicon wafer: using a chain machine (acid etching) to remove the coating on the front and side surfaces of the silicon wafer.

[0095] S12, cleaning and texturing: put the silicon wafer after winding and plating into the alkaline texturing tank for wet cleaning and texturing integrated treatment, wherein the temperature is maintained at 82℃ for 7 minutes. Figure 8As shown, since there is no coating layer on the front side of the silicon wafer, an effective light-trapping velvet surface (i.e., pyramid velvet surface 9) can be formed during the texturing process; for the back side of the silicon wafer, since the boron-doped mask layer at the bottom of the phosphorus diffusion area is removed during the S10 process, the boron-doped polysilicon layer can be effectively etched and removed during the wet cleaning process until the PSG layer stops, so that the bottom phosphorus diffusion layer is not damaged; at the same time, the boron-doped mask layer in the isolation area design area is also removed by laser, and this part of the silicon substrate can be exposed during the wet cleaning + texturing process to form a pyramid velvet surface 9. In addition, since the boron-doped mask layer in the p-region is not laser-processed, the bottom boron-doped polysilicon layer and the high-concentration / high-crystallization boron-doped polysilicon layer can still be protected from damage during the wet process. Finally, the residual PSG layer and boron-doped mask layer on the back side of the silicon wafer can be removed by pickling.

[0096] S13, double-sided coating: after double-sided coating, a passivation anti-reflection layer 10 is formed on the front and back sides of the silicon wafer. Specifically, an atomic layer deposition (ALD) method is used to first deposit AlO on the front and back sides of the processed silicon wafer. x The film is generated by the reaction of Al(CH3)3 and water vapor, with a thickness of about 8 nm and a process temperature of 250°C. Then SiN is deposited on both sides of the silicon wafer using a tubular PECVD device. x Thin film, SiN x The film thickness is about 90 nm and the refractive index is 2.0. x During thin film deposition, the reaction gases in the tubular chamber are SiH4 and NH3, the working pressure is 1600 mTorr, the power is 12000 W, the temperature is 440℃, the flow rate of SiH4 gas is 980 sccm, the flow rate of NH3 gas is 8000 sccm, the silicon-nitrogen ratio is 1:5, and the deposition time is 10 min.

[0097] S14, screen printing the coated silicon wafer on the back to form a metal contact, then sintering at 770°C to form an Ag-Si ohmic contact, forming an electrode layer 11, and finally performing light injection repair to obtain a final finished TBC solar cell, such as Fig. 9 shown.

[0098] Comparative Example 1

[0099] The only difference between Comparative Example 1 and Example 1 is that Comparative Example 1 does not include S7 laser primary crystallization treatment, S8 laser secondary crystallization treatment and S9 chain oxygen treatment, that is, it directly enters S10 after S6.

[0100] Comparative Example 2

[0101] The only difference between Comparative Example 2 and Example 1 is that the S8 laser secondary crystallization treatment is not included, that is, S9 is directly entered after S7.

[0102] Comparative Example 3

[0103] The difference between Comparative Example 3 and Example 1 is that in S6 , only a tunneling oxide layer and a boron-doped amorphous silicon layer are deposited, and the boron-doped mask layer 6 is not deposited.

[0104] Performance comparison

[0105] The performance of the finished TBC solar cells obtained in the above embodiments and comparative examples was tested, as shown in Table 1:

[0106] Table 1: Electrical performance data of different batteries

[0107]

[0108] From the data in Table 1, we can see that:

[0109] First, compared with Comparative Example 1, Example 1 adopts the "two-step method" laser crystallization form, which avoids the risk of excessive diffusion of boron atoms in the boron-doped layer into the phosphorus diffusion layer on the one hand; on the other hand, the boron-doped polysilicon layer has a higher crystallization rate, especially the boron-doped polysilicon layer preset gate line area, whose surface doping concentration and crystallization rate are higher, thereby making the gold / semiconductor contact resistance lower and the battery FF In contrast, in Comparative Example 1, since the boron-doped amorphous silicon layer was not effectively transformed into boron-doped polysilicon, the parasitic absorption of the battery was high and the contact resistance was poor, which affected the final battery performance.

[0110] Secondly, for Comparative Example 2, compared with Comparative Example 1, in Comparative Example 2, the boron-doped amorphous silicon is further crystallized and converted into a boron-doped polycrystalline silicon layer, thereby further improving the battery performance. However, compared with Example 1, the crystallization rate and surface doping concentration of the boron-doped polycrystalline silicon layer in the preset gate line area are still relatively low, resulting in a high subsequent gold / semi contact resistance, which affects the final performance of the battery.

[0111] Finally, for Comparative Example 3, since no boron-doped mask layer (buffer layer) is provided, on the one hand, excessive laser energy will result in direct damage to the boron-doped amorphous silicon layer during the subsequent laser crystallization process; on the other hand, the surface doping concentration of the boron-doped polysilicon layer in the preset gate line area cannot be further increased during the laser secondary crystallization process, resulting in the inability to further reduce the subsequent gold / semi contact resistance, which makes the battery FF The numerical improvement is limited, so the final electrical performance is lower than that of Example 1.

[0112] The raw materials and equipment used in the present invention, unless otherwise specified, are all commonly used raw materials and equipment in the art; the methods used in the present invention, unless otherwise specified, are all conventional methods in the art.

[0113] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any simple modification, change and equivalent transformation made to the above embodiment based on the technical essence of the present invention still falls within the protection scope of the technical solution of the present invention.

Claims

1. A method for preparing a TBC solar cell by laser crystallization, characterized in that include: S1, double-sided polishing of silicon wafer; S2, depositing a tunnel oxide layer and an intrinsic polysilicon layer on the back side; S3, phosphorus diffusion, converting the intrinsic polysilicon layer into a phosphorus diffusion layer and a PSG layer; S4, laser grooving to remove the PSG layer in the boron doped area and the isolation area design area; S5, alkali cleaning; S6, depositing a tunneling oxide layer, a boron-doped amorphous silicon layer, and a boron-doped mask layer on the back side; S7, laser once crystallizes the boron-doped amorphous silicon layer in the grooved area of ​​S4, with a wavelength of 400-600 nm, a pulse time of 10-20 ns, a frequency of 10-20 KHz, and a power of 1-10 W to form a boron-doped polysilicon layer; S8, laser secondary crystallization of the preset gate line area of ​​the boron-doped polysilicon layer, wavelength 400~600 nm, pulse time 50~100ns, frequency 100~500 KHz, power 40~100 W; S9, chain oxygen treatment; S10, laser grooving to remove the boron-doped mask layer in the phosphorus diffusion region and the isolation region design area; S11, removing the coating; S12, cleaning and velveting; S13, double-sided coating; S14, screen printing, sintering, light injection.

2. The method according to claim 1, characterized in that: In S3, the phosphorus diffusion conditions are: phosphorus diffusion temperature 750~850℃, diffusion time 5~30 min, POCl3 is carried by nitrogen with a flow rate of 500~1200 sccm, and O2 flow rate 500~1000 sccm; then O2 is introduced for oxidation advancement, the temperature is 850~950℃, the advancement time is 20~60 min, and the O2 flow rate is 1000~10000sccm.

3. The method according to claim 2, characterized in that: In S3, the thickness of the PSG layer is 30-70 nm.

4. The method according to claim 1, characterized in that: In S6, the crystallization rate of the boron-doped amorphous silicon layer is 10-50%.

5. The method according to claim 1 or 4, characterized in that: In S6, the deposition conditions of the boron-doped amorphous silicon layer are: BH3 flow rate 1000~5000 sccm, SiH4 flow rate 2000~4000 sccm, H2 flow rate 5000~10000 sccm, temperature 400~600°C, time 5~20 min, working pressure 2000~5000 mTorr.

6. The method according to claim 5, characterized in that: In S6, the thickness of the boron-doped amorphous silicon layer is 100-300 nm.

7. The method according to claim 1, characterized in that: In S6, the deposition conditions of the boron-doped mask layer are: BH3 flow rate 2000~10000 sccm, SiH4 flow rate 1000~5000 sccm, N2O flow rate 9000~11000 sccm, temperature 400~600°C, time 60~300 s, working pressure 1000~3000 mTorr, and the thickness of the boron-doped mask layer is 10~100 nm.

8. The method according to claim 4, characterized in that: In S7, the crystallization rate of the boron-doped polysilicon layer formed after the laser primary crystallization is 60-85%.

9. The method according to claim 8, characterized in that: In S8, the crystallization rate of the boron-doped polysilicon layer after laser secondary crystallization is 85-95%.

10. The method according to claim 1, characterized in that: In S9, the chain oxidation treatment includes: turning the back side of the silicon wafer upside down and performing chain oxidation treatment; the chain oxidation belt speed is 3~4 m / min, the temperature is 750~800℃, and the oxygen flow rate is 100~300 L / min.

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