Design, fabrication and integration method of on-chip energy storage chip

Abstract

The application discloses a design, manufacture and integration method of a crystal-on-energy storage chip, and belongs to the field of advanced microelectronic technology. According to the characteristics of the layered configuration of the current collector, electrode, diaphragm and electrolyte of the energy storage battery, a multi-wafer layered preparation method of the crystal-on-energy storage chip is innovatively proposed: a semiconductor manufacturing CMOS process is used to etch a chamber and a template in the same area of different wafers to provide a packaging shell for the energy storage chip; the current collector, positive / negative electrode and electrolyte are deposited and prepared on the upper and lower wafers respectively, and the crystal-on-energy storage chip is formed through low-temperature bonding of alignment marks; a deposition stripping process is used to form an RDL conductive circuit, a DRIE and Bosch process are used to prepare a TSV, the electrical connection of the crystal-on-energy storage chip and a multi-layer interface structure, a chip and a device is realized, and the integration degree of an intelligent system is improved. The application can obtain a high-performance, lightweight, high-integration and customizable energy storage chip, ensures stable power supply of miniaturized electronic equipment as an integrated energy chip, and provides a key core chip for an intelligent microsystem in the post-moore era.

Description

Technical fields:

[0001] This invention belongs to the field of advanced microelectronics technology, and more specifically relates to the design, manufacturing and integration methods of on-chip energy storage chips. Background technology:

[0002] The rapid development of advanced microelectronics has created new demands for on-chip energy storage chips. For example, miniaturized electronic devices such as microsensors, microactuators, microrobots, and implantable medical devices require integrated energy devices to ensure a stable current supply. Traditional sandwich-type electrochemical energy storage devices are difficult to integrate into certain microsystems due to limitations in battery size, form factor, and integrability. To date, micro monolithic energy storage devices are typically fabricated by using epitaxial growth, chemical / physical vapor deposition, and screen printing processes on a single wafer to prepare the functional structure, followed by electrolyte filling and final simple packaging. The main problems with this type of energy storage device are as follows: 1) Incompatibility between the fabrication process and CMOS process makes on-chip interconnection difficult; 2) Battery structural defects result in limited capacity. Micro-monocell batteries are made by stacking thin layers of functional materials on a single wafer, resulting in limited vertical height, less active material capacity, and lower single-cell capacity; 3) The battery is a discrete device, lacking in-plane or cross-surface interconnect metal circuits on the same wafer (substrate). Charging and discharging require external wires on the current collector (tabs) for interconnection, significantly reducing integration density; 4) Battery packaging technology remains in the demonstration and verification stage, with poor safety. Existing monolithic micro lithium-ion batteries use rigid plastic shells and adhesives for encapsulation, which are prone to failure after multiple charge-discharge cycles, making practical application difficult. Therefore, there is an urgent need to develop an on-chip energy storage chip with high capacity, lightweight, high integration, and customizability to meet the energy demands of intelligent microsystems in the post-Moore's Law era.

[0003] This invention discloses a method for designing, manufacturing, and integrating on-chip energy storage chips. Based on the characteristics of the layered configuration of energy storage batteries, including current collectors, electrodes, separators, and electrolytes, an innovative multi-wafer layered fabrication method for on-chip energy storage chips is proposed. Using CMOS semiconductor manufacturing processes, the multi-layered structure of the battery is fabricated on different wafers. Through wafer-level bonding, through-silicon vias (TSVs), and redistribution layers (RDLs), the chips are integrated and packaged to obtain high-performance, lightweight, highly integrated, and customizable energy storage chips, providing key core chips for intelligent microsystem architectures in the post-Moore's Law era. Summary of the Invention:

[0004] To address the shortcomings or improvement needs of existing technologies, this invention provides a highly integrated, miniaturized design and manufacturing method for energy storage chips suitable for intelligent microsystems in the post-Moore's Law era. It has the advantages of rich application scenarios, high performance, customizability, and high integration, and improves the integrability with multi-source environmental energy harvesting devices such as light and heat energy and back-end energy management chips, ensuring the energy supply of highly integrated and high-functional-density intelligent systems.

[0005] This invention proposes a method for designing, manufacturing, and integrating on-chip energy storage chips, employing the following technical solution:

[0006] The design, fabrication, and integration method for on-chip energy storage chips involves etching chambers and templates in the same area on different wafers to provide a packaging shell for the energy storage chip; depositing current collectors and positive / negative electrodes on the upper and lower wafers respectively and filling them with electrolyte; and bonding them with alignment marks to form the energy storage chip; and using TSVs and RDLs to achieve external electrical interconnection. The specific fabrication method includes the following steps:

[0007] (1) Anode layer wafer fabrication: Using CMOS semiconductor manufacturing technology, electrode chambers and TSV vias are etched in the corresponding areas of the silicon wafer, conductive materials are filled, current collectors are deposited, and anode materials are coated to form the anode of the energy storage chip. The specific steps are as follows.

[0008] S1 uses a double-polished silicon wafer. The front side of the silicon wafer is formed by photolithography and dry etching processes to create an electrode chamber of a certain depth.

[0009] Specifically, the process involves coating, pre-baking, exposure, post-baking, development, hardening, and removal of photoresist on the silicon wafer surface. Coating can be performed using spin coating, atomized spraying, or dry film application. The photoresist can be positive or negative.

[0010] S2, determine the size of the TSV conductive via diameter and arrange the geometric position of the array of TSV vias on the back side of the silicon wafer; then use photolithography and dry etching processes to etch the TSV vias on the back side to form a through-hole array from the back side to the electrode chamber.

[0011] S3 utilizes the thermal oxidation process of silicon to grow SiO2 on the entire wafer. x Insulating layer and barrier layer;

[0012] S4 uses conductive material to solid-fill TSV vias and performs chemical mechanical polishing (CMP) on the back side of the silicon wafer;

[0013] Specifically, conductive paste, metal materials, or other conductive materials are used to solidly fill TSV vias using processes such as negative pressure filling and electroplating; CMP process is used to planarize the back side of the silicon wafer and expose the conductive material inside the TSV vias; RDL is used to achieve electrical interconnection between the negative electrode of the energy storage chip and the outside world.

[0014] S5, using a deposition process, a certain thickness of conductive metal is uniformly deposited at the bottom of the front electrode chamber of a silicon wafer as a current collector.

[0015] Specifically, the current collector is uniformly deposited at the bottom of the electrode chamber and electrically interconnected with the conductive material filled in the TSV;

[0016] S6, using coating technology, uniformly sprays negative electrode paste onto the front electrode chamber of the silicon wafer until it is completely filled, and then forms a negative electrode layer wafer through vacuum high-temperature treatment;

[0017] (2) Preparation of the positive electrode-electrolyte layer wafer 1: Using the CMOS semiconductor manufacturing process, the positive electrode-electrolyte chamber and TSV via are etched in the corresponding area of ​​the silicon wafer, conductive material is filled, current collector is deposited, positive electrode material is coated and electrolyte is filled in sequence to form the positive electrode-electrolyte of the energy storage chip. The specific steps are as follows.

[0018] S1 provides double-polished silicon wafers. The front side of the silicon wafer is formed with photolithography and dry etching processes to create cavities of a certain depth, which serve as positive electrode-electrolyte filling chambers.

[0019] Specifically, the large-hole chamber, which serves as the electrolyte filling chamber, is etched first, followed by the small-hole chamber, which serves as the electrode chamber, with the centers of the two chambers aligned.

[0020] S2, repeat the negative electrode layer wafer fabrication steps S2-S5 to form a TSV conductive array from the back side to the electrode chamber and a current collector at the bottom of the electrode chamber, realizing the electrical interconnection between the positive electrode of the energy storage chip and the outside world.

[0021] S3, using coating technology, a positive electrode slurry is uniformly sprayed onto the front electrode chamber of the silicon wafer until it is completely filled, and then vacuum high-temperature treatment is performed to form a positive electrode layer;

[0022] S4, fill the electrolyte filling chamber with a diaphragm and electrolyte, gel electrolyte or solid electrolyte to form a positive electrode-electrolyte layer wafer;

[0023] Specifically, the filling of the diaphragm and electrolyte, gel electrolyte or solid electrolyte is carried out in a vacuum or inert gas environment;

[0024] (3) Preparation of the positive electrode-electrolyte layer wafer 2: Using the CMOS semiconductor manufacturing process, the positive electrode filling template is etched in the corresponding area of ​​the silicon wafer, the current collector is deposited, the positive electrode material is filled, and after curing, the positive electrode filling template is removed and the electrolyte is filled to form the positive electrode-electrolyte of the energy storage chip. The specific steps are as follows.

[0025] S1 provides a double-polished silicon wafer, which uses a deposition process to uniformly deposit a certain thickness of conductive metal on the back of the silicon wafer as a current collector.

[0026] S2, determine the size and spacing of the positive electrode pillars, and the arrangement of the positive electrode pillar array on the front side of the silicon wafer; use photolithography and dry etching processes to form a porous through-hole array on the front side of the silicon wafer as a positive electrode filling template;

[0027] S3 utilizes droplet technology to fill positive electrode slurry into a positive electrode filling template, and then forms a 3D positive electrode column array through vacuum high-temperature treatment.

[0028] Specifically, the positive electrode slurry should be filled to a certain height, but not completely.

[0029] S4, using silicon etching process to remove the positive electrode filling template, and completely fill the gel electrolyte or solid electrolyte to form a positive electrode-electrolyte layer wafer;

[0030] (4) The negative electrode layer wafer and the positive electrode-electrolyte layer wafer are bonded together by wafer bonding process to form an on-chip energy storage chip.

[0031] Specifically, during wafer bonding, wafers are sequentially mounted in special mechanical fixtures, with the negative electrode layer wafer placed above the positive electrode-electrolyte layer wafer. Alignment marks are used to align the bonding surfaces in a double-sided alignment manner. The bonding process is carried out in a vacuum or inert gas environment, and the bonding temperature should not be too high, using a low-temperature bonding method.

[0032] Furthermore, conductive metals are deposited on both sides of the bonded wafer, photolithography is performed, and combined with lift-off process and CMP, RDL conductive lines are formed to realize the electrical connection between the on-chip energy storage chip and the multilayer interface structure, chip and device.

[0033] Specifically, the array of TSV holes is geometrically distributed within the effective conductive area of ​​the on-chip energy storage chip, forming an effective electrical interconnect with the current collector in the front electrode chamber and the external circuit or RDL layer.

[0034] Specifically, RDL conductive lines can be pre-embedded on the front side of the negative electrode layer wafer and the positive electrode-electrolyte layer wafer using processes such as deposition, stripping, and polishing. Energy-consuming structures, chips, devices, and management circuits can be fabricated using similar processes. Then, TSV conductive vias can be used to achieve electrical interconnection between them and between them and the energy storage chip. At the same time, wafers with other functional chips, such as energy harvesting, sensing, and communication chips, can be further bonded to achieve electrical connection between the on-chip energy storage chip and the multi-layer interface structure, chip, and device, thereby improving the integration of intelligent systems.

[0035] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention. Other features of this application will become readily apparent from the following description. Attached image description:

[0036] Figure 1 This is a technical roadmap of an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the layout and mask pattern of a single on-chip energy storage chip in Embodiment 1 of the present invention;

[0038] Figure 3 This is a flowchart of the anode layer wafer fabrication process in Embodiment 1 of the present invention;

[0039] Figure 4 This is a flowchart of the positive electrode-electrolyte layer wafer fabrication process in Embodiment 1 of the present invention;

[0040] Figure 5 This is a wafer layout diagram of the energy storage chip according to an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the on-chip lithium-ion energy storage chip in Embodiment 1 of the present invention;

[0042] Figure 7 This is a schematic diagram of the layout and mask pattern of a single on-chip energy storage chip in Embodiment 2 of the present invention;

[0043] Figure 8 This is a flowchart of the positive electrode-electrolyte layer wafer fabrication process in Embodiment 2 of the present invention;

[0044] Figure 9 This is a schematic diagram of the on-chip 3D positive electrode lithium-ion energy storage chip in Embodiment 2 of the present invention; Detailed implementation method:

[0045] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by those skilled in the art without creative effort based on the embodiments in this application should fall within the scope of protection of this application.

[0046] like Figure 1The diagram shown is a technical roadmap of an embodiment of the present invention.

[0047] Example 1

[0048] A method for designing and manufacturing an on-chip lithium-ion energy storage chip specifically includes the following steps:

[0049] First, the wafer layout of the on-chip energy storage chip is designed according to customized requirements and process flow (including parameters such as chip size, shape, and internal structure dimensions), and a photomask is fabricated, such as... Figure 2 The diagram shows the layout and mask patterns A, B, and C of a single on-chip energy storage chip. Pattern A is the electrode chamber, pattern B is the TSV via array, and pattern C is the electrolyte filling chamber.

[0050] (1) Fabrication of the negative electrode layer wafer: such as Figure 3 The diagram shown is a flow chart of the anode layer wafer fabrication process.

[0051] Furthermore, a 300μm thick double-polished silicon wafer 1 is provided. After coating the front side of the silicon wafer 1 with a uniformly thick photoresist 2, a photolithographic pattern A is formed. After development and baking, a negative electrode chamber 3 with a diameter of 9mm and a depth of 150μm is etched on the front side of the silicon wafer using deep reactive ion etching (DRIE) combined with Bosch process. Finally, the photoresist patterned on the front side of the silicon wafer 1 is removed by dry or wet stripping.

[0052] Specifically, the dry photoresist removal process uses Ar+O2 or O2+CF4 gas. The chamber is filled with sufficient oxygen or argon and radio frequency is applied to the electrodes under stable vacuum conditions, causing the gas to generate active plasma to bombard the cleaning object. The wet photoresist removal process involves immersing the wafer with photoresist in a suitable organic solvent to dissolve or decompose the photoresist and remove the photoresist from the wafer surface. The selected solvent includes, but is not limited to, dimethyl sulfoxide.

[0053] Further, the silicon wafer is flipped, and a uniformly thick photoresist 2 is coated on the back side of the silicon wafer 1. After photolithography pattern B is formed, after development and baking, the TSV via array is etched on the back side of the silicon wafer using the DRIE combined with Bosch process method to form a through-hole array 4 from the back side to the front negative electrode chamber. Finally, the photoresist is removed.

[0054] Specifically, the aperture range of the array TSV vias is 50-100 μm; the via depth range is 150±20 μm (in this embodiment, the via aperture is 100 μm and the depth is 150 μm); the aspect ratio is less than or equal to 5:1; the etching and passivation processes for preparing the TSV vias are performed alternately to obtain vias with high steepness, wherein the etching process gas is mainly SF6 and the passivation process gas is C4F8;

[0055] Furthermore, using the thermal oxidation process of silicon, an insulating barrier layer 5 is thermally grown on all surfaces of the entire wafer.

[0056] Specifically, thermal oxidation is used to prepare insulating layers of silicon oxide, silicon nitride, or polymers, such as SiO2 or Si3N4, on all surfaces of the wafer, with the thickness of the insulating barrier layer being 100–200 nm.

[0057] Furthermore, a composite metal layer and a seed layer 6 are deposited on the inner wall of the TSV hole using magnetron sputtering (MS) or vapor deposition.

[0058] Specifically, the electroplated metal inside the TSV hole diffuses rapidly in the insulating layer, which can easily cause its dielectric properties to degrade severely. Furthermore, the electroplated metal has poor adhesion to the inner sidewall of the hole. Therefore, a diffusion barrier layer containing, but not limited to, Ta, TaN / Ta, TiN, TiW, Cr, or Ti needs to be deposited on the surface of the insulating layer to prevent the electroplated metal from diffusing and to improve the adhesion strength of the seed layer. The seed layer is not limited to Cu or Ni and has a thickness of 1 to 2 μm.

[0059] Furthermore, a conductive material 7, such as a copper target, is used to fill the TSV vias with a solid by electroplating, and CMP is performed on the back side to planarize the surface of the silicon wafer 1, thereby exposing the conductive metal inside the TSV vias.

[0060] Specifically, if conductive gel materials such as conductive silver paste are used to fill the TSV vias, there is no need for steps such as depositing composite metal layers and seed layers, as well as electroplating and filling. After the conductive gel material is cured, it is polished flat and conductive, directly realizing the electrical interconnection between the current collector and the outside world.

[0061] Furthermore, by using deposition processes including but not limited to vapor deposition, PVD, CVD, and ALD, a current collector 8 such as Cu or Al with a thickness of 5–20 μm is deposited at the bottom of the front negative electrode chamber to collect the charge;

[0062] Furthermore, the remaining space in the chamber is filled with lithium-ion negative electrode slurry 9, such as graphite slurry, by spraying, and then cured in a vacuum at 70°C for 4 hours to form a negative electrode layer wafer.

[0063] (2) Preparation of cathode-electrolyte layer wafer: such as Figure 4 The diagram shown is a flow chart of the positive electrode-electrolyte layer wafer fabrication process.

[0064] Furthermore, a 300μm thick double-polished silicon wafer 10 is provided. After coating the front side of the silicon wafer 10 with a uniformly thick photoresist 2, a photolithographic pattern C is formed. After development and baking, an electrolyte filling chamber 11 with a diameter of 16mm and a depth of 20μm is etched on the front side of the silicon wafer using the DRIE process, and then the photoresist is removed.

[0065] Further, after uniformly thick photoresist 2 is sprayed onto the front side of silicon wafer 10, a photolithographic pattern A is formed. After development and baking, the positive electrode chamber 12 with a diameter of 9 mm and a depth of 150 μm is etched in the electrolyte filling chamber using the DRIE combined with Bosch process method, and then the photoresist is removed.

[0066] Further, the silicon wafer is flipped, and a uniformly thick photoresist 2 is coated on the back side of the silicon wafer 10. After photolithography pattern B is formed, developed and baked, the TSV via array is etched on the back side of the silicon wafer using the DRIE combined with Bosch process method to form a through-hole array 4 from the back side to the positive electrode chamber on the front side. Then the photoresist is removed. The depth of the TSV via here is 130μm.

[0067] Furthermore, the thermal oxidation process, TSV deposition and filling process, and current collector deposition process in the anode layer wafer fabrication are repeated to achieve TSV via filling and current collector deposition.

[0068] Furthermore, the lithium-ion positive electrode slurry 13, including but not limited to LFP, LCO, and NCA slurries, is filled into the chamber to the bottom plane of the electrolyte chamber by spraying, and then cured under vacuum at 70°C for 4 hours to form a positive electrode layer.

[0069] Furthermore, in a vacuum or inert gas environment, the separator and electrolyte or gel electrolyte or solid electrolyte 14 are completely filled in the electrolyte filling chamber to form a positive electrode-electrolyte layer wafer;

[0070] (3) Wafer-level bonding:

[0071] The negative electrode layer wafer is prepared in step (1), and the positive electrode-electrolyte layer wafer is prepared in step (2). Figure 5 After alignment with alignment mark 15 on the wafer layout diagram of the energy storage chip shown, the chips are bonded together using a low-temperature wafer bonding process to form a structure as shown. Figure 6 The on-chip energy storage chip 16 is shown.

[0072] Example 2

[0073] A method for designing and manufacturing a 3D on-chip cathode lithium-ion energy storage chip, specifically including the following steps:

[0074] First, the wafer layout of the on-chip energy storage chip is designed according to the customized requirements and process flow, and a mask is fabricated, such as... Figure 7 The diagram shows the layout and mask patterns A, B, D, and E of a single on-chip energy storage chip. Pattern A is the negative electrode chamber, pattern B is the TSV via array, pattern D is the 3D positive electrode pillar array, and pattern E is the desiliconization template.

[0075] (1) Fabrication of the negative electrode layer wafer:

[0076] Same as the negative electrode layer wafer fabrication steps in Example 1 (1);

[0077] (2) Preparation of cathode-electrolyte layer wafer: such as Figure 8 The diagram shown is a flow chart of the positive electrode-electrolyte layer wafer fabrication process.

[0078] Furthermore, a 300μm thick double-polished silicon wafer 17 is provided, and a current collector 8 with a thickness of 5 to 20μm is deposited on the back side by means of PVD or CVD, including but not limited to PVD or CVD.

[0079] Further, after coating the front side of the silicon wafer 17 with a uniformly thick photoresist 2, a photolithographic pattern D is formed. After development and baking, a 3D positive electrode pillar array filling template 18 with a diameter of 80-150μm and a depth of 300μm is etched on the front side of the silicon wafer using the DRIE combined with Bosch process. Then the photoresist is removed to form a 3D positive electrode pillar array filling template.

[0080] Furthermore, a certain height of the 3D positive electrode column array filling template is filled with a certain fluidity positive electrode slurry 13, including but not limited to LFP, LCO, and NCA slurry. In this embodiment, the filling height is 280 μm, and it is cured in vacuum at 70°C for 12 hours to form a 3D positive electrode column array 19.

[0081] Further, after coating the front side of the silicon wafer 1 with a uniformly thick photoresist 2, a photolithographic pattern E is formed. After development and baking, a silicon etching process is used to remove the silicon around the 3D positive electrode column array to form an electrolyte filling template 18. In this embodiment, the etching depth is 280μm. Then the photoresist is removed to form the electrolyte filling template.

[0082] Furthermore, using the thermal oxidation process of silicon, an insulating barrier layer 5 is thermally grown on all surfaces of the entire wafer;

[0083] Furthermore, the gel electrolyte 14 is completely filled into the electrolyte filling template to form a positive electrode-electrolyte layer wafer;

[0084] (3) Wafer-level bonding:

[0085] The negative electrode layer wafer is prepared in step (1), and the positive electrode-electrolyte layer wafer is prepared in step (2). Figure 5 After alignment with alignment mark 15 on the wafer layout diagram of the energy storage chip shown, the chips are bonded together using a low-temperature wafer bonding process to form a structure as shown. Figure 9 The on-chip energy storage chip 20 is shown.

Claims

1. A method for designing, manufacturing, and integrating on-chip energy storage chips, characterized in that, The chamber and template are etched in the same area on different wafers to provide a packaging shell for the energy storage chip; current collectors, positive / negative electrodes are deposited and prepared on the upper and lower wafers respectively and filled with electrolyte, and then bonded by alignment marks to form the energy storage chip; external electrical interconnection is realized by using TSV and RDL. Includes the following steps, (1) Anode layer wafer fabrication: Using CMOS semiconductor manufacturing technology, electrode chambers and TSV vias are etched in the corresponding areas of the silicon wafer, conductive materials are filled, current collectors are deposited, and anode materials are coated to form the anode of the energy storage chip. The specific steps are as follows. S1 uses a double-polished silicon wafer. The front side of the silicon wafer is sequentially etched using photolithography and dry etching processes to form electrode chambers. S2, TSV vias are etched on the back side of the silicon wafer using photolithography and dry etching processes in sequence to form a through-hole array from the back side to the electrode chamber; S3 utilizes the thermal oxidation process of silicon to grow SiO2 on the entire wafer. x Insulating layer and barrier layer; S4 uses conductive material to solid-fill TSV vias and chemically mechanically polishes the back side of the silicon wafer. S5 utilizes a deposition process to uniformly deposit conductive metal as a current collector at the bottom of the front electrode chamber of a silicon wafer. S6, using coating technology, uniformly sprays negative electrode paste onto the front electrode chamber of the silicon wafer until it is completely filled, and then forms a negative electrode layer wafer through vacuum high-temperature treatment; (2) The methods for preparing the cathode-electrolyte layer wafer include: method 1 for preparing cathode-electrolyte layer wafer 2 or method 2 for preparing cathode-electrolyte layer wafer 1. Method for fabricating the positive electrode-electrolyte layer wafer 1: Using CMOS semiconductor manufacturing technology, positive electrode-electrolyte chambers and TSV vias are etched in the corresponding areas of a silicon wafer. Conductive material is then filled, current collector is deposited, and positive electrode material and electrolyte are sequentially coated and filled to form the positive electrode-electrolyte of the energy storage chip. The specific steps are as follows. S1 provides a double-polished silicon wafer. The front side of the silicon wafer is sequentially etched using photolithography and dry etching processes to form large and small cavity chambers as positive electrode-electrolyte filling chambers. S2, repeat the negative electrode layer wafer fabrication steps S2-S5 to form a TSV conductive array from the back side to the electrode chamber and a current collector at the bottom of the electrode chamber; S3, using coating technology, a positive electrode slurry is uniformly sprayed onto the front electrode chamber of the silicon wafer until it is completely filled, and then vacuum high-temperature treatment is performed to form a positive electrode layer; S4, fill the electrolyte filling chamber with a diaphragm and electrolyte, gel electrolyte or solid electrolyte to form a positive electrode-electrolyte layer wafer; Method for fabricating the positive electrode-electrolyte layer wafer 2: Using CMOS semiconductor manufacturing technology, a positive electrode filling template is etched in the corresponding area of ​​a silicon wafer, a current collector is deposited, and the positive electrode material is filled. After curing, the positive electrode filling template is removed, and the electrolyte is filled to form the positive electrode-electrolyte layer of the energy storage chip. The specific steps are as follows. S1 provides a double-polished silicon wafer, which uses a deposition process to uniformly deposit conductive metal as a current collector on the back side of the silicon wafer. S2, a porous through-array is formed on the front side of the silicon wafer using photolithography and dry etching processes in sequence, serving as a positive electrode filling template; S3 utilizes droplet technology to fill positive electrode slurry into a positive electrode filling template, and then forms a 3D positive electrode column array through vacuum high-temperature treatment. S4, using silicon etching process to remove the positive electrode filling template, and completely fill the gel electrolyte or solid electrolyte to form a positive electrode-electrolyte layer wafer; (3) The negative electrode layer wafer and the positive electrode-electrolyte layer wafer are bonded together by wafer bonding process to form an on-chip energy storage chip.

2. The design, manufacturing, and integration method for on-chip energy storage chips according to claim 1, characterized in that, Using conductive paste or metal materials, TSV vias are solidly filled using negative pressure filling or electroplating processes; chemical mechanical polishing is used to planarize the back side of the silicon wafer and expose the conductive material inside the TSV vias; and RDL is used to achieve electrical interconnection between the negative electrode of the energy storage chip and the outside world.

3. The design, manufacturing, and integration method for on-chip energy storage chips according to claim 1, characterized in that, The current collector is uniformly deposited at the bottom of the electrode chamber and electrically interconnected with the conductive material filled in the TSV.

4. The design, manufacturing, and integration method of on-chip energy storage chip according to claim 1, characterized in that, During the fabrication of the positive electrode-electrolyte layer wafer 1, the large-hole chamber serving as the electrolyte filling chamber is etched first, followed by the small-hole chamber serving as the electrode chamber, with the centers of the two chambers aligned.

5. The design, manufacturing, and integration method of on-chip energy storage chip according to claim 1, characterized in that, During the fabrication of the positive electrode-electrolyte layer wafer 2, the filling height of the positive electrode slurry is lower than the hole depth of the positive electrode filling template.

6. The method for designing, manufacturing, and integrating on-chip energy storage chips according to claim 1, characterized in that, During wafer bonding, wafers are sequentially mounted in a mechanical fixture, with the negative electrode layer wafer placed above the positive electrode-electrolyte layer wafer. Alignment marks are used to align the bonding surfaces in a double-sided alignment manner. The bonding process is carried out in a vacuum or inert gas environment and is implemented using a low-temperature bonding method.

7. The design, manufacturing, and integration method of on-chip energy storage chip according to claim 1, characterized in that, After bonding, conductive metal is deposited on both sides of the wafer, photolithography is performed, and combined with lift-off process and CMP, RDL conductive lines are formed to realize the electrical connection between the on-chip energy storage chip and the multilayer interface structure, chip and device.

8. The design, manufacturing, and integration method of on-chip energy storage chip according to claim 1, characterized in that, The array of TSV holes is geometrically located within the effective conductive area of ​​the on-chip energy storage chip, forming an effective electrical interconnect with the current collector in the front electrode chamber, external circuitry, and RDL layer.

9. The method for designing, manufacturing, and integrating on-chip energy storage chips according to claim 1, characterized in that, RDL conductive lines are pre-embedded on the surfaces of the negative electrode layer wafer and the positive electrode-electrolyte layer wafer using deposition, stripping, and polishing processes. At the same time, energy-consuming structures, chips, devices, and management circuits are fabricated on the wafer. Electrical interconnection with the energy storage chip is achieved using TSV conductive vias and RDL conductive lines. Furthermore, chips with energy harvesting, sensing, and communication functions are bonded to achieve electrical connection between the on-chip energy storage chip and the multilayer interface structure, chip, and device, thereby improving the integration of the intelligent system.

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