A high-precision frequency measurement method and device

Abstract

The invention discloses a high-precision frequency measurement method, which relates to the technical field of frequency measurement. The high-precision frequency measurement method includes roughly estimating the frequency of a measured signal to obtain a rough measurement value of the measured signal; determining the period value of the measured signal; substituting the period value of the measured signal into a nonlinear period-doubling gate function to obtain a nonlinear period-doubling gate time; calculating and obtaining the frequency of the measured signal under the nonlinear period-doubling gate time; wherein the period value of the measured signal is the ratio of the nonlinear period-doubling gate time to the period of the measured signal. The invention uses the period value of the measured signal and the nonlinear period-doubling function to adaptively select a gate time suitable for the frequency band of the measured frequency when performing frequency measurement, thereby realizing high-precision broadband signal frequency measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of frequency measurement, and in particular to a high-precision frequency measurement method and device. Background Art

[0002] As one of the most basic and commonly used measurement parameters in electronic measurement systems, frequency has great value in digital and electronic technology. The earliest frequency measurement method was the direct frequency measurement method, including the direct frequency measurement method and the direct period measurement method. Because the direct frequency measurement method has some limitations in practical applications, some researchers later made some direct and simple improvements to the direct frequency measurement method and developed a multi-cycle synchronous frequency measurement method. Nowadays, with the continuous development of hardware circuits, some measurement methods that were originally impossible or difficult to implement are becoming easier to implement, and some new measurement methods are gradually being proposed. In addition to the direct frequency measurement method and the multi-cycle synchronous frequency measurement method, the frequency measurement methods currently used at home and abroad also include the cursor method, the interpolation method, the difference frequency method, the phase detection bandwidth method, and the digital phase shift counting method.

[0003] The direct frequency measurement method is convenient to measure and the readings are direct, but its measurement error is greatly correlated with the frequency of the measured signal. When the frequency of the measured signal is high, the error of the direct period measurement method is large. When the frequency of the measured signal is low, the error of the direct frequency measurement method is large, and it is impossible to achieve equal-precision frequency measurement. When there is a high measurement accuracy, the measurement range will be subject to certain limitations.

[0004] Both the vernier method and the interpolation method process the time interval using analog methods before counting, which can improve the measurement accuracy to a certain extent. However, like the difference frequency method, the vernier method and the interpolation method have very high performance requirements on the stability and accuracy of the oscillator, high cost, and complex circuit structure, which reduces the possibility of using these three methods. The phase detection bandwidth method not only eliminates the ±1 counting error of the measured signal, but also eliminates the ±1 counting of the standard signal. However, if the frequency difference between the measured signal and the standard signal is too small, the interval between the two phase coincidence points will be large, and the gate time will be very long; if the frequency difference between the measured signal and the standard signal is too large, the phase coincidence points of the two cannot find the corresponding rules, and the expected accuracy cannot be achieved. The digital phase shift counting method can be equivalent to multiplying the original standard clock signal, but it has very high requirements on the accuracy of the digital delay. When the frequency of the original standard clock signal is very high, the error of the digital delay will be very large.

[0005] The relative error of the multi-cycle synchronous frequency measurement method has nothing to do with the magnitude of the measured signal frequency, but only with the gate time and the reference clock frequency, that is, it achieves equal-precision measurement of the entire test frequency band. The longer the gate time, the higher the reference clock frequency, and the smaller the relative error of the frequency measurement. It should be noted that, in principle, the longer the gate time, the higher the accuracy. However, for the multi-cycle synchronous frequency measurement method, in practice, because the gate time is fixed, when the measured signal frequency is low, if its period is less than the gate time, the multi-cycle synchronous frequency measurement method cannot be measured. If a large amount of measurement efficiency is sacrificed for a small increase in the frequency measurement range, this is obviously not worth the loss. Therefore, the multi-cycle synchronous frequency measurement method is not applicable in the low frequency band. In addition, although the relative error is independent of the measured signal frequency, the absolute error is directly proportional to the measured signal frequency. If this point is ignored when measuring high-frequency signals, there will be a large absolute error. In the experiment, because the high-frequency interference between circuit components has a greater impact on the high-frequency signal and will have a great impact on the stability of the system, it is difficult to achieve high accuracy when measuring high-frequency signals. Therefore, the actual relative error of the measured signal frequency will be much larger than the theoretical value. In order to achieve wide-band measurement and suppress high-frequency signal measurement errors, this paper proposes a high-precision frequency measurement method and device to achieve high-precision wide-band frequency measurement while taking into account the measurement time. Summary of the invention

[0006] In view of the above problems existing in the prior art, the present invention is proposed.

[0007] Therefore, the problem to be solved by the present invention is how to achieve high-precision wide-band frequency measurement.

[0008] To solve the above technical problems, the first object of the present invention is to provide a high-precision frequency measurement method, which includes: roughly estimating the frequency of a measured signal to obtain a rough measurement value of the measured signal; determining the period value of the measured signal; substituting the period value of the measured signal into a nonlinear period-doubling gate function to obtain a nonlinear period-doubling gate time; calculating and obtaining the frequency of the measured signal under the nonlinear period-doubling gate time; wherein the period value of the measured signal is the ratio of the nonlinear period-doubling gate time to the period of the measured signal.

[0009] As a preferred solution of the high-precision frequency measurement method of the present invention, the method for measuring the coarse value of the measured signal includes generating a fixed coarse measurement gate using a standard clock signal, counting the period of the measured signal within the coarse measurement gate, and the coarse measurement value of the measured signal is:

[0010] ,

[0011] in is a coarse measurement value of the measured signal frequency, T1 is the coarse measurement gate time, and N is a count value obtained by counting the cycles of the measured signal within the coarse measurement gate time.

[0012] As a preferred solution of the high-precision frequency measurement method of the present invention, the formula for calculating the multiple frequency value of the measured signal is:

[0013] ,

[0014] in, is the multiple of the measured signal, is a rough measured value of the frequency of the measured signal.

[0015] As a preferred solution of the high-precision frequency measurement method of the present invention, the nonlinear frequency doubling gate function is:

[0016] ,

[0017] Where T is the nonlinear cycle-doubling gate time, is a rough measured value of the frequency of the measured signal.

[0018] As a preferred solution of the high-precision frequency measurement method of the present invention, the frequency calculation formula of the measured signal is:

[0019] ,

[0020] in, is the frequency of the measured signal, is the standard clock signal frequency, is the cycle count value of the standard clock signal within the nonlinear cycle doubling gate time T, is the multiple of the measured signal.

[0021] Another object of the present invention is to provide a high-precision frequency measurement device, which includes a frequency prediction module for inputting a measured signal and obtaining a rough measured value of the measured signal frequency. and multiple value ;

[0022] A nonlinear cyclic gate generation module is used to generate a nonlinear cyclic gate; a standard signal counting module is used to count the standard clock signal within the nonlinear cyclic gate time T to obtain a count value ; Frequency measurement data cache module, used to store the multiple cycle value and the standard clock signal count value The frequency measurement data is integrated into frequency measurement data; and a frequency measurement data sending module is used to send the frequency measurement data to the micro control unit.

[0023] As a preferred solution of the high-precision frequency measurement device of the present invention, the predicted frequency module includes a coarse measurement gate generation unit for generating the coarse measurement gate time; a counting unit for counting the number of rising edges of the measured signal within the coarse measurement gate time and obtaining a coarse measurement value of the measured signal. ; Multiple frequency value output unit, equipped with multiple frequency value of the measured signal piecewise function, and outputs the double frequency value through the nonlinear double frequency gate function .

[0024] As a preferred solution of the high-precision frequency measurement device of the present invention, the nonlinear frequency-doubling gate generation module includes a synchronization unit for synchronizing the generated nonlinear frequency-doubling gate with the measured signal, and the nonlinear frequency-doubling gate time T is a period of the measured signal. times.

[0025] As a preferred solution of the high-precision frequency measurement device of the present invention, the frequency measurement data is a 64-bit binary data, which is composed of the data types of the multiple cycle values ​​of 32-bit binary. and the count value Integrated.

[0026] As a preferred solution of the high-precision frequency measurement device of the present invention, the frequency measurement data sending module includes a clock signal generating unit for generating a reference clock and a communication clock for communication with the micro control unit.

[0027] The beneficial effects of the present invention are as follows: the present invention uses the frequency multiple value and nonlinear frequency multiple function of the measured signal to adaptively select a gate time suitable for the measured frequency band during frequency measurement, thereby achieving high-precision broadband signal frequency measurement. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a timing diagram of the rough measurement of the measured signal frequency in Example 1.

[0030] Figure 2 Graph showing the relationship between the measured signal frequency and the derivative of the measured signal multiple in Example 1.

[0031] Figure 3Graph showing the relationship between the measured signal frequency and the nonlinear frequency doubling gate time in Example 1.

[0032] Figure 4 This is a connection diagram of each module in the FPGA in Example 2.

[0033] Figure 5 This is a schematic diagram of the structure of the frequency prediction module in Example 2.

[0034] Figure 6 This is a schematic diagram of the operation flow of the prediction frequency module in Example 2.

[0035] Figure 7 This is a schematic diagram of the structure of the nonlinear cyclotron gate generation module in Example 2.

[0036] Figure 8 Schematic diagram of the operation flow of the nonlinear cyclotron gate generation module in Example 2.

[0037] Fig. 9 This is a schematic diagram of the structure of the standard signal counting module in Example 2.

[0038] Fig.10 This is a schematic diagram of the operation flow of the standard signal counting module in Example 2.

[0039] Fig.11 This is a structural schematic diagram of the frequency measurement data cache module in Example 2.

[0040] Fig.12 This is a schematic diagram of the operation flow of the frequency measurement data cache module in Example 2.

[0041] Fig.13 This is a structural schematic diagram of the frequency measurement data sending module in Example 2.

[0042] Fig.14 This is a schematic diagram of the operation flow of the frequency measurement data sending module in Example 2.

[0043] Fig.15 Schematic diagram of the interaction between FPGA and micro control unit in Example 2.

[0044] Fig.16 This is a timing diagram of data transmission between FPGA and micro control unit in Example 2.

[0045] Fig.17 This is a schematic diagram of the data transmission program flow between the FPGA and the micro control unit in Example 2.

[0046] Fig.18 This is a graph showing the relationship between the actual value of the measured signal multiple value and its derivation formula curve in Example 3 with respect to the frequency of the square wave signal of the signal generator.

[0047] Fig.19This is a graph showing the relationship between the actual value of the standard signal count value in Example 3 and its derivation formula curve with respect to the frequency of the square wave signal of the signal generator.

[0048] Fig. 20 This is a relationship diagram of the relative error of the measured value of the measured signal frequency in Example 3 with respect to the frequency of the square wave signal of the signal generator.

[0049] Fig.21 This is a comparison diagram of relative errors of the measured signal frequency values ​​under different frequency measurement methods in Example 3.

[0050] In the figure: 100, prediction frequency module; 200, nonlinear frequency-doubling gate generation module; 300, standard signal counting module; 400, frequency measurement data buffer module; 500, frequency measurement data sending module; 600, micro control unit. DETAILED DESCRIPTION

[0051] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings.

[0052] In the following description, many specific details are set forth to facilitate a full understanding of the present invention, but the present invention may also be implemented in other ways different from those described herein, and those skilled in the art may make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0053] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure or characteristic that may be included in at least one implementation of the present invention. The term "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an embodiment that is mutually exclusive with other embodiments, either individually or selectively.

[0054] Example 1

[0055] Reference Figure 1~Figure 3 , which is the first embodiment of the present invention, and this embodiment provides a high-precision frequency measurement method, the high-precision frequency measurement method comprising:

[0056] S1: Perform a rough estimation on the frequency of the measured signal to obtain a rough measurement value of the measured signal.

[0057] Specifically, Figure 1 As shown, T1 is the coarse measurement gate time, which is generated by the standard clock signal. The cycle of the measured signal is counted within the coarse measurement gate time T1 to obtain the count value N, then the coarse measurement value of the measured signal frequency is The calculation formula is:

[0058] ,

[0059] Where N is an integer, and the rough value of the measured signal frequency is The minimum resolution is 1 / T1, because the rough measurement value It is only used to generate a nonlinear frequency-doubling gate, and the requirements for accuracy and error are not high, so the resolution of 1 / T1 is sufficient to meet the estimation requirements of the frequency of the measured signal.

[0060] S2: Determine the multiple of the measured signal.

[0061] Specifically, first define the multiple of the measured signal is the nonlinear period-doubling gate time T and the period of the measured signal The ratio of, that is:

[0062] ,

[0063] Preferably, the frequency measurement relative error calculation formula under this method is:

[0064] ,

[0065] in, is the relative error, is the measured signal frequency, N c is the standard signal count value, T is the nonlinear cycle-doubling gate time, is the standard signal frequency.

[0066] At standard frequency For 200MHz, the expected relative error Less than 5×10 -6 Under the requirement of , the lower limit of the nonlinear cycle-doubling gate time T can be obtained. min for:

[0067] ,

[0068] It can be seen that in order to achieve the desired accuracy, the nonlinear double-cycle gate time T must be at least greater than 0.01s. About the measured signal frequency The relationship is

[0069] ,

[0070] At the measured signal frequency In the frequency range of 1Hz~100Hz, the measured signal multiple value Should be 0.01~1, but considering the multiple value It is an integer, which should actually be 1. In order to obtain a lower relative error, set the frequency multiple value in this frequency band. is 2.

[0071] At the measured signal frequency When the frequency is between 100Hz and 10kHz, the measured signal frequency multiple is It should be 1~100. The hardware and other factors in this frequency band have little effect on the error of the measured signal. Set the nonlinear gate time T as its lower limit T min twice, that is, 0.02s. At this time, the measured signal frequency value The frequency of the signal being measured In direct proportion, the proportionality coefficient is 2T min .

[0072] When the measured signal frequency is greater than 10kHz, factors such as hardware and environmental noise will have a greater impact on the measured signal frequency measurement error. The measured signal frequency In a simple proportional relationship, as the measured signal frequency The increase of its relative error will also increase and eventually exceed the allowed range. Therefore, a parameter about the frequency of the measured signal can be added. The quadratic term of is used to suppress the measurement errors caused by factors such as hardware and environmental noise at high frequencies.

[0073] The coefficient of the first-order term is set to the lower limit of the gate time T min 2 times, to ensure that the standard clock signal ±1 count error under ideal conditions is within the allowable range, and the quadratic term coefficient is set to T min / 10kHz to suppress errors caused by hardware, environmental noise and other factors at high frequencies.

[0074] At this time, the measured signal multiple value About the measured signal frequency It can be written as a piecewise function:

[0075] ,

[0076] In order to better illustrate the measured signal multiple value The measured signal frequency Now, the above piecewise function is derived, and the measured signal multiple value is About the measured signal frequency The derivative of is:

[0077] ,

[0078] Reference Figure 2 , from the figure analysis, we can see that at the measured signal frequency When the measured signal is less than 10kHz, the frequency value of the measured signal is About the measured signal frequency The derivative of is fixed at 0 or 0.02. Therefore, the measured signal multiple is The growth rate is slower, and when the measured signal frequency When the frequency is greater than 10kHz, factors such as hardware and environmental noise will have a greater impact on the frequency measurement error of the measured signal. About the measured signal frequency The derivative of starts to grow linearly at the measured signal frequency When the frequency is 1MHz, the derivative of the measured signal's frequency multiple even exceeds 2.

[0079] Since the measured signal frequency It has not been measured yet, so the rough value of the measured signal can be substituted ,Right now:

[0080] ,

[0081] Therefore, the rough measured value of the measured signal can be Choose the appropriate multiplication value of the measured signal .

[0082] S3: Substituting the frequency multiple value of the measured signal into the nonlinear frequency multiple gate function to obtain the nonlinear frequency multiple gate time.

[0083] Specifically, according to the formula:

[0084] ,

[0085] We can get:

[0086] ,

[0087] Since the measured signal frequency It has not been measured yet, so the rough value of the measured signal can be substituted , so the nonlinear period-doubling gate function is:

[0088] ,

[0089] Therefore, according to the rough value of the measured signal By knowing the frequency band range, you can choose the appropriate gate time to perform frequency measurement, thereby improving the measurement accuracy.

[0090] It should be noted that the nonlinear gate time T is related to the rough value of the measured signal. The relationship diagram is as follows Figure 3As shown in the figure, when the measured signal frequency is in the frequency band of 1Hz to 100Hz, the nonlinear cyclotron gate time T shows a downward trend, with a minimum value of 20ms and a maximum value of 2s. In the frequency band of 100Hz to 10kHz, the nonlinear cyclotron gate time T is fixed at 20ms, because other factors in the medium and low frequency bands have little effect on the measured signal error, and the nonlinear cyclotron gate time of 20ms to 2s fully meets the requirements. When the measured signal frequency is greater than 10kHz, the nonlinear cyclotron gate time shows an upward trend, and the rising speed increases with the increase of the measured signal frequency. When the measured signal frequency is 1MHz, the gate time reaches 1s, and when it is 10MHz, the gate time reaches 10s. Therefore, while taking into account the relative error, the upper limit of the measured signal frequency is set to 10MHz to maximize the measurement efficiency.

[0091] S4: Calculate and obtain the frequency of the measured signal under the nonlinear frequency doubling gate time.

[0092] Specifically, based on the rough measured value of the measured signal After selecting the appropriate nonlinear double-cycle gate time T in the frequency band range, count the standard signal cycles within this nonlinear double-cycle gate time T to obtain the count value , then according to the formula:

[0093] ,

[0094] We can get:

[0095] ,

[0096] Right now:

[0097] ,

[0098] in, The standard clock signal frequency. At this time, the rough value of the measured signal frequency measured in advance is input The measured signal frequency can be obtained .

[0099] Example 2

[0100] Reference Figure 4 to Figure 17 , which is the second embodiment of the present invention, and this embodiment is based on the previous embodiment.

[0101] This embodiment provides a high-precision frequency measurement device, which is based on FPGA and includes a prediction frequency module 100, a nonlinear frequency-doubling gate generation module 200, a standard signal counting module 300, a frequency measurement data buffer module 400, a frequency measurement data sending module 500 and a micro control unit 600. Figure 4 .

[0102] Specifically, the prediction frequency module 100 includes a coarse measurement gate generation unit for generating a coarse measurement gate time;

[0103] The counting unit is used to count the number of rising edges of the measured signal within the rough measurement gate time and obtain the rough measurement value of the measured signal frequency. ;

[0104] The multiple-cycle value output unit is configured with a piecewise function of the multiple-cycle value of the measured signal, and outputs the multiple-cycle value through a nonlinear multiple-cycle gate function .

[0105] Better, refer to Figure 5 , is a structural schematic diagram of the prediction frequency module 100, wherein:

[0106] clock_1m: The clock signal of the prediction frequency module. The clock is a 1MHz square wave generated by a PLL (phase locked loop) to generate a coarse measurement gate;

[0107] sig: input terminal of the measured signal;

[0108] key: signal acquisition enable input terminal. When a rising edge is received, it will start counting the number of rising edges of the measured signal within the coarse measurement gate time;

[0109] sig_num[SIZES-1..0]: Output terminal of the measured signal multiple value. SIZES is 32. When the rough measurement is completed, the 32-bit binary multiple value will be generated and output according to the piecewise function of the measured signal multiple value. ;

[0110] ed: module end output terminal. After the module has finished running, a pulse will be sent to control the operation of the nonlinear frequency-doubling gate module 200 and the frequency measurement data buffer module 400.

[0111] Further, see Figure 6 , is a flowchart of the operation of the prediction frequency module 100. Figure 6 As shown, the prediction frequency module 100 starts running after detecting the rising edge of key1.

[0112] When running, the program first clears the two variables i and j to zero, i represents the number of rising edges of the 1MHz clock signal after the rising edge of key1, and j represents the number of rising edges of the measured signal after the rising edge of key1.

[0113] When i is equal to 1000, that is, the gate time is 1ms, the rough value of the measured signal frequency is obtained based on the value of j when i is equal to 1000 , substitute it into the formula for calculating the multiple of the measured signal and then find the multiple of the measured signal , output multiple value After that, an end pulse is sent to control the operation of the nonlinear frequency-doubling gate generation module 200 and the frequency measurement data buffer module 400. Finally, the next key1 rising edge is waited for to re-run the frequency prediction module 100.

[0114] Specifically, the nonlinear frequency-doubling gate generating module 200 is used to generate a nonlinear frequency-doubling gate, and includes a synchronization unit, which is used to synchronize the generated nonlinear frequency-doubling gate with the measured signal.

[0115] Better, refer to Figure 7 , is a structural schematic diagram of the nonlinear cyclotron gate generation module 200, wherein:

[0116] sig: input terminal of the measured signal. Used to synchronize the generated nonlinear frequency-doubling gate with the measured signal;

[0117] en: module enable input. When receiving a rising edge, the gate generation module will receive the multiple frequency value output by the prediction frequency module. ;

[0118] sn[SIZES-1..0]: Input terminal for the measured signal multiple value. SIZES is 32, receiving the multiple value of 32-bit binary data. ;

[0119] q: Gate signal output terminal. The module will output the gate signal according to the measured signal and the multiple value. , a nonlinear period-doubling gate is generated that is synchronized with the measured signal, and the nonlinear period-doubling gate time T is the period of the measured signal. times.

[0120] Further, see Figure 8 , is an operation flow chart of the nonlinear frequency-doubling gate generation module 200. Figure 8 As shown, after detecting the rising edge of the end pulse en output by the prediction frequency module 100, the measured signal multiple value is received. , and clear i and gate at the same time, i is the number of rising edges of the measured signal after the rising edge of en, and gate is the nonlinear multiplication gate signal.

[0121] After the rising edge of en, if the rising edge of the measured signal is detected for the first time, the nonlinear frequency-multiplication gate signal gate is assigned a value of 1, and then i is compared with the frequency-multiplication value. Compare, if the ratio is multiple If i is equal to the multiple value, add 1 to i, then wait for the next rising edge of the measured signal and repeat the above procedure. , clear i and gate to generate a nonlinear double-cycle gate time T that is times the length of the measured signal period. Finally, continue to wait for the next rising edge of en to re-run the nonlinear double-cycle gate generation program.

[0122] Specifically, the standard signal counting module 300 is used to count the standard clock signal within the nonlinear cycle-doubling gate time T to obtain a count value The standard signal here is a 200MHz square wave generated by the FPGA's PLL

[0123] Better, refer to Fig. 9 , is a structural schematic diagram of a standard signal counting module 300, wherein:

[0124] gate: gate signal input terminal. The module will only count the standard signal during the time when the gate is at a high level.

[0125] clk: standard signal input terminal. The standard signal is a 200MHz clock signal generated by pll.

[0126] cnum[SIZEC-1..0]: standard signal count value output terminal, SIZEC is 32;

[0127] ed: The module ends output terminal. After the standard signal counting module finishes running, a pulse will be output to control the operation of the frequency measurement data cache module.

[0128] Further, see Fig.10 , is an operation flow chart of the standard signal counting module 300. Fig.10 As shown, before starting the operation, first set i and Cleared to zero, i represents the number of rising edges of the standard signal collected after the gate is opened. Indicates the standard signal count value within the gate time.

[0129] When the gate signal gate is detected to change from 0 to 1, when the rising edge of the standard signal is detected, i will be increased by 1. If the gate signal gate is still 1 at this time, wait for the next rising edge of the standard signal to arrive, and then repeat the above work. If the gate signal gate is detected to be 0, the value of i at this time is assigned to the count value within the gate time. , and then send the end pulse to control the operation of the frequency measurement data cache program. Finally, i and Clear to zero and wait for the gate signal gate to be 1 again to re-run the standard signal counting module 300.

[0130] Specifically, the function of the frequency measurement data buffer module 400 is to make data transmission convenient and concise, so it is necessary to buffer the measured signal multiple value before transmitting the data. And the standard signal count value , and integrate these two 32-bit binary data into one 64-bit data.

[0131] Better, refer to Fig.11 , is a structural schematic diagram of the frequency measurement data buffer module 400, wherein:

[0132] num_s[SIZES-1..0]: Input terminal for the measured signal multiple value. SIZES is 32, indicating the measured signal multiple value It is 32-bit binary data;

[0133] en_s: Multiple frequency value receiving enable input terminal. Only when a rising edge is collected on the en_s input terminal, the module will receive the multiple frequency value of the measured signal. ;

[0134] num_c[SIZEC-1..0]: Standard signal count value input terminal. SIZEC is 32, indicating the standard signal count value It is 32-bit binary data;

[0135] en_s: count value receiving enable input. The module will receive the standard signal count value only when a rising edge is collected on the en_c input. ;

[0136] clock_1m: The clock signal of the frequency measurement data buffer module. The clock is a 1MHz square wave generated by PLL.

[0137] rst: Initialization signal input terminal. After a rising edge is collected on the rst port, the frequency measurement data cache module will be initialized immediately and the previously saved multiple frequency value will be cleared. and count value , and clear some variables to zero.

[0138] data[SIZES+ SIZEC-1..0]: Cache data output terminal. Used to convert the multiple cycle value and count value The integrated 64-bit binary data is output to the frequency measurement data sending module;

[0139] def[SIZEC-]: Test data output terminal. Sometimes, for testing purposes, this port is used to display some data on a digital tube;

[0140] ed: The end output terminal of the frequency measurement data buffer module. After the frequency measurement data buffer module ends, ed will output a pulse to control the operation of the frequency measurement data sending module.

[0141] Further, see Fig.12 , is a flow chart of the operation of the frequency measurement data buffer module 400. Fig.12 As shown, before the operation starts, , And the buff is cleared, Indicates the received measured signal multiple value, Indicates the received standard signal count value and the multiple cycle value and count value They are all 32-bit binary data, and buff is the multiplier value. and count value 64 bits of binary data combined together.

[0142] When the program starts running, after detecting the rising edge of en_s, it starts receiving the standard signal count value After detecting the rising edge of en_c, it starts to receive the standard signal count value within the gate time , when the multiple cycle value and count value The two numbers have been received, and the two numbers are integrated into a 64-bit binary data buff and sent. Then a receiving pulse is sent to control the operation of the frequency measurement data sending module 500. Finally, , And buff is cleared, and waits for the next rising edge of en_s and en_c to re-run the frequency measurement data cache program.

[0143] Specifically, the frequency measurement data sending module 500 adopts port-to-port serial communication to send the frequency measurement data to the micro control unit 600 .

[0144] Better, refer to Fig.13 , is a structural schematic diagram of the frequency measurement data sending module 500, wherein:

[0145] sin[63..0]: Transmission data input terminal. Receives the measured signal multiple value and standard signal count values The integrated 64-bit binary data is the frequency measurement data;

[0146] clk: the clock signal of the frequency measurement data transmission module, which is a 1MHz square wave generated by the pll and can generate a 5kHz communication clock for transmitting data between the micro control unit 600;

[0147] en_s: Data receiving enable input. The multiplier value will be received only when a rising edge is collected on the en_s input. and count value 64-bit binary data integrated together;

[0148] en_d: feedback input terminal of the micro control unit 600. Only after receiving the feedback signal from the micro control unit 600, the sending module will send data at the falling edge of the communication clock;

[0149] gate: gate signal output terminal. Only when the gate signal is at a high level, the FPGA will send data and the micro control unit 600 will enter the data receiving mode;

[0150] Data: Data sending end. When receiving feedback from the microcontroller unit 600, it sends one bit of binary data at the falling edge of the communication clock until the measured signal is doubled. and standard signal count values The integrated 64-bit binary data are all sent to the micro control unit 600;

[0151] clock_5k: Communication clock output terminal. It is a 5KHz square wave generated by the 1kHz frequency measurement data transmission module clock signal.

[0152] Further, see Fig.14 , is an operation flow chart of the frequency measurement data sending module 500. Fig.14 As shown, the frequency measurement data sending module 500 has two clocks, and clk1 is the reference clock for data transmission between it and the frequency measurement data buffer module 400, which is a 1 MHz square wave.

[0153] clk2 is the reference clock for data transmission between it and the micro control unit 600, which is generated by clk1 and is a 5kHz square wave. When the rising edge of clock clk1 is detected, the program starts running. When the rising edge of en_s is detected, the 64-bit binary data sent by the frequency measurement data cache module 400 is received. After the reception is completed, the gate signal gate is set from 0 to 1 to notify the micro control unit 600 to receive data. When a short pulse sent from the micro control unit 600 is received at the en_d enable end, a bit of binary data is sent when the clock clk2 is at a low level. After that, each time en_d receives a short pulse, it sends a bit of binary data when the clock clk2 is at a low level. After that, when 64 bits of binary data are sent, the gate signal is set to 0 to exit the data sending mode.

[0154] The microcontroller unit 600 in this embodiment selects the AVR single-chip microcomputer ATmega128 as the processing and display frequency measurement data. Its structure is as follows Fig.15 As shown, where:

[0155] gate: gate signal input terminal. Only when the gate signal is high level, the AVR microcontroller will enter the data receiving mode;

[0156] Data: Data receiving end. Receives one bit of binary data at the rising edge of the communication clock to receive the multiple value of the measured signal. and standard signal count values 64-bit binary data integrated together;

[0157] clk: Communication clock signal receiving end. It is a 5KHz square wave generated by the FPGA frequency measurement data sending module, which is used to keep the frequency measurement data sending and receiving synchronously;

[0158] ed: Feedback signal output terminal. Every time a binary data bit is received from data or a rising edge is collected from gate, a pulse signal is sent to the FPGA frequency measurement data sending module, indicating that FPGA can send the next binary data bit.

[0159] The data transmission timing diagram is as follows Fig.16 As shown, gate is the gate signal input terminal, clock is the 5kHz clock, data is the data receiving terminal, and ed is the pulse feedback output terminal. When gate is at a high level, the micro control unit 600 will enter the data acquisition mode and send a short pulse to the FPGA frequency measurement data receiving module at the ed terminal. After that, the micro control unit 600 will collect a bit of binary data on the data terminal at the rising edge of the clock clock and send a short pulse to the FPGA frequency measurement data receiving module at the ed terminal until all 64 bits of binary data are received, the micro control unit 600 exits the data acquisition mode, and gate becomes a low level.

[0160] Further, see Fig.17 , is a flow chart of data receiving and processing of the micro control unit 600. Fig.17 As shown, the micro control unit 600 receives and processes data in a state machine manner. The state variable is set to state. When it is 0, it indicates no working mode, when it is 1, it indicates data collection mode, and when it is 2, it indicates data processing mode.

[0161] After receiving the rising edge of the gate signal gate, state is assigned a value of 1 and enters the data acquisition mode. The data acquisition mode has two key requirements: one is to receive a binary data at the rising edge of the clock, and the other is to send a short pulse through en_d after receiving it. This method implements these two requirements through ATmega128 timer counter 0 and timer counter 2.

[0162] Timer counter 2 is used to receive a binary data at the rising edge of the clock. Its control register TCCR2 is set to 0X0F, indicating that the interrupt mode of timer counter 2 is the comparison match interrupt under the external pin T2, and the rising edge is triggered. Its output comparison register OCR2 is 0X00, indicating that the T2 pin will trigger a comparison match interrupt when receiving a rising edge, so that data can be collected in this interrupt program. Timer counter 0 plays a timing role. TCCR0 is 0X0A and OCR0 is 0X09, indicating that an interrupt is triggered once every 10 microseconds. When the feedback signal en_d is 1, en_d can be cleared in the next interrupt through the interrupt program of timer counter 0. In this way, after receiving the rising edge of the gate signal gate and collecting a binary data, a short pulse can be sent by setting en_d to 1.

[0163] After receiving the 64-bit binary data, state is assigned a value of 2, and then the collected 64-bit binary data is processed through a for loop to obtain the two values ​​of the measured signal multiple value num_s and the standard signal count value num_c. Finally, the formula is used:

[0164] ,

[0165] The measured value of the measured signal frequency can be calculated ,in is a float type variable, and then the sprintf function is used to convert Convert it into a string s, and finally display the string s on the LCD, which is the measured value of the signal frequency. .

[0166] Example 3

[0167] Reference Figure 18~Figure 21 In order to better verify the technical effect of the present invention, this embodiment conducts experimental verification and error analysis on the measurement method of the present invention.

[0168] In this embodiment, the FPGA development board AX515 is responsible for data acquisition and transmission, and the AVR microcontroller ATMEGA128 is responsible for data reception and processing. In order to verify whether the frequency measurement value meets the requirements, the arbitrary waveform generator AFG3252 will generate a square wave signal with a known frequency to compare with the final measurement value. For some set output signals, the digital oscilloscope SDS1072CML can be used to verify whether the frequency and amplitude of the signal are correct.

[0169] Specifically, the chip model of the FPGA development board AX515 is EP4CE15F23C8, with a total of 484 pins, 56 multipliers, 4 phase-locked loops PLL, 20 global clock networks, and 343 available IOs.

[0170] ATmega128 is an AVR 8-bit microcontroller that uses low-power CMOS technology and RISC (Reduced Instruction Set Computer) architecture. It integrates a wealth of hardware interface circuits and 128KB Flash memory and is programmable in the system.

[0171] The arbitrary waveform generator AFG3252 has a bandwidth of 10MHz to 240MHz, realizes dual channels, and can generate waveforms with fine timing resolution with a sampling rate of up to 2GS / s. The output amplitude can reach a maximum of 20Vp-p without the need for an external power amplifier. After connecting the CH1 end of the arbitrary waveform generator to pin 3 in J1 of the FPGA with a BNC cable, select the square wave waveform, set the low level to 0V, and the high level to 3V, and adjust the frequency of the square wave signal through the numeric keys or using the general knob to perform measurement experiments.

[0172] The digital oscilloscope SDS1072CML has a bandwidth of 70MHZ, real-time sampling up to 1GSa / s, equivalent sampling of 50GSa / s, storage depth of 2Mpts, and has 5 trigger functions: edge, pulse, video, slope, and alternating, as well as digital filtering and waveform recording, one-key storage and printing. Through a BNC cable, the output square wave waveform of the arbitrary waveform generator and the waveform of the clock signal generated by the pll inside the FPGA can be displayed through the CH1 end of the arbitrary waveform generator.

[0173] This embodiment mainly analyzes the measured signal multiple value from four frequency bands: 1Hz~100Hz, 100Hz~10kHz, 10kHz~1MHz, and 1MHz~60MHz , Standard signal count value And the measured value of the measured signal frequency of error.

[0174] (1) The measured signal multiple Error analysis.

[0175] According to the calculation formula of the measured signal's multiple value:

[0176] ,

[0177] Because the frequency ƒ of the square wave signal output by the arbitrary waveform generator is known, the frequency ƒ of the square wave signal can be used to approximately replace the estimated value of the measured signal frequency. As the function variable, the theoretical estimate of the measured signal multiple value can be obtained. for:

[0178] ,

[0179] The theoretical estimate of the measured signal multiple is is an integer.

[0180] Then, the actual data of the measured signal multiple value when the square wave signal frequency is within the four frequency bands of 1Hz~100Hz, 100Hz~10kHz, 10kHz~1MHz, and 1MHz~60MHz are sampled, and the following four tables can be obtained:

[0181] Table 1 Count values ​​from 1Hz to 100Hz.

[0182]

[0183] Table 2 Frequency multiples from 0.1kHz to 10kHz.

[0184]

[0185] Table 3 Frequency multiples at 10kHz-1MHz.

[0186]

[0187] Table 4 Frequency multiples from 1MHz to 60MHz.

[0188]

[0189] It can be seen from Table 1, Table 2, Table 3, and Table 4 that when the frequency of the square wave signal output by the arbitrary waveform generator is 1Hz~100Hz, the measured signal multiple value is only 2 and 3. When the square wave signal frequency is 100Hz~10kHz, the measured signal multiple value ranges from 2 to 13, and the growth rate is slow. When the square wave signal frequency is 10kHz~1MHz, the multiple value changes from 13 to 10981, and the growth rate is fast. In 1MHz~60MHz, the multiple value changes from 10981 to 35987740, which is expanded by three orders of magnitude.

[0190] In order to analyze the relationship between the measured signal multiple value and the measured signal frequency, a curve graph of the multiple value can be drawn when the square wave signal frequency output by the waveform generator is 1Hz~60MHz, such as Fig.18 shown.

[0191] like Fig.18 As shown, the horizontal axis is the square wave signal frequency ƒ generated by the signal generator, and the vertical axis is the measured signal multiple value The dots represent the multiples of the square wave signal generated by the signal generator when the frequency is different. The actual value of the curve is the theoretical estimated value of the gate signal multiple derived from the calculation formula of the measured signal multiple. The relationship curve between the square wave signal frequency ƒ.

[0192] Depend on Fig.18 It can be seen that the actual multiple of the measured signal increases nonlinearly with the increase of the measured signal frequency. In the full frequency band, the minimum value is 1 and the maximum value is 35987740. When the square wave signal frequency changes from 1Hz to 10kHz, the actual multiple of the measured signal only increases from 2 to 13, and the growth rate is slow. When the square wave signal frequency ƒ changes from 10kHz to 60MHz, the actual multiple of the measured signal increases very quickly. Theoretical estimated value The relationship curve with the square wave signal frequency ƒ also increases slowly when it changes from 1Hz to 10kHz, and increases rapidly when it changes from 10kHz to 60MHz.

[0193] Therefore, the actual multiple of the measured signal and the theoretical estimate of the gate signal multiple derived from the calculation formula of the multiple of the measured signal are Match.

[0194] (2) Standard signal count value Error analysis.

[0195] When the frequency ƒ of the square wave signal generated by the signal generator is known, according to the formula:

[0196] ,

[0197] The theoretical estimate of the nonlinear cycle-doubling gate time can be obtained for:

[0198] ,

[0199] Because the standard signal frequency The frequency is 200MHz, and the theoretical estimate of the count value of the standard signal within the gate time can be obtained. for:

[0200] ,

[0201] Then, the actual data of the standard signal count values ​​in the four frequency bands of 1Hz~100Hz, 100Hz~10kHz, 10kHz~1MHz, and 1MHz~60MHz are sampled, and the following four tables can be obtained:

[0202] Table 5 Count values ​​at 1Hz~100Hz.

[0203]

[0204] Table 6 Count values ​​at 100Hz~10kHz.

[0205]

[0206] Table 7 Count values ​​from 10kHz to 1MHz.

[0207]

[0208] Table 8 Count values ​​at 1MHz-60MHz.

[0209]

[0210] It can be seen from Table 5, Table 6, Table 7, and Table 8 that when the frequency of the square wave signal output by the arbitrary waveform generator is 1Hz~100Hz, the count value of the standard signal within the gate time is From 400000536 to 6000008. When the square wave signal frequency ƒ is 100Hz~10kHz, the count value of the standard signal within the gate time From 6000008 to 260001, the count value decreased by two orders of magnitude compared with the previous frequency band. When the square wave signal frequency ƒ is 10kHz~1MHz, the count value increases from 260001 to 2196203, and the trend of the count value changes from decreasing to increasing. From 1MHz to 60MHz, the count value increases from 2196203 to 119959296, expanding by two orders of magnitude.

[0211] In order to analyze the standard signal count value within the gate time The relationship between the count value and the frequency of the measured signal can be plotted when the frequency of the square wave signal output by the arbitrary waveform generator is 1Hz~60MHz, as shown in Fig.19 shown.

[0212] like Fig.19 As shown, the horizontal axis is the square wave signal frequency ƒ generated by the signal generator, and the vertical axis is the standard signal count value within the gate time. The dots represent the square wave signal frequency generated by the signal generator. The standard signal count value at different frequencies The actual value of the curve is the theoretical estimated value of the count value of the standard signal within the gate time derived from the theoretical formula. The relationship curve between the square wave signal frequency ƒ.

[0213] Depend on Fig.19 It can be seen that the standard signal count value within the gate time The standard signal count value within the gate time in the full frequency band decreases when the square wave signal frequency ƒ changes from 1Hz to 10kHz, and increases when it changes from 10kHz to 60MHz. The minimum value is 260001 and the maximum value is 119959296. Theoretical estimate of the standard signal count value The relationship curve with the square wave signal frequency ƒ also shows a downward trend when ƒ changes from 1Hz to 10kHz, and an upward trend when it changes from 10kHz to 60MHz. Therefore, the actual count value of the standard signal Theoretical estimate of the standard signal count value derived from the formula Match.

[0214] (3) Frequency measurement value of the measured signal Error analysis.

[0215] According to Example 1, The calculation formula is:

[0216] ,

[0217] Among them, the standard clock signal frequency It is 200MHz.

[0218] Then the square wave signal frequency is sampled in four frequency bands: 1Hz~100Hz, 100Hz~10kHz, 10kHz~1MHz, and 1MHz~60MHz. The actual value of and calculate its relative error, we can get the following four tables:

[0219] Table 9 Relative error from 1Hz to 100Hz.

[0220]

[0221] Table 10 Relative error from 100Hz to 10kHz.

[0222]

[0223] Table 11 Relative error from 10kHz to 1MHz.

[0224]

[0225] Table 12 Relative error from 1MHz to 60MHz.

[0226]

[0227] It can be seen from Tables 9, 10, 11 and 12 that when the square wave signal frequency ƒ output by the arbitrary waveform generator is 1 Hz to 100 Hz, the maximum relative error of the measured signal frequency is only 2.0×10 -6 When the square wave signal frequency ƒ is between 100Hz and 10kHz, the relative error of the measured signal frequency will reach the maximum value of 3.8×10 -6 , which is about twice the highest relative error of the previous frequency band. When the square wave signal frequency ƒ is 10kHz~1MHz, except for the 3.8×10 -6 Relative error, the maximum relative error of the rest is only 2.5×10 -6 In the range of 1MHz to 60MHz, the maximum relative error is only 1.8×10 -6 .

[0228] In order to analyze the relative error of the measured value of the measured signal frequency, a curve graph of the count value when the frequency of the square wave signal output by the arbitrary waveform generator is 1Hz~60MHz can be drawn, such as Fig. 20 shown.

[0229] like Fig. 20 As shown in the figure, the horizontal axis is the square wave signal frequency ƒ generated by the signal generator, and the vertical axis is the relative error of the measured signal frequency. As can be seen from the figure, when the square wave signal frequency ƒ is 1Hz~100Hz, the relative error of the measured signal frequency is generally low, with the highest being only 2.0×10 -6 , while when the square wave signal frequency ƒ is 100Hz~1MHz, the relative error of the measured value varies greatly, with the minimum being 0.0×10 -6 , the highest is 3.8×10 -6 When the square wave signal frequency ƒ is 1MHz~60MHz, the relative error of the measured value is relatively stable, only ranging from 1.2×10 -6 Change to 1.8×10 -6 In summary, when the square wave signal frequency ƒ changes from 1Hz to 60MHz, the maximum relative error of the measured signal frequency is 3.8×10 -6 The average relative error is 1.1×10 -6 , achieving high-precision broadband signal frequency measurement.

[0230] In order to compare whether the relative error of the measured signal frequency in this method is reasonable, the direct frequency measurement method and the multi-cycle synchronous frequency measurement method are selected to compare with the nonlinear frequency-doubling gate frequency measurement method proposed in this paper. The comparison range is the relative error when the measured signal frequency is 100kHz~60MHz. The direct frequency measurement method uses a gate time of 1s, which is the baseline method. Because when the measured signal frequency is less than 100kHz, its relative error is too large, exceeding 100×10 -6 Therefore, the nonlinear frequency-doubling gate frequency measurement method proposed in this paper does not compare the data when the measured signal frequency is less than 100kHz with the direct frequency measurement method. The multi-cycle synchronous frequency measurement method selects the frequency measurement method with a designed 1ms gate time. Because the gate time is only 1ms, it can only measure a square wave signal of 1kHz at the lowest. To be conservative, the frequency measurement range of the measured signal starts from 100kHz. The data of the measured signal frequency measurement values ​​and relative errors of the nonlinear frequency-doubling gate frequency measurement method, multi-cycle synchronous frequency measurement method and direct frequency measurement method proposed in this paper are shown in the following table:

[0231] Table 13 Comparison of nonlinear frequency doubling gate method with other methods.

[0232]

[0233] In order to clearly and intuitively compare and display the relative errors of the nonlinear frequency-doubling gate frequency measurement method, the multi-cycle synchronous frequency measurement method and the direct frequency measurement method when the measured signal frequency ranges from 100kHz to 60MHz, the following plot is made: Fig.21 .

[0234] like Fig.21 As shown in the figure, the horizontal axis is the square wave signal frequency ƒ generated by the signal generator, and the vertical axis is the relative error of the measured signal frequency. The experimental results show that the nonlinear frequency-doubling gate frequency measurement proposed in this paper has a much lower relative error than the multi-cycle synchronous frequency measurement method and the direct frequency measurement method. When the square wave signal frequency ƒ changes from 100kHz to 60MHz, the maximum relative error of the multi-cycle synchronous frequency measurement method is 9.3×10 -6 The average relative error is 7.4×10 -6 The maximum relative error of the direct frequency measurement method is 43.8×10 -6 The average relative error is 21.4×10 -6 , while the maximum relative error of the method proposed in this paper is 2.5×10 -6 The average relative error is 1.4×10 -6 The maximum relative error is 6.8×10 lower than that of the multi-cycle synchronous frequency measurement method. -6 , which is 41.3×10 lower than the highest relative error of the direct frequency measurement method. -6The average relative error is 6.0×10 lower than that of the multi-cycle synchronous frequency measurement method. -6 , which is 20.0×10 lower than the average relative error of the direct frequency measurement method. -6 It can be seen that in terms of the relative error of the measured signal frequency, the method in this paper has a higher advantage than the multi-cycle synchronous frequency measurement method and the direct frequency measurement method, and solves the problem of large error in the multi-cycle synchronous frequency measurement method when measuring high-frequency signals.

[0235] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present invention may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present invention, which should all be included in the scope of the claims of the present invention.

Claims

1. A high-precision frequency measurement method, characterized in that: include, Performing a rough estimation on the frequency of the measured signal to obtain a rough measurement value of the frequency of the measured signal; Determine the multiple of the measured signal; Substituting the frequency multiple value of the measured signal into the nonlinear frequency multiple gate function to obtain the nonlinear frequency multiple gate time; Calculating and obtaining the frequency of the measured signal under the nonlinear frequency doubling gate time; Wherein, the frequency multiple value of the measured signal is the ratio of the nonlinear frequency multiple gate time to the period of the measured signal; The method for measuring the coarse value of the measured signal frequency includes generating a fixed coarse measurement gate using a standard clock signal, and counting the period of the measured signal within the coarse measurement gate. Then, the coarse value of the measured signal frequency is: in is the coarse measurement value of the measured signal frequency, T1 is the coarse measurement gate time, and N is the count value obtained by counting the cycles of the measured signal within the coarse measurement gate time; The calculation formula of the multiple value of the measured signal is: Among them, N x is the multiple of the measured signal, is a rough measured value of the measured signal frequency; The nonlinear cyclic gate function is: Where T is the nonlinear cycle-doubling gate time, is a rough measured value of the measured signal frequency; The frequency calculation formula of the measured signal is: Among them, f x is the frequency of the measured signal, f c is the standard clock signal frequency, N c is the cycle count value of the standard clock signal within the nonlinear cycle-doubling gate time T, N x is the multiple of the measured signal.

2. A high-precision frequency measurement device, characterized in that: include, A frequency prediction module (100) is used to input a measured signal and obtain a rough value of the measured signal frequency. and the multiple value N x ; A nonlinear cyclotron gate generation module (200) is used to generate a nonlinear cyclotron gate; The standard signal counting module (300) is used to count the standard clock signal within the nonlinear cycle-doubling gate time T to obtain a count value N. c ; The frequency measurement data buffer module (400) is used to store the multiple cycle value N x and the standard clock signal count value N c Integrate into frequency measurement data; A frequency measurement data sending module (500), used for sending the frequency measurement data to a micro control unit (600); The micro control unit (600) is configured to generate a plurality of cycles according to the multiple value N. x and the standard clock signal count value N c Calculate the measured value f of the measured signal frequency x ; Wherein, the prediction frequency module (100) comprises: A coarse measurement gate generation unit, used to generate the coarse measurement gate time; A counting unit, used to count the number of rising edges of the measured signal within the rough measurement gate time and obtain a rough measurement value of the measured signal frequency The multiple value output unit is equipped with the multiple value N of the measured signal. x piecewise function, and passes the coarse measured value of the measured signal frequency Output the multiple value N x ; The nonlinear cyclotron gate generation module (200) comprises: A synchronization unit is used to synchronize the generated nonlinear frequency-doubling gate with the measured signal, wherein the nonlinear frequency-doubling gate time T is N times the period of the measured signal. x times.

3. The high-precision frequency measuring device according to claim 2, characterized in that: The frequency measurement data is a 64-bit binary data, which consists of the data types of the multiple cycle value N of 32-bit binary. x and the count value N c Integrated.

4. The high-precision frequency measuring device according to claim 3, characterized in that: The frequency measurement data sending module (500) comprises: The clock signal generating unit is used to generate a reference clock and a communication clock for communicating with the micro control unit (600).

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