A method and device for batch testing of components

Abstract

The present invention provides a batch testing method and device for components, which is used to detect multiple opposite-side electrode wafers, including: S1, exposing the opposite-side electrode of the wafer to be detected; S2, connecting the first electrode of the wafer to be detected to the receiving end of the signal processing component; S3, electrically connecting one end of the probe to the second electrode of part of the wafer, and the other end to the transmitting end of the signal processing component; S4, moving multiple probes, and repeating step S3 until the probe contacts all wafers to complete the wafer batch detection. The present invention simultaneously performs batch detection on multiple opposite-side electrode wafers through a closed detection circuit. During this process, multiple probes independently detect multiple wafers, thereby ensuring the accuracy of detection while also greatly improving the detection efficiency. In addition, compared with the current conventional detection technology, the present application also has the advantages of simple operation process, easy adjustment and control, low device cost, improved component safety, and a wide detection range.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer testing, and in particular to a method and device for batch testing of components. Background Art

[0002] As the basic units in the field of electronic and electrical systems, electronic components are widely used. The electrode configuration of these components usually has two basic forms: one is that the two electrodes are located on the same side, such as both on the bottom or top surface of the component; the other is that the two electrodes are located on different sides, such as one electrode on the top surface and the other electrode on the bottom surface. In the batch testing process of electronic wafers, these two different electrode configurations pose different challenges to the testing methods.

[0003] For wafers with electrodes on the same side, the test method is relatively simple and can be performed by directly pressing down on two test ports to achieve rapid testing. However, for wafers with electrodes on different sides, especially those that still have blue or UV film after dicing, the test process is more complicated. At present, the test methods for such wafers mainly include the following:

[0004] First, the wafer is sucked and grabbed from the blue film or UV film by a suction nozzle, and then placed in a customized test fixture. In this method, the bottom surface of the wafer contacts a test point, and the top is connected through another test point to complete the performance test. Although this method is feasible, it not only requires additional customized tooling with matching sizes, but also is inefficient and easy to damage the wafer during the transfer process. Taking a 1mm×1mm wafer as an example, assuming that the wafer size is 12 inches, the number of products to be tested inside it can reach more than 70,000. Only one wafer can be sucked for testing at a time. If each test takes two seconds, it takes about 40 hours to test the entire 12-inch wafer.

[0005] Secondly, in order to improve the test efficiency, the industry is currently trying to adopt a multi-nozzle design based on the above method, sucking multiple wafers for testing each time. Although this method can improve the test efficiency to a certain extent, the number of nozzles installed on most current equipment is limited, and the maximum number of nozzles supported is 6. Taking the same 1mm×1mm wafer as an example, it takes about 7 hours to test a 12-inch wafer using this method. Although the efficiency has been improved, the cost of the equipment has also increased.

[0006] With the rapid development of modern communication technology, the demand for electronic equipment and system integration is growing, and the requirements for wafer size are getting smaller and smaller. Wafers with a size of less than 1mm×1mm have become very common, which puts higher requirements on batch testing. The existing mass production test methods have limitations in meeting the requirements of high efficiency and low cost, and cannot take into account these two key factors at the same time. Summary of the invention

[0007] To this end, the technical problem to be solved by the present invention is to overcome the problems of low efficiency and high cost in the wafer detection process on the opposite side of the electrode in the prior art, and to provide a batch testing method and device for components.

[0008] In order to solve the above technical problems, the present invention provides a batch testing method for components, which is used to detect multiple wafers with electrodes on different sides, wherein the multiple wafers are arranged in an array, and the method comprises the following steps: step S1, exposing the electrodes on different sides of multiple wafers to be detected; step S2, connecting the first electrodes of all wafers to be detected to the receiving end of the signal processing component; step S3, electrically connecting one end of multiple probes arranged in the array to the second electrodes of some wafers respectively, and connecting the other ends to the transmitting end of the signal processing component respectively to form a closed detection circuit; step S4, moving the multiple probes, and repeating step S3 until the probes are in contact with all the wafers, thereby completing the batch detection of the wafers.

[0009] In one embodiment of the present invention, in step S1, holes are opened on the blue film and / or UV film of the wafer to be inspected to expose a plurality of electrodes of the wafer to be inspected.

[0010] In one embodiment of the present invention, step S2 specifically includes: placing the wafer to be inspected on a conductive plate, and after making the first electrodes of all the wafers to be inspected contact the conductive plate, electrically connecting the conductive plate to the receiving end of the signal processing component.

[0011] In one embodiment of the present invention, in step S3, a positioning mechanism is used to arrange the plurality of probes in one-to-one correspondence with the plurality of wafers to be inspected, wherein the positioning mechanism comprises a plurality of positioning holes, and the plurality of positioning holes are arranged corresponding to the second electrodes of the plurality of wafers to be inspected.

[0012] In one embodiment of the present invention, the wafers to be inspected include marked wafers, and the alignment mechanism positions the wafers by using the marks.

[0013] In one embodiment of the present invention, in step S3, the number of the positioning holes is N1 times the number of the probes, wherein N1≥1; and the spacing distance between adjacent probes is N2 times the spacing distance between the centers of adjacent positioning holes, wherein N2≥1.

[0014] In one embodiment of the present invention, in step S3, a plurality of the probes are arranged in an array according to the size of the wafer to be inspected, the number, spacing and arrangement density of the wafers to be inspected.

[0015] In one embodiment of the present invention, in step S3, the plurality of probes are respectively connected to PCB boards, and the PCB boards are connected to the transmitting end of the signal processing component.

[0016] The present invention also provides a batch testing device for wafers, which detects wafers on different sides of electrodes through the above-mentioned batch testing method for components, and comprises: a first testing component, the first testing component comprises a conductive plate, and the conductive plate is connected to the first electrodes of all wafers to be detected; a second testing component, the second testing component comprises a plurality of probes, the plurality of probes are arranged in an array, and are respectively set toward the second electrodes of the plurality of wafers to be detected; a signal processing component, the conductive plate is connected to the receiving port of the signal processing component, and the plurality of probes are respectively connected to the transmitting port of the signal processing component, and when the plurality of probes contact the plurality of wafers to be detected, a closed detection circuit is formed between the probes, the conductive plate and the signal processing component.

[0017] In one embodiment of the present invention, it also includes a positioning mechanism, which is supported on the wafer to be inspected, and a plurality of positioning holes are provided on its body, and the plurality of positioning holes are arranged in one-to-one correspondence with the plurality of wafers to be inspected.

[0018] In one embodiment of the present invention, the first test component also includes a first signal connection board, one side of the conductive board is connected to the first electrodes of all wafers to be tested, and the other side is connected to the first signal connection board, and the first signal connection board is connected to the receiving port of the signal processing component; the second test component also includes a second signal connection board, and a plurality of the probes are arranged in an array on the second signal connection board, and the second signal connection board is connected to the transmitting port of the signal processing component.

[0019] In one embodiment of the present invention, the first test assembly further includes an assembly board, and the conductive board and the assembly board are respectively disposed on two sides of the first signal connection board.

[0020] In one embodiment of the present invention, the second test assembly further includes a connector, the connector is connected to the second signal connection board, a plurality of slots are provided on the connector, and the plurality of probes are respectively connected to the plurality of slots.

[0021] The above technical solution of the present invention has the following advantages compared with the prior art:

[0022] The batch testing method and device of components described in the present invention perform batch testing on multiple wafers with electrodes on the opposite sides at the same time through a closed detection circuit. During this process, multiple probes independently detect multiple wafers, thereby ensuring the accuracy of detection while also greatly improving the detection efficiency. In addition, compared with the current conventional detection technology, the present application also has the advantages of simple operation process, easy adjustment and control, low device cost, improved component safety, and a wide detection range. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0024] Figure 1 It is a schematic diagram of the planar structure of some wafers to be inspected;

[0025] Figure 2 yes Figure 1 The enlarged schematic diagram at A in the middle;

[0026] Figure 3 It is a schematic diagram of the three-dimensional structure of the wafer to be inspected;

[0027] Figure 4 It is a schematic diagram of the three-dimensional structure of a wafer batch testing device in a preferred embodiment of the present invention.

[0028] Explanation of the reference numerals in the specification: 100, first test component; 110, conductive plate; 120, first signal connection board; 130, assembly board; 200, second test component; 210, second signal connection board; 220, connector; 230, probe; 300, signal processing component; 310, transmitting port; 320, receiving port; 400, alignment mechanism; 410, main body; 420, positioning hole; 500, wafer group to be tested; 510, wafer to be tested; 511, main body; 512, first electrode; 513, second electrode; 520, marked position wafer. DETAILED DESCRIPTION

[0029] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0030] Embodiment 1

[0031] This embodiment provides a wafer batch testing device, which is used to detect wafers on opposite sides of electrodes arranged in an array. It is worth noting that, see Figure 1 and Figure 2As shown, the batch testing device for wafers described in this embodiment can detect 16 wafers at the same time, and the above 16 wafers are arranged in a 4×4 array structure, wherein any wafer size is 1mm×1mm. In this embodiment, 400 wafers 510 to be detected are arranged in a 20×20 array structure, which constitute a wafer group 500 to be detected. In this embodiment, a total of 4 wafer groups 500 to be detected are included. Based on this, the detection efficiency of the present application can reach 16 times that of ordinary detection technology. According to the actual operation situation, the present device can also detect other numbers of wafers at the same time, and the present invention does not make specific restrictions on this.

[0032] Further, see Figure 3 As shown, the wafers on the opposite sides of the electrodes to be detected in this embodiment include a main body 511, a first electrode 512 and a second electrode 513. In the wafer thickness direction, the first electrode 512 and the second electrode 513 are respectively arranged on opposite sides of the main body 511. Specifically, Figure 3 The wafer 510 to be inspected is shown as a reference object, the first electrode 512 is located below the main body 511 , and the second electrode 513 is located above the main body 511 .

[0033] See also Figure 4 Based on the structure of the wafer 510 to be detected, the batch testing device of the wafer described in this embodiment includes: a first testing component 100, the first testing component 100 includes a conductive plate 110, and the conductive plate 110 is connected to the first electrodes 512 of all the wafers 510 to be detected; a second testing component 200, the second testing component 200 includes a plurality of probes 230, and the plurality of probes 230 are arranged in an array and are respectively set toward the second electrodes 513 of the plurality of wafers 510 to be detected; a signal processing component 300, the conductive plate 110 is connected to the receiving port 320 of the signal processing component 300, and the plurality of probes 230 are respectively connected to the transmitting port 310 of the signal processing component 300, and when the plurality of probes 230 contact the plurality of wafers 510 to be detected, a closed detection circuit is formed between the probes 230, the conductive plate 110 and the signal processing component 300.

[0034] The batch testing device for components described in this embodiment performs batch testing on multiple wafers with electrodes on the opposite sides at the same time through a closed detection circuit. During this process, multiple probes 230 independently detect multiple wafers, thereby ensuring the accuracy of detection while also greatly improving the detection efficiency. In addition, compared with the current conventional detection technology, the present application also has the advantages of simple operation process, easy adjustment and control, low device cost, and improved component safety.

[0035] by Figure 4The batch testing device of components shown is a reference object. The first test assembly 100 is arranged at the bottom of the wafer 510 to be tested, which is used to realize the electrical connection between the first electrode 512 and the signal processing assembly 300. Further, the first test assembly 100 also includes a first signal connection board 120. One side of the conductive plate 110 is connected to the first electrodes 512 of all the wafers 510 to be tested, and the other side is connected to the first signal connection board 120. The first signal connection board 120 is connected to the receiving port 320 of the signal processing assembly 300, thereby completing the electrical connection between the first electrode 512 and the signal processing assembly 300. Furthermore, in order to facilitate the installation of the first signal connection board 120 and improve the safety and stability of the device during use, the first test assembly 100 in this embodiment also includes an assembly board 130. The conductive plate 110 and the assembly board 130 are respectively arranged on both sides of the first signal connection board 120.

[0036] See also Figure 4 As shown, corresponding to the first test component 100, the second test component 200 in this embodiment is arranged on the top of the wafer 510 to be tested, which is used to realize the electrical connection between the second electrode 513 and the signal processing component 300. Further, the second test component 200 also includes a second signal connection board 210, and a plurality of the probes 230 are arranged in an array on the second signal connection board 210, and the second signal connection board 210 is connected to the transmitting port 310 of the signal processing component 300. Specifically, the first signal connection board 120 and the second signal connection board 210 in this embodiment are both configured as PCB boards. Furthermore, in order to improve the connection stability between the multiple probes 230 and the second signal connection board 210, the second test component 200 in this embodiment also includes a connector 220, which is connected to the second signal connection board 210, and a plurality of slots are provided on the connector 220, and the multiple probes 230 are respectively connected to the multiple slots. Specifically, one end of the multiple probes 230 are respectively connected to the slots by connectors 220 such as screws and are detachably arranged in the slots, and the other end is suspended to facilitate contact with the corresponding wafer 510 to be tested.

[0037] It is worth noting that the present invention does not impose any specific restrictions on the specific type, substrate, and size of the probe 230 , and the probe 230 can be adaptively adjusted according to actual usage requirements.

[0038] See also Figure 4As shown, in order to ensure that the probe 230 can accurately contact the corresponding wafer during the actual test process, the present embodiment also includes a positioning mechanism 400, and the positioning mechanism 400 is supported on the wafer to be detected 510, and a plurality of positioning holes 420 are provided on its main body 410, and the plurality of positioning holes 420 are arranged in a one-to-one correspondence with the plurality of wafers to be detected 510. Based on the setting of the positioning mechanism 400, when the probe 230 moves toward the wafer to be detected 510, it can accurately move to the second electrode 513 of the corresponding wafer through the guiding effect of the plurality of positioning holes 420. Furthermore, in order to further improve the precise positioning effect of the probe 230, a marking position wafer 520 is also set in the wafer to be detected 510 in this embodiment. Specifically, the conventional wafer to be detected 510 and the marking position wafer 520 have the same size, but the surface treatment method is different. Specifically, the surface of the conventional wafer to be detected 510 is gold-plated, which can show light reflection effect during optical photography, while the surface of the conventional marking position wafer 520 is chemically plated, so it does not show reflection even through optical photography. Therefore, in the actual detection process, the probe 230 can be further accurately positioned by optical photography.

[0039] In this embodiment, the closed detection circuit is used to detect the inductance of the wafer. The signal received by the signal processing component 300 will be interconnected with the wafer inductance and generate a specific frequency signal. The inductance value of the wafer under test can be obtained based on the frequency signal, the inductance input signal and the inductance output signal. Furthermore, multiple wafers under test are connected in parallel. At this time, if a high-impedance jumper resistor is connected between two adjacent probes 230, each inductor under test can output a corresponding specific frequency, thereby enabling each inductance value to achieve the purpose of testing. Based on the above principle, in other embodiments, the resistance, capacitance and other properties of the wafer can also be tested.

[0040] Embodiment 2

[0041] This embodiment provides a method for batch testing of components, which uses the wafer batch testing device described in the first embodiment to detect multiple wafers with electrodes on opposite sides, wherein the multiple wafers are arranged in an array, and comprises the following steps:

[0042] Step S1, exposing electrodes on opposite sides of a plurality of wafers to be inspected; in this embodiment, holes are opened on the blue film and / or UV film of the wafers to be inspected to expose the electrodes of the plurality of wafers to be inspected.

[0043] Step S2, connecting the first electrodes of all wafers to be detected to the receiving end of the signal processing component; in this embodiment, step S2 is specifically: placing the wafers to be detected on a conductive plate, and after making the first electrodes of all wafers to be detected contact the conductive plate, electrically connecting the conductive plate to the receiving end of the signal processing component.

[0044] Step S3, electrically connecting one ends of the plurality of probes arranged in an array to the second electrodes of some wafers, and connecting the other ends to the transmitting end of the signal processing component, so as to form a closed detection circuit; in this embodiment, the plurality of probes are arranged in one-to-one correspondence with the plurality of wafers to be detected through an alignment mechanism, wherein the alignment mechanism includes a plurality of positioning holes, and the plurality of positioning holes are arranged corresponding to the second electrodes of the plurality of wafers to be detected. Furthermore, the wafers to be detected in this embodiment include marked position wafers, which can be positioned for the first time through the alignment mechanism and the marked position wafer during actual use, and then the wafers can be positioned for the second time through the positioning holes on the positioning mechanism.

[0045] It is worth noting that, in actual use, the plurality of probes are respectively connected to a PCB board, the PCB board is connected to the transmitting end of the signal processing component, and the operator needs to arrange the array of the plurality of probes according to the size of the wafer to be detected, the number, spacing and arrangement density of the wafers to be detected. Furthermore, the number of the positioning holes is N1 times the number of the probes, wherein N1≥1; the spacing distance between adjacent probes is N2 times the spacing distance between the centers of adjacent positioning holes, wherein N2≥1, thereby ensuring that the probes can be set corresponding to all wafers through the alignment mechanism.

[0046] Step S4, move the multiple probes, and repeat step S3 until the probe contacts all the wafers, and then complete the wafer batch detection. Specifically, the size of the wafer to be tested in this embodiment is 1mm×1mm, and 400 wafers (20 horizontally and 20 vertically) to be tested constitute a wafer group to be tested, and this embodiment contains 4 wafer groups to be tested. Correspondingly, the wafer batch testing device in this embodiment can test the inductance value of 16 (4×4 matrix) wafers at the same time. The specific principle is the same as that in Example 1, and no further elaboration is made here. Based on this, the detection efficiency in this application is about 16 times that of ordinary detection technology.

[0047] Embodiment 3

[0048] This embodiment provides another batch testing method for components, which detects the resistance values ​​of multiple wafers with electrodes on the opposite sides through the wafer batch testing device described in Example 1. The operation process is the same as that of Example 2. In this embodiment, a voltage signal is applied to the two electrodes of the wafer. The voltage signal is given by the transmitting port and the signal receiving port of the signal processing component, and a current is resistively generated when passing through the wafer to be detected. The resistance value of the resistor to be tested can be calculated through the above voltage and current signals.

[0049] Embodiment 4

[0050] This embodiment provides another batch testing method for components, which detects the capacitance values ​​of multiple wafers with electrodes on opposite sides through the batch testing device of the wafer described in the first embodiment, wherein the voltage signal is also applied to both ends of the wafer to be tested. For the capacitor, its resistance value is megohm or above in the DC state, and it has extremely high resistance. When the capacitor is not short-circuited, the current of the entire branch is very small, generally at the nA level. When the capacitor is short-circuited, the current will increase. During the test, a limit value can be set according to actual needs, such as 10uA. When it exceeds 10uA, the capacitor is judged to be a defective product to achieve the purpose of protecting the test equipment. The above-mentioned capacitor test does not need to return the signal to the test instrument, and a single-channel signal can complete the test.

[0051] In summary, the batch testing method and device of components described in the present invention perform batch testing on multiple wafers with electrodes on the opposite sides at the same time through a closed detection circuit. During this process, multiple probes independently detect multiple wafers, thereby ensuring the accuracy of detection while also greatly improving the detection efficiency. In addition, compared with the current conventional detection technology, the present application also has the advantages of simple operation process, easy adjustment and control, low device cost, wide detection range, and improved component safety.

[0052] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A method for batch testing of components, characterized in that: The method is used to detect a plurality of wafers with electrodes on opposite sides, wherein the plurality of wafers are arranged in an array, and comprises the following steps: Step S1, exposing electrodes on opposite sides of a plurality of wafers to be inspected; Step S2, connecting the first electrodes of all wafers to be detected to the receiving end of the signal processing component, specifically: placing the wafers to be detected on a conductive plate, and after making the first electrodes of all wafers to be detected contact the conductive plate, electrically connecting the conductive plate to the receiving end of the signal processing component; Step S3, electrically connecting one end of the plurality of probes arranged in an array to the second electrodes of some wafers respectively, and connecting the other ends to the transmitting end of the signal processing component respectively, so as to form a closed detection circuit, wherein the plurality of probes are arranged one-to-one with the plurality of wafers to be detected through an alignment mechanism, wherein the alignment mechanism comprises a plurality of positioning holes, and the plurality of positioning holes are arranged corresponding to the second electrodes of the plurality of wafers to be detected, and the number of the positioning holes is N1 times the number of the probes, wherein N1≥1; the spacing distance between adjacent probes is N2 times the spacing distance between the centers of adjacent positioning holes, wherein N2≥1; Step S4, moving the plurality of probes, and repeating step S3, until the probes are in contact with all the wafers, thereby completing the wafer batch inspection.

2. The method for batch testing components according to claim 1, characterized in that: In step S1, holes are opened on the blue film and / or UV film of the wafer to be inspected to expose a plurality of electrodes of the wafer to be inspected.

3. The method for batch testing components according to claim 1, characterized in that: The wafers to be inspected include marked wafers, and the alignment mechanism positions the wafers according to the marks.

4. The method for batch testing components according to claim 1, characterized in that: In step S3, a plurality of the probes are arranged in an array according to the size of the wafer to be inspected, the number, spacing and arrangement density of the wafers to be inspected.

5. The method for batch testing components according to claim 1, characterized in that: In step S3, the plurality of probes are respectively connected to PCB boards, and the PCB boards are connected to the transmitting end of the signal processing component.

6. A wafer batch testing device, characterized in that: The method for batch testing components according to any one of claims 1 to 5 is used to detect wafers on opposite sides of electrodes, comprising: A first test assembly, the first test assembly comprising a conductive plate, the conductive plate connecting first electrodes of all wafers to be tested; A second testing component, the second testing component comprising a plurality of probes, the plurality of probes being arranged in an array and respectively disposed toward the second electrodes of the plurality of wafers to be tested; A signal processing component, wherein the conductive plate is connected to the receiving port of the signal processing component, and the plurality of probes are respectively connected to the transmitting ports of the signal processing component. When the plurality of probes contact the plurality of wafers to be detected, a closed detection circuit is formed between the probes, the conductive plate and the signal processing component.

7. The wafer batch testing device according to claim 6, characterized in that: It also includes a positioning mechanism, which is supported on the wafer to be detected. A plurality of positioning holes are arranged on the main body of the positioning mechanism, and the plurality of positioning holes are arranged in a one-to-one correspondence with the plurality of wafers to be detected.

8. The wafer batch testing device according to claim 6, characterized in that: The first test component also includes a first signal connection board, one side of the conductive board is connected to the first electrodes of all wafers to be tested, and the other side is connected to the first signal connection board, and the first signal connection board is connected to the receiving port of the signal processing component; the second test component also includes a second signal connection board, and a plurality of the probes are arranged in an array on the second signal connection board, and the second signal connection board is connected to the transmitting port of the signal processing component.

9. The wafer batch testing device according to claim 8, characterized in that: The first test assembly further includes an assembly board, and the conductive board and the assembly board are respectively arranged on two sides of the first signal connection board.

10. The wafer batch testing device according to claim 8, characterized in that: The second test assembly further includes a connector, which is connected to the second signal connection board. The connector is provided with a plurality of slots, and the plurality of probes are respectively connected to the plurality of slots.

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