Three-dimensional memory and preparation method thereof

Abstract

The present invention provides a three-dimensional memory and a preparation method thereof. The present invention optimizes the upper and lower electrode layers into left and right electrode layers, thereby optimizing the traditional horizontal memory unit into a vertical memory unit. The effective area of ​​a single memory unit is increased, and the area of ​​a single memory unit can be made smaller to save the occupied area of ​​the memory unit. The increase in the effective area of ​​the device can improve the storage performance, optimize and improve the operating efficiency and reliability of the device. Moreover, the arrangement of the vertical memory unit will not affect the deposition and phase change performance of the memory layer even if there is a protrusion in the first main connection structure in contact with the first metal structure as the first electrode layer; and when the second metal structure as the second electrode layer is formed, there is no problem of etching through the memory layer, thereby avoiding affecting the performance of the memory unit. Moreover, the second metal structure serves as the second electrode layer and the second main connection structure at the same time, saving a contact hole mask process, which can effectively reduce production costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a three-dimensional memory and a preparation method thereof. Background Art

[0002] New memory devices such as phase change memory (PRAM) or ferroelectric memory (FeRAM) are devices that integrate memory cells in the back-end of the line (BEOL). The storage performance of a memory cell is proportional to the effective area of ​​the storage layer and electrode layer in the memory cell.

[0003] The storage unit of the traditional two-dimensional (2D) memory is composed of an upper and lower electrode layer and a storage layer in the middle. The upper and lower electrode layers and the storage layer are deposited and grown layer by layer by atomic layer deposition (ALD). The storage layer is formed by phase change materials or ferroelectric materials. However, as the semiconductor process shrinks, the storage unit area of ​​the traditional two-dimensional memory becomes smaller, which further reduces the effective area of ​​the storage layer and the electrode layer, thereby affecting the storage performance of the memory; and the preparation of the connection structure connecting the upper and lower electrode layers of the storage unit requires multiple mask processes, resulting in increased production costs. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a preparation method thereof, which can save the occupied area of ​​the storage unit and increase the effective area of ​​the device, thereby improving the storage performance, and can save the mask process and reduce the production cost.

[0005] In order to solve the above problems, the present invention provides a method for preparing a three-dimensional memory, the method comprising the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering the surface of the substrate, a first main connection structure penetrating the first dielectric layer along a second direction and arranged at intervals along the first direction, and a first metal structure formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure, wherein the first direction is parallel to the substrate surface, and the second direction is perpendicular to the substrate surface; forming a storage layer, the storage layer covering a side wall of the first metal structure and having an extension extending to the surface of the first dielectric layer; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer, all the first metal structures and all the storage layers; and forming a second metal structure, the second metal structure penetrating the second dielectric layer along the second direction and in contact with a side of the storage layer away from the first metal structure and the extension; wherein the first metal structure serves as a first electrode layer, the second metal structure serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.

[0006] In some embodiments, the second metal structure is made of the same material as the first metal structure and is different from the first main connection structure.

[0007] In some embodiments, the material of the storage layer is a ferroelectric material or a phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the material of the first main connection structure is metal tungsten, and the material of the first metal structure and the second metal structure are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

[0008] In some embodiments, the steps of forming a semiconductor substrate specifically include: providing a substrate, the first dielectric layer being formed on the surface of the substrate, the first dielectric layer having first contact holes formed therein, the first contact holes penetrating the first dielectric layer along the second direction and arranged at intervals along the first direction; filling the first contact holes with a first metal material to form the first main connection structure; forming an etch stop layer and a sacrificial layer on the surface of the first dielectric layer; etching the sacrificial layer and the etch stop layer using a preset mask as a mask to form a first through hole exposing the first main connection structure; depositing a second metal material and planarizing it to form the first metal structure in the first through hole; and removing the remaining sacrificial layer and the etch stop layer.

[0009] In some embodiments, the step of forming a storage layer specifically includes: depositing storage material to form a storage material layer covering the first dielectric layer and all the first metal structures; depositing anti-reflection material on the surface of the storage material layer and flattening it to form a first anti-reflection layer, and forming a first photoresist structure on the surface of the first anti-reflection layer, the first photoresist structure having a shielding portion that shields a side wall of the first metal structure and a portion of the first dielectric layer corresponding to the side wall; etching using the first photoresist structure as a mask to etch the remaining storage material layer to form the storage layer.

[0010] In some embodiments, the material of the first metal structure is metallic copper, and the step of forming the second dielectric layer includes: forming a diffusion barrier layer, the diffusion barrier layer at least covers the first metal structure, and the material of the diffusion barrier layer is a material that can block the diffusion of metallic copper.

[0011] In some embodiments, the step of forming the second metal structure specifically includes: forming a second contact hole in the second dielectric layer that exposes the side of the storage layer away from the first metal structure and the extension portion; enlarging the aperture of the second contact hole at the end away from the extension portion to form a groove connected to the second contact hole; depositing a second metal material and flattening it to form the second metal structure; wherein the second metal structure in the second contact hole serves as the second electrode layer and the second main connection structure at the same time, and the second metal structure in the groove serves as a lead-out structure or a pad.

[0012] In some embodiments, the step of enlarging the aperture of the second contact hole at the end away from the extension portion to form a groove connected to the second contact hole specifically includes: depositing anti-reflection material in the second contact hole and on the surface of the second dielectric layer and flattening it to form a second anti-reflection layer, and forming a second photoresist structure with an opening on the surface of the second anti-reflection layer, wherein the opening of the second photoresist structure completely exposes the corresponding area of ​​the storage layer; etching the second anti-reflection layer and the second dielectric layer using the second photoresist structure as a mask to form the groove; and removing the second photoresist structure and the remaining second anti-reflection layer.

[0013] In some embodiments, the second metal structure is a T-shaped structure, including a first portion in contact with a side of the storage layer away from the first metal structure and the extension portion, and a second portion in contact with an end of the first portion away from the extension portion, the second portion having protrusions protruding from both sides of the first portion along the first direction, and a surface of the second portion is flush with a surface of the second dielectric layer; wherein the first portion serves as both a second electrode layer and a second main connection structure, and the second portion serves as a lead-out structure or a pad.

[0014] In some embodiments, a first auxiliary connection structure is formed at the same time as the first main connection structure is formed. The first auxiliary connection structure penetrates the first dielectric layer along the second direction and is spaced apart from the first main connection structure in the first direction. The second metal structure also includes a third part, one end of the third part is in contact with the second part and the other end is in contact with the first auxiliary connection structure, and the third part serves as a second auxiliary connection structure.

[0015] In order to solve the above problems, the present invention also provides a three-dimensional memory, comprising: a substrate; a first dielectric layer, covering the surface of the substrate; a first main connection structure, penetrating the first dielectric layer along a second direction and arranged at intervals along the first direction, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; a first metal structure, formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure; a storage layer, covering a side wall of the first metal structure and having an extension extending to the surface of the first dielectric layer; a second dielectric layer, covering the first dielectric layer, all the first metal structures and all the storage layers; and a second metal structure, penetrating the second dielectric layer along the second direction and in contact with a side of the storage layer away from the first metal structure and the extension; wherein the first metal structure serves as a first electrode layer, the second metal structure serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.

[0016] In some embodiments, the second metal structure is made of the same material as the first metal structure and is different from the first main connection structure.

[0017] In some embodiments, the material of the storage layer is a ferroelectric material or a phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the material of the first main connection structure is metal tungsten, and the material of the first metal structure and the second metal structure are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

[0018] In some embodiments, the material of the first metal structure is metallic copper; the three-dimensional memory further includes: a diffusion barrier layer, the diffusion barrier layer at least covers the first metal structure, and the material of the diffusion barrier layer is a material capable of blocking diffusion of metallic copper.

[0019] In some embodiments, the second metal structure is a T-shaped structure, including a first portion in contact with a side of the storage layer away from the first metal structure and the extension portion, and a second portion in contact with an end of the first portion away from the extension portion, the second portion having protrusions protruding from both sides of the first portion along the first direction, and a surface of the second portion is flush with a surface of the second dielectric layer; wherein the first portion serves as both a second electrode layer and a second main connection structure, and the second portion serves as a lead-out structure or a pad.

[0020] In some embodiments, the three-dimensional memory also includes: a first auxiliary connection structure, which is formed by the same process as the first main connection structure, the first auxiliary connection structure penetrates the first dielectric layer along the second direction, and is spaced apart from the first main connection structure in the first direction; wherein the second metal structure also includes a third part, one end of the third part is in contact with the second part, and the other end is in contact with the first auxiliary connection structure, and the third part serves as a second auxiliary connection structure.

[0021] The above technical solution optimizes the traditional horizontal storage unit into a vertical storage unit by optimizing the upper and lower electrode layers into left and right electrode layers, and increases the effective area of ​​a single storage unit, so that the area of ​​a single storage unit can be smaller, thereby saving the occupied area of ​​the storage unit; the increase in the effective area of ​​the device can improve the storage performance, optimize and improve the operating efficiency and reliability of the device. Moreover, the arrangement of the vertical storage unit will not affect the deposition and phase change performance of the storage layer even if there is a protrusion in the first main connection structure in contact with the first metal structure as the first electrode layer; and when the second metal structure as the second electrode layer is formed, there is no problem of etching through the storage layer, thereby avoiding affecting the performance of the storage unit. Moreover, the second metal structure serves as the second electrode layer and the second main connection structure at the same time, saving a contact hole mask process, and can effectively reduce the production cost. The present invention solves the problem in the prior art that as the semiconductor process is miniaturized, the area of ​​the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of ​​the storage layer and the electrode layer, thereby affecting the storage performance of the memory, and saves the mask process, which can effectively reduce the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments of the present invention are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0023] Figure 1 It is a schematic diagram of the device structure of a memory in the prior art;

[0024] Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention;

[0025] Figure 3~Figure 8 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention;

[0026] Figure 9~Figure 11 A schematic diagram of a device structure for forming a storage layer according to an embodiment of the present invention;

[0027] Fig.12 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention;

[0028] Figure 13~Figure 16 FIG. 1 is a schematic diagram of a device structure for forming a second metal structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] See also Figure 1 , which is a schematic diagram of the device structure of a memory in the prior art. Figure 1As shown, the existing memory includes: a supporting layer 10, a first dielectric layer 111 formed on the supporting layer 10, a first connecting structure 121 formed in the first dielectric layer 111, a second dielectric layer 112 formed on the first dielectric layer 111, a first conductive structure 131 formed in the second dielectric layer 112 and in contact with the first connecting structure 121, a second connecting structure 122 formed in the second dielectric layer 112 and in contact with the first conductive structure 131, a storage unit 14 formed on the second dielectric layer 112 and in contact with the second connecting structure 122, a third dielectric layer 113 covering the second dielectric layer 112 and covering the storage unit 14, a third connecting structure 123 formed in the third dielectric layer 113 and in contact with the storage unit 14, and a second conductive structure 132 formed on the surface of the third dielectric layer 113 and in contact with the third connecting structure 123. The storage unit 14 is composed of a lower electrode layer, a middle storage layer and an upper electrode layer. The support layer 10 can be a substrate, the first dielectric layer 111, the second dielectric layer 112, and the third dielectric layer 113 can be corresponding dielectric layers, and the first conductive structure 131 and the second conductive structure 132 can be corresponding metal structures.

[0031] The storage performance of the memory cell 14 is proportional to the effective area of ​​the memory layer and the electrode layer. However, as the semiconductor process is miniaturized, the area of ​​the memory layer and the electrode layer is reduced, resulting in a reduction in the effective area of ​​the memory layer and the electrode layer, thereby affecting the storage performance of the memory. At the same time, when preparing the existing memory, the preparation of the first connection structure 121, the second connection structure 122, and the third connection structure 123 requires three photomask processes, resulting in an increase in production costs.

[0032] In order to solve the problem in the prior art that as the semiconductor process is miniaturized, the area of ​​the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of ​​the storage layer and the electrode layer, thereby affecting the storage performance of the memory, the present invention provides a three-dimensional (3D) structured three-dimensional memory and a preparation method thereof, which can save the occupied area of ​​the storage unit and increase the effective area of ​​the device, thereby improving the storage performance, optimizing and improving the operating efficiency and reliability of the device, and can save the mask process and reduce the production cost.

[0033] An embodiment of the present invention provides a method for preparing a three-dimensional memory.

[0034] Please also read Figure 2 to Figure 16 ,in, Figure 2 A schematic diagram of the steps of a method for preparing a three-dimensional memory according to an embodiment of the present invention; Figure 3~Figure 8 A schematic diagram of a device structure of a semiconductor substrate provided by an embodiment of the present invention; Figure 9~Figure 11A schematic diagram of a device structure for forming a storage layer according to an embodiment of the present invention; Fig.12 A schematic diagram of a device structure for forming a second dielectric layer according to an embodiment of the present invention; Figure 13~Figure 16 FIG. 1 is a schematic diagram of a device structure for forming a second metal structure according to an embodiment of the present invention.

[0035] like Figure 2 As shown, the preparation method of the three-dimensional memory described in this embodiment includes the following steps: S21, forming a semiconductor substrate, the semiconductor substrate includes a substrate, a first dielectric layer covering the surface of the substrate, a first main connection structure that penetrates the first dielectric layer along the second direction and is arranged at intervals along the first direction, and a first metal structure that is formed on the surface of the first dielectric layer and is in one-to-one contact with the first main connection structure; S22, forming a storage layer, the storage layer covers a side wall of the first metal structure and has an extension extending to the surface of the first dielectric layer; S23, forming a second dielectric layer, the second dielectric layer covers the first dielectric layer, all the first metal structures and all the storage layers; and S24, forming a second metal structure, the second metal structure penetrates the second dielectric layer along the second direction and is in contact with a side of the storage layer away from the first metal structure and the extension; wherein the first metal structure serves as a first electrode layer, the second metal structure serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.

[0036] Please refer to step S21 and Figure 8 , forming a semiconductor substrate, the semiconductor substrate includes a substrate 30, a first dielectric layer 31 covering the surface of the substrate 30, first main connection structures 322 penetrating the first dielectric layer 31 along the second direction D2 and arranged at intervals along the first direction D1, and a first metal structure 33 formed on the surface of the first dielectric layer 31 and in one-to-one contact with the first main connection structure 322. The first direction D1 is parallel to the surface of the substrate 30, and the second direction D2 is perpendicular to the surface of the substrate 30.

[0037] In this embodiment, the material of the first metal structure 33 is different from the material of the first main connection structure 322 .

[0038] In this embodiment, the step of forming a semiconductor substrate specifically includes: (1) providing a substrate 30, wherein the first dielectric layer 31 is formed on the surface of the substrate 30, and the first dielectric layer 31 is formed with first contact holes 320 that penetrate the first dielectric layer 31 along the second direction D2 and are arranged at intervals along the first direction D1, such as Figure 3(2) Filling the first contact hole 320 with a first metal material to form the first main connection structure 322, as shown in FIG. Figure 4 (3) An etching stop layer 301 and a sacrificial layer 302 are formed on the surface of the first dielectric layer 31, as shown in FIG. Figure 5 (4) Using a preset mask as a mask, the sacrificial layer 302 and the etching stop layer 301 are etched to form a first through hole 330 exposing the first main connection structure 322, as shown in FIG. Figure 6 (5) Depositing a second metal material and planarizing it to form the first metal structure 33 in the first through hole 330, as shown in FIG. Figure 7 (6) removing the remaining sacrificial layer 302 and the etching stop layer 301, obtaining a first metal structure 33 located on the surface of the first dielectric layer 31 and in one-to-one contact with the first main connection structure 322, as shown in FIG. Figure 8 Specifically, the second metal material is different from the first metal material.

[0039] In this embodiment, the planarization can be achieved by a chemical mechanical polishing (CMP) process. The material of the first dielectric layer 31 can be an oxide (OX) material, such as silicon oxide (SiO). The material of the first main connection structure 322 can be metal tungsten; the material of the first metal structure 33 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably copper wire.

[0040] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30, the first dielectric layer 31 further covers the gate structure 39, and the first main connection structure 322 is disposed on both sides of the gate structure 39 along the first direction D1. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and a sidewall 393 located on the sidewall of the polysilicon gate 391. Figure 3 shown.

[0041] In this embodiment, the top surface of the first main connection structure 322 is flush with the top surface of the first dielectric layer 31 .

[0042] In this embodiment, the first metal structures 33 are in one-to-one contact with the first main connection structures 322 , and a plurality of the first metal structures 33 are disposed on the surface of the first dielectric layer 31 at intervals.

[0043] In some embodiments, the first contact hole 320 is filled with a first metal material to form the first main connection structure 322, and the first metal structure 33 may also be formed by the following steps: forming a second metal material layer on the surface of the first dielectric layer 31, and patterning the second metal material layer to form the first metal structure 33. Accordingly, the second metal material layer may be deposited and grown by atomic layer deposition (ALD).

[0044] Please refer to step S22 and Fig.11 , forming a storage layer 34 , the storage layer 34 covers a side wall of the first metal structure 33 and has an extension portion 341 extending to the surface of the first dielectric layer 31 .

[0045] In this embodiment, the step S22 includes: (1) depositing a storage material to form a storage material layer 340 covering the first dielectric layer 31 and all the first metal structures 33, such as Fig. 9 (2) depositing an anti-reflection material on the surface of the storage material layer 340 and flattening it to form a first anti-reflection layer 41, and forming a first photoresist structure 42 on the surface of the first anti-reflection layer 41, wherein the first photoresist structure 42 has a shielding portion 420 that shields a side wall of the first metal structure 33 and a portion of the first dielectric layer 31 corresponding to the side wall, as shown in FIG. Fig.10 (3) Using the first photoresist structure 42 as a mask, etching is performed to etch the remaining storage material layer 340 to form the storage layer 34, as shown in FIG. Fig.11 shown.

[0046] In this embodiment, the storage layer 34 also covers a portion of the top surface of the first metal structure 33 .

[0047] In some embodiments, the storage material layer 340 can be deposited and grown by maskless atomic layer deposition (ALD). The material of the storage layer 34 is a ferroelectric material or a phase change material. The first anti-reflective layer 41 can be a bottom anti-reflective coating (BARC), which is a layer of organic or inorganic anti-reflective material deposited before photolithography coating to achieve the purpose of increasing the photolithography process window and improving the photolithography strip width control. The process of forming the first anti-reflective layer 41 can also include a planarization process so that the formed first anti-reflective layer 41 has a relatively flat surface. The planarization can be achieved by a chemical mechanical polishing (CMP) process. The shielding portion 420 of the first photoresist structure 42 is projected on the first dielectric layer 31 to cover a side wall of the first metal structure 33 and a portion of the first dielectric layer 31 corresponding to the side wall.

[0048] Please refer to step S23 and Fig.12 , forming a second dielectric layer 35 , wherein the second dielectric layer 35 covers the first dielectric layer 31 , all the first metal structures 33 and all the storage layers 34 .

[0049] The material of the second dielectric layer 35 may be the same as that of the first dielectric layer 31 , both of which are oxide (OX) materials, for example, both are silicon oxide (SiO).

[0050] In this embodiment, the material of the first metal structure 33 is copper metal; before the step of forming the second dielectric layer 35, the step includes: forming a diffusion barrier layer 50, the diffusion barrier layer 50 at least covers the first metal structure 33. In this embodiment, the diffusion barrier layer 50 covers the surface of the first metal structure 33 (including the exposed sidewalls and top surface thereof), the surface of the storage layer 34, and covers the surface of the first dielectric layer 31, so that the diffusion barrier layer 50 can be formed by deposition without a mask. In other embodiments, the diffusion barrier layer 50 can also be formed by growing only on the surface of the first metal structure 33 through a selective growth process. The selective growth process can accurately control the film to be generated only in the growth area, while the non-growth area does not grow. Among them, the material of the diffusion barrier layer 50 is a material that can block the diffusion of copper metal, such as nitrogen-doped silicon carbide (NDC), W-Si-N ternary compound, WCN ternary compound, titanium nitride, tantalum nitride, etc. The nitrogen-doped silicon carbide (NDC) dielectric layer is a thin film containing four elements: nitrogen (N), silicon (Si), hydrogen (H), and carbon (C), and can be used as a diffusion barrier layer to prevent the diffusion of metallic copper.

[0051] Please refer to step S24 and Fig.16 , forming a second metal structure 36, the second metal structure 36 penetrates the second dielectric layer 35 along the second direction D2, and contacts the side of the storage layer 34 away from the first metal structure 33 and the extension portion 341; wherein the first metal structure 33 serves as a first electrode layer, and the second metal structure 36 serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory.

[0052] In this embodiment, the material of the second metal structure 36 can be the same as that of the first metal structure 33 , for example, both can be selected from one of aluminum, copper, or an aluminum-copper alloy, preferably copper wire.

[0053] In this embodiment, in the second direction D2, the height of the second metal structure 36 is greater than the height of the first metal structure 33, so that the effective area of ​​the electrode plate of the formed memory cell can be increased.

[0054] In this embodiment, the second metal structure 36 and the first metal structure 33 are arranged in pairs, and together with the intermediate storage layer 34, form a vertical storage unit (along the D2 direction shown in the figure), which can save the occupied area of ​​the storage unit and increase the effective area of ​​the device. The arrangement of the vertical storage unit in this embodiment makes it possible to avoid the problem of etching through the storage layer when forming the second metal structure 36 as the second electrode layer (upper contact hole process), thereby further avoiding affecting the performance of the storage unit. And the second metal structure 36 is also used as the second electrode layer and the second main connection structure. Compared with Figure 1 In the conventional method, there are three dielectric layers and three contact hole (VIA) mask processes. In this embodiment, only two dielectric layers and two contact hole (VIA) mask processes are required, thereby saving one contact hole mask process and effectively reducing production costs.

[0055] In this embodiment, a plurality of storage units are formed and distributed at intervals, and adjacent storage units are separated by a second dielectric layer 35 .

[0056] In this embodiment, the step of forming the second metal structure 36 specifically includes: (1) forming a second contact hole 350 in the second dielectric layer 35 that exposes the side of the storage layer 34 away from the first metal structure 33 and the extension portion 341, such as Fig.13 (2) enlarging the aperture of the second contact hole 350 at one end away from the extension portion 341 to form a groove 351 connected to the second contact hole 350, as shown in FIG. Fig.15 (3) depositing a second metal material and planarizing it to form the second metal structure 36, as shown in Fig.16 As shown. The second metal structure in the second contact hole 350 serves as the second electrode layer and the second main connection structure at the same time, and the second metal structure in the groove 351 serves as the lead-out structure or pad. The second electrode layer and the second main connection structure are integrally formed with the lead-out structure or pad using the same process, which can effectively save material and process costs.

[0057] In some embodiments, the step of enlarging the aperture of the second contact hole 350 at the end away from the extension portion 341 to form a groove 351 connected to the second contact hole 350 specifically includes: (21) depositing an anti-reflection material in the second contact hole 350 and on the surface of the second dielectric layer 35 and planarizing to form a second anti-reflection layer 51, and forming a second photoresist structure 52 having an opening 520 on the surface of the second anti-reflection layer 51, wherein the opening 520 of the second photoresist structure 52 completely exposes the corresponding area of ​​the storage layer 34, such as Fig.14As shown; (22) using the second photoresist structure 52 as a mask to etch the second anti-reflection layer 51 and the second dielectric layer 35 to form the groove 351; (23) removing the second photoresist structure 52 and the remaining second anti-reflection layer 51 to obtain the groove 351 connected to the second contact hole 350, as shown Fig.15 shown.

[0058] In this embodiment, the second metal structure 36 is a T-shaped structure, including a first portion 361 in contact with a side of the storage layer 34 away from the first metal structure 33 and the extension portion 341, and a second portion 362 in contact with an end of the first portion 361 away from the extension portion 341; the second portion 362 has protrusions protruding from both sides of the first portion 361 along the first direction D1, and the surface of the second portion 362 is flush with the surface of the second dielectric layer 35. The first portion 361 is used as a second electrode layer and a second main connection structure at the same time, and the second portion 362 is used as a lead-out structure or a pad.

[0059] In this embodiment, a first auxiliary connection structure 321 is formed while forming the first main connection structure 322. The first auxiliary connection structure 321 penetrates the first dielectric layer 31 along the second direction D2 and is spaced apart from the first main connection structure 322 in the first direction D1. The second metal structure 36 further includes a third portion 363. One end of the third portion 363 contacts the second portion 362 and the other end contacts the first auxiliary connection structure 321. The third portion 363 serves as a second auxiliary connection structure. Fig.16 shown.

[0060] The memory cell of the three-dimensional memory prepared in this embodiment optimizes the upper and lower electrode layers into left and right electrode layers to realize the transformation of the traditional lateral memory cell (Cell) (such as Figure 1The storage unit 14 shown in the figure is optimized as a longitudinal storage unit (along the direction D2 shown in the figure). The effective area of ​​a single storage unit is increased, and a smaller area (Footprint) of a single storage unit can be achieved to save the occupied area of ​​the storage unit; the increase in the effective area of ​​the device can improve the storage performance, optimize and improve the operating efficiency and reliability of the device. In addition, the arrangement of the longitudinal storage unit in this embodiment makes it possible to form a first main connection structure 322 (lower contact hole process) when forming the first main connection structure 322 (lower contact hole process). Even if the lower contact hole process causes a protrusion in the first main connection structure 322 that contacts the first metal structure 33 (left electrode layer shown in the figure) as the first electrode layer, it will not affect the deposition and phase change performance of the storage layer 34, thereby avoiding affecting the performance of the storage unit; and when forming the second metal structure 36 (upper contact hole process) as the second electrode layer, there is no problem of etching through the storage layer 34, thereby further avoiding affecting the performance of the storage unit. In addition, the second metal structure 36 serves as both the second electrode layer and the second main connection structure. Compared with Figure 1 In the conventional method, there are three dielectric layers and three contact holes (VIA) mask processes. This embodiment only requires two dielectric layers and two contact holes (VIA) mask processes, saving one contact hole mask process, which can effectively reduce production costs. This embodiment solves the problem in the prior art that as the semiconductor process shrinks, the area of ​​the storage layer and the electrode layer of the storage unit becomes smaller, resulting in a reduction in the effective area of ​​the storage layer and the electrode layer, thereby affecting the storage performance of the memory, and saves the mask process, which can effectively reduce production costs.

[0061] Based on the same inventive concept, the present invention also provides a three-dimensional memory prepared by the above method of the present invention.

[0062] See also Figure 3~Figure 16 The three-dimensional memory described in this embodiment includes: a substrate 30, a first dielectric layer 31, a first main connection structure 322, a first metal structure 33, a storage layer 34, a second dielectric layer 35 and a second metal structure 36. The first metal structure 33 serves as a first electrode layer, the second metal structure 36 serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory.

[0063] In this embodiment, the second metal structure 36 is made of the same material as the first metal structure 33 , and is different from the first main connection structure 322 .

[0064] Specifically, the first dielectric layer 31 covers the surface of the substrate 30. The material of the first dielectric layer 31 may be an oxide (OX) material, such as silicon oxide (SiO).

[0065] Specifically, the first main connection structures 322 penetrate the first dielectric layer 31 along the second direction D2 and are arranged at intervals along the first direction D1. The first direction D1 is parallel to the surface of the substrate 30, and the second direction D2 is perpendicular to the surface of the substrate 30. The material of the first main connection structure 322 is metal tungsten. The top surface of the first main connection structure 322 is flush with the top surface of the first dielectric layer 31.

[0066] Specifically, the first metal structure 33 is formed on the surface of the first dielectric layer 31 and is in one-to-one contact with the first main connection structure 322. A plurality of the first metal structures 33 are arranged at intervals on the surface of the first dielectric layer 31. The material of the first metal structure 33 is selected from one of aluminum, copper, or aluminum-copper alloy, preferably copper wire.

[0067] Specifically, the storage layer 34 covers a side wall of the first metal structure 33 and has an extension portion 341 extending to the surface of the first dielectric layer 31. The material of the storage layer 34 is a ferroelectric material or a phase change material.

[0068] Specifically, the second dielectric layer 35 covers the first dielectric layer 31, all the first metal structures 33 and all the storage layers 34. The material of the second dielectric layer 35 can be the same as that of the first dielectric layer 31, both are oxide (OX) materials, such as silicon oxide (SiO).

[0069] Specifically, the second metal structure 36 penetrates the second dielectric layer 35 along the second direction D2, and contacts the side of the storage layer 34 away from the first metal structure 33 and the extension portion 341. The material of the second metal structure 36 can be selected from one of aluminum, copper, or aluminum-copper alloy, preferably copper wire. In the second direction D2, the height of the second metal structure 36 is greater than the height of the first metal structure 33, so that the effective area of ​​the electrode plate of the formed storage unit can be increased. The second metal structure 36 and the first metal structure 33 are arranged in pairs, and form a longitudinal (along the D2 direction shown in the figure) storage unit with the middle storage layer 34, which can save the occupied area of ​​the storage unit and increase the effective area of ​​the device.

[0070] In this embodiment, a gate structure 39 is further formed on the surface of the substrate 30, the first dielectric layer 31 further covers the gate structure 39, and the first main connection structure 322 is disposed along the first direction D1 on both sides of the gate structure 39. The gate structure 39 includes a polysilicon gate 391, a gate oxide layer 392 located below the polysilicon gate 391, and a sidewall 393 located on the sidewall of the polysilicon gate 391.

[0071] In this embodiment, the material of the storage layer 34 is a ferroelectric material or a phase change material, the materials of the first dielectric layer 31 and the second dielectric layer 35 are both oxide materials, the material of the first main connection structure 322 is metal tungsten, and the material of the first metal structure 33 and the second metal structure 36 is the same and are both selected from one of aluminum, copper, or aluminum-copper alloy, preferably copper wire.

[0072] In this embodiment, the material of the first metal structure 33 is copper metal; the three-dimensional memory further includes a diffusion barrier layer 50, the diffusion barrier layer 50 at least covers the first metal structure 33. The material of the diffusion barrier layer 50 is a material that can block the diffusion of copper metal, for example, W-Si-N ternary compound, WCN ternary compound, titanium nitride, tantalum nitride, etc.

[0073] In this embodiment, the second metal structure 36 is a T-shaped structure, including a first portion 361 in contact with a side of the storage layer 34 away from the first metal structure 33 and the extension portion 341, and a second portion 362 in contact with an end of the first portion 361 away from the extension portion 341; the second portion 362 has protrusions protruding from both sides of the first portion 361 along the first direction D1, and the surface of the second portion 362 is flush with the surface of the second dielectric layer 35. The first portion 361 is used as a second electrode layer and a second main connection structure at the same time, and the second portion 362 is used as a lead-out structure or a pad.

[0074] In this embodiment, the three-dimensional memory further includes: a first auxiliary connection structure 321, the first auxiliary connection structure 321 and the first main connection structure 322 are formed by the same process, the first auxiliary connection structure 321 penetrates the first dielectric layer 31 along the second direction D2, and is spaced apart from the first main connection structure 322 in the first direction D1. The second metal structure 36 further includes a third portion 363, one end of the third portion 363 is in contact with the second portion 362, and the other end is in contact with the first auxiliary connection structure 321, and the third portion 363 serves as a second auxiliary connection structure, such as Fig.16 shown.

[0075] In the above description, the description of well-known components and technologies is omitted to avoid unnecessary confusion of the concept of the present invention. In the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0076] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only include those elements, but also include other elements not clearly listed, or also include elements inherent to such process, method, article or equipment. In the absence of more restrictions, there is a sentence "also includes a ..." The elements limited do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In addition, the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0077] The above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. It should be noted that a person skilled in the art may make several improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention.

Claims

1. A method for preparing a three-dimensional memory, characterized in that: The method comprises the following steps: forming a semiconductor substrate, the semiconductor substrate comprising a substrate, a first dielectric layer covering the surface of the substrate, first main connection structures penetrating the first dielectric layer along a second direction and arranged at intervals along the first direction, and a first metal structure formed on the surface of the first dielectric layer and in one-to-one contact with the first main connection structure, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; forming a storage layer, the storage layer covering a side wall of the first metal structure and having an extension extending to the surface of the first dielectric layer; forming a second dielectric layer, the second dielectric layer covering the first dielectric layer, all the first metal structures and all the storage layers; and forming a second metal structure, the second metal structure penetrating the second dielectric layer along the second direction and contacting the storage layer away from the first metal structure. One side of the metal structure is in contact with the extension portion; wherein the first metal structure serves as the first electrode layer, the second metal structure serves as the second electrode layer and the second main connection structure at the same time, and the first electrode layer, the storage layer, and the second electrode layer constitute a storage unit of the three-dimensional memory; the step of forming the second metal structure specifically includes: forming a second contact hole in the second dielectric layer to expose the side of the storage layer away from the first metal structure and the extension portion; enlarging the aperture of the second contact hole at one end away from the extension portion to form a groove connected to the second contact hole; depositing a second metal material and flattening it to form the second metal structure; wherein the second metal structure in the second contact hole serves as the second electrode layer and the second main connection structure at the same time, and the second metal structure in the groove serves as a lead-out structure or a pad.

2. The method according to claim 1, characterized in that The second metal structure is made of the same material as the first metal structure and is different from the first main connection structure.

3. The method according to claim 1, characterized in that The material of the storage layer is ferroelectric material or phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the material of the first main connection structure is metal tungsten, and the material of the first metal structure and the second metal structure are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

4. The method according to claim 1, characterized in that: The steps of forming a semiconductor substrate specifically include: providing a substrate, the first dielectric layer is formed on the surface of the substrate, and first contact holes are formed in the first dielectric layer, which penetrate the first dielectric layer along the second direction and are arranged at intervals along the first direction; filling the first contact hole with a first metal material to form the first main connection structure; forming an etching stop layer and a sacrificial layer on the surface of the first dielectric layer; etching the sacrificial layer and the etching stop layer with a preset mask as a mask to form a first through hole exposing the first main connection structure; depositing a second metal material and planarizing it to form the first metal structure in the first through hole; and removing the remaining sacrificial layer and the etching stop layer.

5. The method according to claim 1, characterized in that The step of forming the storage layer specifically includes: depositing storage material to form a storage material layer covering the first dielectric layer and all the first metal structures; depositing anti-reflection material on the surface of the storage material layer and flattening it to form a first anti-reflection layer, and forming a first photoresist structure on the surface of the first anti-reflection layer, wherein the first photoresist structure has a shielding portion that shields a side wall of the first metal structure and a portion of the first dielectric layer corresponding to the side wall; etching using the first photoresist structure as a mask to etch the remaining storage material layer to form the storage layer.

6. The method according to claim 1, characterized in that The material of the first metal structure is copper. The step of forming the second dielectric layer includes: forming a diffusion barrier layer, the diffusion barrier layer at least covers the first metal structure, and the material of the diffusion barrier layer is a material that can block the diffusion of copper.

7. The method according to claim 1, characterized in that The step of enlarging the aperture of the second contact hole at the end away from the extension portion to form a groove connected to the second contact hole specifically includes: depositing an anti-reflection material in the second contact hole and on the surface of the second dielectric layer and flattening it to form a second anti-reflection layer, and forming a second photoresist structure with an opening on the surface of the second anti-reflection layer, wherein the opening of the second photoresist structure completely exposes the corresponding area of ​​the storage layer; etching the second anti-reflection layer and the second dielectric layer using the second photoresist structure as a mask to form the groove; and removing the second photoresist structure and the remaining second anti-reflection layer.

8. The method according to claim 1, characterized in that The second metal structure is a T-shaped structure, including a first part that contacts a side of the storage layer away from the first metal structure and the extension, and a second part that contacts an end of the first part away from the extension, the second part having protrusions protruding from both sides of the first part along the first direction, and the surface of the second part is flush with the surface of the second dielectric layer; wherein the first part serves as both a second electrode layer and a second main connection structure, and the second part serves as a lead-out structure or a pad.

9. The method according to claim 8, characterized in that A first auxiliary connection structure is formed while the first main connection structure is formed. The first auxiliary connection structure penetrates the first dielectric layer along the second direction and is spaced apart from the first main connection structure in the first direction. The second metal structure also includes a third part, one end of the third part is in contact with the second part and the other end is in contact with the first auxiliary connection structure, and the third part serves as a second auxiliary connection structure.

10. A three-dimensional memory, characterized in that: include: substrate; A first dielectric layer, covering the surface of the substrate; A first main connection structure penetrates the first dielectric layer along a second direction and is arranged at intervals along the first direction, wherein the first direction is parallel to the substrate surface and the second direction is perpendicular to the substrate surface; a first metal structure is formed on the surface of the first dielectric layer and is in one-to-one contact with the first main connection structure; a storage layer covers a side wall of the first metal structure and has an extension extending to the surface of the first dielectric layer; a second dielectric layer covers the first dielectric layer, all the first metal structures and all the storage layers; and a second metal structure penetrates the second dielectric layer along the second direction and is in contact with a side of the storage layer away from the first metal structure and the extension; wherein the first metal structure serves as a first electrode layer, the second metal structure serves as a second electrode layer and a second main connection structure at the same time, and the first electrode layer, the storage layer and the second electrode layer constitute a storage unit of the three-dimensional memory; the second metal structure The structure is a T-shaped structure, including a first part in contact with a side of the storage layer away from the first metal structure and the extension, and a second part in contact with an end of the first part away from the extension, the second part has protrusions protruding from both sides of the first part along the first direction, and the surface of the second part is flush with the surface of the second dielectric layer; wherein the first part is used as a second electrode layer and a second main connection structure at the same time, and the second part is used as a lead-out structure or a pad; the three-dimensional memory also includes: a first auxiliary connection structure, which is formed by the same process as the first main connection structure, the first auxiliary connection structure penetrates the first dielectric layer along the second direction, and is spaced apart from the first main connection structure in the first direction, wherein the second metal structure also includes a third part, one end of the third part is in contact with the second part, and the other end is in contact with the first auxiliary connection structure, and the third part is used as a second auxiliary connection structure.

11. The three-dimensional memory according to claim 10, characterized in that: The second metal structure is made of the same material as the first metal structure and is different from the first main connection structure.

12. The three-dimensional memory according to claim 10, characterized in that: The material of the storage layer is ferroelectric material or phase change material, the materials of the first dielectric layer and the second dielectric layer are both oxide materials, the material of the first main connection structure is metal tungsten, and the material of the first metal structure and the second metal structure are the same and are both selected from one of aluminum, copper, or aluminum-copper alloy.

13. The three-dimensional memory according to claim 10, characterized in that: The material of the first metal structure is metal copper; The three-dimensional memory further includes: a diffusion barrier layer, the diffusion barrier layer at least covers the first metal structure, and the material of the diffusion barrier layer is a material capable of blocking the diffusion of metal copper.

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