Gallium oxide devices with strong heat dissipation integrating thermoelectric materials and their fabrication methods

Abstract

This invention discloses a gallium oxide device with integrated thermoelectric material for enhanced heat dissipation, aiming to solve the problems of severe self-heating, reduced reliability, and decreased output power in existing gallium oxide devices. The key technology is to improve the device's heat dissipation performance through the thermoelectric effect. Specifically, a series of thermoelectric cooling modules are added between the substrate and the heat transfer interface layer of the gallium oxide field-effect transistor. These modules are surrounded by an insulating support material, and patterned metal electrode layers are set on their upper and lower surfaces to achieve isolation between the modules. By applying a voltage to the thermoelectric material to generate a current, the temperature on one side of the substrate is significantly reduced, accelerating heat transfer from the substrate to the heat transfer interface layer. For vertical gallium oxide diodes, this thermoelectric cooling unit is added between the cathode electrode and the heat transfer interface layer. Applying a voltage induces a thermoelectric effect, increasing heat transfer from the cathode electrode to the heat transfer interface layer. This invention can alleviate the device's self-heating effect, improve device reliability, and can be used as a microwave power device and a power electronic device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a gallium oxide device and its preparation method, which can be used as a microwave power device and a power electronic device. Background Technology

[0002] Ga2O3 is a type of ultra-wide bandgap semiconductor material, classified into five categories based on its crystal structure: α-Ga2O3, β-Ga2O3, γ-Ga2O3, δ-Ga2O3, and ε-Ga2O3. Among these, β-Ga2O3 exhibits the best physical and chemical stability, remaining the most stable under normal temperature and pressure conditions, making it the preferred material for fabricating Ga2O3 devices. Compared to traditional semiconductors like Si and Ge, and third-generation semiconductors such as SiC and GaN, β-Ga2O3 boasts a high bandgap of 4.8 eV and a critical breakdown field strength of 8 MV / cm, resulting in higher output power density and breakdown voltage. Furthermore, since β-Ga2O3 can be grown using the melt-grown method, similar to Si, it offers a significant cost advantage compared to the expensive production costs of other wide-bandgap semiconductor materials, making it a highly promising material for next-generation electronic devices.

[0003] Although β-Ga₂O₃ devices have been extensively studied and reported, demonstrating excellent performance in microwave power devices and power electronic devices, this material also faces many challenges that need to be addressed. The most critical issue is the extremely low thermal conductivity of β-Ga₂O₃, which is only one-thirtieth that of SiC and one-tenth that of GaN. Under high-power operation, this low thermal conductivity makes it difficult to effectively dissipate heat from the device's heat source, leading to a rapid accumulation of heat in a small area, thus affecting electron mobility and device stability. Furthermore, high temperatures can induce thermal stress within the device, which can cause performance failure or shorten its lifespan. The low thermal conductivity of β-Ga₂O₃ significantly limits its application in high-power, high-temperature environments. Therefore, optimizing the heat dissipation performance of β-Ga₂O₃ devices is crucial for enhancing their electrical performance and stability.

[0004] Patent application CN202111669320.2 discloses a method for fabricating a high-efficiency heat-dissipating diamond / Ga2O3 heterojunction diode. This method involves growing an n-type Ga2O3 epitaxial layer on a diamond substrate and then fabricating the device, thereby enhancing the device's high-temperature stability. However, a significant interfacial thermal resistance exists between the high thermal conductivity substrate and the Ga2O3, which limits the improvement of the device's heat dissipation performance. Therefore, further optimization is needed to improve its heat dissipation effect.

[0005] Patent document CN202210192776.2 discloses a Ga2O3 Schottky diode with a P-type diamond tilted mesa junction termination, the device structure of which is as follows: Figure 5 As shown, from top to bottom, the device comprises an anode metal, a P-type diamond layer, an n-Ga2O3 drift layer, an n+-Ga2O3 layer, and a cathode metal. The device deposits a diamond layer on the Ga2O3 surface, which allows heat to dissipate directly from the device surface near the heat source. However, the diamond deposition process requires extremely high temperatures, which may generate additional stress at the diamond interface, thus affecting the overall performance of the device.

[0006] Patent document with application number CN202310474680.X discloses a heterogeneous integrated Ga2O3 field-effect transistor with microchannels and its fabrication method. The device structure is as follows: Figure 6 As shown, it includes a supporting substrate and a gallium oxide layer with metal electrodes above it. The gallium oxide layer has a first trench penetrating the gallium oxide layer, and the supporting substrate has a second trench and a third trench with a cooling medium inlet / outlet. The second trench connects the first trench and the third trench. This Ga2O3 field-effect transistor uses embedded microchannels fabricated in the substrate, allowing coolant to flow directly through the region near the heat source, effectively reducing the heat conduction distance and improving the device's heat dissipation capacity. However, this method requires continuous coolant delivery during device operation, which increases additional energy consumption, and its process is complex and costly. Summary of the Invention

[0007] The purpose of this invention is to address the shortcomings of the prior art by proposing a Ga2O3 device with integrated thermoelectric materials and its preparation method, so as to further improve the heat dissipation efficiency of Ga2O3 devices, avoid the negative impact of introducing additional stress on device performance, and reduce energy loss.

[0008] The technical solutions for achieving the objectives of this invention include the following:

[0009] Technical Solution 1:

[0010] A high-heat-dissipation Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) integrating thermoelectric materials, comprising, from bottom to top: a heat sink layer, a heat transfer interface layer, a substrate, a buffer layer, a channel layer, a dielectric layer, and metal electrodes located on the channel layer and the dielectric layer, characterized in that:

[0011] The substrate and the heat transfer interface layer are provided with a plurality of thermoelectric cooling modules arranged in sequence. Each thermoelectric cooling module includes a symmetrical N-type thermoelectric material layer and a P-type thermoelectric material layer, and its upper and lower surfaces are respectively provided with a patterned upper metal electrode layer and a lower metal electrode layer.

[0012] The upper surface of the upper metal electrode layer and the lower surface of the substrate are provided with a substrate insulating layer to achieve electrical isolation between the thermoelectric cooling module and the substrate;

[0013] Each thermoelectric cooling module is surrounded by an insulating support material to support the deposition and patterning of the underlying metal electrode layer and to achieve mutual isolation between each thermoelectric cooling module.

[0014] Preferably, the N-type thermoelectric material layer and the P-type thermoelectric material layer in each thermoelectric cooling module are symmetrically distributed with a spacing of 10μm to 20μm, and adjacent thermoelectric cooling modules are distributed with an equal spacing of 10μm to 30μm.

[0015] Preferably, the N-type thermoelectric material layer in the thermoelectric cooling module is any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03μm to 3000μm and a side length of 60μm to 200μm;

[0016] The P-type thermoelectric material layer in the thermoelectric cooling module is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3, or other P-type materials with thermoelectric effect, and its thickness and side length are the same as those of the N-type thermoelectric material layer.

[0017] Preferably, the patterned upper and lower metal electrode layers are made of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material, with a thickness of 240-2100 nm, and are connected in series with each thermoelectric cooling module to apply voltage to form current, so as to create a temperature difference between the upper and lower surfaces of the thermoelectric cooling module and improve the heat dissipation capacity of the device.

[0018] The substrate insulating layer is made of SiO2 or Si3N4, and its thickness is 0.1μm to 1μm;

[0019] The insulating support material is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer and the thermoelectric cooling module.

[0020] Technical Solution 2:

[0021] A high-heat-dissipation vertical Ga2O3 heterojunction diode (HJD) integrating thermoelectric materials, comprising, from bottom to top: a heat dissipation layer, a thermal interface layer, a cathode electrode, and an n-type electrode. + β-Ga2O3 substrate, n - The β-Ga2O3 epitaxial layer, the p-type epitaxial layer, and the anode electrode are characterized by:

[0022] The cathode electrode and the thermal interface layer are provided with a plurality of thermoelectric cooling units arranged in sequence. Each thermoelectric cooling unit includes a symmetrically distributed N-type thermoelectric material layer and a P-type thermoelectric material layer, and its upper and lower surfaces are respectively provided with a patterned upper electrode layer and a lower electrode layer.

[0023] An isolation layer is provided on one side from the upper surface of the upper electrode layer to the lower surface of the cathode electrode to achieve electrical isolation between the thermoelectric refrigeration unit and the cathode electrode;

[0024] Each thermoelectric cooling unit is surrounded by an insulating filler material to support the deposition and patterning of the lower electrode layer, while also achieving electrical isolation between adjacent thermoelectric cooling units.

[0025] Preferably, the N-type thermoelectric material layer in the thermoelectric refrigeration unit is any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0026] The P-type thermoelectric material layer in the thermoelectric refrigeration unit is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0027] The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in a single thermoelectric refrigeration unit is 10-20 μm, and the spacing between two adjacent thermoelectric refrigeration units is 10-30 μm.

[0028] The patterned upper and lower electrode layers are made of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material, with a thickness of 240-2100nm. They are used to connect each thermoelectric cooling unit in series and apply voltage to form current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling unit, thereby improving the heat dissipation capacity of the device.

[0029] The isolation layer is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm;

[0030] The insulating filler material is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper electrode layer and the thermoelectric cooling unit.

[0031] Technical Solution 3:

[0032] A method for fabricating a device according to technical solution 1, characterized by comprising the following steps:

[0033] S1) High-temperature annealing was used to heterobond the pre-prepared β-Ga2O3 wafer with buffer layer and channel layer to the substrate, and the β-Ga2O3 wafer was thinned by ion cutting and the surface of the channel layer was smoothed.

[0034] S2) An epitaxial dielectric layer is grown on the channel layer, and then the electrode metal is deposited by electron beam evaporation of E-Beam, followed by ion implantation isolation;

[0035] S3) The upper surface of the device after electrode deposition is connected to an external carrier wafer through a bonding process;

[0036] S4) Pre-treatment of the back side of the substrate by grinding, thinning, and surface polishing;

[0037] S5) A substrate insulating layer and an upper metal electrode layer are deposited sequentially on the lower surface of the pretreated substrate by plasma-enhanced chemical vapor deposition (PECVD) and electron beam evaporation (E-Beam).

[0038] S6) On the upper metal electrode layer, N-type thermoelectric material and P-type thermoelectric material deposition areas are defined and N-type thermoelectric material layers and P-type thermoelectric material layers are deposited respectively by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module.

[0039] S7) Insulating support material is deposited or spin-coated around the thermoelectric cooling module by plasma-enhanced chemical vapor deposition (PECVD).

[0040] S8) A metal electrode layer is deposited on the thermoelectric cooling module and the insulating support material by electron beam evaporation of E-Beam;

[0041] S9) The heat sink material is bonded to the surface of the lower metal electrode layer through a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

[0042] Technical Solution 4:

[0043] A method for fabricating a device according to technical solution 2, characterized by comprising the following steps:

[0044] 1) For n + The surface of the β-Ga2O3 substrate was first subjected to organic ultrasonic cleaning, followed by metal-organic chemical vapor deposition (MOCVD) epitaxy and magnetron sputtering deposition of n-type substrates. - β-Ga2O3 epitaxial layer and p-type epitaxial layer;

[0045] 2) In n + The cathode electrode is deposited on the back side of the β-Ga2O3 substrate by electron beam evaporation of E-beam, followed by rapid thermal annealing;

[0046] 3) The anode electrode region is first formed on the p-type epitaxial layer by photolithography, and then the anode electrode is deposited by electron beam evaporation of E-beam;

[0047] 4) The upper surface of the device after anode electrode deposition is connected to an external carrier wafer via a bonding process;

[0048] 5) An isolation layer and an upper electrode layer are deposited sequentially on the lower surface of the cathode electrode by plasma-enhanced chemical vapor deposition (PECVD) and electron beam evaporation (E-Beam).

[0049] 6) On the upper electrode layer, N-type thermoelectric material and P-type thermoelectric material deposition regions are defined and N-type thermoelectric material layers and P-type thermoelectric material layers are deposited respectively by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling unit.

[0050] 7) Insulating filler material is deposited or spin-coated around the thermoelectric refrigeration unit using plasma-enhanced chemical vapor deposition (PECVD).

[0051] 8) Electrode layers are deposited on the thermoelectric cooling unit and insulating filler material by electron beam evaporation of E-Beam;

[0052] 9) The heat sink material is bonded to the surface of the lower electrode layer using a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

[0053] Compared with the prior art, the present invention has the following advantages:

[0054] Firstly, the Ga2O3 device of technical solution 1 of this invention has a thermoelectric cooling module between the substrate and the heat transfer interface layer. Voltage is applied to the upper and lower metal electrode layers on the upper and lower surfaces of the thermoelectric cooling module, thereby generating current within the module. This maintains a low temperature on the upper surface of the thermoelectric cooling module near the substrate, accelerating heat conduction from the substrate and optimizing the device's heat dissipation capacity. Simultaneously, since the thermoelectric cooling technology only requires applying voltage to the thermoelectric cooling module to generate current, the energy consumed in transporting coolant is reduced compared to microfluidic cooling technology, thus lowering energy loss. Furthermore, the use of a high thermal conductivity substrate, SiC or AlN, significantly reduces heat accumulation in the device, further improving heat dissipation performance. Moreover, since the heat dissipation structure is optimized directly during device fabrication, the tedious process and process damage associated with subsequent heat dissipation optimization are avoided.

[0055] Secondly, the Ga2O3 device of technical solution 2 of the present invention has a thermoelectric cooling unit between the cathode electrode and the thermal interface layer. By applying voltage to the upper and lower electrode layers on the upper and lower surfaces of the thermoelectric cooling unit, the thermoelectric material in the thermoelectric cooling unit can generate heat through a thermoelectric effect, which reduces the temperature of the upper surface of the thermoelectric cooling unit, thereby significantly improving the heat dissipation performance of the device. At the same time, the thermoelectric cooling technology used is an active cooling strategy. Compared with the passive cooling method that relies on a high thermal conductivity substrate or passivation layer, it can more effectively reduce the thermal resistance of the device, thereby achieving a better heat dissipation effect. This solution also solves the problem of additional stress that may be generated when the high thermal conductivity material is in direct contact with the Ga2O3 device. In addition, by directly heterogeneously integrating the thermoelectric cooling unit on the device, not only is the heat propagation path shortened, but the overall heat dissipation efficiency of the device is also improved. This integration method also facilitates the miniaturization of the device, which helps to reduce the size and weight of the device, thereby improving the reliability and stability of the device. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the structure of the device in technical solution 1 of the present invention;

[0057] Figure 2 This is a schematic diagram of the structure of the device in technical solution 2 of the present invention;

[0058] Figure 3 This is a schematic diagram of the manufacturing process of the device in technical solution 1 of the present invention;

[0059] Figure 4 This is a schematic diagram of the manufacturing process of the device in technical solution 2 of the present invention;

[0060] Figure 5 This is a schematic diagram of a gallium oxide Schottky diode with a P-type diamond tilted mesa junction terminal, as described in patent document CN202210192776.2.

[0061] Figure 6 This is a schematic diagram of a heterogeneous integrated gallium oxide field-effect transistor with microchannels from the patent document with application number CN202310474680.X. Detailed Implementation

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0063] Reference Figure 1 The present invention relates to a Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated thermoelectric materials, comprising a heat sink layer 1, a heat transfer interface layer 2, a thermoelectric cooling module 3, a substrate insulating layer 41, a substrate 4, a buffer layer 5, a channel layer 6, a dielectric layer 7, and a source S, a drain D, and a gate G, wherein:

[0064] The substrate 4 is made of SiC or AlN and has a thickness of 100–400 μm.

[0065] The buffer layer 5 is made of β-Ga2O3 with a thickness of 0.3 to 3 μm and is located on the substrate 4.

[0066] The channel layer 6 is made of β-Ga2O3 with a thickness of 10-500 nm and is located above the buffer layer 5.

[0067] The dielectric layer 7 is made of Al2O3 or NiO or Al2O3 and Hf. 0.5 Zr 0.5 O2, with a thickness of 20–100 nm, is located above channel layer 6.

[0068] The source S and drain D are made of Ti / Au with a thickness of 20-60 / 60-300 nm and are located above the channel layer 6; the gate G is made of Ni / Au with a thickness of 20-60 / 60-300 nm and is located between the source S and drain D and above the dielectric layer 7.

[0069] The substrate insulating layer 41 is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm. It is located on the back side of the substrate 4.

[0070] The adjacent thermoelectric cooling modules 3 are spaced 10–30 μm apart. Each thermoelectric cooling module 3 includes an N-type thermoelectric material layer and a P-type thermoelectric material layer spaced 10–20 μm apart. The N-type thermoelectric material layer is any one of Bi2Te3, Bi2(TeSe)3, PbTe, or other N-type materials with thermoelectric effect, with a thickness of 0.03–3000 μm and a side length of 60–200 μm. The P-type thermoelectric material layer is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3, or other P-type materials with thermoelectric effect, with a thickness of 0.03–3000 μm and a side length of 60–200 μm. It is located on the lower surface of the substrate insulating layer 41.

[0071] The thermoelectric cooling module 3 has an upper metal electrode layer 31 and a lower metal electrode layer 32 on its upper and lower surfaces, respectively. The thickness of each layer is 240-2100 nm, and both layers are formed by deposition of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material.

[0072] The thermoelectric cooling module 3 is surrounded by an insulating support material 33, which can be any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer 31 and the thermoelectric cooling module 3.

[0073] The heat transfer interface layer 2 is made of any one of silicone, silicone grease or epoxy resin, with a thickness of 1 to 50 μm, and is located on the lower surface of the lower metal electrode layer.

[0074] The heat sink layer 1 is made of any one of copper alloy, aluminum alloy or high thermal conductivity ceramic material, with a thickness of 0.1 to 10 mm, and is located on the lower surface of the heat transfer interface layer.

[0075] Reference Figure 2 The present invention relates to a high-heat-dissipation vertical Ga2O3 heterojunction diode (HJD) integrating thermoelectric materials, comprising a heat dissipation layer a, a thermal interface layer b, a thermoelectric cooling unit c, an isolation layer d, a cathode electrode e, and n. + β-Ga2O3 substrate f, n - β-Ga₂O₃ epitaxial layer g, p-type epitaxial layer h, anode electrode i, wherein:

[0076] The n + The substrate is β-Ga2O3 with a thickness of 300–500 μm.

[0077] The n - The β-Ga2O3 epitaxial layer g has a thickness of 5–30 μm and is located at n. + On a β-Ga2O3 substrate f.

[0078] The p-type epitaxial layer h is made of NiO with a thickness of 300–600 nm, and it is located in the n-type epitaxial layer. - Above the β-Ga2O3 epitaxial layer g.

[0079] The anode electrode i is made of Ni / Au with a thickness of 20-60 / 60-300 nm and is located on the p-type epitaxial layer h.

[0080] The cathode electrode e is made of Ti / Au with a thickness of 20–60 / 60–300 nm, and it is located at n + Back side of β-Ga2O3 substrate.

[0081] The isolation layer d is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm. It is located on the back side of the cathode electrode e.

[0082] The adjacent thermoelectric cooling units c are spaced 10–30 μm apart. Each thermoelectric cooling unit c includes an N-type thermoelectric material layer and a P-type thermoelectric material layer spaced 10–20 μm apart. The N-type thermoelectric material layer is any one of Bi2Te3, Bi2(TeSe)3, PbTe, or other N-type materials with thermoelectric effect, with a thickness of 0.03–3000 μm and a side length of 60–200 μm. The P-type thermoelectric material layer is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3, or other P-type materials with thermoelectric effect, with a thickness of 0.03–3000 μm and a side length of 60–200 μm, and is located on the lower surface of the isolation layer d.

[0083] The upper and lower surfaces of the thermoelectric cooling unit c are respectively provided with an upper electrode layer c1 and a lower electrode layer c2, both with a thickness of 240-2100nm, and both are deposited using Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material.

[0084] The thermoelectric cooling unit c is surrounded by an insulating filler material c3, which can be any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper electrode layer c1 and the thermoelectric cooling unit c.

[0085] The thermal interface layer b is made of any one of silicone, silicone grease or epoxy resin, with a thickness of 1 to 50 μm, and is located on the lower surface of the lower electrode layer.

[0086] The heat dissipation layer a is made of any one of copper alloy, aluminum alloy or high thermal conductivity ceramic material, with a thickness of 0.1 to 10 mm, and is located on the lower surface of the thermal interface layer.

[0087] Reference Figure 3 This invention provides three embodiments for fabricating a Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) structure with integrated thermoelectric materials and strong heat dissipation, but the embodiments of this invention are not limited to these. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials described are commercially available unless otherwise specified.

[0088] Example 1: A Ga2O3 metal oxide semiconductor field-effect transistor (MOSFET) is fabricated in a thermoelectric cooling module with an N-type thermoelectric material layer of Bi2Te3, a P-type thermoelectric material layer of Sb2Te3, a thickness of 50nm, a dielectric layer of Al2O3, and a thickness of 20nm.

[0089] Step 1: The pre-prepared β-Ga2O3 wafer with buffer layer 5 and channel layer 6 is heterobonded to substrate 4, and the β-Ga2O3 wafer is thinned. Then, the channel layer 6 is smoothed, as shown below. Figure 3 (a).

[0090] 1.1) Select a SiC substrate 4 with a thickness of 600μm and perform organic ultrasonic cleaning with acetone, isopropanol and deionized water in sequence. The cleaning time is 15min, 10min and 5min respectively, and the ultrasonic power is 100W. After cleaning, use N2 to dry the surface of SiC substrate 4.

[0091] 1.2) Select a pre-prepared β-Ga2O3 wafer, which includes a 0.3 μm thick, unintentionally doped β-Ga2O3 buffer layer 5 and a 500 μm thick, doped layer with a concentration of 1×10⁻⁶. 18 cm -3 H ion implantation is performed on one side of the β-Ga2O3 channel layer 6, with the aim of forming defects in the β-Ga2O3 wafer 1 μm away from the surface of the buffer layer 5.

[0092] 1.3) The front side of the SiC substrate 4 was bombarded with Ar ions for 2 min to form an amorphous layer. Then, the front side of the SiC substrate 4 and one side of the β-Ga2O3 wafer buffer layer 5 were bonded by high-temperature annealing in a vacuum. The annealing temperature was 860℃ and the time was 30s.

[0093] 1.4) The bonded wafer is placed in an N2 environment and subjected to a second annealing at 830°C for 20 min to remove the β-Ga2O3 wafer from the defect, leaving a buffer layer 5 with a thickness of 0.3 μm and a channel layer 6 with a thickness of 0.7 μm on the SiC substrate surface.

[0094] 1.5) The surface of the channel layer 6 is ground and polished using chemical mechanical polishing (CMP) technology to reduce the thickness of the channel layer 6 to 50 nm.

[0095] Step 2: Epitaxially grow a dielectric layer 7 on the channel layer 6, then deposit source (S), drain (D), and gate (G) metals on the channel layer 6 and dielectric layer 7 respectively, and perform ion implantation to isolate the device, such as... Figure 3 (b)

[0096] 2.1) Using atomic layer deposition (ALD) technology, an Al2O3 dielectric layer 7 with a thickness of 20 nm was deposited on the channel layer 6 under the process conditions of a reaction chamber temperature of 360℃ and a pressure of 1.5 mbar.

[0097] 2.2) Photolithography is performed on the surface of dielectric layer 7, that is, a layer of photoresist is first coated on dielectric layer 7, and then alignment, exposure, development and pattern detection are performed in sequence to form the active region of the device from source S to drain D.

[0098] 2.3) The dielectric layer 7 outside the active region is etched by inductively coupled plasma etching (ICP) until the channel layer 6 is exposed. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0099] 2.4) The source and drain regions are formed by photolithography on the surface of channel layer 6. The channel layer 6 in the source and drain regions is then ion-implanted and doped to reduce the resistance of the source and drain regions. The doping element is Si, and the doping concentration is 1×10⁻⁶. 19 cm -3 ;

[0100] 2.5) E-Beam is evaporated by electron beam, with the working chamber evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 6KV, electron gun beam current of 1A, and evaporation time of 80s, Ti / Au with a thickness of 20 / 60nm is deposited in the source and drain regions as source (S) and drain (D), and then the wafer is placed in photoresist stripping solution to remove photoresist.

[0101] 2.6) The wafer with completed source S and drain D metal deposition was rapidly annealed in N2 environment for 35s at an annealing temperature of 860℃ to form good ohmic contact at the contact surface of source, drain and channel layer 6.

[0102] 2.7) The gate region is formed again by photolithography on the surface of dielectric layer 7, and E-Beam is evaporated by electron beam evaporation. The vacuum level in the working chamber is then reduced to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 6KV, electron gun beam current of 1A, and evaporation time of 80s, Ni / Au with a thickness of 20 / 60nm is deposited in the gate region as gate G, and then the wafer is placed in photoresist stripping solution to remove photoresist.

[0103] 2.8) Ion implantation technology was used, with an implantation energy of 360 keV and an ion concentration of 1×10⁻⁶. 14 cm -2 Under the specified process conditions, high-energy ion implantation is performed on the surface of the channel layer outside the active region of the wafer to complete device isolation.

[0104] Step 3: The upper surface of the device with deposited electrode metal is bonded to the external carrier wafer using bonding adhesive, and pressure is applied to bond them together, such as... Figure 3 (c)

[0105] Step 4: Pre-treat the back side of SiC substrate 4, such as... Figure 3 (d)

[0106] 4.1) Thin the back side of the SiC substrate 4, which has a substrate 4, a buffer layer 5, a channel layer 6, a dielectric layer 7, and a source electrode S, a drain electrode D, and a gate electrode G, by grinding to reduce its thickness to 100 μm.

[0107] 4.2) Polishing technology is used to finely process the back side of the thinned SiC substrate 4 in order to improve the smoothness and flatness of the wafer surface.

[0108] Step 5: Deposit a substrate insulating layer 41 and an upper metal electrode layer 31 sequentially on the back side of the pretreated substrate 4, such as... Figure 3 (e).

[0109] 5.1) Plasma-enhanced chemical vapor deposition (PECVD) was used, with flow rates of 10 cm⁻¹ for SiH₄ and NH₃, respectively. 3 / min, 5cm 3 Under the process conditions of 0.1 μm / min, temperature of 200℃, growth pressure of 100Pa, and RF power of 50W, a Si3N4 substrate insulating layer 41 with a thickness of 0.1 μm was deposited on the back side of a SiC substrate.

[0110] 5.2) Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0111] 5.3) E-Beam was evaporated by electron beam, and the working chamber was evacuated to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 260s, Au / Ni with a thickness of 200 / 60nm is deposited as the upper metal electrode layer 31 in the region where the upper metal electrode is deposited, and then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0112] Step 6: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as... Figure 3 (f).

[0113] 6.1) Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 60μm and the spacing is 80μm.

[0114] 6.2) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TMBi of 5, a temperature of 350℃, and a growth pressure of 450mbar, a 50nm thick N-type Bi2Te3 layer was deposited in the region where N-type thermoelectric material was deposited as an N-type thermoelectric material layer. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0115] 6.3) The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 60 μm and is 10 μm away from the adjacent N-type thermoelectric material layer.

[0116] 6.4) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a DipTe to TDSb flow rate ratio of 2, a temperature of 300℃, and a growth pressure of 350mbar, a 50nm thick P-type Sb2Te3 layer was deposited in the region where P-type thermoelectric material was deposited as a P-type thermoelectric material layer. The wafer was then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of the thermoelectric cooling module 3.

[0117] Step 7: Deposit insulating support material 33 around the thermoelectric cooling module 3, such as... Figure 3 (g)

[0118] 7.1) Photolithography is performed again on the surface of the substrate insulating layer 41. That is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the insulating support material is deposited.

[0119] 7.2) Plasma-enhanced chemical vapor deposition (PECVD) was used, with flow rates of 30 cm⁻¹ for SiH₄ and NH₃, respectively. 3 / min, 20cm 3 Under the process conditions of 400℃, 150Pa growth pressure, and 500W RF power, Si3N4 is deposited in the area where the insulating support material is deposited until its height is flush with the thermoelectric cooling module as the insulating support material 33. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0120] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as... Figure 3 (h).

[0121] 8.1) Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer.

[0122] 8.2) E-Beam was evaporated by electron beam, with the working chamber evacuated to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 260s, a Ni / Au layer with a thickness of 60 / 200nm is deposited as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0123] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, as shown. Figure 3 (i).

[0124] 9.1) Using a spin coating process, epoxy resin is dropped onto a copper-molybdenum alloy heat sink 1 with a thickness of 0.1 mm, and then rotated at a speed of 4000 r / s for 40 s to obtain an epoxy resin film with a thickness of 2 μm as the heat transfer interface layer 2. The surface 32 of the lower metal electrode layer and the epoxy resin film are bonded together, and then the film is placed in an oven to cure the epoxy resin film at 80°C for 10 min to complete the heat sink connection.

[0125] 9.2) Use debonding adhesive to remove the temporarily bonded carrier wafers on the device surface to complete the device fabrication.

[0126] Example 2: A Ga2O3 metal oxide semiconductor field-effect transistor with a heterojunction is fabricated in a thermoelectric cooling module. The N-type thermoelectric material layer is Bi2(TeSe)3, the P-type thermoelectric material layer is (BiSb)2Te3 with a thickness of 50μm, and the dielectric layer is NiO with a thickness of 120nm.

[0127] Step 1: The pre-prepared β-Ga2O3 wafer with buffer layer 5 and channel layer 6 is heterobonded to the substrate, and the β-Ga2O3 wafer is thinned. Then, the channel layer 6 is smoothed. Figure 3 (a).

[0128] An AlN substrate 4 with a thickness of 600 μm was selected and subjected to organic ultrasonic cleaning in sequence with acetone, isopropanol and deionized water. The cleaning times were 15 min, 10 min and 5 min respectively, and the ultrasonic power was 100 W. After cleaning, the surface of AlN substrate 4 was dried with N2.

[0129] A pre-prepared β-Ga2O3 wafer was selected, comprising a 1.5 μm thick, unintentionally doped β-Ga2O3 buffer layer 5 and a 500 μm thick, doped layer with a doping concentration of 5 × 10⁻⁶. 17 cm -3 H ion implantation is performed on one side of the β-Ga2O3 channel layer 6, with the aim of forming defects in the β-Ga2O3 wafer at a distance of 2.5 μm from the surface of the buffer layer 5.

[0130] Ar ions were bombarded on the front side of AlN substrate 4 for 2 min to form an amorphous layer. Then, the front side of AlN substrate 4 and one side of β-Ga2O3 wafer buffer layer 5 were bonded by high-temperature annealing in vacuum at a temperature of 800℃ for 1 min.

[0131] The bonded wafer was placed in an N2 environment and subjected to a second annealing at 760°C for 40 minutes to remove the β-Ga2O3 wafer from the defect, leaving a buffer layer 5 with a thickness of 1.5 μm and a channel layer 6 with a thickness of 1 μm on the AlN substrate.

[0132] Chemical mechanical polishing (CMP) technology was used to grind and polish the surface of the channel layer 6 to reduce the thickness of the channel layer 6 to 250 nm.

[0133] Step 2: Epitaxially grow a dielectric layer 7 on the channel layer 6, then deposit source (S), drain (D), and gate (G) metals on the channel layer 6 and dielectric layer 7 respectively, and perform ion implantation to isolate the device, such as... Figure 3 (b)

[0134] The vacuum level in the deposition chamber is set to 6 × 10⁻⁶. -4 Under the process conditions of 3 Pa growth pressure and 25 W sputtering power, a p-type NiO dielectric layer 7 with a thickness of 120 nm and a doping concentration of 2 × 10⁻⁶ was deposited on the channel layer 6 by magnetron sputtering. 18 cm -3 .

[0135] Photolithography is performed on the surface of dielectric layer 7, that is, a layer of photoresist is first coated on dielectric layer 7, and then alignment, exposure, development, and pattern detection are performed in sequence to form the active region from the source S to the drain D of the device.

[0136] The dielectric layer 7 outside the active region is etched using inductively coupled plasma etching (ICP) technology until the channel layer 6 is exposed. Then the wafer is placed in a photoresist stripping solution to remove the photoresist.

[0137] The source and drain regions were formed by photolithography on the surface of channel layer 6. Ion implantation doping was then performed on the channel layer of the source and drain regions to reduce their resistance. The doping element was Si, and the doping concentration was 1×10⁻⁶. 19 cm -3 ;

[0138] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 0.5A, and evaporation time of 240s, Ti / Au with a thickness of 40 / 200nm is deposited in the source and drain regions as source (S) and drain (D) by electron beam evaporation of E-Beam. The wafer is then placed in photoresist stripping solution to remove the photoresist.

[0139] The wafer with completed source S and drain D metal deposition was placed in an annealing furnace and rapidly annealed for 40 seconds in an N2 environment at a temperature of 830°C to form ohmic contacts on the contact surfaces of the source, drain and channel layer 6.

[0140] The gate region was formed again by photolithography on the surface of dielectric layer 7, with the working chamber vacuum level set to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 0.5A, and evaporation time of 240s, Ni / Au with a thickness of 40 / 200nm is deposited as gate G in the gate region by electron beam evaporation of E-Beam. Then the wafer is placed in photoresist stripping solution to remove photoresist.

[0141] The injection energy was set to 340 keV and the ion concentration to 5 × 10⁻⁶. 14 cm -2 Under the specified process conditions, high-energy ion implantation is performed on the surface of the channel layer 6 outside the active region of the wafer using ion implantation technology to complete device isolation.

[0142] Step 3: The upper surface of the device with deposited electrode metal is bonded to the external carrier wafer using bonding adhesive, and pressure is applied to bond them together. Figure 3 (c)

[0143] Step 4: Pre-treat the back side of AlN substrate 4, such as... Figure 3 (d)

[0144] The back side of the AlN substrate 4, which contains a substrate 4, a buffer layer 5, a channel layer 6, a dielectric layer 7, and source S, drain D, and gate G, is thinned by grinding to reduce its thickness to 200 μm.

[0145] Polishing technology was used to finely process the back side of the thinned AlN substrate 4, aiming to improve the smoothness and flatness of the wafer surface.

[0146] Step 5: Deposit a substrate insulating layer 41 and an upper metal electrode layer 31 sequentially on the back side of the pretreated substrate 4, such as... Figure 3 (e).

[0147] The flow rates of SiH4 and N2O were set to 60 cm⁻¹. 3 / min, 180cm 3 Under the process conditions of 270℃, 90Pa growth pressure, and 80W RF power, a SiO2 substrate insulating layer 41 with a thickness of 0.4μm was deposited on the back side of AlN substrate 4 by plasma-enhanced chemical vapor deposition (PECVD).

[0148] Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0149] Set the working chamber to a vacuum level of 2.5 x 10. -4Under the process conditions of Pa, electron gun accelerating voltage of 9KV, electron gun beam current of 0.7A, and evaporation time of 880s, Cu / Au with a thickness of 800 / 80nm is deposited as the upper metal electrode layer 31 in the region where the upper metal electrode is deposited by electron beam evaporation of E-Beam. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0150] Step Six: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as... Figure 3 (f).

[0151] Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. Each region has a side length of 120μm and a spacing of 155μm.

[0152] The process conditions were set as follows: the flow rate ratio of DipTe to TMBi was 8, the flow rate ratio of DipTe to DESe was 3, the temperature was 500℃, and the growth pressure was 460mbar. Using metal-organic chemical vapor deposition (MOCVD), a 50μm thick layer of N-type Bi2(TeSe)3 was deposited as the N-type thermoelectric material layer in the region where N-type thermoelectric material was deposited. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0153] The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 120 μm and is 15 μm away from the nearest adjacent N-type thermoelectric material layer and 20 μm away from the farthest adjacent N-type thermoelectric material layer.

[0154] The process conditions were set as follows: the flow rate ratio of DipTe to TMBi was 5, the flow rate ratio of TMBi to TDSb was 3, the temperature was 380℃, and the growth pressure was 420mbar. Using metal-organic chemical vapor deposition (MOCVD), a 50μm thick layer of P-type (BiSb)2Te3 was deposited as the P-type thermoelectric material layer in the region where P-type thermoelectric material was deposited. The wafer was then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of thermoelectric cooling module 3.

[0155] Step 7: Deposit insulating support material 33 around the thermoelectric cooling module 3, such as... Figure 3 (g)

[0156] Photolithography is performed again on the surface of the substrate insulating layer 41. That is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the insulating support material is deposited.

[0157] The flow rates of SiH4 and N2O were set to 80 cm⁻¹. 3 / min, 200cm 3 Under the process conditions of 90W / min, temperature of 280℃, growth pressure of 100Pa, and RF power of 90W, SiO2 was deposited in the area where the insulating support material was deposited until its height was flush with that of the thermoelectric cooling module, as the insulating support material 33. Then the wafer was placed in the photoresist stripping solution to remove the photoresist.

[0158] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as... Figure 3 (h).

[0159] Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer.

[0160] Set the working chamber to a vacuum level of 2.5 x 10. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9KV, electron gun beam current of 0.7A, and evaporation time of 880s, E-Beam is evaporated by electron beam to deposit Au / Cu with a thickness of 80 / 800nm ​​as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0161] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, as follows. Figure 3 (i).

[0162] Using a spin coating process, silicone is dropped onto an aluminum-magnesium-silicon alloy heat sink 1 with a thickness of 1 mm, and then rotated at a speed of 3500 r / s for 35 s to obtain a silicone film with a thickness of 5 μm as a heat transfer interface layer 2. The surface of the lower metal electrode layer 32 and the silicone film are bonded together, and then the silicone film is cured in an oven at 120℃ for 15 min to complete the heat sink connection.

[0163] The device fabrication is completed by using a debonding adhesive to remove the temporarily bonded carrier wafers on the device surface.

[0164] In Example 3, the N-type thermoelectric material layer of the thermoelectric cooling module is PbTe, the P-type thermoelectric material layer is Bi2Te3, and the thickness is 500μm. The dielectric layer is Al2O3 and Hf. 0.5 Zr 0.5 O2, Ga2O3 metal oxide semiconductor field-effect transistors with ferroelectric storage gates with thicknesses of 15nm and 30nm respectively.

[0165] Step A: The pre-prepared β-Ga2O3 wafer with buffer layer 5 and channel layer 6 is heterobonded to substrate 4, and the β-Ga2O3 wafer is thinned. Then, the channel layer 6 is smoothed, as shown below. Figure 3 (a).

[0166] A1) Select a SiC substrate 4 with a thickness of 600μm and perform organic ultrasonic cleaning with acetone, isopropanol and deionized water in sequence. The cleaning time is 15min, 10min and 5min respectively, and the ultrasonic power is 100W. After cleaning, use N2 to dry the surface of SiC substrate 4.

[0167] A2) Select a pre-prepared β-Ga2O3 wafer, which includes a 2μm thick, unintentionally doped β-Ga2O3 buffer layer 5 and a 500μm thick, doped layer with a doping concentration of 8×10⁻⁶. 17 cm -3 H ion implantation is performed on one side of the β-Ga2O3 channel layer 6, with the aim of forming defects in the β-Ga2O3 wafer at a distance of 3 μm from the surface of the buffer layer 5.

[0168] A3) The front side of the SiC substrate 4 is bombarded with Ar ions for 2 min to form an amorphous layer. Then, the front side of the SiC substrate 4 and one side of the β-Ga2O3 wafer buffer layer 5 are bonded by high-temperature annealing in a vacuum. The annealing temperature is 760℃ and the time is 2 min.

[0169] A4) The bonded wafer is placed in an N2 environment and subjected to a second annealing at 680°C for 2 hours to remove the β-Ga2O3 wafer from the defect, leaving a buffer layer 5 with a thickness of 2μm and a channel layer 6 with a thickness of 1μm on the SiC substrate.

[0170] A5) The surface of the channel layer 6 is ground and polished using chemical mechanical polishing (CMP) technology to reduce the thickness of the channel layer 6 to 400 nm.

[0171] Step B: Epitaxially grow a dielectric layer 7 on the channel layer 6, then deposit source (S), drain (D), and gate (G) metals on the channel layer 6 and dielectric layer 7 respectively, and perform ion implantation to isolate the device, such as... Figure 3 (b)

[0172] B1) Using atomic layer deposition (ALD) technology, Al2O3 with a thickness of 15 nm and Hf with a thickness of 30 nm were sequentially deposited on channel layer 6. 0.5 Zr 0.5 The process conditions for atomic layer deposition (ALD) of Al2O3 in which O2 is used as the dielectric layer 7 are as follows:

[0173] The temperature of the reaction chamber is 360℃.

[0174] The pressure in the reaction chamber is 2 mbar.

[0175] Deposition of Hf 0.5 Zr 0.5 The process conditions for atomic layer deposition (ALD) of O2 are as follows:

[0176] The temperature of the reaction chamber is 280℃.

[0177] The pressure in the reaction chamber is 3.2 mbar;

[0178] B2) Photolithography is performed on the surface of dielectric layer 7, that is, a layer of photoresist is first coated on dielectric layer 7, and then alignment, exposure, development and pattern detection are performed in sequence to form the active region from the source S to the drain D of the device.

[0179] B3) The dielectric layer 7 outside the active region is etched using inductively coupled plasma etching (ICP) technology until the channel layer 6 is exposed. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0180] B4) Photolithography is performed on the surface of channel layer 6 to form source and drain regions. Ion implantation technology is used to dope the channel layer in the source and drain regions to reduce the resistance of the source and drain regions. The ion implantation process conditions are as follows:

[0181] The doping element is Si.

[0182] Doping concentration of 1×10 19 cm -3 ;

[0183] B5) Electron beam evaporation of E-Beam is used to deposit Ti / Au with a thickness of 60 / 300 nm as the source (S) and drain (D) regions. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0184] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Pa,

[0185] The electron gun accelerating voltage is 10 kV.

[0186] The electron gun beam current is 0.1A.

[0187] The evaporation time is 360 seconds.

[0188] B6) Place the wafer with completed source S and drain D metal deposition into an annealing furnace and rapidly anneal it in an N2 environment for 45 seconds at an annealing temperature of 800°C to form ohmic contacts on the contact surfaces of the source, drain and channel layer 6.

[0189] B7) The surface of dielectric layer 7 is photolithographically etched again to form the gate region. E-Beam is evaporated by electron beam to deposit a Ni / Au layer with a thickness of 60 / 300nm as the gate G in the gate region. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0190] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Pa,

[0191] The electron gun accelerating voltage is 10 kV.

[0192] The electron gun beam current is 0.1A.

[0193] The evaporation time is 360 seconds.

[0194] B8) Set the injection energy to 320 keV and the ion concentration to 8 × 10⁻⁶. 14 cm -2 Under the specified process conditions, ion implantation technology was used to perform high-energy ion implantation on the surface of the channel layer 6 outside the active region of the wafer to complete device isolation.

[0195] Step C: The upper surface of the device with deposited electrode metal is bonded to the external carrier wafer using bonding adhesive, and pressure is applied to bond them together, such as... Figure 3 (c)

[0196] Step D: Pre-treat the back side of SiC substrate 4, such as... Figure 3 (d)

[0197] D1) Thinning the back side of the SiC substrate 4, which contains a substrate 4, a buffer layer 5, a channel layer 6, a dielectric layer 7, and source S, drain D, and gate G, to reduce its thickness to 300 μm.

[0198] D2) Polishing technology is used to finely process the back side of the thinned SiC substrate 4, aiming to improve the smoothness and flatness of the wafer surface.

[0199] Step E: Deposit a substrate insulating layer 41 and an upper metal electrode layer 31 sequentially on the back side of the pretreated substrate 4, such as... Figure 3 (e).

[0200] E1) A SiO2 substrate insulating layer 41 with a thickness of 0.8 μm was deposited on the back side of the SiC substrate 4 using plasma-enhanced chemical vapor deposition (PECVD) technology. The PECVD process conditions are as follows:

[0201] The flow rates of SiH4 and N2O were 70 cm⁻¹. 3 / min, 190cm 3 / min,

[0202] The temperature is 280℃.

[0203] The growth pressure is 90 Pa.

[0204] The radio frequency power is 90W;

[0205] E2) Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0206] E3) Electron beam evaporation of E-Beam is used to deposit a Cu / Ni layer with a thickness of 2000 / 100 nm as the upper metal electrode layer 31 in the region where the upper metal electrode is deposited. Then, the wafer is placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0207] The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa,

[0208] The electron gun accelerating voltage is 10 kV.

[0209] The electron gun beam current is 0.4A.

[0210] The evaporation time is 2100s.

[0211] Step F: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as... Figure 3 (f).

[0212] F1) Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 200μm and the spacing is 250μm.

[0213] F2) Metal-organic chemical vapor deposition (MOCVD) technology was used to deposit a 500 μm thick N-type PbTe layer as the N-type thermoelectric material layer in the region where N-type thermoelectric material was deposited. The wafer was then placed in a photoresist stripping solution to remove the photoresist. The MOCVD process conditions were as follows:

[0214] The flow rate ratio of DipTe to TEL is 3.

[0215] The temperature is 500℃.

[0216] The growth pressure is 450 mbar;

[0217] F3) The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 200 μm and is 20 μm away from the nearest adjacent N-type thermoelectric material layer and 30 μm away from the farthest adjacent N-type thermoelectric material layer.

[0218] F4) Using metal-organic chemical vapor deposition (MOCVD), a 500 μm thick P-type Bi2Te3 layer is deposited as the P-type thermoelectric material layer in the region where P-type thermoelectric material is deposited. The wafer is then immersed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of thermoelectric cooling module 3. The MOCVD process conditions are as follows:

[0219] When the flow rate ratio of DipTe to TMBi is 8,

[0220] The temperature is 480℃.

[0221] The growth pressure is 560 mbar.

[0222] Step G: Deposit insulating support material 33 around the thermoelectric cooling module 3, such as... Figure 3 (g)

[0223] G1) Photolithography is performed on the surface of the substrate insulating layer 41. A layer of photoresist is first coated on the substrate insulating layer 41 using spin coating technology. Then, alignment, exposure, development, and pattern detection are performed sequentially. In the area where the insulating support material needs to be deposited, photoresist with a height flush with the thermoelectric cooling module is retained as the insulating support material 33. The spin coating process conditions are as follows:

[0224] The rotational speed is 2200 r / s.

[0225] Spin coating time is 30 seconds;

[0226] G2) The wafer with the completed insulating support material deposition is subjected to hard baking to prevent the photoresist from dissolving in the subsequent photoresist stripping solution or other etching solvents. The hard baking process conditions are as follows:

[0227] The baking temperature is 280℃.

[0228] Baking time is 15 minutes.

[0229] Step H: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as Figure 3 (h).

[0230] H1) Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer.

[0231] H2) By electron beam evaporation of E-Beam, a Ni / Cu layer with a thickness of 100 / 2000 nm is deposited as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0232] The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa,

[0233] The electron gun accelerating voltage is 10 kV.

[0234] The electron gun beam current is 0.4A.

[0235] The evaporation time is 2100s.

[0236] Step I: The heat sink layer 1 is bonded to the surface of the lower metal electrode layer via the heat transfer interface layer 2, and the carrier wafer is removed, as shown below. Figure 3 (i).

[0237] I1) Using a spin coating process, silicone grease is dropped onto a 6mm thick SiC ceramic heat sink 1 and then rotated at 1800r / s for 50s to obtain a 50μm thick silicone grease film as the heat transfer interface layer 2. The surface of the lower metal electrode layer 32 is bonded to the silicone grease film, and then it is placed in an oven to cure the silicone grease film at 280℃ for 20min to complete the heat sink connection.

[0238] I2) Use debonding adhesive to remove the temporarily bonded carrier wafers on the device surface to complete device fabrication.

[0239] Reference Figure 4 This invention provides three embodiments for fabricating a high-heat-dissipation vertical Ga2O3 heterojunction diode (HJD) structure integrating thermoelectric materials, but the implementation of this invention is not limited to these.

[0240] Example 4: A vertical Ga2O3 heterojunction diode (HJD) with a thickness of 40 μm is fabricated, in which the N-type thermoelectric material layer is Bi2(TeSe)3, the P-type thermoelectric material layer is (BiSb)2Te3.

[0241] Operation 1: After cleaning the substrate f, deposit n sequentially. - β-Ga2O3 epitaxial layer g and p-type epitaxial layer h, such as Figure 4 (a).

[0242] 1-1) Select a thickness of 400 μm and a Si doping concentration of 2 × 10⁻⁶. 18 cm -3 n +The β-Ga2O3 substrate f was subjected to organic ultrasonic cleaning in sequence with acetone, isopropanol and deionized water for 15 min, 10 min and 5 min respectively, with an ultrasonic power of 80 W. After cleaning, the substrate surface was dried with N2.

[0243] 1-2) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of an O2 to TMGa flow rate ratio of 25, a temperature of 620℃, and a growth pressure of 60 mbar, at n + The β-Ga2O3 substrate f has a deposition thickness of 15 μm and a Si doping concentration of 2 × 10⁻⁶. 16 cm -3 n - β-Ga2O3 epitaxial layer g.

[0244] 1-3) Using magnetron sputtering technology, the deposition chamber is evacuated to a vacuum of 6×10⁻⁶. -4 Under process conditions of Pa, growth pressure of 2 Pa, and sputtering power of 25 W, at n - The β-Ga2O3 epitaxial layer g has a deposition thickness of 450 nm and a doping concentration of 5 × 10⁻⁶. 17 cm -3 The p-NiO epitaxial layer h.

[0245] Operation 2: Fabricate the cathode electrode e, such as Figure 4 (b)

[0246] 2-1) E-beam is evaporated by electron beam, and the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8 kV, electron gun beam current of 0.5 A, and evaporation time of 250 s, at n + A Ti / Au cathode electrode with a thickness of 50 / 200 nm is deposited on the back side of a β-Ga2O3 substrate;

[0247] 2-2) The wafer with the cathode electrode deposited is placed in an annealing furnace and rapidly annealed in a N2 environment at a temperature of 840℃ for 35 seconds, in order to deposit the cathode electrode and the N2 atmosphere. + The β-Ga2O3 substrate forms a good ohmic contact at the interface.

[0248] Operation 3: Fabricate the anode electrode i, such as Figure 4 (c)

[0249] 3-1) Photolithography is performed on the surface of the p-NiO epitaxial layer h, that is, a layer of photoresist is first coated on the p-NiO epitaxial layer, and then alignment, exposure, development and pattern detection are performed in sequence to form the anode region of the device.

[0250] 3-2) E-beam is evaporated by electron beam, and the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8 kV, electron gun beam current of 0.5 A, and evaporation time of 250 s, a Ni / Au anode electrode with a thickness of 50 / 200 nm is deposited in the anode region to form a Schottky contact at the interface between the anode electrode and the p-NiO epitaxial layer. Finally, the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0251] Step 4: The upper surface of the device with deposited electrode metal is bonded to the external carrier wafer using bonding adhesive, and pressure is applied to bond them together. Figure 4 (d)

[0252] Step 5: Fabricate the isolation layer d and the upper electrode layer c1, as follows Figure 4 (e).

[0253] 5-1) Plasma-enhanced chemical vapor deposition (PECVD) was used with flow rates of 25 cm⁻¹ for SiH₄ and NH₃. 3 / min, 15cm 3 Under the process conditions of 0.6 μm / min, temperature of 320℃, growth pressure of 110 Pa, and RF power of 360 W, a Si3N4 isolation layer d with a thickness of 0.6 μm was deposited on the back side of the cathode electrode e.

[0254] 5-2) Photolithography is performed on the surface of the isolation layer d, that is, a layer of photoresist is first coated on the isolation layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area for deposition of the upper electrode;

[0255] 5-3) E-Beam is evaporated by electron beam in a chamber with a vacuum of 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9KV, electron gun beam current of 0.7A, and evaporation time of 1000s, a Cu / Ni layer with a thickness of 900 / 100nm is deposited as the upper electrode layer c1 in the region where the upper electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0256] Operation 6: Construct thermoelectric refrigeration unit c, such as Figure 4 (f).

[0257] 6-1) Photolithography is performed on the surface of the upper electrode layer c1. That is, a layer of photoresist is first coated on the upper metal electrode layer, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 120μm and the spacing is 155μm.

[0258] 6-2) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TMBi of 4, a flow rate ratio of DipTe to DESe of 1, a temperature of 480℃, and a growth pressure of 420mbar, an N-type Bi2(TeSe)3 layer with a thickness of 40μm was deposited in the region where N-type thermoelectric material was deposited as an N-type thermoelectric material layer. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0259] 6-3) The surface of the upper electrode layer c1 is photolithographically etched again to form a region for depositing P-type thermoelectric material. Multiple regions for depositing P-type thermoelectric material are formed, each region having a side length of 120 μm and a distance of 15 μm from the nearest adjacent N-type thermoelectric material layer and a distance of 20 μm from the farthest adjacent N-type thermoelectric material layer.

[0260] 6-4) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TMBi of 3, a flow rate ratio of TMBi to TDSb of 3, a temperature of 360℃, and a growth pressure of 420mbar, a 40μm thick P-type (BiSb)2Te3 layer is deposited in the region where P-type thermoelectric material is deposited as a P-type thermoelectric material layer. The wafer is then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of thermoelectric cooling unit c.

[0261] Operation 7: Deposit insulating filler material c3, such as Figure 4 (g)

[0262] 7-1) Photolithography is performed again on the surface of the isolation layer d, that is, a layer of photoresist is first coated on the isolation layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the insulating filling material is deposited;

[0263] 7-2) Using plasma-enhanced chemical vapor deposition (PECVD) technology, the flow rates of SiH4 and NH3 were 30 cm⁻¹. 3 / min, 20cm 3 Under the process conditions of 400℃, 150Pa growth pressure, and 500W RF power, Si3N4 is deposited in the area where the insulating filler material is deposited until its height is flush with the thermoelectric cooling unit as the insulating filler material c3. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0264] Step 8: Fabricate the lower electrode layer c2, as follows Figure 4 (h).

[0265] 8-1) Photolithography is performed on the surfaces of thermoelectric cooling unit c and insulating filling material c3. That is, a layer of photoresist is first coated on the thermoelectric cooling unit and insulating filling material, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited electrode layer.

[0266] 8-2) E-Beam is evaporated by electron beam in a chamber with a vacuum of 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.7 A, and evaporation time of 1000 s, a Ni / Cu layer with a thickness of 100 / 900 nm is deposited as the lower electrode layer c2 in the region where the lower electrode layer is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0267] Operation 9: Connect the heat dissipation layer a through the thermal interface layer b, and remove the carrier wafer, as follows. Figure 4 (i).

[0268] 9-1) After dripping silicone onto the surface of the copper-tungsten alloy heat dissipation layer a, rotate it at 3200 r / s for 35 s to obtain a silicone film with a thickness of 5 μm as the thermal interface layer b. Adhere the surface of the lower electrode layer to the silicone film, and then put it into an oven to cure the silicone film at 180℃ for 15 min to complete the heat dissipation layer connection.

[0269] 9-2) Use debonding adhesive to remove the temporarily bonded carrier wafers on the device surface, and finally complete the device fabrication.

[0270] Example 5: A vertical Ga2O3 heterojunction diode with an N-type thermoelectric material layer of PbTe and a P-type thermoelectric material layer of Bi2Te3 and a thickness of 400μm was fabricated in a thermoelectric refrigeration unit.

[0271] §1: After cleaning the substrate f, deposit n sequentially - β-Ga2O3 epitaxial layer g and p-type epitaxial layer h, such as Figure 4 (a).

[0272] A thickness of 500 μm and a Sn doping concentration of 1 × 10⁻⁶ were selected. 19 cm -3 n + The β-Ga2O3 substrate f was sequentially cleaned with acetone, isopropanol, and deionized water at an organic ultrasonic power of 80W for 15 min, 10 min, and 5 min, respectively, and then the substrate surface was dried with N2.

[0273] The process conditions were set as follows: O2 to TMGa flow rate ratio of 40, temperature of 700℃, and growth pressure of 65 mbar. Metal-organic chemical vapor deposition (MOCVD) technology was used to grow the material in n... + The β-Ga₂O₃ substrate f has a growth thickness of 30 μm and a Sn doping concentration of 1 × 10⁻⁶. 17 cm -3 n - β-Ga2O3 epitaxial layer g;

[0274] The vacuum level in the deposition chamber is set to 6 × 10⁻⁶. -4 Under process conditions of Pa, growth pressure of 5 Pa, and sputtering power of 30 W, magnetron sputtering technology was used to achieve the desired effect. - The β-Ga2O3 epitaxial layer g has a thickness of 600 nm and a doping concentration of 1 × 10⁻⁶. 19 cm -3 The p-NiO epitaxial layer h.

[0275] §2: Fabrication of the cathode electrode e, such as Figure 4 (b)

[0276] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Under process conditions of Pa, electron gun accelerating voltage of 6 kV, electron gun beam current of 1 A, and evaporation time of 360 s, E-beam is evaporated by electron beam in n + A Ti / Au cathode electrode with a thickness of 60 / 300 nm is deposited on the back side of a β-Ga2O3 substrate;

[0277] The wafer with the cathode electrode deposited is then placed in an annealing furnace and rapidly annealed for 40 seconds in a N2 environment at 820°C to deposit the cathode electrode and N2. + The β-Ga2O3 substrate forms a good ohmic contact at the interface.

[0278] §3: Fabrication of the anode electrode i, such as Figure 4 (c)

[0279] Photolithography is performed on the surface of the p-NiO epitaxial layer h, that is, a layer of photoresist is first coated on the p-NiO epitaxial layer, and then alignment, exposure, development, and pattern detection are performed sequentially to form the anode region of the device.

[0280] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 6KV, electron gun beam current of 1A, and evaporation time of 360s, E-beam is evaporated by electron beam to deposit a Ni / Au anode electrode with a thickness of 60 / 300nm in the anode region, so as to form a Schottky contact at the interface between the anode electrode and the p-NiO epitaxial layer. The wafer is then placed in the photoresist stripping solution to remove the photoresist.

[0281] §4: The upper surface of the device with deposited electrode metal is bonded to an external carrier wafer using bonding adhesive, and pressure is applied to achieve bonding, such as... Figure 4 (d)

[0282] §5: Fabrication of the isolation layer d and the upper electrode layer c1, as follows Figure 4 (e).

[0283] The flow rates of SiH4 and N2O were set to 80 cm⁻¹.3 / min, 200cm 3 Under the process conditions of 100 Pa growth pressure and 100 W RF power, a 1 μm thick SiO2 isolation layer d was deposited on the back side of the cathode electrode e by plasma enhanced chemical vapor deposition (PECVD).

[0284] Photolithography is performed on the surface of the isolation layer d, that is, a layer of photoresist is first coated on the isolation layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area for deposition of the upper electrode;

[0285] Set the vacuum level of the working chamber to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 2100s, Cu / Au with a thickness of 2000 / 100nm is deposited as the upper electrode layer c1 in the region where the upper electrode is deposited by electron beam evaporation of E-Beam. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0286] §6: Constructing thermoelectric refrigeration unit c, such as Figure 4 (f).

[0287] Photolithography is performed on the surface of the upper electrode layer c1. That is, a layer of photoresist is first coated on the upper metal electrode layer, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. Each region has a side length of 200μm and a spacing of 250μm.

[0288] The process conditions were set as follows: the flow rate ratio of DipTe to TEL was 3, the temperature was 500℃, and the growth pressure was 450mbar. Using metal-organic chemical vapor deposition (MOCVD), a 400μm thick N-type PbTe layer was deposited in the region where N-type thermoelectric material was deposited as an N-type thermoelectric material layer. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0289] The surface of the upper electrode layer c1 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 200 μm and is 20 μm away from the nearest adjacent N-type thermoelectric material layer and 30 μm away from the farthest adjacent N-type thermoelectric material layer.

[0290] Under process conditions of a DipTe to TMBi flow rate ratio of 10, a temperature of 500℃, and a growth pressure of 600mbar, a 400μm thick P-type Bi2Te3 layer was deposited as a P-type thermoelectric material layer in the region where P-type thermoelectric material was deposited using metal-organic chemical vapor deposition (MOCVD). The wafer was then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of the thermoelectric cooling unit c.

[0291] §7: Deposited insulating filler material c3, such as Figure 4 (g)

[0292] The process conditions are set to a rotation speed of 2500 r / s and a spin coating time of 40 s. Photolithography is performed on the surface of the isolation layer d. A layer of photoresist is first coated on the isolation layer by spin coating technology. Then, alignment, exposure, development, and pattern detection are performed in sequence. In the area where insulating filling material needs to be deposited, photoresist with a height flush with the thermoelectric cooling unit is retained as insulating filling material c3.

[0293] The wafer with the completed insulating filler material deposition was hard-baked under the process conditions of 260℃ and 8min to prevent the photoresist from dissolving in the photoresist stripping solution or other etching solvents used subsequently.

[0294] §8: Fabrication of the lower electrode layer c2, as follows Figure 4 (h).

[0295] Photolithography is performed on the surfaces of the thermoelectric cooling unit c and the insulating filling material c3. That is, a layer of photoresist is first coated on the thermoelectric cooling unit and the insulating filling material, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited electrode layer.

[0296] Set the vacuum level of the working chamber to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 2100s, E-Beam is evaporated by electron beam to deposit Au / Cu with a thickness of 100 / 2100nm as the lower electrode layer c2 in the region where the lower electrode layer is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0297] §9: Connect the heat dissipation layer a through the thermal interface layer b, and remove the carrier wafer, as shown. Figure 4 (i).

[0298] After applying silicone grease to the surface of the aluminum-silicon-carbon alloy heat dissipation layer a, rotate it at a speed of 2200 r / s for 40 s to obtain a silicone grease film with a thickness of 10 μm as the thermal interface layer b. Adhere the surface of the lower electrode layer to the silicone grease film, and then place it in an oven to cure the silicone grease film at 220℃ for 15 min to complete the heat dissipation layer connection.

[0299] The temporary bonded wafers on the device surface are removed using debonding adhesive to complete device fabrication.

[0300] Example 6: A vertical Ga2O3 heterojunction diode with an N-type thermoelectric material layer of Bi2Te3 and a P-type thermoelectric material layer of Sb2Te3 and a thickness of 50nm was fabricated in a thermoelectric cooling unit.

[0301] Step 1: After cleaning the substrate f, deposit n sequentially.- β-Ga2O3 epitaxial layer g and p-type epitaxial layer h, such as Figure 4 (a).

[0302] A-1) Select a thickness of 300 μm and a Si doping concentration of 5 × 10⁻⁶. 17 cm -3 n + The β-Ga2O3 substrate f was sequentially cleaned with acetone, isopropanol and deionized water using organic ultrasonic cleaning for 15 min, 10 min and 5 min respectively, with an ultrasonic power of 80 W. After cleaning, the substrate surface was dried with N2.

[0303] A-2) Using metal-organic chemical vapor deposition (MOCVD) technology, in n + The β-Ga2O3 substrate f has a deposition thickness of 5 μm and a Sn doping concentration of 5 × 10⁻⁶. 15 cm -3 n - The β-Ga2O3 epitaxial layer g, wherein the process conditions for metal-organic chemical vapor deposition (MOCVD) are as follows:

[0304] The flow rate ratio of O2 to TMGa is 10.

[0305] The temperature is 550℃.

[0306] The growth pressure is 55 mbar;

[0307] A-3) Employing magnetron sputtering technology, in n - The β-Ga2O3 epitaxial layer g has a thickness of 300 nm and a doping concentration of 1 × 10⁻⁶. 16 cm -3 The p-NiO epitaxial layer h, wherein the magnetron sputtering process conditions are as follows:

[0308] The vacuum level in the deposition chamber is 6×10 -4 Pa,

[0309] The growth pressure is 1 Pa.

[0310] The sputtering power is 20W.

[0311] Step 2: Fabricate the cathode electrode e, such as... Figure 4 (b)

[0312] B-1) Electron beam evaporation of E-beam is employed, in n + A Ti / Au cathode electrode with a thickness of 20 / 60 nm is deposited on the back side of the β-Ga2O3 substrate f, wherein the electron beam evaporation process conditions for the E-beam are as follows:

[0313] The vacuum level of the working chamber is 2.0 × 10⁻⁶.-4 Pa,

[0314] The electron gun accelerating voltage is 10 kV.

[0315] The electron gun beam current is 0.1A.

[0316] The evaporation time is 80 seconds;

[0317] B-2) The wafer with the cathode electrode deposited is placed in an annealing furnace. In an N2 environment, the furnace temperature is set to 860℃ for annealing for 30 seconds to deposit the cathode electrode and N2. + The β-Ga2O3 substrate forms a good ohmic contact at the interface.

[0318] Step 3: Fabricate the anode electrode i, as follows Figure 4 (c)

[0319] C-1) First, a layer of photoresist is coated on the p-NiO epitaxial layer h, and then alignment, exposure, development and pattern detection are performed in sequence to photolithographically form the anode region of the device on the surface of the p-NiO epitaxial layer.

[0320] C-2) An electron beam evaporation (E-Beam) is used to deposit a Ni / Au anode electrode I with a thickness of 20 / 60 nm in the anode region to form a Schottky contact. The process conditions for E-Beam evaporation are as follows:

[0321] The vacuum level of the working chamber is 2.0 × 10⁻⁶. -4 Pa,

[0322] The electron gun accelerating voltage is 10 kV.

[0323] The electron gun beam current is 0.1A.

[0324] The evaporation time is 80 seconds;

[0325] C-3) The wafer with the deposited anode electrode is placed in the photoresist stripping solution to remove the photoresist.

[0326] Step 4: The upper surface of the device with deposited electrode metal is bonded to the external carrier wafer using bonding adhesive, and pressure is applied to bond them together, such as... Figure 4 (d)

[0327] Step 5: Fabricate the isolation layer d and the upper electrode layer c1, as follows Figure 4 (e).

[0328] D-1) Plasma-enhanced chemical vapor deposition (PECVD) was used to deposit a 0.1 μm thick Si3N4 isolation layer d on the back side of the cathode electrode e. The PECVD process conditions were as follows:

[0329] The flow rates of SiH4 and NH3 were 10 cm⁻¹. 3 / min, 5cm 3 / min,

[0330] The temperature is 200℃.

[0331] The growth pressure is 100 Pa.

[0332] The radio frequency power is 50W;

[0333] D-2) Photolithography is performed on the surface of the isolation layer d, that is, a layer of photoresist is first coated on the isolation layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area for deposition of the upper electrode;

[0334] D-3) Electron beam evaporation of E-Beam is used to deposit a Ni / Au layer with a thickness of 200 / 40 nm as the upper electrode layer c1 in the region where the upper electrode is deposited. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0335] The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa,

[0336] The electron gun accelerating voltage is 8 kV.

[0337] The electron gun beam current is 0.9A.

[0338] The evaporation time is 240 seconds.

[0339] Step 6: Construct thermoelectric refrigeration unit c, such as Figure 4 (f).

[0340] E-1) Photolithography is performed on the surface of the upper electrode layer c1. That is, a layer of photoresist is first coated on the upper electrode layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 60μm and the spacing is 80μm.

[0341] E-2) Metal-organic chemical vapor deposition (MOCVD) technology is used to deposit a 50 nm thick N-type Bi₂Te₃ layer as the N-type thermoelectric material layer in the region where N-type thermoelectric material is deposited. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The MOCVD process conditions are as follows:

[0342] The flow rate ratio of DipTe to TMBi is 6.

[0343] The temperature is 260℃.

[0344] The growth pressure is 380 mbar;

[0345] E-3) The surface of the upper electrode layer c1 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 60 μm and is 10 μm away from the adjacent N-type thermoelectric material layer.

[0346] E-4) Using metal-organic chemical vapor deposition (MOCVD), a 50 nm thick P-type Sb₂Te₃ layer is deposited in the region where P-type thermoelectric material is deposited. The wafer is then immersed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of the thermoelectric cooling unit c. The MOCVD process conditions are as follows:

[0347] The flow rate ratio of DipTe to TDSb is 1.

[0348] The temperature is 320℃.

[0349] The growth pressure is 360 mbar.

[0350] Step 7: Deposit insulating filler material c3, such as Figure 4 (g)

[0351] F-1) Photolithography is performed again on the surface of the isolation layer d, that is, a layer of photoresist is first coated on the isolation layer, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the insulating filling material is deposited.

[0352] F-2) Plasma-enhanced chemical vapor deposition (PECVD) technology is used to deposit Si3N4 as insulating filler material c3 in the area where insulating filler material is deposited until its height is flush with the thermoelectric cooling unit. Then, the wafer is placed in a photoresist stripping solution to remove the photoresist. The process conditions of PECVD technology are as follows:

[0353] The flow rates of SiH4 and NH3 were 25 cm⁻¹. 3 / min, 15cm 3 / min,

[0354] The temperature is 380℃.

[0355] The growth pressure is 120 Pa.

[0356] The radio frequency power is 460W.

[0357] Step 8: Fabricate the lower electrode layer c2, as follows Figure 4 (h).

[0358] G-1) Photolithography is performed on the surfaces of the thermoelectric cooling unit c and the insulating filling material c3. That is, a layer of photoresist is first coated on the thermoelectric cooling unit and the insulating filling material, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited electrode layer.

[0359] G-2) Electron beam evaporation of E-Beam is used to deposit a 40 / 200 nm thick Au / Ni layer as the upper electrode layer c2 in the region where the lower electrode is deposited. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0360] The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa,

[0361] The electron gun accelerating voltage is 8 kV.

[0362] The electron gun beam current is 0.9A.

[0363] The evaporation time is 240 seconds.

[0364] Step 9: Connect the heat dissipation layer a through the thermal interface layer b, and remove the carrier wafer, as shown. Figure 4 (i).

[0365] H-1) After dripping epoxy resin onto the surface of the copper-molybdenum alloy heat dissipation layer a, rotate it at a speed of 4000 r / s for 30s to obtain an epoxy resin film with a thickness of 1μm as the thermal interface layer b. Then, bond the surface of the lower electrode layer to the epoxy resin film and place it in an oven to cure the epoxy resin film at 100℃ for 5min to complete the heat dissipation layer connection.

[0366] H-2) Use debonding adhesive to remove the temporarily bonded carrier wafers on the device surface to complete the final device fabrication.

[0367] The above descriptions are merely six specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to copper alloys and aluminum alloys, AlN ceramics can also be used for the heat sink layer and heat dissipation layer, and SiC ceramics can also be used; in addition to Bi2Te3 / Sb2Te3, Bi2(TeSe)3 / (BiSb)2Te3, and PbTe / Bi2Te3, other materials with thermoelectric effects can also be used for the thermoelectric cooling module and thermoelectric cooling unit; in addition to Au / Cu, Ni / Cu, and Ni / Au, other metals that match the thermoelectric materials can also be used for the upper and lower metal electrode layers. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A Ga2O3 metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated thermoelectric material, comprising, from bottom to top: a heat sink layer (1), a heat transfer interface layer (2), a substrate (4), a buffer layer (5), a channel layer (6), a dielectric layer (7), and metal electrodes located on the channel layer and the dielectric layer, characterized in that: The substrate (4) and the heat transfer interface layer (2) are provided with a plurality of thermoelectric cooling modules (3) arranged in sequence. Each thermoelectric cooling module includes a symmetrical N-type thermoelectric material layer and a P-type thermoelectric material layer, and its upper and lower surfaces are respectively provided with a patterned upper metal electrode layer (31) and a lower metal electrode layer (32). The upper surface of the upper metal electrode layer (31) and the lower surface of the substrate (4) are provided with a substrate insulating layer (41) to achieve electrical isolation between the thermoelectric cooling module and the substrate; Each thermoelectric cooling module (3) is surrounded by an insulating support material (33) to support the deposition and patterning of the lower metal electrode layer and to achieve mutual isolation between each thermoelectric cooling module.

2. The MOSFET device according to claim 1, characterized in that: In each thermoelectric cooling module (3), the N-type thermoelectric material layer and the P-type thermoelectric material layer are symmetrically distributed with a spacing of 10μm to 20μm, and adjacent thermoelectric cooling modules are distributed with an equal spacing of 10μm to 30μm.

3. The MOSFET device according to claim 1, characterized in that: The N-type thermoelectric material layer in the thermoelectric cooling module (3) is any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03μm to 3000μm and a side length of 60μm to 200μm; The P-type thermoelectric material layer in the thermoelectric cooling module (3) is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, and its thickness and side length are the same as those of the N-type thermoelectric material layer.

4. The MOSFET device according to claim 1, characterized in that: The patterned upper metal electrode layer (31) and lower metal electrode layer (32) are both made of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material, with a thickness of 240-2100nm, and are connected in series with each thermoelectric cooling module to apply voltage to form current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling module, thereby improving the heat dissipation capacity of the device. The substrate insulating layer (41) is made of SiO2 or Si3N4 and has a thickness of 0.1μm to 1μm; The insulating support material (33) is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer and the thermoelectric cooling module.

5. The MOSFET device according to claim 1, characterized in that: The heat transfer interface layer (2) is made of any one of silicone, silicone grease or epoxy resin, and its thickness is 1 to 50 μm; The heat sink layer (1) is made of any one of copper alloy, aluminum alloy or high thermal conductivity ceramic material, and its thickness is 0.1 to 10 mm. The copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

6. The MOSFET device according to claim 1, characterized in that: The substrate (4) is made of SiC or AlN and has a thickness of 100-400 μm; The buffer layer (5) is made of β-Ga2O3 and has a thickness of 0.3 to 3 μm; The channel layer (6) is made of β-Ga2O3 and has a thickness of 10-500 nm; The dielectric layer (7) is made of Al2O3 or NiO or Al2O3 and Hf. 0.5 Zr 0.5 O2, with a thickness of 20–100 nm.

7. A high-heat-dissipation vertical Ga2O3 heterojunction diode (HJD) integrating thermoelectric materials, comprising, from bottom to top: a heat dissipation layer (a), a thermal interface layer (b), a cathode electrode (e), and an n... + β-Ga2O3 substrate (f), n - The β-Ga2O3 epitaxial layer (g), the p-type epitaxial layer (h), and the anode electrode (i) are characterized by: Between the cathode electrode (e) and the thermal interface layer (b), there are multiple thermoelectric cooling units (c) arranged in sequence. Each thermoelectric cooling unit includes symmetrically distributed N-type thermoelectric material layers and P-type thermoelectric material layers, and its upper and lower surfaces are respectively provided with a patterned upper electrode layer (c1) and a lower electrode layer (c2). An isolation layer (d) is provided between the upper surface of the upper electrode layer (c1) and the lower surface of the cathode electrode (e) to achieve electrical isolation between the thermoelectric refrigeration unit (c) and the cathode electrode (e). Each thermoelectric cooling unit (c) is surrounded by an insulating filler material (c3) to support the deposition and patterning of the lower electrode layer (c2) and to achieve electrical isolation between each thermoelectric cooling unit (c).

8. The HJD device according to claim 7, characterized in that: The N-type thermoelectric material layer in the thermoelectric refrigeration unit (c) is any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The P-type thermoelectric material layer in the thermoelectric refrigeration unit (c) is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in a single thermoelectric refrigeration unit (c) is 10-20 μm, and the spacing between two adjacent thermoelectric refrigeration units is 10-30 μm; The patterned upper electrode layer (c1) and lower electrode layer (c2) are both made of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material, with a thickness of 240-2100nm. They are used to connect each thermoelectric cooling unit in series and apply voltage to it to form current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling unit, thereby improving the heat dissipation capacity of the device. The isolation layer (d) is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm; The insulating filler material (c3) is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper electrode layer and the thermoelectric cooling unit.

9. The HJD device according to claim 7, characterized in that: The thermal interface layer (b) is made of any one of silicone, silicone grease or epoxy resin, and its thickness is 1 to 50 μm. The heat dissipation layer (a) is made of any one of copper alloy, aluminum alloy or high thermal conductivity ceramic material, and its thickness is 0.1 to 10 mm. The copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

10. The HJD device according to claim 7, characterized in that: The n + A β-Ga₂O₃ substrate (f) with a thickness of 300–500 μm, doped with Si or Sn at a doping concentration of 5 × 10⁻⁶. 17 ~1×10 19 cm -3 ; The n - A β-Ga₂O₃ epitaxial layer (g) with a thickness of 5–30 μm, doped with Si or Sn at a doping concentration of 5 × 10⁻⁶. 15 ~1×10 17 cm -3 ; The p-type epitaxial layer (h) is made of NiO, with a thickness of 300–600 nm, and is doped with boron at a concentration of 1 × 10⁻⁶. 16 ~1×10 19 cm -3 .

11. A method for manufacturing a field-effect transistor as claimed in claim 1, characterized in that, Includes the following steps: S1) High-temperature annealing was used to heterobond the pre-prepared β-Ga2O3 wafer with buffer layer and channel layer to the substrate, and the β-Ga2O3 wafer was thinned by ion cutting, and the surface of the channel layer was smoothed. S2) An epitaxial dielectric layer is grown on the channel layer, and then the electrode metal is deposited by electron beam evaporation of E-Beam, followed by ion implantation isolation; S3) The upper surface of the electrode deposition sample is connected to the external carrier wafer through a bonding process; S4) Pre-treatment of the back side of the substrate by grinding, thinning, and surface polishing; S5) A substrate insulating layer and an upper metal electrode layer are deposited sequentially on the lower surface of the pretreated substrate by plasma-enhanced chemical vapor deposition (PECVD) and electron beam evaporation (E-Beam). S6) On the upper metal electrode layer, N-type thermoelectric material and P-type thermoelectric material deposition areas are defined and N-type thermoelectric material layers and P-type thermoelectric material layers are deposited respectively by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module. S7) Insulating support material is deposited or spin-coated around the thermoelectric cooling module by plasma-enhanced chemical vapor deposition (PECVD). S8) A metal electrode layer is deposited on the thermoelectric cooling module and the insulating support material by electron beam evaporation of E-Beam; S9) The heat sink material is bonded to the surface of the lower metal electrode layer through a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

12. The method according to claim 11, characterized in that: The electron beam evaporation of E-Beam in step S2) is performed under the following process conditions: The studio was vacuumed to 2.0×10. -4 Pa, electron gun accelerating voltage is 6-10 kV, electron gun beam current is 0.1-1 A, and evaporation time is 80-360 s; The electron beam evaporation of E-Beam in step S5) is performed under the following process conditions: The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa, electron gun accelerating voltage is 8-10 kV, electron gun beam current is 0.4-1 A, and evaporation time is 240-2100 s; In step S5), the plasma-enhanced chemical vapor deposition (PECVD) process conditions are as follows: SiO2 deposition uses SiH4 and N2O as precursor gases, with the flow rate maintained at 50–80 cm⁻¹. 3 / min, 160~200cm 3 The growth rate was maintained at 250–300℃, the growth pressure at 80–100Pa, and the RF power at 60–100W. Si3N4 was deposited using SiH4 and NH3 as precursor gases, with the flow rate maintained at 10–30 cm⁻¹. 3 / min, 5~20cm 3 The growth rate was maintained at 200–400℃, the growth pressure at 100–150 Pa, and the RF power at 50–500 W. The metal-organic chemical vapor deposition (MOCVD) process in step S6 is as follows: TMBi was used as the precursor of Bi, TDSb as the precursor of Sb, DipTe as the precursor of Te, TEL as the precursor of Pb, DESe as the precursor of Se, and high-purity H2 as the carrier gas. The flow rate ratio of DipTe to TMBi for Bi2Te3 deposition was 2–10, the temperature was maintained at 200–500℃, and the growth pressure was maintained at 300–600 mbar. The flow rate ratio of DipTe to TDSb for depositing Sb2Te3 was 1–6, the temperature was maintained at 250–450℃, and the growth pressure was maintained at 200–500 mbar. The flow rate ratio of DipTe to TEL for PbTe deposition was 1–3, the temperature was maintained at 300–500℃, and the growth pressure was maintained at 200–450 mbar. The flow rate ratio of DipTe to TMBi for depositing Bi2(TeSe)3 was 1–8, the flow rate ratio of DipTe to DESe was 1–3, the temperature was maintained at 220–600℃, and the growth pressure was maintained at 200–600 mbar. The flow rate ratio of DipTe to TMBi for (BiSb)2Te3 deposition was 1–5, the flow rate ratio of TMBi to TDSb was 2–4, the temperature was maintained at 200–550℃, and the growth pressure was maintained at 300–500 mbar.

13. A method for manufacturing the Ga2O3 diode of claim 7, characterized in that, Includes the following steps: 1) For n + The surface of the β-Ga2O3 substrate was first subjected to organic ultrasonic cleaning, followed by metal-organic chemical vapor deposition (MOCVD) epitaxy and magnetron sputtering deposition of n-type substrates. - β-Ga2O3 epitaxial layer and p-type epitaxial layer; 2) In n + The cathode electrode is deposited on the back side of the β-Ga2O3 substrate by electron beam evaporation of E-beam, followed by rapid thermal annealing; 3) The anode electrode region is first formed on the p-type epitaxial layer by photolithography, and then the anode electrode is deposited by electron beam evaporation of E-beam; 4) The upper surface of the device with the completed anode electrode deposition is connected to the external carrier wafer through a bonding process; 5) An isolation layer and an upper electrode layer are deposited sequentially on the lower surface of the cathode electrode by plasma-enhanced chemical vapor deposition (PECVD) and electron beam evaporation (E-Beam). 6) On the upper electrode layer, N-type thermoelectric material and P-type thermoelectric material deposition regions are defined and N-type thermoelectric material layers and P-type thermoelectric material layers are deposited respectively by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling unit. 7) Insulating filler material is deposited or spin-coated around the thermoelectric refrigeration unit using plasma-enhanced chemical vapor deposition (PECVD). 8) Electrode layers are deposited on the thermoelectric cooling unit and insulating filler material by electron beam evaporation of E-Beam; 9) The heat sink material is bonded to the surface of the lower electrode layer using a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

14. The method according to claim 13, characterized in that: The metal-organic chemical vapor deposition (MOCVD) process conditions in step 1) are as follows: TMGa is used as the precursor of Ga, O2 is used as the oxygen source, N2 is used as the carrier gas, the flow rate ratio of O2 to TMGa is 10 to 40, the temperature is maintained at 550 to 700°C, and the growth pressure is maintained at 55 to 65 mbar. The magnetron sputtering process in step 1) is performed under the following conditions: the deposition chamber is evacuated to 6 × 10⁻⁶ m³ / s. -4 Pa, the growth pressure is maintained at 1-5 Pa, and the sputtering power is set to 20-30 W; The electron beam evaporation (E-Beam) process conditions for steps 2) and 3) are as follows: the working chamber is evacuated to 2.0 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 6-10 kV, electron gun beam current is 0.1-1 A, and evaporation time is 80-360 s; The electron beam evaporation (E-Beam) process conditions in steps 5) and 8) are as follows: the working chamber is evacuated to 2.5 × 10⁻⁶. -4 Pa, electron gun accelerating voltage is 8-10 kV, electron gun beam current is 0.4-1 A, and evaporation time is 240-2100 s; The plasma-enhanced chemical vapor deposition (PECVD) in steps 5) and 7) is performed under the following process conditions: SiO2 deposition uses SiH4 and N2O as precursor gases, with the flow rate maintained at 50–80 cm⁻¹. 3 / min, 160~200cm 3 The growth rate was maintained at 250–300℃, the growth pressure at 80–100Pa, and the RF power at 60–100W. Si3N4 was deposited using SiH4 and NH3 as precursor gases, with the flow rate maintained at 10–30 cm⁻¹. 3 / min, 5~20cm 3 The growth rate was maintained at 200–400℃, the growth pressure at 100–150 Pa, and the RF power at 50–500 W. The metal-organic chemical vapor deposition (MOCVD) process in step 6) is performed under the following conditions: TMBi was used as the precursor of Bi, TDSb as the precursor of Sb, DipTe as the precursor of Te, TEL as the precursor of Pb, DESe as the precursor of Se, and high-purity H2 as the carrier gas. The flow rate ratio of DipTe to TMBi for Bi2Te3 deposition was 2–10, the temperature was maintained at 200–500℃, and the growth pressure was maintained at 300–600 mbar. The flow rate ratio of DipTe to TDSb for depositing Sb2Te3 was 1–6, the temperature was maintained at 250–450℃, and the growth pressure was maintained at 200–500 mbar. The flow rate ratio of DipTe to TEL for PbTe deposition was 1–3, the temperature was maintained at 300–500℃, and the growth pressure was maintained at 200–450 mbar. The flow rate ratio of DipTe to TMBi for depositing Bi2(TeSe)3 was 1–8, the flow rate ratio of DipTe to DESe was 1–3, the temperature was maintained at 220–600℃, and the growth pressure was maintained at 200–600 mbar. The flow rate ratio of DipTe to TMBi for (BiSb)2Te3 deposition was 1–5, the flow rate ratio of TMBi to TDSb was 2–4, the temperature was maintained at 200–550℃, and the growth pressure was maintained at 300–500 mbar.

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