An adaptive parameter configuration method for EMIF storage control interface

Abstract

An adaptive parameter configuration method for an EMIF storage control interface includes the following steps: 1. connecting a host to the EMIF interface, and then connecting multiple chip select spaces (CEs) on the EMIF interface to different and / or the same memory; 2. determining whether the adaptive configuration function is enabled; if not, proceeding to step 3; if so, proceeding to step 4; 3. manually configuring the parameters of the multiple chip select spaces (CEs) based on the storage characteristics; and 4. selecting one of two methods, an adaptive configuration method and a loop traversal method, to configure the parameters of the multiple chip select spaces (CEs). The present invention introduces an adaptive configuration mechanism with different configuration modes for three storage types. The controller automatically configures parameters using different strategies based on the connected storage type, thus resolving the technical problem of users needing to understand the storage characteristics, then manually configure and continuously debug the parameters based on the characteristics and timing, thereby shortening project development time.

Description

Technical Field

[0001] The present invention relates to the technical field of computer storage communication, and in particular to an adaptive parameter configuration method of an EMIF storage control interface. Background Art

[0002] The EMIF interface is the memory access interface for the chip to access external memory, enabling on-chip arithmetic units to access external memory. Supported memory types include synchronous static RAM, synchronous dynamic RAM, and asynchronous memory. The EMIF and external memory control signals primarily include the four chip select spaces (EMIFCE) CE0 to CE3 for connecting to the external memory space, the read / write data I / O signal EMIFD, the address signal EMIFA, the slot address select signal EMIFBA, the byte mask signal EMIFBE, and the write enable signal EMIFWE. Due to differences in external memory ports, the usage of these signals may vary slightly. The MTYPE (storage type) field in the CE space control register of the EMIF memory interface is used to configure the corresponding CE space connection storage type, indicating whether the space should perform synchronous or asynchronous storage operations. After the type is selected, parameters are configured in the corresponding CEx space control register for each type. Only after the parameter configuration is completed can storage read and write operations be performed.

[0003] Due to the wide variety of storage types, each with its own unique usage and process, controllers require extensive parameter configuration to adapt. This extensive configuration is required before any storage operations can be performed. Furthermore, when users lack a thorough understanding of certain parameters or are unfamiliar with the characteristics of storage chips, incorrect parameter configuration can lead to incorrect data transmission. These issues can consume significant developer time in storage debugging, delaying project development. Summary of the Invention

[0004] The present invention provides an adaptive parameter configuration method for an EMIF storage control interface to solve the technical problems mentioned in the background technology.

[0005] To achieve the above object, the technical solution of the present invention is achieved as follows:

[0006] The present invention provides an adaptive parameter configuration method for an EMIF storage control interface, which specifically includes the following steps:

[0007] S1. Connect the host to the EMIF storage control interface, and then connect multiple chip select spaces CE on the EMIF storage control interface to different and / or the same memories respectively;

[0008] S2, after the EMIF storage control interface waits for the system to be reset, it determines whether the adaptive configuration function is started. If not, it enters S3; if so, it enters S4;

[0009] S3. The user manually configures the parameters of multiple chip select spaces CE according to storage characteristics;

[0010] S4. According to the selection parameters configured by the user, one of the two methods, an adaptive configuration method and a cyclic traversal method, is selected to configure the parameters of one or more chip select spaces CE.

[0011] Furthermore, there are three types of memories in S1, namely asynchronous memory, synchronous static memory and synchronous dynamic random access memory.

[0012] Furthermore, the number of the chip select spaces CE is four, the four chip select spaces CE are respectively connected to one of the three memories, and the four chip select spaces CE are not connected to the same memory.

[0013] Furthermore, the S3 specifically includes the following steps:

[0014] S31, the user queries the connection status of the system to understand the connection status of each chip select space CE and the memory;

[0015] S32. Configure the memory parameters according to the information learned in S31;

[0016] If the current chip select space CE is connected to an asynchronous memory, manually configure the setup, trigger, and hold parameters;

[0017] If the current chip select space CE is connected to the synchronous static memory, manually configure the synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters;

[0018] If the current chip select space CE is connected to the synchronous dynamic random access memory, manually configure the column address bit number, row address bit number, and memory number parameters, and then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM;

[0019] S34. Write the corresponding storage parameters through manual programming, and then perform read and write communication with the memory.

[0020] Furthermore, the adaptive configuration method in S4 is specifically as follows:

[0021] S411, the EMIF storage control interface enters idle mode and waits for an enable signal;

[0022] S412. After receiving the enable signal, the EMIF storage control interface enters the registration mode. In the registration mode, the memory registers with the EMIF storage control interface according to the status of the EMIF interface chip select signal and the registration enable signal. During the registration, the type of memory connected to the current chip select space CE needs to be reported.

[0023] S413. If the registration fails or times out, proceed to S411; if the registration succeeds, proceed to S414;

[0024] S414, entering the configuration mode, the EMIF storage control interface configures the storage type field of the control register in the chip select space CE through the local configuration interface according to the registration information of the memory response, thereby performing the corresponding memory type configuration;

[0025] S415, entering the working mode and performing different configuration operations according to different storage type configurations;

[0026] If the current chip select space CE is connected to the asynchronous memory, the configuration establishment, triggering, and holding parameters are configured. The controller randomly generates configuration parameters and constrains the range within the configuration interval. It writes the asynchronous memory first and then reads it. If the read and write data are consistent, the parameters are correct and the configuration process ends. If the read data is inconsistent with the written data, further parameters are generated for read and write tests until the data is read and written correctly, and the configuration process ends. If the configuration parameters are not read or written correctly, the configuration mode is exited and manual configuration is performed in S3.

[0027] If the synchronous static memory connected to the current chip select space CE is connected, the synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters are configured; the controller randomly generates configuration parameters and then constrains the range within the configuration range to write first and then read the synchronous static memory. If the read and write are consistent, the parameters are correct and the configuration process ends. If they are inconsistent, reconfiguration is performed; if the timeout expires, the configuration process is exited and manual configuration is entered in S3;

[0028] If the current chip select space CE is connected to the synchronous dynamic random access memory, the column address bit number, row address bit number, and memory number parameters are configured; then the synchronous dynamic random access memory SDRAM needs to be initialized; then the SDTIMR and SDSRETR registers are set, and the RR value in the SDRCR register is set to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; the constraint memory sets the synchronous dynamic configuration parameters as a default value in the memory configuration space. In the synchronous dynamic memory configuration mode, the configuration state uses the configuration bus to read the dynamic memory parameter configuration default value, and then configure the read parameters into the controller. Finally, a read and write test is performed. If the test passes, the configuration process ends. If there is inconsistency, the configuration test is re-read. If the timeout occurs, the configuration process is exited and manual configuration is entered into S3.

[0029] Furthermore, the local configuration interface in S413 mainly includes an internal register local address, a read / write signal, read / write data, and a read / write response.

[0030] Furthermore, the loop traversal method in S4 is specifically as follows:

[0031] S421, reading and writing the connected memory after grouping according to different storage types and corresponding parameters;

[0032] S422. If the storage type is asynchronous memory, the corresponding asynchronous parameters are randomly set within the set range. The asynchronous parameters are the establishment, triggering, and holding parameters. The storage type and the asynchronous parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal is continued until the configuration is successful, and the configuration process ends.

[0033] If the storage type is synchronous static memory, the corresponding synchronous static parameters are randomly set within the set range. The synchronous static parameters are synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters. The storage type and synchronous static parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal continues until the configuration is successful, and the configuration process ends.

[0034] If the storage type is synchronous dynamic random access memory, configure the column address bit number, row address bit number, and memory number parameters; then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; if the read and write are successful, the configuration is successful; if the read and write fail, continue to traverse until the configuration is successful, and end the configuration process.

[0035] Beneficial effects of the present invention:

[0036] 1. The present invention introduces an adaptive configuration method. In addition, the adaptive configuration method introduces a registration mechanism. In the registration mode, the controller collects the registration information of each chip select space CE, and then automatically completes the configuration of the chip select space CE connection type through the internal configuration interface, which solves the problem that the user needs to find the hardware department to check the schematic diagram to understand the SOC connection status before configuring the connection type.

[0037] 2. The present invention introduces an adaptive configuration mechanism (i.e., adaptive configuration method and cyclic traversal method), which has different configuration modes for the three storage types. The controller automatically configures parameters with different strategies according to the different connected storage types, solving the technical problem that users need to understand the storage characteristics, and then manually configure and continuously debug the parameters according to the characteristics and timing, thereby shortening the project development time. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 It is a flowchart of the present invention;

[0039] Figure 2 Schematic diagram of the connection between the EMIF storage control interface and multiple chip select spaces CE in the present invention;

[0040] Figure 3 is an adaptive operation state diagram in an embodiment of the present invention;

[0041] Figure 4 This is a registration waveform diagram under the registration mode of the present invention. DETAILED DESCRIPTION

[0042] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the accompanying drawings. The accompanying drawings illustrate preferred embodiments of the present invention. However, the present invention may be implemented in many other forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0043] All technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention pertains. The terms used in the present specification are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0044] Reference Figure 1 The embodiment of the present application provides an adaptive parameter configuration method for an EMIF storage control interface, which specifically includes the following steps:

[0045] S1. Connect the host to the EMIF storage control interface, and then connect multiple chip select spaces CE on the EMIF storage control interface to different and / or the same memories respectively;

[0046] S2, after the EMIF storage control interface waits for the system to be reset, it determines whether the adaptive configuration function is started. If not, it enters S3; if so, it enters S4;

[0047] S3. The user manually configures the parameters of multiple chip select spaces CE according to storage characteristics;

[0048] S4. According to the selection parameters configured by the user, one of the two methods, an adaptive configuration method and a cyclic traversal method, is selected to configure the parameters of one or more chip select spaces CE.

[0049] In some embodiments, there are three types of memories in S1, namely asynchronous memory, synchronous static memory and synchronous dynamic random access memory. The following introduces the storage parameter configurations of the three types.

[0050] a. Asynchronous memory, the controller provides flexible read and write cycle settings for various asynchronous memory devices. The main asynchronous memory types include SRAM, EPROM, Flash memory and FIFO, and even some FPGA and ASIC chips. The ASRAM must first set the timing width of its read / write operations in the three stages of setup, strobe, and hold for storage operations. The timing of the asynchronous memory device can be controlled by configuring parameters in the EMIF global control register and the corresponding CEx space control register. Asynchronous storage access mainly configures the timing of the read and write cycles of the CEx register. Different parameter settings can realize the timing interface with different asynchronous devices. Each read / write cycle of the asynchronous interface consists of parameter settings: setup, trigger (strobe), and hold (hold). Their respective definitions are:

[0051] Setup: From the start of the memory access cycle (chip select, address valid) to the arrival of the read / write enable signal;

[0052] strobe: From the read / write signal valid to invalid;

[0053] hold: From the time when the read / write signal is invalid to the end of the access cycle.

[0054] b. Synchronous static memory, its biggest advantage is its high read and write speed. For continuous read operations of synchronous static storage, a new address strobe is output to SBSRAM in each cycle, and EMIFRW is selected as low. The initial setup time of 2 cycles is required for the first read, and a read operation is completed in each subsequent cycle. After the read is completed, there is also a read cancellation action. Continuous write operations of synchronous static storage. A new address strobe is output to SBSRAM in each cycle, and EMIFRW is selected as low. A write operation is completed in each cycle. Synchronous storage access mainly configures the timing parameters of the second register of CEx. Different parameter settings can realize the timing interface with different synchronous devices. The parameter settings are defined as follows:

[0055] SYNCRL: Synchronous interface data write delay, configure the write data delay period;

[0056] SYNCWL: Synchronous interface data read delay, configure the read data delay period;

[0057] CEEXT: CE extension register is enabled, and configuration read and write are invalid after the last command is completed, or the timing is controlled by the SYNCRL bit during the read cycle.

[0058] RENEN: Read enable valid bit, configures whether the read use signal is valid during reading and writing or when the read and write are released.

[0059] c. Synchronous dynamic random access memory (SDRAM). Synchronous refers to the memory's operation requiring a synchronized clock; internal commands and data transmission are all based on the clock. Dynamic refers to the memory array's constant refresh to ensure data is not lost. SDRAM stores data via capacitors. If the capacitors are fully discharged, the data in the SDRAM is lost. Therefore, the SDRAM must be refreshed before the capacitors are fully discharged. Random refers to the fact that data is not stored linearly, but rather read and written at freely specified addresses. Before reading or writing to SDRAM, you must set the SDCSZ (column address bits, indicating the memory page size), SDRSZ (row address bits, indicating the number of pages per memory), and SDBSZ (memory number, indicating the maximum number of pages that can be opened). Then, initialize the SDRAM. Set the SDTIMR and SDSRETR registers. These values ​​must meet the timing parameters specified in the SDRAM chip manual. Set the RR value in the SDRCR register to meet the SDRAM refresh interval parameters.

[0060] In some embodiments, the number of the chip select spaces CE is four, the four chip select spaces CE are respectively connected to one of the three memories, and the four chip select spaces CE are not connected to the same memory.

[0061] In some embodiments, S3 specifically includes the following steps:

[0062] S31. The user queries the connection status of the system to understand the connection status of each chip select space CE and the memory; that is, what memory is connected to each chip select space CE; and then becomes familiar with the characteristic parameters of the memory;

[0063] S32. Configure the memory parameters according to the information learned in S31;

[0064] If the current chip select space CE is connected to an asynchronous memory, manually configure the setup, trigger, and hold parameters;

[0065] If the current chip select space CE is connected to the synchronous static memory, manually configure the synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters;

[0066] If the current chip select space CE is connected to the synchronous dynamic random access memory, manually configure the column address bit number, row address bit number, and memory number parameters, and then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM;

[0067] S34. Write the corresponding storage parameters through manual programming, and then perform read and write communication with the memory.

[0068] In some embodiments, the adaptive configuration method in S4 is specifically as follows:

[0069] S411, the EMIF storage control interface enters idle mode and waits for an enable signal;

[0070] S412, after the EMIF storage control interface receives the enable signal, it enters the registration mode. In the registration mode, the memory registers with the EMIF storage control interface according to the status of the EMIF interface enable chip select signal and the registration enable signal. During the registration, the type of memory connected to the current chip select space CE needs to be reported, such as Figure 4 As shown, after the register enable is pulled high, the Mytype value 00 is asynchronous memory, 01 is synchronous static memory, and 10 is synchronous dynamic random access memory;

[0071] S413. If the registration fails or times out, proceed to S411; if the registration succeeds, proceed to S414;

[0072] S414, entering the configuration mode, the EMIF storage control interface configures the storage type (MTYPE) field of the control register in the chip select space CE through the local configuration interface according to the registration information responded by the memory, thereby performing the corresponding memory type configuration;

[0073] S415, entering the working mode and performing different configuration operations according to different storage type configurations;

[0074] If the current chip select space CE is connected to the asynchronous memory, the configuration establishment, triggering, and holding parameters are performed. Since the asynchronous memory has fewer parameter variables and the parameter range is controllable, it is possible to randomly generate data to try to configure the asynchronous memory parameters. Therefore, the controller randomly generates configuration parameters and then constrains the range within the configuration interval to write the asynchronous memory first and then read it. If the read and write are consistent, the parameters are correct and the configuration process ends. If the read data is inconsistent with the written data, further parameters are generated for read and write tests until the data is read and written correctly, and the configuration process ends. If the configuration parameters are not read or written correctly, the configuration mode is exited by timeout, and manual configuration is performed in S3.

[0075] If the synchronous static memory connected to the current chip select space CE is connected, the synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters are configured; similarly, since the synchronous static memory has fewer parameter variables and the parameter range is controllable, it can randomly generate data to try to configure the parameters of the synchronous static memory. Therefore, the controller randomly generates configuration parameters and then constrains the range within the configuration interval to write the synchronous static memory first and then read it. If the read and write are consistent, the parameters are correct and the configuration process ends. If they are inconsistent, reconfiguration is performed; if the timeout expires, the configuration process is exited and manual configuration is performed in S3;

[0076] If the current chip select space CE is connected to the synchronous dynamic random access memory, the column address bit number, row address bit number, and memory number parameters are configured; then the synchronous dynamic random access memory SDRAM needs to be initialized; then the SDTIMR and SDSRETR registers are set, and the RR value in the SDRCR register is set to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; the constraint memory sets the synchronous dynamic configuration parameters as a default value in the memory configuration space. In the synchronous dynamic memory configuration mode, the configuration state uses the configuration bus to read the dynamic memory parameter configuration default value, and then configure the read parameters into the controller. Finally, a read and write test is performed. If the test passes, the configuration process ends. If there is inconsistency, the configuration test is re-read. If the timeout occurs, the configuration process is exited and manual configuration is entered into S3.

[0077] The configuration process of the adaptive configuration method is completed, and the controller enters the working state after completion. In the working state, the CPU can directly read and write data to the controller of the EMIF storage control interface without going through configuration. If the user needs to adjust the parameters of the adaptive configuration, the user can reconfigure the storage controller parameters and then perform data transmission. The state diagram of the self-use process is as follows Figure 3 shown.

[0078] The adaptive configuration method defines four modes: idle mode, registration mode, configuration mode, and operating mode. The transition conditions for each mode are then defined, focusing on the adaptive configuration process for three types of memory. For asynchronous memory, adaptive configuration includes setup, strobe, and hold parameters. For synchronous static memory, adaptive configuration includes synchronous interface data write delay (SYNCRL), synchronous interface data read delay (SYNCWL), CE extension register enable (CEEXT), and read enable valid bit (RENEN). For synchronous dynamic memory, adaptive configuration includes SDCSZ (column address bits, indicating the memory page size), SDRSZ (row address bits, indicating the number of pages per memory), and SDBSZ (memory number, indicating the maximum number of open pages). The SDRAM is then initialized. The SDTIMR and SDSRETR registers are then set, and the RR value in the SDRCR register is set to meet the SDRAM refresh interval parameters. After adaptive configuration is complete, the system enters the operating state, and the user can perform memory read and write operations.

[0079] In some embodiments, the local configuration interface in S413 mainly includes an internal register local address, read / write signals, read / write data, and read / write responses. Through these local configuration interfaces, the EMIF storage control interface is adaptively configured without the need for host participation.

[0080] In some embodiments, the loop traversal method in S4 is specifically as follows:

[0081] S421, reading and writing the connected memory after grouping according to different storage types and corresponding parameters;

[0082] S422. If the storage type is asynchronous memory, the corresponding asynchronous parameters are randomly set within the set range. The asynchronous parameters are the establishment, triggering, and holding parameters. The storage type and the asynchronous parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal is continued until the configuration is successful, and the configuration process ends.

[0083] If the storage type is synchronous static memory, the corresponding synchronous static parameters are randomly set within the set range. The synchronous static parameters are synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters. The storage type and synchronous static parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal continues until the configuration is successful, and the configuration process ends.

[0084] If the storage type is synchronous dynamic random access memory, configure the column address bit number, row address bit number, and memory number parameters; then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; if the read and write are successful, the configuration is successful; if the read and write fail, continue to traverse until the configuration is successful, and end the configuration process.

[0085] The loop-based configuration method determines the external memory type and automatically configures it by looping through different MYTPE (storage type) values ​​and corresponding configuration parameters. Asynchronous memory adaptive configuration includes setup, strobe, and hold parameters. Synchronous static memory adaptive configuration includes synchronous interface data write delay (SYNCRL), synchronous interface data read delay (SYNCWL), CE extension register enable (CEEXT), and read enable valid bit (RENEN) parameters. Synchronous dynamic memory adaptive configuration includes SDCSZ (column address bits, indicating the page size of the memory bank), SDRSZ (row address bits, indicating the number of pages per memory bank), and SDBSZ (number of memory banks, indicating the maximum number of open pages). SDRAM initialization is then required. The SDTIMR and SDSRETR registers are then set, and the RR value in the SDRCR register is set to meet the SDRAM refresh interval parameters.

[0086] The biggest advantage of the cyclic traversal configuration method over the adaptive configuration method is that it does not require registration and directly traverses possible parameters to determine the external storage type. The advantage of this method is that it does not require adding new interface signals to the original EMIF components. The disadvantage is that it is more time-consuming than the adaptive configuration method.

[0087] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or replacements within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. In addition, the technical solutions between the various embodiments of the present invention can be combined with each other, but it must be based on the ability of ordinary technicians in this field to implement. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the protection scope required by the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A method for configuring adaptive parameters of an EMIF storage control interface, characterized in that: The specific steps include: S1. Connect the host to the EMIF storage control interface, and then connect multiple chip select spaces CE on the EMIF storage control interface to different and / or the same memories respectively; S2, the EMIF storage control interface waits for the system to be reset, and then determines whether the adaptive configuration function is started. If not, it enters S3; If yes, then go to S4; S3. The user manually configures the parameters of multiple chip select spaces CE according to storage characteristics; S4. Select one of the two methods, adaptive configuration method and cyclic traversal method, to configure parameters of one or more chip select spaces CE according to the selection parameters configured by the user; The adaptive configuration method in S4 is specifically as follows: S411, the EMIF storage control interface enters idle mode and waits for an enable signal; S412. After receiving the enable signal, the EMIF storage control interface enters the registration mode. In the registration mode, the memory registers with the EMIF storage control interface according to the status of the EMIF interface chip select signal and the registration enable signal. During the registration, the type of memory connected to the current chip select space CE needs to be reported. S413. If the registration fails or times out, proceed to S411; if the registration succeeds, proceed to S414; S414, entering the configuration mode, the EMIF storage control interface configures the storage type field of the control register in the chip select space CE through the local configuration interface according to the registration information of the memory response, thereby performing the corresponding memory type configuration; S415: Enter the working mode and perform different configuration operations according to different storage type configurations.

2. The adaptive parameter configuration method according to claim 1, characterized in that: There are three types of memories in S1, namely asynchronous memory, synchronous static memory and synchronous dynamic random access memory.

3. The adaptive parameter configuration method according to claim 2, wherein: The number of the chip select spaces CE is four. The four chip select spaces CE are respectively connected to one of the three memories, and the four chip select spaces CE are not connected to the same memory.

4. The adaptive parameter configuration method according to claim 3, characterized in that: The S3 specifically includes the following steps: S31, the user queries the connection status of the system to understand the connection status of each chip select space CE and the memory; S32. Configure the memory parameters according to the information learned in S31; If the current chip select space CE is connected to an asynchronous memory, manually configure the setup, trigger, and hold parameters; If the current chip select space CE is connected to the synchronous static memory, manually configure the synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters; If the current chip select space CE is connected to the synchronous dynamic random access memory, manually configure the column address bit number, row address bit number, and memory number parameters, and then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; S34. Write the corresponding storage parameters through manual programming, and then perform read and write communication with the memory.

5. The adaptive parameter configuration method according to claim 3, characterized in that: The local configuration interface in S413 mainly includes the local address of the internal register, read and write signals, read and write data, and read and write responses.

6. The adaptive parameter configuration method according to claim 3, characterized in that: The loop traversal method in S4 is as follows: S421, reading and writing the connected memory after grouping according to different storage types and corresponding parameters; S422. If the storage type is asynchronous memory, the corresponding asynchronous parameters are randomly set within the set range. The asynchronous parameters are the establishment, triggering, and holding parameters. The storage type and the asynchronous parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal is continued until the configuration is successful, and the configuration process ends. If the storage type is synchronous static memory, the corresponding synchronous static parameters are randomly set within the set range. The synchronous static parameters are synchronous interface data write delay, synchronous interface data read delay, CE extension register enable, and read enable valid bit parameters. The storage type and synchronous static parameters are packaged and configured. If the read and write are successful, the configuration is successful. If the read and write fail, the traversal continues until the configuration is successful, and the configuration process ends. If the storage type is synchronous dynamic random access memory, configure the column address bit number, row address bit number, and memory number parameters; then initialize the synchronous dynamic random access memory SDRAM; then set the SDTIMR and SDSRETR registers, and set the RR value in the SDRCR register to meet the refresh interval parameters of the synchronous dynamic random access memory SDRAM; if the read and write are successful, the configuration is successful; if the read and write fail, continue to traverse until the configuration is successful, and end the configuration process.

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