Capacitance simulation method and device, communication device and storage medium

Abstract

Embodiments of the present application provide a kind of capacitance simulation method, device, communication device and storage medium, the method comprises: if the number of closed gap pattern including port is preset quantity, the expected capacitance value of single capacitor, capacitance error, the minimum width of closed gap pattern is set in advance;According to the expected capacitance value and capacitance error of single capacitor, first threshold and second threshold are determined respectively;Judge whether the first simulation result of single capacitor meets first preset condition;If it meets first preset condition, it is determined that single capacitor simulation succeeds;If it does not meet first preset condition, the area of single capacitor or the width of closed gap pattern is adjusted, until the simulation result of single capacitor meets first preset condition.The present application realizes the automatic simulation of single capacitor by automatically adjusting the area of single capacitor or the width of closed gap pattern, solves the problem of low simulation efficiency and low simulation accuracy caused by manually adjusting related parameters multiple times.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of superconducting quantum chips, and particularly relates to a capacitor simulation method and device, a communication device and a storage medium. BACKGROUND

[0002] In the rapid development of quantum computing, the progress of the design and simulation technology of superconducting quantum chips as its core components is particularly crucial. As a basic element in superconducting quantum chips, the accurate calculation and simulation of capacitors directly affect the performance and reliability of the chips. Therefore, accurately evaluating and optimizing capacitor parameters through simulation is crucial for improving the processing success rate of superconducting quantum chips, reducing manufacturing costs, and accelerating the research and development cycle.

[0003] The existing capacitor simulation method often needs to manually adjust the related parameters multiple times to adapt to different capacitor configurations and layouts. This process not only consumes time but also is prone to human error. Therefore, the existing capacitor simulation method has the problems of low simulation efficiency and low simulation accuracy. SUMMARY

[0004] Therefore, the present application aims to provide a capacitor simulation method, device, equipment and storage medium to solve the problems of low simulation efficiency and low simulation accuracy caused by the need for manual adjustment of related parameters multiple times.

[0005] According to a first aspect of the present application, a capacitor simulation method is provided, characterized in that the method comprises:

[0006] performing a single capacitor simulation or performing a coupled capacitor simulation between two capacitors according to the number of closed gap patterns including ports, wherein the ports are arranged on the capacitors;

[0007] if the number of closed gap patterns including the ports is a preset number, pre-setting an expected capacitor value, a capacitor error and a minimum width of the closed gap pattern of a single capacitor;

[0008] determining a first threshold value and a second threshold value according to the expected capacitor value and the capacitor error of a single capacitor, respectively, wherein the first threshold value is less than the second threshold value;

[0009] simulating a single capacitor to obtain a first simulation result of a single capacitor;

[0010] determining whether the first simulation result of a single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold value and less than or equal to the second threshold value;

[0011] If the first simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0012] If the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition.

[0013] Optionally, if the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, which includes:

[0014] The maximum width of the single capacitor and the maximum height of the single capacitor are preset.

[0015] If the first simulation result of the single capacitor is less than the first threshold value, the initial width and the initial height of the single capacitor are obtained.

[0016] If the initial width of the single capacitor is less than or equal to the maximum width or the initial height of the single capacitor is less than or equal to the maximum height, the initial area of the single capacitor is obtained.

[0017] The step of repeatedly increasing the initial area of the single capacitor by a unit of the pre-obtained area and simulating the single capacitor with the increased area as the new initial area of the single capacitor is repeated until the simulation result of the single capacitor meets the first preset condition.

[0018] Optionally, if the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, which includes:

[0019] If the first simulation result of the single capacitor is greater than the second threshold value, the step of repeatedly reducing the initial area of the single capacitor by a unit of the pre-obtained area and simulating the single capacitor with the reduced area as the new initial area of the single capacitor is repeated until the simulation result of the single capacitor meets the first preset condition.

[0020] Optionally, if the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, which includes:

[0021] If the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, the step of reducing the initial width of the closed gap pattern by a pre-obtained unit reduction width, simulating the single capacitor, and taking the reduced width of the closed gap pattern as the initial width of the new closed gap pattern is repeatedly performed until the simulation result of the single capacitor meets the first preset condition.

[0022] Optionally, the step of repeatedly increasing the initial area of the single capacitor by a pre-obtained unit increase area, simulating the single capacitor, and taking the increased area of the single capacitor as the initial area of the new single capacitor until the simulation result of the single capacitor meets the first preset condition comprises:

[0023] determining a first unit increase area according to the first simulation result of the single capacitor, the expected capacitance value of the single capacitor, and the initial area of the single capacitor;

[0024] determining a second area of the single capacitor according to the initial area of the single capacitor and the first unit increase area;

[0025] obtaining a second width and a second height of the single capacitor corresponding to the second area of the single capacitor;

[0026] If the second width of the single capacitor is less than or equal to the maximum width and the second height of the single capacitor is less than or equal to the maximum height, simulating the single capacitor to obtain a second simulation result of the single capacitor;

[0027] If the second simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful;

[0028] If the second simulation result of the single capacitor does not meet the first preset condition, a second unit increase area is determined according to the second simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of the single capacitor, and the first simulation result of the single capacitor;

[0029] determining a third area of the single capacitor according to the second area of the single capacitor and the second unit increase area;

[0030] obtaining a third width and a third height of the single capacitor corresponding to the third area of the single capacitor;

[0031] If the third width of the single capacitor is less than or equal to the maximum width and the third height of the single capacitor is less than or equal to the maximum height, the single capacitor is simulated to obtain a third simulation result of the single capacitor;

[0032] If the third simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0033] Optionally, after the step of simulating the single capacitor to obtain the third simulation result of the single capacitor, the method comprises:

[0034] If the third simulation result of the single capacitor is greater than the second threshold value and the second simulation result of the single capacitor is less than the first threshold value, a third unit increase area is determined according to a preset first area coefficient, the third simulation result of the single capacitor, an expected capacitance value of the single capacitor, an initial area of the single capacitor, and the first simulation result of the single capacitor.

[0035] A fourth area of the single capacitor is determined according to the third area of the single capacitor and the third unit increase area.

[0036] The single capacitor is simulated to obtain a fourth simulation result of the single capacitor.

[0037] If the fourth simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0038] Optionally, after the step of simulating the single capacitor to obtain the fourth simulation result of the single capacitor, the method comprises:

[0039] If the fourth simulation result of the single capacitor is less than the first threshold value, a fourth unit increase area is determined according to a preset second area coefficient, the fourth simulation result of the single capacitor, an expected capacitance value of the single capacitor, an initial area of the single capacitor, and the first simulation result of the single capacitor.

[0040] A fifth area of the single capacitor is determined according to the fourth area of the single capacitor and the fourth unit increase area.

[0041] The single capacitor is simulated to obtain a fifth simulation result of the single capacitor.

[0042] If the fifth simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0043] Optionally, the method comprises the following steps of: reducing the initial area of the single capacitor by a pre-acquired unit reduction area, and simulating the single capacitor, taking the reduced area of the single capacitor as a new initial area of the single capacitor, until the simulation result of the single capacitor meets the first preset condition, which comprises the following steps of:

[0044] If the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, the initial width of the single capacitor is determined as the maximum width of the single capacitor, the initial height of the single capacitor is determined as the maximum height of the single capacitor, and the single capacitor is simulated to obtain a sixth simulation result of the single capacitor;

[0045] If the sixth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0046] If the sixth simulation result of the single capacitor does not meet the first preset condition, a sixth area of the single capacitor is acquired.

[0047] According to the sixth simulation result of the single capacitor, the expected capacitance value of the single capacitor and the sixth area of the single capacitor, a first unit reduction area is determined.

[0048] According to the sixth area of the single capacitor and the first unit reduction area, a seventh area of the single capacitor is determined.

[0049] The single capacitor is simulated to obtain a seventh simulation result of the single capacitor.

[0050] If the seventh simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0051] If the seventh simulation result of the single capacitor does not meet the first preset condition, according to the seventh area of the single capacitor and the first unit reduction area, an eighth area of the single capacitor is determined.

[0052] The single capacitor is simulated to obtain an eighth simulation result of the single capacitor.

[0053] Optionally, after the step of simulating the single capacitor to obtain the eighth simulation result of the single capacitor, the method comprises the following steps of:

[0054] If the eighth simulation result of the single capacitor is less than the first threshold value and the seventh simulation result of the single capacitor is greater than the second threshold value, a second unit reduction area is determined according to a pre-set third area coefficient and the first unit reduction area.

[0055] determining a ninth area of the single capacitor according to the eighth area of the single capacitor and the second unit reduction area;

[0056] simulating the single capacitor to obtain a ninth simulation result of the single capacitor;

[0057] if the ninth simulation result of the single capacitor meets the first preset condition, determining that the simulation of the single capacitor is successful.

[0058] Optionally, after the step of simulating the single capacitor to obtain the ninth simulation result of the single capacitor, the method comprises:

[0059] if the ninth simulation result of the single capacitor is greater than the second threshold value, determining a third unit reduction area according to a fourth preset area coefficient and the first unit reduction area;

[0060] determining a tenth area of the single capacitor according to the ninth area of the single capacitor and the third unit reduction area;

[0061] simulating the single capacitor to obtain a tenth simulation result of the single capacitor;

[0062] if the tenth simulation result of the single capacitor meets the first preset condition, determining that the simulation of the single capacitor is successful.

[0063] Optionally, the step of repeatedly performing the reduction of the initial width of the closed gap pattern according to the unit reduction width obtained in advance and the simulation of the single capacitor, taking the width of the closed gap pattern after the reduction as the initial width of the new closed gap pattern, until the simulation result of the single capacitor meets the first preset condition comprises:

[0064] obtaining an initial width of the closed gap pattern;

[0065] determining a first unit reduction width according to the initial width of the closed gap pattern and a preset width value;

[0066] determining a first width of the closed gap pattern according to the initial width of the closed gap pattern and the first unit reduction width;

[0067] simulating the single capacitor to obtain an eleventh simulation result of the single capacitor;

[0068] if the eleventh simulation result of the single capacitor meets the first preset condition, determining that the simulation of the single capacitor is successful.

[0069] If the eleventh simulation result of the single capacitor does not meet the first preset condition, a second width of the closed gap pattern is determined according to the first width of the closed gap pattern and the first unit reduction width;

[0070] The single capacitor is simulated to obtain a twelfth simulation result of the single capacitor.

[0071] Optionally, after the step of simulating the single capacitor to obtain the twelfth simulation result of the single capacitor, the method comprises:

[0072] If the twelfth simulation result of the single capacitor is greater than the second threshold value and the eleventh simulation result of the single capacitor is less than the first threshold value, a second unit reduction width is determined according to a preset first width coefficient, an initial width of the closed gap pattern and the width value;

[0073] A third width of the closed gap pattern is determined according to the second width of the closed gap pattern and the second unit reduction width.

[0074] The single capacitor is simulated to obtain a thirteenth simulation result of the single capacitor.

[0075] If the thirteenth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0076] Optionally, after the step of performing simulation on a single capacitor or performing simulation on a coupling capacitor between two capacitors according to the number of closed gap patterns including a port, the method comprises:

[0077] If the number of the closed gap patterns including the port is greater than a preset number, a desired coupling capacitor value, a coupling capacitor error and a minimum distance between the two capacitors of the coupling capacitor are preset.

[0078] A third threshold value and a fourth threshold value are respectively determined according to the desired coupling capacitor value and the coupling capacitor error of the coupling capacitor, wherein the third threshold value is less than the fourth threshold value.

[0079] The coupling capacitor is simulated to obtain a first simulation result of the coupling capacitor.

[0080] It is judged whether the first simulation result of the coupling capacitor meets a second preset condition, wherein the second preset condition is greater than or equal to the third threshold value and less than or equal to the fourth threshold value.

[0081] If the first simulation result of the coupling capacitor meets the second preset condition, it is determined that the simulation of the coupling capacitor is successful.

[0082] if the first simulation result of the coupling capacitor is greater than the fourth threshold value and the first distance between the two capacitors is greater than the minimum distance, determining a second distance between the two capacitors according to a preset distance value and the first distance between the two capacitors;

[0083] simulating the coupling capacitor to obtain a second simulation result of the coupling capacitor;

[0084] if the second simulation result of the coupling capacitor meets the second preset condition, determining that the simulation of the coupling capacitor is successful.

[0085] According to a second aspect of the present application, a capacitor simulation device is provided, which comprises:

[0086] a capacitor simulation judgment module, configured to perform simulation on a single capacitor or perform simulation on a coupling capacitor between two capacitors according to a number of closed gap patterns including a port, wherein the port is arranged on the capacitor;

[0087] a first value preset module, configured to preset an expected capacitor value, a capacitor error and a minimum width of the closed gap pattern of a single capacitor if the number of the closed gap patterns including the port is a preset number;

[0088] a first threshold value determination module, configured to determine a first threshold value and a second threshold value according to the expected capacitor value and the capacitor error of a single capacitor respectively, wherein the first threshold value is less than the second threshold value;

[0089] a single capacitor simulation module, configured to simulate a single capacitor to obtain a first simulation result of the single capacitor;

[0090] a single capacitor first simulation result analysis module, configured to determine whether the first simulation result of the single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold value and less than or equal to the second threshold value;

[0091] a single capacitor simulation success determination module, configured to determine that the simulation of the single capacitor is successful if the first simulation result of the single capacitor meets the first preset condition;

[0092] a first capacitor adjustment module, configured to adjust an area of the single capacitor or a width of the closed gap pattern if the first simulation result of the single capacitor does not meet the first preset condition, until the simulation result of the single capacitor meets the first preset condition.

[0093] Optionally, the first capacitor adjustment module comprises:

[0094] The maximum width and height setting sub-module is configured to set the maximum width of the single capacitor and the maximum height of the single capacitor in advance.

[0095] The initial width and height obtaining sub-module is configured to obtain the initial width and the initial height of the single capacitor if the first simulation result of the single capacitor is less than the first threshold.

[0096] The capacitor initial area obtaining sub-module is configured to obtain the initial area of the single capacitor if the initial width of the single capacitor is less than or equal to the maximum width or the initial height of the single capacitor is less than or equal to the maximum height.

[0097] The capacitor area iterative increasing sub-module is configured to repeatedly perform the steps of increasing the initial area of the single capacitor by a unit increasing area obtained in advance, and simulating the single capacitor, taking the increased area of the single capacitor as the initial area of the single capacitor, until the simulation result of the single capacitor meets the first preset condition.

[0098] Optionally, the first capacitor adjustment module comprises:

[0099] The capacitor area iterative decreasing sub-module is configured to repeatedly perform the steps of decreasing the initial area of the single capacitor by a unit decreasing area obtained in advance, and simulating the single capacitor, taking the decreased area of the single capacitor as the initial area of the single capacitor, until the simulation result of the single capacitor meets the first preset condition, if the first simulation result of the single capacitor is greater than the second threshold.

[0100] Optionally, the first capacitor adjustment module comprises:

[0101] The closed gap pattern width iterative decreasing sub-module is configured to repeatedly perform the steps of decreasing the initial width of the closed gap pattern by a unit decreasing width obtained in advance, and simulating the single capacitor, taking the decreased width of the closed gap pattern as the initial width of the closed gap pattern, until the simulation result of the single capacitor meets the first preset condition, if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height.

[0102] Optionally, the capacitor area iterative increasing sub-module comprises:

[0103] The first unit increasing area determining unit is configured to determine a first unit increasing area according to the first simulation result of the single capacitor, an expected capacitance value of the single capacitor, and the initial area of the single capacitor.

[0104] The capacitor second area determining unit is configured to determine a second area of the single capacitor according to the initial area of the single capacitor and the first unit increase area;

[0105] The second width and height obtaining unit is configured to obtain a second width and a second height of the single capacitor corresponding to the second area of the single capacitor;

[0106] The capacitor second simulation result determining unit is configured to perform simulation on the single capacitor to obtain a second simulation result of the single capacitor if the second width of the single capacitor is less than or equal to the maximum width and the second height of the single capacitor is less than or equal to the maximum height.

[0107] The capacitor second simulation result detecting unit is configured to determine that the simulation of the single capacitor is successful if the second simulation result of the single capacitor meets the first preset condition.

[0108] The second unit increase area determining unit is configured to determine a second unit increase area according to the second simulation result of the single capacitor, an expected capacitance value of the single capacitor, the initial area of the single capacitor and the first simulation result of the single capacitor if the second simulation result of the single capacitor does not meet the first preset condition.

[0109] The capacitor third area determining unit is configured to determine a third area of the single capacitor according to the second area of the single capacitor and the second unit increase area.

[0110] The third width and height obtaining unit is configured to obtain a third width and a third height of the single capacitor corresponding to the third area of the single capacitor.

[0111] The capacitor third simulation result determining unit is configured to perform simulation on the single capacitor to obtain a third simulation result of the single capacitor if the third width of the single capacitor is less than or equal to the maximum width and the third height of the single capacitor is less than or equal to the maximum height.

[0112] The capacitor third simulation result detecting unit is configured to determine that the simulation of the single capacitor is successful if the third simulation result of the single capacitor meets the first preset condition.

[0113] Optionally, the capacitor area iterative increase sub-module comprises:

[0114] The third unit area increase determination unit is configured to, if the third simulation result of the single capacitor is greater than the second threshold value and the second simulation result of the single capacitor is less than the first threshold value, determine a third unit area increase according to a preset first area coefficient, the third simulation result of the single capacitor, an expected capacitance value of the single capacitor, an initial area of the single capacitor, and the first simulation result of the single capacitor.

[0115] The capacitor fourth area determination unit is configured to determine a fourth area of the single capacitor according to the third area of the single capacitor and the third unit area increase.

[0116] The capacitor fourth simulation result determination unit is configured to simulate the single capacitor to obtain a fourth simulation result of the single capacitor.

[0117] The capacitor fourth simulation result detection unit is configured to, if the fourth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0118] Optionally, the capacitor area iterative increase submodule comprises:

[0119] The fourth unit area increase determination unit is configured to, if the fourth simulation result of the single capacitor is less than the first threshold value, determine a fourth unit area increase according to a preset second area coefficient, the fourth simulation result of the single capacitor, an expected capacitance value of the single capacitor, an initial area of the single capacitor, and the first simulation result of the single capacitor.

[0120] The capacitor fifth area determination unit is configured to determine a fifth area of the single capacitor according to the fourth area of the single capacitor and the fourth unit area increase.

[0121] The capacitor fifth simulation result determination unit is configured to simulate the single capacitor to obtain a fifth simulation result of the single capacitor.

[0122] The capacitor fifth simulation result detection unit is configured to, if the fifth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0123] Optionally, the capacitor area iterative decrease submodule comprises:

[0124] The capacitor sixth simulation result determination unit is configured to, if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, determine the initial width of the single capacitor as the maximum width of the single capacitor and the initial height of the single capacitor as the maximum height of the single capacitor, and simulate the single capacitor to obtain a sixth simulation result of the single capacitor.

[0125] a capacitor sixth simulation result detection unit, configured to determine that the simulation of the single capacitor is successful if the sixth simulation result of the single capacitor meets the first preset condition;

[0126] a capacitor sixth area determination unit, configured to obtain a sixth area of the single capacitor if the sixth simulation result of the single capacitor does not meet the first preset condition;

[0127] a first unit reduction area determination unit, configured to determine a first unit reduction area according to the sixth simulation result of the single capacitor, an expected capacitor value of the single capacitor, and the sixth area of the single capacitor;

[0128] a capacitor seventh area determination unit, configured to determine a seventh area of the single capacitor according to the sixth area of the single capacitor and the first unit reduction area;

[0129] a capacitor seventh simulation result determination unit, configured to simulate the single capacitor to obtain a seventh simulation result of the single capacitor;

[0130] a capacitor seventh simulation result detection unit, configured to determine that the simulation of the single capacitor is successful if the seventh simulation result of the single capacitor meets the first preset condition;

[0131] a capacitor eighth area determination unit, configured to determine an eighth area of the single capacitor according to the seventh area of the single capacitor and the first unit reduction area if the seventh simulation result of the single capacitor does not meet the first preset condition;

[0132] a capacitor eighth simulation result determination unit, configured to simulate the single capacitor to obtain an eighth simulation result of the single capacitor.

[0133] Optionally, the capacitor area iterative reduction submodule comprises:

[0134] a second unit reduction area determination unit, configured to determine a second unit reduction area according to a preset third area coefficient and the first unit reduction area if the eighth simulation result of the single capacitor is less than the first threshold value and the seventh simulation result of the single capacitor is greater than the second threshold value;

[0135] a capacitor ninth area determination unit, configured to determine a ninth area of the single capacitor according to the eighth area of the single capacitor and the second unit reduction area;

[0136] a capacitor ninth simulation result determination unit, configured to simulate the single capacitor to obtain a ninth simulation result of the single capacitor;

[0137] The capacitor ninth simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the ninth simulation result of the single capacitor meets the first preset condition.

[0138] Optionally, the capacitor area iterative reduction submodule comprises:

[0139] The third unit reduction area determination unit is configured to determine a third unit reduction area according to a fourth area coefficient and the first unit reduction area if the ninth simulation result of the single capacitor is greater than the second threshold value.

[0140] The capacitor tenth area determination unit is configured to determine a tenth area of the single capacitor according to the ninth area of the single capacitor and the third unit reduction area.

[0141] The capacitor tenth simulation result determination unit is configured to simulate the single capacitor to obtain a tenth simulation result of the single capacitor.

[0142] The capacitor tenth simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the tenth simulation result of the single capacitor meets the first preset condition.

[0143] Optionally, the closed gap pattern width iterative reduction submodule comprises:

[0144] The closed gap pattern initial width acquisition submodule is configured to acquire an initial width of the closed gap pattern.

[0145] The first unit reduction width determination unit is configured to determine a first unit reduction width according to the initial width of the closed gap pattern and a preset width value.

[0146] The closed gap pattern first width determination unit is configured to determine a first width of the closed gap pattern according to the initial width of the closed gap pattern and the first unit reduction width.

[0147] The capacitor eleventh simulation result determination unit is configured to simulate the single capacitor to obtain an eleventh simulation result of the single capacitor.

[0148] The capacitor eleventh simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the eleventh simulation result of the single capacitor meets the first preset condition.

[0149] The closed gap pattern second width determination unit is configured to determine a second width of the closed gap pattern according to the first width of the closed gap pattern and the first unit reduction width if the eleventh simulation result of the single capacitor does not meet the first preset condition.

[0150] The capacitor twelfth simulation result determination unit is configured to simulate the single capacitor to obtain a twelfth simulation result of the single capacitor.

[0151] Optionally, the closed gap pattern width iteration reduction submodule comprises:

[0152] The second unit reduction width determination unit is configured to, if the twelfth simulation result of the single capacitor is greater than the second threshold value and the eleventh simulation result of the single capacitor is less than the first threshold value, determine a second unit reduction width according to a preset first width coefficient, an initial width of the closed gap pattern, and the width value.

[0153] The closed gap pattern third width determination unit is configured to determine a third width of the closed gap pattern according to the second width of the closed gap pattern and the second unit reduction width.

[0154] The capacitor thirteenth simulation result determination unit is configured to simulate the single capacitor to obtain a thirteenth simulation result of the single capacitor.

[0155] The capacitor thirteenth simulation result detection unit is configured to, if the thirteenth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0156] Optionally, the device comprises:

[0157] The second value preset module is configured to, if the number of the closed gap patterns including the port is greater than a preset number, preset a desired coupling capacitor value of the coupling capacitor, a coupling capacitor error, and a minimum distance between the two capacitors.

[0158] The second threshold value determination module is configured to determine a third threshold value and a fourth threshold value according to the desired coupling capacitor value of the coupling capacitor and the coupling capacitor error, respectively, wherein the third threshold value is less than the fourth threshold value.

[0159] The coupling capacitor first simulation result determination module is configured to simulate the coupling capacitor to obtain a first simulation result of the coupling capacitor.

[0160] The coupling capacitor first simulation result analysis module is configured to determine whether the first simulation result of the coupling capacitor meets a second preset condition, wherein the second preset condition is greater than or equal to the third threshold value and less than or equal to the fourth threshold value.

[0161] The first coupling capacitor simulation success determination module is configured to, if the first simulation result of the coupling capacitor meets the second preset condition, determine that the simulation of the coupling capacitor is successful.

[0162] a second distance determination module, configured to determine a second distance between the two capacitors according to a preset distance value and the first distance between the two capacitors if the first simulation result of the coupling capacitor is greater than the fourth threshold value and the first distance between the two capacitors obtained in advance is greater than the minimum distance;

[0163] a coupling capacitor second simulation result determination module, configured to simulate the coupling capacitor to obtain a second simulation result of the coupling capacitor;

[0164] a second coupling capacitor simulation success determination module, configured to determine that the simulation of the coupling capacitor is successful if the second simulation result of the coupling capacitor meets the second preset condition.

[0165] According to still another aspect of the present application, an electronic device is also provided, comprising:

[0166] a processor;

[0167] a memory for storing instructions executable by the processor;

[0168] wherein the processor is configured to execute the instructions to implement the capacitor simulation method as described above.

[0169] According to still another aspect of the present application, a readable storage medium is also provided, on which a computer program is stored, the computer program being executed by a processor to implement the steps of the capacitor simulation method as described above.

[0170] The capacitor simulation method provided by the embodiment of the application comprises the following steps: according to the number of closed gap patterns including ports, performing single capacitor simulation or performing coupled capacitor simulation between two capacitors, wherein the ports are arranged on the capacitors; if the number of closed gap patterns including the ports is a preset number, presetting an expected capacitor value, a capacitor error and a minimum width of the closed gap pattern of the single capacitor; determining a first threshold value and a second threshold value according to the expected capacitor value and the capacitor error of the single capacitor respectively, wherein the first threshold value is smaller than the second threshold value; simulating the single capacitor to obtain a first simulation result of the single capacitor; judging whether the first simulation result of the single capacitor meets a first preset condition or not, wherein the first preset condition is greater than or equal to the first threshold value and smaller than or equal to the second threshold value; if the first simulation result of the single capacitor meets the first preset condition, determining that the single capacitor simulation is successful; and if the first simulation result of the single capacitor does not meet the first preset condition, adjusting the area of the single capacitor or the width of the closed gap pattern until the simulation result of the single capacitor meets the first preset condition. The area of the single capacitor or the width of the closed gap pattern is automatically adjusted, so that the automatic simulation of the single capacitor is realized, and the problems of low simulation efficiency and low simulation accuracy caused by manual adjustment of related parameters multiple times are solved. The first preset condition is preset, so that the capacitor simulation result is within the expected capacitor value and the capacitor error range, and the capacitor simulation result is closer to the capacitor value in actual application, and the accuracy of the capacitor simulation is improved. According to the number of closed gap patterns including the ports, the single capacitor simulation or the coupled capacitor simulation between two capacitors is performed, so that different capacitor configurations and layouts can be adapted, and the application range of the technical solution is expanded.

[0171] The above description is only a summary of the technical solution of the application. In order to more clearly understand the technical means of the application, the application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the specific embodiments of the application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0172] In order to more clearly illustrate the technical solutions in the embodiments of the application or the prior art, the drawings needed in the embodiment or the prior art description will be briefly introduced below.

[0173] Figure 1 One of the step flowcharts of the capacitor simulation method provided by the embodiment of the application;

[0174] Figure 2 The second step flowchart of the capacitor simulation method provided by the embodiment of the application;

[0175] Figure 3 The third step flowchart of the capacitor simulation method provided by the embodiment of the application;

[0176] Figure 4 Figure 4 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0177] Figure 5 Figure 5 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0178] Figure 6 Figure 6 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0179] Figure 7 Figure 7 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0180] Figure 8 Figure 8 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0181] Figure 9 Figure 9 is a step flow chart of a method for simulating a capacitance according to an embodiment of the present application;

[0182] Figure 10 Figure 10 is a device block diagram of a device for simulating a capacitance according to an embodiment of the present application;

[0183] Figure 11 Figure 11 is a schematic diagram of a communication device according to an embodiment of the present application. DETAILED DESCRIPTION

[0184] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the drawings. However, those skilled in the art can understand that, in the embodiments of the present application, many technical details are presented in order to make the readers better understand the present application. However, the technical solutions claimed by the present application can be implemented even without these technical details and based on various changes and modifications of the following embodiments. The division of the following embodiments is for the convenience of description, and should not constitute any limitation on the specific implementation of the present application, and the embodiments can be combined and referenced with each other on the premise of no contradiction.

[0185] Referring to Figure 1 , a step flow chart of a method for simulating a capacitance according to an embodiment of the present application is shown, which can include:

[0186] Step 101, performing a simulation for a single capacitance or performing a simulation for a coupling capacitance between two capacitances according to the number of closed gap patterns including a port, wherein the port is arranged on the capacitance.

[0187] It should be noted that in the embodiment of the present application, before judging whether the step of simulating a single capacitor or the step of simulating a coupling capacitor between two capacitors is performed according to the number of closed gap patterns including ports, the closed gap patterns including ports need to be obtained from the quantum device layout. Specifically, first, all the pattern elements in the quantum device layout and the element values of each pattern element are extracted. For the element value of each pattern element, it is judged whether the element value is #ffffff. If the element value is #ffffff, the pattern element is a gap pattern element. After judging the element value of each pattern element, all the gap pattern elements can form a closed gap pattern.

[0188] The number of closed gap patterns including ports in the quantum device layout is obtained, and whether the step of simulating a single capacitor or the step of simulating a coupling capacitor between two capacitors is performed is judged according to the number of closed gap patterns including ports.

[0189] In step 102, if the number of closed gap patterns including ports is a preset number, the expected capacitance value, the capacitance error, and the minimum width of the closed gap pattern of a single capacitor are pre-set.

[0190] In step 103, a first threshold value and a second threshold value are determined according to the expected capacitance value and the capacitance error of the single capacitor respectively, wherein the first threshold value is less than the second threshold value.

[0191] It should be noted that in the embodiment of the present application, the preset number can be 1. If the number of closed gap patterns including ports in the quantum device layout is the preset number, the step of simulating a single capacitor is performed.

[0192] Specifically, the expected capacitance value, the capacitance error, and the minimum width of the closed gap pattern set due to limited layout space for reasonable layout of a single capacitor are pre-set. The single capacitor can be a bit capacitor or a coupler capacitor of a single superconducting quantum chip, etc.

[0193] The first threshold value is determined according to the expected capacitance value and the capacitance error of the single capacitor, specifically, the first threshold value = the expected capacitance value of the single capacitor - the capacitance error. The second threshold value is determined according to the expected capacitance value and the capacitance error of the single capacitor, specifically, the second threshold value = the expected capacitance value of the single capacitor + the capacitance error. The first threshold value is less than the second threshold value.

[0194] In step 104, a single capacitor is simulated to obtain a first simulation result of the single capacitor.

[0195] In step 105, it is judged whether the first simulation result of the single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold value and less than or equal to the second threshold value.

[0196] Step 106, if the first simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor simulation is successful.

[0197] It should be noted that in the embodiment of the present application, the single capacitor in the quantum device layout is simulated to obtain the first simulation result of the single capacitor.

[0198] It is determined whether the first simulation result of the single capacitor is greater than or equal to the first threshold value and less than or equal to the second threshold value. If the first simulation result of the single capacitor is greater than or equal to the first threshold value and less than or equal to the second threshold value, it is determined that the single capacitor simulation is successful, and the GDSII graph is derived.

[0199] Step 107, if the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition.

[0200] If the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern can be adjusted multiple times until the simulation result of the single capacitor meets the first preset condition.

[0201] The present application automatically adjusts the area of the single capacitor or the width of the closed gap pattern to realize automatic simulation of the single capacitor, solving the problem of low simulation efficiency and low simulation accuracy caused by manual adjustment of related parameters multiple times. The present application sets the first preset condition in advance, so that the capacitor simulation result is within the expected capacitor value and the capacitor error range, thereby ensuring that the capacitor simulation result is closer to the capacitor value in actual application, and improving the accuracy of capacitor simulation. The present application determines to perform single capacitor simulation or to perform coupled capacitor simulation between two capacitors according to the number of closed gap patterns including the port, so that different capacitor configurations and layouts can be adapted, and the application range of the technical solution is expanded.

[0202] Further, as shown in Figure 2 Fig. 2 is a second step flowchart of the capacitor simulation method provided by the embodiment of the present application. In the embodiment of the present application, step 107 can further include the following steps:

[0203] Step 201, the maximum width of the single capacitor and the maximum height of the single capacitor are set in advance.

[0204] Step 202, if the first simulation result of the single capacitor is less than the first threshold value, the initial width and the initial height of the single capacitor are obtained.

[0205] Step 203, if the initial width of the single capacitor is less than or equal to the maximum width or the initial height of the single capacitor is less than or equal to the maximum height, the initial area of the single capacitor is obtained.

[0206] Step 204, repeat the step of increasing the initial area of the single capacitor according to the pre-acquired unit increase area, and simulate the single capacitor, take the increased area of the single capacitor as the initial area of the new single capacitor, until the simulation result of the single capacitor meets the first preset condition.

[0207] It should be noted that in the embodiment of the present application, due to the limited layout space, in order to reasonably layout, the maximum width of the single capacitor and the maximum height of the single capacitor need to be pre-set.

[0208] If the first simulation result of the single capacitor is less than the first threshold value, the initial width and the initial height of the single capacitor are acquired. If the initial width of the single capacitor is less than or equal to the maximum width or the initial height of the single capacitor is less than or equal to the maximum height, the initial area of the single capacitor is acquired.

[0209] Repeat the step of increasing the initial area of the single capacitor according to the pre-acquired unit increase area, and simulate the single capacitor, take the increased area of the single capacitor as the initial area of the new single capacitor, until the simulation result of the single capacitor meets the first preset condition.

[0210] The present application automatically repeats the operation of increasing the area of the capacitor, and simulates the capacitor until the simulation result of the capacitor meets the first preset condition, the process of automatically increasing the area of the capacitor reduces the step of manual adjustment, improves the efficiency of the simulation of the capacitor, and gradually approaches the expected simulation result through iteration.

[0211] Further, in the embodiment of the present application, step 107 can further include the following steps: if the first simulation result of the single capacitor is greater than the second threshold value, repeat the step of reducing the initial area of the single capacitor according to the pre-acquired unit reduction area, and simulate the single capacitor, take the reduced area of the single capacitor as the initial area of the new single capacitor, until the simulation result of the single capacitor meets the first preset condition.

[0212] It should be noted that in the embodiment of the present application, if the first simulation result of the single capacitor is greater than the second threshold value, repeat the step of reducing the initial area of the single capacitor according to the pre-acquired unit reduction area, and simulate the single capacitor, take the reduced area of the single capacitor as the initial area of the new single capacitor, until the simulation result of the single capacitor meets the first preset condition.

[0213] The application reduces the operation of reducing the capacitor area automatically and repeatedly, and simulates the capacitor until the simulation result of the capacitor meets the first preset condition, so that the process of automatically reducing the capacitor area reduces the step of manual adjustment, improves the efficiency of capacitor simulation, and gradually approaches the desired simulation result in an iterative manner.

[0214] Further, in the embodiment of the application, step 107 can further include the following steps: if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, repeatedly performing the step of reducing the initial width of the closed gap pattern according to the pre-acquired unit reduction width, simulating the single capacitor, and taking the width of the reduced closed gap pattern as the initial width of the new closed gap pattern until the simulation result of the single capacitor meets the first preset condition.

[0215] It should be noted that in the embodiment of the application, if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, the step of reducing the initial width of the closed gap pattern according to the pre-acquired unit reduction width, simulating the single capacitor, and taking the width of the reduced closed gap pattern as the initial width of the new closed gap pattern is repeatedly performed until the simulation result of the single capacitor meets the first preset condition.

[0216] The application can not only ensure the physical and design feasibility of the size of the capacitor, but also ensure the rationality of the simulation result of the capacitor by automatically and repeatedly reducing the width of the closed gap pattern and simulating the capacitor until the simulation result meets the first preset condition when the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height.

[0217] Further, in the embodiment of the application, the step of "repeatedly performing the step of increasing the initial area of the single capacitor according to the pre-acquired unit increase area, simulating the single capacitor, and taking the increased area of the single capacitor as the initial area of the new single capacitor until the simulation result of the single capacitor meets the first preset condition" can further include the following steps:

[0218] According to the first simulation result of the single capacitor, the expected capacitance value of the single capacitor, and the initial area of the single capacitor, a first unit increase area is determined.

[0219] According to the initial area of the single capacitor and the first unit increase area, a second area of the single capacitor is determined.

[0220] The second width and the second height of the single capacitor corresponding to the second area of the single capacitor are acquired.

[0221] If the second width of the single capacitor is less than or equal to the maximum width and the second height of the single capacitor is less than or equal to the maximum height, the single capacitor is simulated to obtain a second simulation result of the single capacitor.

[0222] If the second simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0223] If the second simulation result of the single capacitor does not meet the first preset condition, a second unit increase area is determined according to the second simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of the single capacitor, and the first simulation result of the single capacitor.

[0224] A third area of the single capacitor is determined according to the second area of the single capacitor and the second unit increase area.

[0225] A third width and a third height of the single capacitor corresponding to the third area of the single capacitor are obtained.

[0226] If the third width of the single capacitor is less than or equal to the maximum width and the third height of the single capacitor is less than or equal to the maximum height, the single capacitor is simulated to obtain a third simulation result of the single capacitor.

[0227] If the third simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0228] It should be noted that in the embodiments of the present application, the initial area of the single capacitor needs to be obtained in advance. Specifically, for a closed gap pattern in the quantum device layout, the coordinates (the horizontal coordinates of the gap pattern elements and the vertical coordinates of the gap pattern elements) of all gap pattern elements included in the closed gap pattern are obtained. The horizontal coordinates of all gap pattern elements are compared to obtain the maximum horizontal coordinate and the minimum horizontal coordinate, and the maximum horizontal coordinate is denoted by Xmax and the minimum horizontal coordinate is denoted by Xmin. The vertical coordinates of all gap pattern elements are compared to obtain the maximum vertical coordinate and the minimum vertical coordinate, and the maximum vertical coordinate is denoted by Ymax and the minimum vertical coordinate is denoted by Ymin.

[0229] The width of the closed gap pattern is obtained, specifically, the gap pattern elements with the same vertical coordinates are obtained from the coordinates of all gap pattern elements. For the gap pattern elements with the same vertical coordinates, the horizontal coordinates of the gap pattern elements are subtracted two by two to obtain a plurality of horizontal coordinate difference values. The maximum horizontal coordinate difference value is determined from the plurality of horizontal coordinate difference values, and the maximum horizontal coordinate difference value is taken as the width of the closed gap pattern, and the width of the closed gap pattern is denoted by D.

[0230] Further, the initial width of the capacitor is denoted as W, the initial height of the capacitor is denoted as H, the initial width of the capacitor can be calculated according to the maximum value of the abscissa, the minimum value of the abscissa and the width of the closed gap pattern, that is, W = Xmax-Xmin-2D. The initial height of the capacitor can be calculated according to the maximum value of the ordinate, the minimum value of the ordinate and the width of the closed gap pattern, that is, H = Ymax-Ymin-2D.

[0231] According to the initial width of the capacitor and the initial height of the capacitor, the initial area of the capacitor can be calculated, and the initial area of the capacitor is denoted as S1. After obtaining the initial area of the capacitor, the first unit increase area can be calculated according to the first simulation result of the single capacitor, the expected capacitance value of the single capacitor and the initial area of the single capacitor, specifically, the first unit increase area is (C1-C q )*(S1 / C1), wherein C1 is the first simulation result of the single capacitor, C q is the expected capacitance value of the single capacitor, and S1 is the initial area of the single capacitor. Adding the first unit increase area to the initial area of the single capacitor can obtain the second area of the single capacitor, S2 = S1+(C1-C q )*(S1 / C1), wherein S2 is the second area of the single capacitor.

[0232] After obtaining the second area of the single capacitor, the second width and the second height of the single capacitor corresponding to the second area of the single capacitor are obtained according to the initial width and the initial height of the reference capacitor. If the second width of the single capacitor is less than or equal to the maximum width and the second height of the single capacitor is less than or equal to the maximum height, the single capacitor is simulated to obtain the second simulation result of the single capacitor, and the second simulation result of the single capacitor is denoted as C2.

[0233] It is judged whether the second simulation result of the single capacitor meets the first preset condition, and if the second simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0234] If the second simulation result of the single capacitor does not meet the first preset condition, the second unit increase area can be calculated according to the second simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of the single capacitor and the first simulation result of the single capacitor, specifically, the second unit increase area is (C2-C q )*(S1 / C1), wherein C2 is the second simulation result of the single capacitor, C q is the expected capacitance value of the single capacitor, S1 is the initial area of the single capacitor, and C1 is the first simulation result of the single capacitor. Adding the second unit increase area to the second area of the single capacitor can obtain the third area of the single capacitor, S3 = S2+(C2-C q)*(S1 / C1), wherein S3 is a third area of the single capacitor.

[0235] After obtaining the third area of the single capacitor, the third width and the third height of the single capacitor corresponding to the third area of the single capacitor are obtained according to the initial width and the initial height of the reference capacitor. If the third width of the single capacitor is less than or equal to the maximum width and the third height of the single capacitor is less than or equal to the maximum height, the single capacitor is simulated to obtain a third simulation result of the single capacitor, and the third simulation result of the single capacitor is denoted as C3.

[0236] If the third simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0237] From the above content, it can be known that the initial area of the single capacitor is iteratively increased by 1 time, the first unit increase area is (C1-C q )*(S1 / C1), the second area of the single capacitor is S2=S1+(C1-C q )*(S1 / C1), and the second simulation result of the single capacitor is C2; the initial area of the single capacitor is iteratively increased by 2 times, the second unit increase area is (C2-C q )*(S1 / C1), the third area of the single capacitor is S3=S2+(C2-C q )*(S1 / C1), the second simulation result of the single capacitor is C3; therefore, if the initial area of the single capacitor is iteratively increased by n times, the nth unit increase area is (C n -C q )*(S1 / C1), the nth area of the single capacitor is S n+1 =S n +(C n -C q )*(S1 / C1), and the nth simulation result of the single capacitor is C n+1 , wherein n=1, 2, 3, ….

[0238] The initial area of the single capacitor is iteratively increased by n times according to the unit increase area (C n -C q )*(S1 / C1) until the simulation result of the single capacitor meets the first preset condition.

[0239] The application flexibly adjusts the size of the unit increase area each time according to the feedback of the simulation result of the capacitor, so that the simulation strategy of the capacitor can be dynamically adjusted according to the actual situation, thereby more effectively approaching the expected simulation result.

[0240] Further, as Figure 3As shown, three step flow charts of the method for simulating the capacitance are shown. In the embodiment of the present application, after the step of "simulating the single capacitance to obtain the third simulation result of the single capacitance", the following steps can be further included:

[0241] In step 301, if the third simulation result of the single capacitance is greater than the second threshold value and the second simulation result of the single capacitance is less than the first threshold value, a third unit increasing area is determined according to the preset first area coefficient, the third simulation result of the single capacitance, the expected capacitance value of the single capacitance, the initial area of the single capacitance and the first simulation result of the single capacitance.

[0242] In step 302, a fourth area of the single capacitance is determined according to the third area of the single capacitance and the third unit increasing area.

[0243] In step 303, the single capacitance is simulated to obtain a fourth simulation result of the single capacitance.

[0244] In step 304, if the fourth simulation result of the single capacitance meets the first preset condition, it is determined that the simulation of the single capacitance is successful.

[0245] It should be noted that in the embodiment of the present application, if the third simulation result of the single capacitance is greater than the second threshold value and the second simulation result of the single capacitance is less than the first threshold value, it means that the unit increasing area for iteratively increasing the initial area of the capacitance is too large, and the increasing unit area needs to be reduced. Specifically, the third unit increasing area can be calculated according to the preset first area coefficient, the third simulation result of the single capacitance, the expected capacitance value of the single capacitance, the initial area of the single capacitance and the first simulation result of the single capacitance.

[0246] The third unit increasing area is added to the third area of the single capacitance to obtain the fourth area of the single capacitance. After obtaining the fourth area of the single capacitance, the single capacitance is simulated to obtain the fourth simulation result of the single capacitance. If the fourth simulation result of the single capacitance meets the first preset condition, it is determined that the simulation of the single capacitance is successful.

[0247] That is, in the process of iteratively increasing the initial area of the single capacitance by (C n -C q )*(S1 / C1) each time, if the single capacitance is iterated for n times, the nth simulation result C n+1 of the single capacitance is greater than the second threshold value and the (n-1)th simulation result C n of the single capacitance is less than the first threshold value, it means that the unit increasing area (C n -C q )*(S1 / C1) for iteratively increasing the initial area of the single capacitance is too large, and the increasing unit area needs to be reduced. Specifically, the increasing unit area is reduced to 1 / 2m (C n -C q )*(S1 / C1) is used as a new unit to increase the area, m=1,2,3…….

[0248] The (n-1)th area S of a single capacitor obtained after n-1 iterations n Based on this, the area is continuously increased by 1 / 2 according to the new unit. m (C n -C q )*(S1 / C1) represents the (n-1)th area S of a single capacitor n The iteration is increased m times until the simulation result of a single capacitor meets the first preset condition.

[0249] This invention, by dynamically adjusting the unit area increase when the capacitor simulation result does not meet the first preset condition, can more accurately control the simulation result to meet the first preset condition. This precise control helps improve the accuracy of capacitor simulation and ensures that the capacitor simulation result can accurately reflect the physical characteristics of the capacitor.

[0250] Furthermore, such as Figure 4 The diagram illustrates the fourth step of the capacitance simulation method provided in this embodiment of the invention. In this embodiment, the following steps may be included after step 303:

[0251] Step 401: If the fourth simulation result of a single capacitor is less than the first threshold, then the fourth unit increase area is determined based on the preset second area coefficient, the fourth simulation result of a single capacitor, the expected capacitance value of a single capacitor, the initial area of ​​a single capacitor, and the first simulation result of a single capacitor.

[0252] Step 402: Determine the fifth area of ​​a single capacitor based on the fourth area of ​​the single capacitor and the fourth unit increase area.

[0253] Step 403: Simulate a single capacitor to obtain the fifth simulation result for a single capacitor.

[0254] Step 404: If the fifth simulation result of a single capacitor meets the first preset condition, then the simulation of a single capacitor is determined to be successful.

[0255] It should be noted that, in this embodiment of the invention, if the fourth simulation result of a single capacitor is less than the first threshold, it indicates that the third unit increase area is too small, and the third unit increase area needs to be increased. Specifically, the fourth unit increase area can be calculated based on the preset second area coefficient, the fourth simulation result of a single capacitor, the expected capacitance value of a single capacitor, the initial area of ​​a single capacitor, and the first simulation result of a single capacitor.

[0256] The fourth area of the single capacitor is increased by the fourth unit increase area, and the fifth area of the single capacitor is obtained. After obtaining the fifth area of the single capacitor, the single capacitor is simulated to obtain the fifth simulation result of the single capacitor. If the fifth simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor simulation is successful.

[0257] That is, in the process of increasing the (n-1)th area S n Each iteration increases 1 / 2 m (C n -C q )*(S1 / C1), if the nth simulation result C n+1 of the single capacitor is less than the first threshold value, at this time, the nth area S n+1 of the single capacitor is S n +1 / 2(C n -C q )*(S1 / C1), it indicates that the third unit increase area 1 / 2 n (C m -C n )*(S1 / C1) of the iteration increase of the (n-1)th area S q of the single capacitor is too small, and the third unit increase area needs to be increased. Specifically, (1-1 / 2 m )(Cn-C q )*(S1 / C1) is taken as a new unit increase area, that is, the fourth unit increase area, m=2, 3, ….

[0258] On the basis of the (n-1)th area S n of the single capacitor obtained by iteration n-1 times, the (n-1)th area S m of the single capacitor is iteratively increased m times according to the fourth unit increase area (1-1 / 2 q )(Cn-C n )*(S1 / C1), until the simulation result of the single capacitor meets the first preset condition.

[0259] The application further dynamically adjusts the unit increase area when the simulation result of the capacitor does not meet the first preset condition, so that the simulation result is closer to the expected capacitor value. This dynamic adjustment mechanism helps to ensure that the capacitor simulation result is within the expected capacitor value and the error range.

[0260] Further, in the embodiment of the application, the step of "repeating the step of reducing the initial area of the single capacitor according to the pre-obtained unit reduction area, and simulating the single capacitor, taking the reduced area of the single capacitor as the new initial area of the single capacitor, until the simulation result of the single capacitor meets the first preset condition" can further include the following steps:

[0261] If the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, the initial width of the single capacitor is determined as the maximum width of the single capacitor, the initial height of the single capacitor is determined as the maximum height of the single capacitor, and the single capacitor is simulated to obtain a sixth simulation result of the single capacitor.

[0262] If the sixth simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0263] If the sixth simulation result of the single capacitor does not meet the first preset condition, a sixth area of the single capacitor is obtained.

[0264] According to the sixth simulation result of the single capacitor, the expected capacitance value of the single capacitor and the sixth area of the single capacitor, a first unit reduction area is determined.

[0265] According to the sixth area of the single capacitor and the first unit reduction area, a seventh area of the single capacitor is determined.

[0266] The single capacitor is simulated to obtain a seventh simulation result of the single capacitor.

[0267] If the seventh simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully.

[0268] If the seventh simulation result of the single capacitor does not meet the first preset condition, according to the seventh area of the single capacitor and the first unit reduction area, an eighth area of the single capacitor is determined.

[0269] The single capacitor is simulated to obtain an eighth simulation result of the single capacitor.

[0270] It should be noted that in the embodiment of the application, if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, the initial width of the single capacitor is determined as the maximum width of the single capacitor, the initial height of the single capacitor is determined as the maximum height of the single capacitor, and the single capacitor is simulated to obtain a sixth simulation result of the single capacitor.

[0271] It is determined whether the sixth simulation result of the single capacitor meets the first preset condition. If the sixth simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor is simulated successfully. If the sixth simulation result of the single capacitor does not meet the first preset condition, the sixth area of the single capacitor is obtained by referring to the process of obtaining the initial area of the single capacitor.

[0272] According to the sixth simulation result of the single capacitor, the expected capacitance value of the single capacitor and the sixth area of the single capacitor, the first unit reduction area can be calculated, if the sixth simulation result of the single capacitor is represented by C1, the sixth area of the single capacitor is represented by S1, and the first unit reduction area is (C1-C q )*(S1 / C1). After obtaining the first unit reduction area, the sixth area of the single capacitor is reduced by the first unit reduction area, and the seventh area of the single capacitor can be obtained, if the seventh area is represented by S2, S2=S1-(C1-C q )*(S1 / C1). After obtaining the seventh area of the single capacitor, the single capacitor is simulated, and the seventh simulation result of the single capacitor can be obtained, which can be represented by C2.

[0273] It is judged whether the seventh simulation result of the single capacitor meets the first preset condition. If the seventh simulation result of the single capacitor meets the first preset condition, it is determined that the single capacitor simulation is successful. If the seventh simulation result of the single capacitor does not meet the first preset condition, the eighth area of the single capacitor can be calculated according to the seventh area of the single capacitor and the first unit reduction area, if the eighth area of the single capacitor is represented by S3, S3=S2-(C1-C q )*(S1 / C1). After obtaining the eighth area of the single capacitor, the single capacitor is simulated, and the eighth simulation result of the single capacitor can be obtained, which can be represented by C3.

[0274] From the above, the sixth area S1 of the single capacitor is iteratively reduced by 1 time, the unit reduction area is the first unit reduction area (C1-C q )*(S1 / C1), the seventh area of the single capacitor is S2=S1-(C1-C q )*(S1 / C1), and the seventh simulation result of the single capacitor is C2; the sixth area S1 of the single capacitor is iteratively reduced by 2 times, the unit reduction area is the first unit reduction area (C1-C q )*(S1 / C1), the eighth area of the single capacitor is S3=S2-(C1-C q )*(S1 / C1), and the second simulation result of the single capacitor is C3; therefore, if the sixth area S1 of the single capacitor is iteratively reduced by n times, the unit reduction area is the first unit reduction area (C1-C q )*(S1 / C1), the nth area of the single capacitor is S n+1 =S n -(C1-C q )*(S1 / C1), and the nth simulation result of the single capacitor is C n+1 , where n=1, 2, 3, ….

[0275] continuously reduce the area (C1-C q iteratively reduce the sixth area S1 of the single capacitor by the first unit reduction area (C1-C

[0276] The present application gradually makes the simulation result of the capacitor approach the expected capacitor value by iteratively reducing the area of the capacitor, so that more complex capacitor simulation requirements can be processed, and the adaptability and flexibility of the capacitor simulation process are improved.

[0277] Further, as Figure 5 shown, Figure five shows a step flowchart of the capacitor simulation method provided by the embodiment of the present application. In the embodiment of the present application, after the step of "simulating the single capacitor to obtain the eighth simulation result of the single capacitor", the following steps can be further included:

[0278] Step 501: If the eighth simulation result of the single capacitor is less than the first threshold value and the seventh simulation result of the single capacitor is greater than the second threshold value, then according to the third area coefficient and the first unit reduction area, a second unit reduction area is determined.

[0279] Step 502: According to the eighth area of the single capacitor and the second unit reduction area, a ninth area of the single capacitor is determined.

[0280] Step 503: Simulate the single capacitor to obtain a ninth simulation result of the single capacitor.

[0281] Step 504: If the ninth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0282] It should be noted that in the embodiment of the present application, if the eighth simulation result of the single capacitor is less than the first threshold value and the seventh simulation result of the single capacitor is greater than the second threshold value, it means that the first unit reduction area of the iteratively reduced sixth area of the single capacitor is too large, and the first unit reduction area needs to be reduced to obtain the second unit reduction area. Specifically, the second unit reduction area is calculated according to the third area coefficient and the first unit reduction area.

[0283] After obtaining the second unit reduction area, the ninth area of the single capacitor is calculated according to the eighth area of the single capacitor and the second unit reduction area. After obtaining the ninth area of the single capacitor, the single capacitor is simulated to obtain the ninth simulation result of the single capacitor. If the ninth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0284] That is, the sixth area S1 of the single capacitor is iteratively reduced (C1-C qIn the process of *(S1 / C1), if iteration is performed for n times, the n-th simulation result C n+1 is less than the first threshold value and the (n-1)-th simulation result C n of the single capacitor is greater than the second threshold value, it is indicated that the first unit reduction area (C1-C q )*(S1 / C1) is too large, and the first unit reduction area needs to be reduced, specifically, 1 / 2 t (C1-C q )*(S1 / C1) is taken as a new unit reduction area, that is, a second unit reduction area, t=1, 2, 3,...

[0285] On the basis of the (n-1)-th area S n of the single capacitor obtained by iteration for n-1 times, the (n-1)-th area S t of the single capacitor is constantly reduced according to the second unit reduction area 1 / 2 q (C1-C n )*(S1 / C1).The iteration is performed for t times until the simulation result of the single capacitor meets the first preset condition.

[0286] The application can make the simulation result of the capacitor closer to the expected capacitor value and improve the simulation efficiency of the capacitor by further automatically and dynamically adjusting the unit reduction area when the simulation result of the capacitor does not meet the first preset condition.

[0287] Further, as shown in Figure 6 of the step flowchart of the capacitor simulation method provided by the embodiment of the application, the embodiment of the application can further include the following steps after step 503: Figure 6

[0288] Step 601: If the ninth simulation result of the single capacitor is greater than the second threshold value, a third unit reduction area is determined according to the preset fourth area coefficient and the first unit reduction area.

[0289] Step 602: A tenth area of the single capacitor is determined according to the ninth area of the single capacitor and the third unit reduction area.

[0290] Step 603: The single capacitor is simulated to obtain a tenth simulation result of the single capacitor.

[0291] Step 604: If the tenth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0292] It should be noted that in the embodiment of the present application, if the ninth simulation result of the single capacitor is greater than the second threshold value, it indicates that the second unit reduction area of the iterative reduction is too small, and the third unit reduction area is obtained by increasing the second unit reduction area. Specifically, the third unit reduction area is calculated according to the fourth preset area coefficient and the first unit reduction area.

[0293] After obtaining the third unit reduction area, the tenth area of the single capacitor can be calculated according to the ninth area of the single capacitor and the third unit reduction area. After obtaining the tenth area of the single capacitor, the single capacitor is simulated to obtain the tenth simulation result of the single capacitor. If the tenth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0294] That is, in the process of reducing the n-1 area S n of the single capacitor by 1 / 2 t (C1-C q )*(S1 / C1) each time, if the n simulation result C n+1 of the single capacitor is greater than the second threshold value, at this time, the n area S n+1 of the single capacitor is S n -1 / 2(C1-C q )*(S1 / C1), it indicates that the second unit reduction area 1 / 2 n (C1-C t )*(S1 / C1) of the iterative reduction of the n-1 area S q of the single capacitor is too small, and the second unit reduction area needs to be increased. Specifically, (1-1 / 2 t )(C1-C q )*(S1 / C1) is taken as a new unit reduction area, that is, a third unit reduction area, t=2, 3, ….

[0295] Based on the n-1 area S n of the single capacitor obtained by iterating n-1 times, the n-1 area S n of the single capacitor is iteratively reduced t times according to the third unit reduction area (1-1 / 2 t )(C1-C q )*(S1 / C1), until the simulation result of the single capacitor meets the first preset condition.

[0296] The present application automatically adjusts the unit reduction area according to the fourth preset area coefficient when the simulation result of the single capacitor is greater than the second threshold value, so that the simulation result is closer to the preset expected capacitor value, which helps to ensure that the capacitor simulation result is within the expected capacitor value and the error range.

[0297] Further, asFigure 7 As shown in Fig. 7, Fig. 7 is a seventh step flow chart of the method for simulating capacitance provided by the embodiment of the present application. In the embodiment of the present application, the step of "repeatedly performing the step of reducing the initial width of the closed gap pattern by a unit reduction width obtained in advance, simulating the single capacitance, and taking the width of the closed gap pattern after the reduction as the initial width of the new closed gap pattern until the simulation result of the single capacitance meets the first preset condition" can further include the following steps:

[0298] In step 701, the initial width of the closed gap pattern is obtained.

[0299] In step 702, the first unit reduction width is determined according to the initial width of the closed gap pattern and a preset width value.

[0300] In step 703, the first width of the closed gap pattern is determined according to the initial width of the closed gap pattern and the first unit reduction width.

[0301] In step 704, the single capacitance is simulated to obtain the eleventh simulation result of the single capacitance.

[0302] In step 705, if the eleventh simulation result of the single capacitance meets the first preset condition, it is determined that the simulation of the single capacitance is successful.

[0303] In step 706, if the eleventh simulation result of the single capacitance does not meet the first preset condition, the second width of the closed gap pattern is determined according to the first width of the closed gap pattern and the first unit reduction width.

[0304] In step 707, the single capacitance is simulated to obtain the twelfth simulation result of the single capacitance.

[0305] It should be noted that in the embodiment of the present application, the initial width of the closed gap pattern is obtained by referring to the specific implementation process of obtaining the width of the closed gap pattern. The initial width of the closed gap pattern can be represented by D. According to the initial width of the closed gap pattern and the preset width value, the first unit reduction width can be calculated. If the preset width value is represented by D, the first unit reduction width is D-D gap . gap

[0306] After the first unit reduction width is obtained, the first width of the closed gap pattern can be calculated according to the initial width of the closed gap pattern and the first unit reduction width. The first width of the closed gap pattern can be represented by D1, and D1=D-(D-D gap ​After obtaining the first width of the closed gap pattern, a single capacitor is simulated to obtain the eleventh simulation result of the single capacitor, which can be represented by C1. If the eleventh simulation result of the single capacitor meets the first preset condition, the simulation of the single capacitor is determined to be successful.

[0307] If the eleventh simulation result of a single capacitor does not meet the first preset condition, then the second width of the closed gap pattern can be calculated based on the first width of the closed gap pattern and the first unit reduction in width. If the second width of the closed gap pattern is represented by D2, then D2 = D1 - (DD) gap Simulation of a single capacitor yields the twelfth simulation result for that capacitor. The eleventh simulation result for a single capacitor can be represented by C2.

[0308] As can be seen from the above, the initial width D of the closed gap pattern is reduced by 1 iteration, and the unit reduction width is the first unit reduction width DD. gap The first width D1 of the closed gap pattern is D-(DD) gap The eleventh simulation result for a single capacitor is C1; the initial width D of the closed gap pattern is reduced by 2 iterations, with each unit reduction being the first unit reduction width DD. gap The second width D2 of the closed gap pattern is D2 = D1 - (DD) gap The twelfth simulation result for a single capacitor is C2; therefore, if the initial width D of the closed gap pattern is reduced n times, the unit reduction width is the first unit reduction width DD. gap The nth width of the closed gap pattern is D n =D n-1 -(DD gap The simulation result for the nth capacitor is C. n .

[0309] Continuously reduce the width DD by the first unit gap The initial width D of the closed gap pattern is reduced n times through iterations until the simulation result of a single capacitor meets the first preset condition.

[0310] This invention reduces the width of the closed gap pattern through automated iteration, allowing the capacitance simulation results to gradually approach the desired capacitance value, reducing the possibility of human error and improving the accuracy of capacitance simulation.

[0311] Furthermore, such as Figure 8 The diagram illustrates the eighth step of the capacitance simulation method provided in this embodiment of the invention. In this embodiment, the following steps may be included after step 706:

[0312] In step 801, if the twelfth simulation result of the single capacitor is greater than the second threshold value and the eleventh simulation result of the single capacitor is less than the first threshold value, a second unit reduction width is determined according to the preset first width coefficient, the initial width of the closed gap pattern and the width value.

[0313] In step 802, a third width of the closed gap pattern is determined according to the second width of the closed gap pattern and the second unit reduction width.

[0314] In step 803, the single capacitor is simulated to obtain a thirteenth simulation result of the single capacitor.

[0315] In step 804, if the thirteenth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0316] It should be noted that in the embodiment of the present application, if the twelfth simulation result of the single capacitor is greater than the second threshold value and the eleventh simulation result of the single capacitor is less than the first threshold value, it indicates that the first unit reduction width of the iterative reduction of the initial width of the closed gap pattern is too large, and the first unit reduction width needs to be reduced to obtain the second unit reduction width. Specifically, the second unit reduction width can be calculated according to the preset first width coefficient, the initial width of the closed gap pattern and the width value.

[0317] After obtaining the second unit reduction width, the third width of the closed gap pattern can be calculated according to the second width of the closed gap pattern and the second unit reduction width. After obtaining the third width of the closed gap pattern, the single capacitor is simulated to obtain the thirteenth simulation result of the single capacitor. If the thirteenth simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful.

[0318] That is, in the process of iteratively reducing the initial width D of the closed gap pattern by the first unit reduction width D-D gap each time, if the iteration is n times, the nth simulation result C n of the single capacitor is greater than the second threshold value and the (n-1)th simulation result C n-1 of the single capacitor is less than the first threshold value, it indicates that the first unit reduction width D-D gap of the iterative reduction of the initial width of the closed gap pattern is too large, and the first unit reduction width needs to be reduced to obtain the second unit reduction width. Specifically, 1 / k(D-Dgap) is taken as the new unit reduction width, that is, the second unit reduction width, and k=2, 3, ….

[0319] On the basis of the nth width D n of the closed gap pattern obtained by iteration n times, the second unit reduction width 1 / k(D-Dgap) is used to iteratively reduce the nth width Dn The iteration is reduced k times until the simulation result of the single capacitor meets the first preset condition.

[0320] If the simulation result of the single capacitor still does not meet the first preset condition, the simulation is terminated, the simulation result is output, the current capacitor simulation fails, and manual data adjustment is required.

[0321] The application adjusts the unit reduction width according to the preset first width coefficient when the simulation result of the single capacitor does not meet the second preset condition, so that the capacitor simulation result is closer to the preset expected capacitor value, which helps to ensure that the capacitor simulation result is within the expected capacitor value and error range.

[0322] Further, in the embodiment of the application, after step 101, the following steps can also be included:

[0323] If the number of closed gap patterns including the port is greater than the preset number, the expected coupling capacitance value of the coupling capacitor, the coupling capacitor error, and the minimum distance between the two capacitors are preset.

[0324] The third threshold and the fourth threshold are determined according to the expected coupling capacitance value of the coupling capacitor and the coupling capacitor error respectively, wherein the third threshold is less than the fourth threshold.

[0325] The coupling capacitor is simulated to obtain a first simulation result of the coupling capacitor.

[0326] It is judged whether the first simulation result of the coupling capacitor meets the second preset condition, wherein the second preset condition is greater than or equal to the third threshold and less than or equal to the fourth threshold.

[0327] If the first simulation result of the coupling capacitor meets the second preset condition, it is determined that the coupling capacitor simulation is successful.

[0328] If the first simulation result of the coupling capacitor is greater than the fourth threshold and the first distance between the two capacitors obtained in advance is greater than the minimum distance, the second distance between the two capacitors is determined according to the preset distance value and the first distance between the two capacitors.

[0329] The coupling capacitor is simulated to obtain a second simulation result of the coupling capacitor.

[0330] If the second simulation result of the coupling capacitor meets the second preset condition, it is determined that the coupling capacitor simulation is successful.

[0331] It should be noted that, in this embodiment of the invention, if the number of closed gap patterns including ports is greater than a preset number, then for all capacitors in the quantum device layout, coupling capacitance simulation is performed between each pair of different capacitors. Specifically, taking the coupling capacitance simulation between two capacitors as an example, the expected coupling capacitance value, coupling capacitance error, and minimum distance between the two capacitors are preset for reasonable layout. A third threshold is calculated based on the expected coupling capacitance value and coupling capacitance error, specifically, the third threshold = expected coupling capacitance value - coupling capacitance error. A fourth threshold is calculated based on the expected coupling capacitance value and coupling capacitance error, specifically, the fourth threshold = expected coupling capacitance value + coupling capacitance error.

[0332] The coupling capacitor is simulated to obtain the first simulation result. It is then determined whether the first simulation result meets a second preset condition, which is greater than or equal to a third threshold and less than or equal to a fourth threshold. If the first simulation result meets the second preset condition, the coupling capacitor simulation is considered successful.

[0333] A first distance between the two capacitors is pre-determined. If the first simulation result of the coupled capacitor is greater than a fourth threshold and the first distance between the two capacitors is greater than a minimum distance, the first distance between the two capacitors is reduced according to a preset distance value to obtain a second distance between the two capacitors. After obtaining the second distance value between the two capacitors, the coupled capacitor is simulated to obtain a second simulation result. If the second simulation result of the coupled capacitor meets a second preset condition, the simulation of the coupled capacitor is determined to be successful. That is, the first distance between the two capacitors is iteratively reduced according to the preset distance value until the second simulation result of the coupled capacitor meets the second preset condition.

[0334] This invention enables automated simulation of coupled capacitors by performing a process for simulating the coupling capacitors between two different capacitors when the number of closed gap patterns including ports exceeds a preset number. This improves the efficiency of coupled capacitor simulation.

[0335] Furthermore, such as Figure 9 The diagram illustrates the ninth step of the capacitor simulation method provided in this embodiment of the invention. In this embodiment, after the step "simulating the coupling capacitor to obtain the second simulation result of the coupling capacitor," the following steps may also be included:

[0336] Step 901: If the second simulation result of the coupling capacitor is greater than the fourth threshold and the second distance between the two capacitors is less than the minimum distance, then simulate the two capacitors separately to obtain the adjusted two capacitors.

[0337] Step 902, the coupling capacitance between the two adjusted capacitors is simulated to obtain a third simulation result of the coupling capacitance.

[0338] Step 903, if the third simulation result of the coupling capacitance meets the second preset condition, it is determined that the simulation of the coupling capacitance between the two adjusted capacitors is successful.

[0339] It should be noted that in the embodiment of the present application, after the first distance between the two capacitors is iteratively reduced according to the preset distance value, if the second simulation result of the coupling capacitance is greater than the fourth threshold value and the second distance between the two capacitors is less than the minimum distance, the process of simulating a single capacitor is called to simulate and design the two capacitors respectively to obtain the two adjusted capacitors. The coupling capacitance between the two adjusted capacitors is simulated again to obtain a third simulation result of the coupling capacitance. If the third simulation result of the coupling capacitance meets the second preset condition, it is determined that the simulation of the coupling capacitance between the two adjusted capacitors is successful.

[0340] That is, if the second simulation result of the coupling capacitance is greater than the fourth threshold value and the second distance between the two capacitors is less than the minimum distance, the process of simulating a single capacitor is repeatedly called to simulate and design the two capacitors respectively to obtain the two adjusted capacitors, and the process of simulating the coupling capacitance between the two adjusted capacitors is repeated until the simulation result of the coupling capacitance meets the second preset condition.

[0341] The present application can make the simulation result of the coupling capacitance meet the preset expected coupling capacitance value and error range by adjusting the simulation of the two capacitors respectively under the condition that the simulation result of the coupling capacitance does not meet the second preset condition, obtaining the two adjusted capacitors, and simulating the two adjusted capacitors again, which helps to improve the accuracy of the coupling capacitance simulation,

[0342] According to the embodiment of the present application, a capacitor simulation device is also provided, which is described with reference to Figure 10 , Figure 10 is a device block diagram of a capacitor simulation device provided by the embodiment of the present application, which comprises:

[0343] The capacitor simulation judgment module 1001 is used to perform a single capacitor simulation or a coupling capacitance simulation between two capacitors according to the number of closed gap patterns including a port, wherein the port is arranged on the capacitor.

[0344] The first numerical preset module 1002 is used to preset the expected capacitance value, capacitance error and minimum width of the closed gap pattern of a single capacitor if the number of closed gap patterns including the port is a preset number.

[0345] The first threshold determination module 1003 is configured to determine a first threshold and a second threshold according to a desired capacitance value of the single capacitor and the capacitance error, respectively, wherein the first threshold is smaller than the second threshold.

[0346] The single capacitor simulation module 1004 is configured to simulate the single capacitor to obtain a first simulation result of the single capacitor.

[0347] The single capacitor first simulation result analysis module 1005 is configured to determine whether the first simulation result of the single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold and less than or equal to the second threshold.

[0348] The single capacitor simulation success determination module 1006 is configured to determine that the simulation of the single capacitor is successful if the first simulation result of the single capacitor meets the first preset condition.

[0349] The first capacitor adjustment module 1007 is configured to adjust an area of the single capacitor or a width of the closed gap pattern until the simulation result of the single capacitor meets the first preset condition if the first simulation result of the single capacitor does not meet the first preset condition.

[0350] Optionally, the first capacitor adjustment module comprises:

[0351] The maximum width and height setting sub-module is configured to pre-set a maximum width of the single capacitor and a maximum height of the single capacitor.

[0352] The initial width and height obtaining sub-module is configured to obtain an initial width and an initial height of the single capacitor if the first simulation result of the single capacitor is less than the first threshold.

[0353] The capacitor initial area obtaining sub-module is configured to obtain an initial area of the single capacitor if the initial width of the single capacitor is less than or equal to the maximum width or the initial height of the single capacitor is less than or equal to the maximum height.

[0354] The capacitor area iterative increasing sub-module is configured to repeatedly perform the steps of increasing the initial area of the single capacitor by a pre-obtained unit increasing area, simulating the single capacitor, and taking the increased area of the single capacitor as a new initial area of the single capacitor until the simulation result of the single capacitor meets the first preset condition.

[0355] Optionally, the first capacitor adjustment module comprises:

[0356] The capacitor area iterative reduction submodule is configured to: if the first simulation result of the single capacitor is greater than the second threshold value, repeatedly perform the step of reducing the initial area of the single capacitor by a pre-acquired unit reduction area and simulating the single capacitor until the simulation result of the single capacitor meets the first preset condition.

[0357] Optionally, the first capacitor adjustment module comprises:

[0358] The closed gap pattern width iterative reduction submodule is configured to: if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, repeatedly perform the step of reducing the initial width of the closed gap pattern by a pre-acquired unit reduction width and simulating the single capacitor until the simulation result of the single capacitor meets the first preset condition.

[0359] Optionally, the capacitor area iterative increase submodule comprises:

[0360] The first unit increase area determination unit is configured to determine a first unit increase area according to the first simulation result of the single capacitor, an expected capacitor value of the single capacitor, and the initial area of the single capacitor.

[0361] The capacitor second area determination unit is configured to determine a second area of the single capacitor according to the initial area of the single capacitor and the first unit increase area.

[0362] The second width and height acquisition unit is configured to acquire a second width and a second height of the single capacitor corresponding to the second area of the single capacitor.

[0363] The capacitor second simulation result determination unit is configured to simulate the single capacitor to obtain a second simulation result of the single capacitor if the second width of the single capacitor is less than or equal to the maximum width and the second height of the single capacitor is less than or equal to the maximum height.

[0364] The capacitor second simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the second simulation result of the single capacitor meets the first preset condition.

[0365] The second unit area increase determining unit is configured to, if the second simulation result of the single capacitor does not meet the first preset condition, determine a second unit area increase according to the second simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of the single capacitor, and the first simulation result of the single capacitor.

[0366] The capacitor third area determining unit is configured to determine a third area of the single capacitor according to the second area of the single capacitor and the second unit area increase.

[0367] The third width and height obtaining unit is configured to obtain a third width and a third height of the single capacitor corresponding to the third area of the single capacitor.

[0368] The capacitor third simulation result determining unit is configured to, if the third width of the single capacitor is less than or equal to the maximum width and the third height of the single capacitor is less than or equal to the maximum height, simulate the single capacitor to obtain a third simulation result of the single capacitor.

[0369] The capacitor third simulation result detecting unit is configured to, if the third simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0370] Optionally, the capacitor area iterative increase sub-module comprises:

[0371] The third unit area increase determining unit is configured to, if the third simulation result of the single capacitor is greater than the second threshold value and the second simulation result of the single capacitor is less than the first threshold value, determine a third unit area increase according to a preset first area coefficient, the third simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of the single capacitor, and the first simulation result of the single capacitor.

[0372] The capacitor fourth area determining unit is configured to determine a fourth area of the single capacitor according to the third area of the single capacitor and the third unit area increase.

[0373] The capacitor fourth simulation result determining unit is configured to simulate the single capacitor to obtain a fourth simulation result of the single capacitor.

[0374] The capacitor fourth simulation result detecting unit is configured to, if the fourth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0375] Optionally, the capacitor area iterative increase sub-module comprises:

[0376] The fourth unit increase area determination unit is configured to, if the fourth simulation result of the single capacitor is less than the first threshold value, determine a fourth unit increase area according to a preset second area coefficient, the fourth simulation result of the single capacitor, an expected capacitance value of the single capacitor, an initial area of the single capacitor, and a first simulation result of the single capacitor.

[0377] The capacitor fifth area determination unit is configured to determine a fifth area of the single capacitor according to the fourth area of the single capacitor and the fourth unit increase area.

[0378] The capacitor fifth simulation result determination unit is configured to simulate the single capacitor to obtain a fifth simulation result of the single capacitor.

[0379] The capacitor fifth simulation result detection unit is configured to, if the fifth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0380] Optionally, the capacitor area iterative reduction sub-module comprises:

[0381] The capacitor sixth simulation result determination unit is configured to, if the initial width of the single capacitor is greater than the maximum width or the initial height of the single capacitor is greater than the maximum height, determine the initial width of the single capacitor as the maximum width of the single capacitor and the initial height of the single capacitor as the maximum height of the single capacitor, and simulate the single capacitor to obtain a sixth simulation result of the single capacitor.

[0382] The capacitor sixth simulation result detection unit is configured to, if the sixth simulation result of the single capacitor meets the first preset condition, determine that the simulation of the single capacitor is successful.

[0383] The capacitor sixth area determination unit is configured to, if the sixth simulation result of the single capacitor does not meet the first preset condition, obtain a sixth area of the single capacitor.

[0384] The first unit reduction area determination unit is configured to determine a first unit reduction area according to the sixth simulation result of the single capacitor, the expected capacitance value of the single capacitor, and the sixth area of the single capacitor.

[0385] The capacitor seventh area determination unit is configured to determine a seventh area of the single capacitor according to the sixth area of the single capacitor and the first unit reduction area.

[0386] The capacitor seventh simulation result determination unit is configured to simulate the single capacitor to obtain a seventh simulation result of the single capacitor.

[0387] The capacitor seventh simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the seventh simulation result of the single capacitor meets the first preset condition.

[0388] The capacitor eighth area determination unit is configured to determine an eighth area of the single capacitor according to the seventh area of the single capacitor and the first unit reduction area if the seventh simulation result of the single capacitor does not meet the first preset condition.

[0389] The capacitor eighth simulation result determination unit is configured to simulate the single capacitor to obtain an eighth simulation result of the single capacitor.

[0390] Optionally, the capacitor area iterative reduction submodule includes:

[0391] The second unit reduction area determination unit is configured to determine a second unit reduction area according to a third area coefficient and the first unit reduction area if the eighth simulation result of the single capacitor is less than the first threshold value and the seventh simulation result of the single capacitor is greater than the second threshold value.

[0392] The capacitor ninth area determination unit is configured to determine a ninth area of the single capacitor according to the eighth area of the single capacitor and the second unit reduction area.

[0393] The capacitor ninth simulation result determination unit is configured to simulate the single capacitor to obtain a ninth simulation result of the single capacitor.

[0394] The capacitor ninth simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the ninth simulation result of the single capacitor meets the first preset condition.

[0395] Optionally, the capacitor area iterative reduction submodule includes:

[0396] The third unit reduction area determination unit is configured to determine a third unit reduction area according to a fourth area coefficient and the first unit reduction area if the ninth simulation result of the single capacitor is greater than the second threshold value.

[0397] The capacitor tenth area determination unit is configured to determine a tenth area of the single capacitor according to the ninth area of the single capacitor and the third unit reduction area.

[0398] The capacitor tenth simulation result determination unit is configured to simulate the single capacitor to obtain a tenth simulation result of the single capacitor.

[0399] The capacitor tenth simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the tenth simulation result of the single capacitor meets the first preset condition.

[0400] Optionally, the closed gap pattern width iterative reduction submodule comprises:

[0401] a closed gap pattern initial width acquisition submodule, configured to acquire an initial width of the closed gap pattern;

[0402] a first unit reduction width determination unit, configured to determine a first unit reduction width according to the initial width of the closed gap pattern and a preset width value;

[0403] a closed gap pattern first width determination unit, configured to determine a first width of the closed gap pattern according to the initial width of the closed gap pattern and the first unit reduction width;

[0404] a capacitor eleventh simulation result determination unit, configured to simulate the single capacitor to obtain a capacitor eleventh simulation result of the single capacitor;

[0405] a capacitor eleventh simulation result detection unit, configured to determine that the simulation of the single capacitor is successful if the capacitor eleventh simulation result of the single capacitor meets the first preset condition;

[0406] a closed gap pattern second width determination unit, configured to determine a second width of the closed gap pattern according to the first width of the closed gap pattern and the first unit reduction width if the capacitor eleventh simulation result of the single capacitor does not meet the first preset condition;

[0407] a capacitor twelfth simulation result determination unit, configured to simulate the single capacitor to obtain a capacitor twelfth simulation result of the single capacitor.

[0408] Optionally, the closed gap pattern width iterative reduction submodule comprises:

[0409] a second unit reduction width determination unit, configured to determine a second unit reduction width according to a preset first width coefficient, the initial width of the closed gap pattern and the width value if the capacitor twelfth simulation result of the single capacitor is greater than the second threshold value and the capacitor eleventh simulation result of the single capacitor is less than the first threshold value;

[0410] a closed gap pattern third width determination unit, configured to determine a third width of the closed gap pattern according to the second width of the closed gap pattern and the second unit reduction width;

[0411] a capacitor thirteenth simulation result determination unit, configured to simulate the single capacitor to obtain a capacitor thirteenth simulation result of the single capacitor;

[0412] The capacitor thirteenth simulation result detection unit is configured to determine that the simulation of the single capacitor is successful if the thirteenth simulation result of the single capacitor meets the first preset condition.

[0413] Optionally, the apparatus comprises:

[0414] The second numerical value preset module is configured to preset an expected coupling capacitance value, a coupling capacitance error and a minimum distance between the two capacitors of the coupling capacitor if the number of the closed gap patterns including the port is greater than a preset number.

[0415] The second threshold value determination module is configured to determine a third threshold value and a fourth threshold value according to the expected coupling capacitance value and the coupling capacitance error of the coupling capacitor respectively, wherein the third threshold value is less than the fourth threshold value.

[0416] The coupling capacitor first simulation result determination module is configured to simulate the coupling capacitor to obtain a first simulation result of the coupling capacitor.

[0417] The coupling capacitor first simulation result analysis module is configured to determine whether the first simulation result of the coupling capacitor meets a second preset condition, wherein the second preset condition is greater than or equal to the third threshold value and less than or equal to the fourth threshold value.

[0418] The first coupling capacitor simulation success determination module is configured to determine that the simulation of the coupling capacitor is successful if the first simulation result of the coupling capacitor meets the second preset condition.

[0419] The second distance determination module is configured to determine a second distance between the two capacitors according to a preset distance value and the first distance between the two capacitors if the first simulation result of the coupling capacitor is greater than the fourth threshold value and the first distance between the two capacitors obtained in advance is greater than the minimum distance.

[0420] The coupling capacitor second simulation result determination module is configured to simulate the coupling capacitor to obtain a second simulation result of the coupling capacitor.

[0421] The second coupling capacitor simulation success determination module is configured to determine that the simulation of the coupling capacitor is successful if the second simulation result of the coupling capacitor meets the second preset condition.

[0422] The embodiment of the present application further provides an electronic device, such as Figure 11 As shown in the figure, the electronic device comprises a processor 1101, a communication interface 1102, a memory 1103 and a communication bus 1104, wherein the processor 1101, the communication interface 1102 and the memory 1103 complete mutual communication through the communication bus 1104,

[0423] The memory 1103 is configured to store a computer program;

[0424] The processor 1101 is configured to implement the following steps when executing the program stored in the memory 1103:

[0425] According to the number of closed gap patterns including the port, a simulation for a single capacitor or a simulation for a coupling capacitor between two capacitors is performed, wherein the port is arranged on the capacitor;

[0426] If the number of closed gap patterns including the port is a preset number, a desired capacitance value, a capacitance error and a minimum width of the closed gap pattern of the single capacitor are preset;

[0427] A first threshold value and a second threshold value are determined according to the desired capacitance value and the capacitance error of the single capacitor respectively, wherein the first threshold value is smaller than the second threshold value;

[0428] The single capacitor is simulated to obtain a first simulation result of the single capacitor;

[0429] It is judged whether the first simulation result of the single capacitor meets a first preset condition or not, wherein the first preset condition is greater than or equal to the first threshold value and less than or equal to the second threshold value;

[0430] If the first simulation result of the single capacitor meets the first preset condition, it is determined that the simulation of the single capacitor is successful;

[0431] If the first simulation result of the single capacitor does not meet the first preset condition, the area of the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition.

[0432] The communication bus mentioned above can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or only one type of bus.

[0433] The communication interface is configured to communicate between the terminal and other devices.

[0434] The memory can include a Random Access Memory (RAM) and can also include a non-volatile memory, for example, at least one disk memory. Optionally, the memory can also be at least one storage device located away from the aforementioned processor.

[0435] The processor described above can be a general processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0436] In another embodiment provided by the present application, a computer readable storage medium is provided, and the computer readable storage medium stores instructions, when the instructions are executed on a computer, the computer executes the capacitive simulation method in any of the above embodiments.

[0437] In the above embodiments, the implementation can be achieved entirely or partially through software, hardware, firmware or any combination thereof. When implemented by using software, the implementation can be achieved entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the flow or function described in the embodiments of the present application is entirely or partially generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) mode. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, solid state disk (SSD)) and the like.

[0438] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0439] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0440] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A capacitance simulation method, characterized in that, The method includes: Depending on the number of closed gap patterns including ports, perform a simulation for a single capacitor or a simulation for the coupled capacitor between two capacitors, wherein the ports are located on the capacitors; If the number of the closed gap patterns including the port is a preset number, then the expected capacitance value, capacitance error, and minimum width of the closed gap pattern for a single capacitor are preset. A first threshold and a second threshold are determined based on the expected capacitance value of a single capacitor and the capacitance error, respectively, wherein the first threshold is less than the second threshold; A simulation of a single capacitor is performed to obtain a first simulation result for the single capacitor; Determine whether the first simulation result of a single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold and less than or equal to the second threshold; If the first simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful. If the first simulation result of a single capacitor does not meet the first preset condition, the area of ​​the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition.

2. The method according to claim 1, characterized in that, If the first simulation result of a single capacitor does not meet the first preset condition, the area of ​​the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, including: The maximum width and maximum height of a single capacitor are preset. If the first simulation result of a single capacitor is less than the first threshold, then the initial width and initial height of the single capacitor are obtained; If the initial width of a single capacitor is less than or equal to the maximum width, or the initial height of a single capacitor is less than or equal to the maximum height, then the initial area of ​​the single capacitor is obtained. Repeat the steps of increasing the initial area of ​​a single capacitor by a pre-obtained unit increase area, simulating a single capacitor, and using the increased area of ​​the single capacitor as the new initial area of ​​the single capacitor, until the simulation result of the single capacitor meets the first preset condition.

3. The method according to claim 2, characterized in that, If the first simulation result of a single capacitor does not meet the first preset condition, the area of ​​the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, including: If the first simulation result of a single capacitor is greater than the second threshold, the steps of reducing the initial area of ​​the single capacitor by the pre-obtained unit reduction area, simulating the single capacitor, and using the reduced area of ​​the single capacitor as the new initial area of ​​the single capacitor are repeated until the simulation result of the single capacitor meets the first preset condition.

4. The method according to claim 2, characterized in that, If the first simulation result of a single capacitor does not meet the first preset condition, the area of ​​the single capacitor or the width of the closed gap pattern is adjusted until the simulation result of the single capacitor meets the first preset condition, including: If the initial width of a single capacitor is greater than the maximum width or the initial height of a single capacitor is greater than the maximum height, then the steps of reducing the initial width of the closed gap pattern by the pre-acquired unit reduction width and simulating the single capacitor are repeated, and the reduced width of the closed gap pattern is used as the new initial width of the closed gap pattern, until the simulation result of the single capacitor meets the first preset condition.

5. The method according to claim 2, characterized in that, The repeated execution of increasing the initial area of ​​a single capacitor by a pre-obtained unit increase area, simulating the single capacitor, and using the increased area of ​​the single capacitor as the new initial area of ​​the single capacitor, until the simulation result of the single capacitor meets the first preset condition, includes: Based on the first simulation results of a single capacitor, the expected capacitance value of a single capacitor, and the initial area of ​​a single capacitor, the first unit increase in area is determined; The second area of ​​a single capacitor is determined based on the initial area of ​​the single capacitor and the first unit increase in area; Obtain the second width and second height of a single capacitor corresponding to the second area of ​​a single capacitor; If the second width of a single capacitor is less than or equal to the maximum width and the second height of a single capacitor is less than or equal to the maximum height, then a simulation is performed on the single capacitor to obtain a second simulation result for the single capacitor; If the second simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful. If the second simulation result of a single capacitor does not meet the first preset condition, then the second unit increase area is determined based on the second simulation result of the single capacitor, the expected capacitance value of the single capacitor, the initial area of ​​the single capacitor, and the first simulation result of the single capacitor. The third area of ​​the individual capacitor is determined based on the second area of ​​the individual capacitor and the second unit increase area; Obtain the third width and third height of a single capacitor corresponding to the third area of ​​the single capacitor; If the third width of a single capacitor is less than or equal to the maximum width and the third height of a single capacitor is less than or equal to the maximum height, then a simulation is performed on the single capacitor to obtain the third simulation result of the single capacitor; If the third simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

6. The method according to claim 5, characterized in that, After the step of simulating a single capacitor to obtain a third simulation result for the single capacitor, the method includes: If the third simulation result of a single capacitor is greater than the second threshold and the second simulation result of a single capacitor is less than the first threshold, then the third unit increase in area is determined based on the preset first area coefficient, the third simulation result of a single capacitor, the expected capacitance value of a single capacitor, the initial area of ​​a single capacitor, and the first simulation result of a single capacitor. The fourth area of ​​the individual capacitor is determined based on the third area of ​​the individual capacitor and the third unit increase area; A simulation of a single capacitor is performed to obtain a fourth simulation result for that single capacitor; If the fourth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

7. The method according to claim 6, characterized in that, After the step of simulating a single capacitor to obtain a fourth simulation result for the single capacitor, the method includes: If the fourth simulation result of a single capacitor is less than the first threshold, then the fourth unit increase in area is determined based on the preset second area coefficient, the fourth simulation result of a single capacitor, the expected capacitance value of a single capacitor, the initial area of ​​a single capacitor, and the first simulation result of a single capacitor. The fifth area of ​​the individual capacitor is determined based on the fourth area of ​​the individual capacitor and the fourth unit increase in area; A simulation of a single capacitor is performed to obtain a fifth simulation result for that single capacitor; If the fifth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

8. The method according to claim 2, characterized in that, The repeated execution of reducing the initial area of ​​a single capacitor according to a pre-obtained unit reduction area, simulating the single capacitor, and using the reduced area of ​​the single capacitor as the new initial area of ​​the single capacitor, until the simulation result of the single capacitor meets the first preset condition, includes: If the initial width of a single capacitor is greater than the maximum width or the initial height of a single capacitor is greater than the maximum height, then the initial width of the single capacitor is determined to be the maximum width of the single capacitor, the initial height of the single capacitor is determined to be the maximum height of the single capacitor, and the single capacitor is simulated to obtain the sixth simulation result of the single capacitor. If the sixth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful. If the sixth simulation result of a single capacitor does not meet the first preset condition, then the sixth area of ​​the single capacitor is obtained; Based on the sixth simulation result of a single capacitor, the expected capacitance value of a single capacitor, and the sixth area of ​​a single capacitor, the first unit reduction area is determined; The seventh area of ​​a single capacitor is determined based on the sixth area of ​​the single capacitor and the first unit reduction area; A simulation of a single capacitor was performed, resulting in a seventh simulation result for that single capacitor. If the seventh simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful. If the seventh simulation result of a single capacitor does not meet the first preset condition, then the eighth area of ​​a single capacitor is determined based on the seventh area of ​​the single capacitor and the first unit reduction area. The simulation was performed on a single capacitor, resulting in the eighth simulation result for that single capacitor.

9. The method according to claim 8, characterized in that, After the step of simulating a single capacitor to obtain an eighth simulation result for the single capacitor, the method includes: If the eighth simulation result of a single capacitor is less than the first threshold and the seventh simulation result of a single capacitor is greater than the second threshold, then the second unit reduction area is determined according to the preset third area coefficient and the first unit reduction area. The ninth area of ​​a single capacitor is determined based on the eighth area of ​​the single capacitor and the second unit reduction area; A simulation of a single capacitor was performed, resulting in a ninth simulation result for that single capacitor. If the ninth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

10. The method according to claim 9, characterized in that, After the step of simulating a single capacitor to obtain a ninth simulation result for the single capacitor, the method includes: If the ninth simulation result of a single capacitor is greater than the second threshold, then the third unit reduction area is determined according to the preset fourth area coefficient and the first unit reduction area; The tenth area of ​​a single capacitor is determined based on the ninth area of ​​the single capacitor and the third unit reduction area; Simulation was performed on a single capacitor, and the tenth simulation result for a single capacitor was obtained; If the tenth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

11. The method according to claim 4, characterized in that, The repeated execution of reducing the initial width of the closed gap pattern according to a pre-acquired unit reduction width, simulating a single capacitor, and using the reduced width of the closed gap pattern as the new initial width of the closed gap pattern, until the simulation result of a single capacitor meets the first preset condition, includes: Obtain the initial width of the closed gap pattern; Based on the initial width of the closed gap pattern and the preset width value, determine the first unit width reduction; The first width of the closed gap pattern is determined based on the initial width of the closed gap pattern and the first unit reduction width; Simulation was performed on a single capacitor, and the eleventh simulation result for a single capacitor was obtained. If the eleventh simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful. If the eleventh simulation result of a single capacitor does not meet the first preset condition, then the second width of the closed gap pattern is determined based on the first width of the closed gap pattern and the first unit reduction width; A simulation of a single capacitor was performed, resulting in the twelfth simulation result for that single capacitor.

12. The method according to claim 11, characterized in that, After the step of simulating a single capacitor to obtain a twelfth simulation result for the single capacitor, the method includes: If the twelfth simulation result of a single capacitor is greater than the second threshold and the eleventh simulation result of a single capacitor is less than the first threshold, then the second unit reduction width is determined according to the preset first width coefficient, the initial width of the closed gap pattern and the width value; The third width of the closed gap pattern is determined based on the second width of the closed gap pattern and the second unit reduction width; A simulation of a single capacitor was performed, yielding the thirteenth simulation result for that single capacitor. If the thirteenth simulation result of a single capacitor meets the first preset condition, then the simulation of the single capacitor is determined to be successful.

13. The method according to claim 1, characterized in that, After the step of performing a simulation for a single capacitor or a simulation for the coupling capacitor between two capacitors based on the number of closed gap patterns including the ports, the method includes: If the number of closed gap patterns including the port is greater than a preset number, then the expected coupling capacitance value, coupling capacitance error, and minimum distance between the two capacitors are preset. A third threshold and a fourth threshold are determined based on the expected coupling capacitance value and the coupling capacitance error, respectively, wherein the third threshold is less than the fourth threshold; The coupling capacitor was simulated to obtain the first simulation result of the coupling capacitor; Determine whether the first simulation result of the coupling capacitor meets the second preset condition, wherein the second preset condition is greater than or equal to the third threshold and less than or equal to the fourth threshold; If the first simulation result of the coupling capacitor meets the second preset condition, then the simulation of the coupling capacitor is determined to be successful. If the first simulation result of the coupling capacitor is greater than the fourth threshold and the first distance between the two capacitors obtained in advance is greater than the minimum distance, then the second distance between the two capacitors is determined according to the preset distance value and the first distance between the two capacitors. The coupling capacitor is simulated to obtain a second simulation result. If the second simulation result of the coupling capacitor meets the second preset condition, then the simulation of the coupling capacitor is determined to be successful.

14. A capacitance simulation device, characterized in that, The capacitance simulation device includes: The capacitor simulation judgment module is used to perform a simulation of a single capacitor or a simulation of the coupling capacitor between two capacitors based on the number of closed gap patterns including the port; wherein the port is disposed on the capacitor. The first numerical preset module is used to preset the expected capacitance value, capacitance error, and minimum width of the closed gap pattern for a single capacitor if the number of the closed gap patterns including the port is a preset number. The first threshold determination module is used to determine a first threshold and a second threshold based on the expected capacitance value of a single capacitor and the capacitance error, respectively, wherein the first threshold is less than the second threshold; A single capacitor simulation module is used to simulate a single capacitor and obtain a first simulation result for the single capacitor; A single capacitor first simulation result analysis module is used to determine whether the first simulation result of a single capacitor meets a first preset condition, wherein the first preset condition is greater than or equal to the first threshold and less than or equal to the second threshold; A single capacitor simulation success determination module is used to determine that the simulation of a single capacitor is successful if the first simulation result of a single capacitor meets the first preset condition. The first capacitor adjustment module is used to adjust the area of ​​the individual capacitor or the width of the closed gap pattern if the first simulation result of the individual capacitor does not meet the first preset condition, until the simulation result of the individual capacitor meets the first preset condition.

15. An electronic device, characterized in that, include: Memory used to store processor-executable instructions; The processor is configured to execute the instructions to implement the capacitance simulation method as described in any one of claims 1 to 13.

16. A readable storage medium, characterized in that, A computer program is stored on the readable storage medium, which, when executed by a processor, implements the capacitance simulation method as described in any one of claims 1 to 13.

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