A memory, a memory operation method and a memory device

Abstract

The embodiments of the present disclosure provide a memory, a memory operation method and a storage device, wherein the memory comprises: a plurality of storage libraries, each storage library comprises a plurality of data storage blocks and ECC storage blocks; a plurality of error detection circuits, each error detection circuit is configured to read storage data and verification data from the storage library respectively, and generate a corresponding error detection signal according to the storage data and verification data; an error address generation circuit is configured to receive a plurality of error detection signals from the plurality of error detection circuits, and when any error detection signal is at an invalid level, store the address information corresponding to the error that does not meet the conditions; in this way, the on-chip ECC can be used to pre-identify the errors occurring in the memory, and after identifying the errors that cannot be corrected by the on-chip ECC, an error detection signal is generated and the error address information is recorded in a timely manner, so as to facilitate the subsequent correction of the errors and improve the accuracy of the memory.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a memory, a method for operating the memory, and a storage device. Background Art

[0002] In the semiconductor industry, the memory cell of a memory chip such as a dynamic random access memory (DRAM) consists of a transistor and a capacitor. DRAM writes data to the memory by storing charge in the capacitor of the memory cell, and reads the charge in the capacitor of the memory cell to complete the data read operation. With the development of semiconductor technology, the integration of DRAM is getting higher and higher, and the number of errors is also increasing. In some cases, the error bit can be corrected by performing an error correction function through ECC encoding and / or decoding circuits. Summary of the invention

[0003] Embodiments of the present disclosure provide a memory, a method for operating the memory, and a storage device.

[0004] According to some embodiments of the present disclosure, a first aspect of the embodiments of the present disclosure provides a memory, comprising: a plurality of storage libraries, each of the storage libraries comprising a plurality of data storage blocks and ECC storage blocks; a plurality of error detection circuits corresponding one-to-one to the plurality of storage libraries; each of the error detection circuits being configured to read storage data and verification data from the plurality of data storage blocks and the ECC storage blocks of the corresponding storage library, respectively, and generate a corresponding error detection signal based on the storage data and the verification data, wherein the error detection signal is used to indicate whether a qualified error has occurred in the storage data and / or the verification data of the corresponding storage library; an error address generation circuit being configured to receive a plurality of the error detection signals from the plurality of the error detection circuits, and to store address information corresponding to a non-qualified error when any of the error detection signals is at an invalid level; wherein the address information comprises: error row address information and error column address information.

[0005] In some embodiments, the error address generation circuit is also configured to generate and store error identification information when any of the error detection signals is at an invalid level; wherein the error identification information is used to indicate whether an unqualified error has occurred in the storage data and / or verification data corresponding to the stored address information.

[0006] In some embodiments, the error detection circuit includes: a first detection circuit, configured to receive the stored data and the verification data, and compare the verification code generated based on the stored data with the verification data to generate a comparison result; a first judgment circuit, configured to receive the comparison result and judge whether a condition is met, and when the comparison result meets the condition, generate the error detection signal at an invalid level, and when the comparison result does not meet the condition, generate the error detection signal at a valid level.

[0007] In some embodiments, the error address generation circuit includes: a merging circuit, configured to receive multiple error detection signals corresponding to multiple storage bins, and merge to generate a total error detection signal, wherein if any of the error detection signals is at an invalid level, the generated total error detection signal is at an invalid level; a row address generation circuit, configured to receive multiple error detection signals and the total error detection signal, and when any of the error detection signals is at an invalid level, output the row address information of the corresponding storage bin as error row address information, and store the error row address information in response to the total error detection signal at an invalid level; and a column address generation circuit, configured to store error column address information corresponding to errors that do not meet the conditions in response to the total error detection signal at an invalid level.

[0008] In some embodiments, the row address generation circuit includes: a plurality of row address latch circuits corresponding one-to-one to the plurality of storage banks, each of the row address latch circuits being configured to latch the row address information corresponding to the activation signal in response to an activation signal of the corresponding storage bank; a row address selection circuit being configured to receive the plurality of error detection signals and the plurality of row address information latched by the plurality of row address latch circuits, and outputting the corresponding row address information as error row address information when any of the error detection signals is at an invalid level; and a row address storage circuit being configured to store the error row address information in response to the total error detection signal being at an invalid level.

[0009] In some embodiments, the column address generation circuit includes: a column address latch circuit, configured to input the column address information corresponding to the read signal into a buffer in response to a read signal, and output the column address information corresponding to the read signal from the buffer as error column address information in response to a read delay signal; wherein the read delay signal is a delayed signal of the read signal; and a column address storage circuit, configured to store the error column address information in a corresponding mode register in response to the error detection total signal being at an invalid level.

[0010] In some embodiments, the row address storage circuit includes: N serially connected row address storage subcircuits; the first row address storage subcircuit is configured to store the received error row address information when the total error detection signal after N-1 first delays is at an invalid level; the i-th row address storage subcircuit is configured to receive and store the error row address information stored by the i-1-th row address storage subcircuit when the total error detection signal after Ni first delays is at an invalid level; the N-th row address storage subcircuit is configured to receive and store the error row address information stored by the N-1-th row address storage subcircuit when the total error detection signal is at an invalid level; wherein the first delay is a number of clock cycles, N is greater than or equal to 2, and i is greater than 1 and A positive integer less than N; the column address storage circuit comprises: N serially connected column address storage sub-circuits; the first column address storage sub-circuit is configured to store the received error row column address information when the total error detection signal after executing N-1 times of the second delay is at an invalid level; the jth column address storage sub-circuit is configured to receive and store the error column address information stored by the j-1th column address storage sub-circuit when the total error detection signal after executing Nj times of the second delay is at an invalid level; the Nth column address storage sub-circuit is configured to receive and store the error column address information stored by the N-1th column address storage sub-circuit when the total error detection signal is at an invalid level; wherein the second delay is a number of clock cycles, and j is a positive integer greater than 1 and less than N.

[0011] According to some embodiments of the present disclosure, the second aspect of the embodiments of the present disclosure also provides a method for operating a memory, wherein the memory includes multiple storage libraries, each of the storage libraries includes multiple data storage blocks and ECC storage blocks, and the operating method includes: receiving storage data and verification data respectively read from the multiple data storage blocks and the ECC storage blocks of any of the storage libraries, and generating a corresponding error detection signal based on the storage data and the verification data; wherein the error detection signal is used to indicate whether a qualified error has occurred in the storage data and / or the verification data of the corresponding storage library; receiving the error detection signal, and when the error detection signal is at an invalid level, storing address information corresponding to the non-qualified error; wherein the address information includes: error row address information and error column address information.

[0012] In some embodiments, when the error detection signal is at an invalid level, error identification information is generated and stored, wherein the error identification information is used to indicate whether an unqualified error has occurred in the storage data and / or verification data corresponding to the stored address information.

[0013] In some embodiments, before receiving the storage data and verification data respectively read from the multiple data storage blocks and the ECC storage blocks of the corresponding storage library, it also includes: responding to an activation signal, receiving the row address information of the storage library corresponding to the activation signal and latching it; responding to a read signal, receiving the column address information corresponding to the read signal and inputting it into a buffer.

[0014] In some embodiments, generating a corresponding error detection signal based on the stored data and the verification data includes: generating a verification code based on the stored data, and comparing the verification code with the verification data to generate a comparison result; receiving the comparison result and determining whether a condition is met, and when the comparison result meets the condition, generating the error detection signal at an invalid level, and when the comparison result does not meet the condition, generating the error detection signal level at a valid level.

[0015] In some embodiments, the receiving of the error detection signal and storing address information corresponding to errors that do not meet the conditions when the error detection signal is at an invalid level includes: receiving multiple error detection signals corresponding to multiple storage libraries, merging them to generate a total error detection signal, wherein when any error detection signal is at an invalid level, an invalid level total error detection signal is generated; selecting the received address information in response to the multiple error detection signals to generate error row address information and error column address information; and storing the error row address information and the error column address information in response to the total error detection signal.

[0016] In some embodiments, the received address information is selected in response to the multiple error detection signals to generate error row address information and error column address information, including: receiving the multiple error detection signals and multiple row address information corresponding to the multiple storage libraries, and when any of the error detection signals is at an invalid level, outputting the row address information of the corresponding storage library as error row address information; in response to a read delay signal, outputting the column address information corresponding to the read signal from the buffer as error column address information, wherein the read delay signal is a delayed signal of the read signal.

[0017] According to some embodiments of the present disclosure, a third aspect of the embodiments of the present disclosure further provides a storage device, comprising multiple memories as described in the first aspect, and multiple ECC chips; the error row address information and the error column address information in the memories are used to locate the data position where an error that does not meet the conditions has occurred, and the check data stored in the ECC chip is used to perform error detection and correction on the storage data and / or check data corresponding to the error row address information and the error column address information.

[0018] The disclosed embodiment provides a memory, a memory operation method and a storage device, wherein the memory includes: a plurality of storage banks and a plurality of ECC storage blocks; a plurality of error detection circuits configured to receive storage data read from corresponding storage banks and verification data read from corresponding ECC storage blocks, and generate error detection signals, wherein the error detection signals are used to indicate whether a qualified error has occurred in the storage data and / or verification data; an error address generation circuit configured to receive address information, and in response to any error detection signal, store the address information corresponding to the error that does not meet the conditions in a mode register. In this way, the error detection circuit can detect whether a qualified error has occurred in the storage bank and / or the ECC storage block, and the error address generation circuit can store the address information corresponding to the error that does not meet the conditions in the mode register. In this way, the on-chip ECC can be used to pre-identify the errors occurring in the memory, and after identifying the on-chip ECC uncorrectable errors, an error detection signal is generated to timely record the error address information, so as to facilitate the subsequent correction of the errors and improve the accuracy of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the composition structure of a memory provided by an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of the structure of an error detection circuit provided by an embodiment of the present disclosure;

[0022] Figure 3 A schematic diagram of the structure of an error address generation circuit provided by an embodiment of the present disclosure;

[0023] Figure 4 A schematic diagram of data configuration of a mode register provided in an embodiment of the present disclosure;

[0024] Figure 5 A schematic diagram of the structure of a row address generation circuit provided in an embodiment of the present disclosure;

[0025] Figure 6 A circuit diagram of a row address generation circuit provided by an embodiment of the present disclosure;

[0026] Figure 7 A schematic diagram of the structure of a column address generation circuit provided in an embodiment of the present disclosure;

[0027] Figure 8 A circuit diagram of a column address generation circuit provided by an embodiment of the present disclosure;

[0028] Fig. 9 A schematic diagram of the structure of a row address storage circuit and a column address storage circuit provided in an embodiment of the present disclosure;

[0029] Fig.10 A circuit diagram of a row address storage circuit and a column address storage circuit provided in an embodiment of the present disclosure;

[0030] Fig.11 A schematic diagram of the process steps of a memory operation method provided by an embodiment of the present disclosure;

[0031] Fig.12 A schematic diagram of another process step of a memory operation method provided by an embodiment of the present disclosure;

[0032] Fig.13 A schematic diagram of another process step of a memory operation method provided by an embodiment of the present disclosure;

[0033] Fig.14 A schematic diagram of another process step of a memory operation method provided by an embodiment of the present disclosure;

[0034] Fig.15 A schematic diagram of another process step of a memory operation method provided by an embodiment of the present disclosure;

[0035] Fig.16 A schematic diagram of another process step of a memory operation method provided by an embodiment of the present disclosure;

[0036] Fig.17 A schematic diagram of the composition structure of a storage device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. In addition, although the disclosure in the present disclosure is introduced according to one or several exemplary examples, it should be understood that each aspect of the disclosure can also constitute a complete implementation method separately.

[0038] It should be noted that the brief description of terms in the present disclosure is only for the convenience of understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise specified, these terms should be understood according to their ordinary and common meanings.

[0039] The terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar or similar objects or entities, and are not necessarily meant to limit a specific order or sequence, unless otherwise noted. It should be understood that the terms used in this way are interchangeable under appropriate circumstances, for example, they can be implemented in an order other than those given in the diagrams or descriptions of the embodiments of the present disclosure.

[0040] In addition, the terms "include" and "have" and any variations thereof are intended to cover but not exclude inclusion, for example, a product or device comprising a list of components is not necessarily limited to those components expressly listed but may include other components not expressly listed or inherent to such products or devices.

[0041] The term "module" as used in this disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware and / or software code that is capable of performing the functions associated with that element.

[0042] In current memory applications, the stability and correctness of memory data storage can be improved through error checking and correction technology (ECC). ECC includes side band ECC and on-die ECC. For side band ECC, an additional DRAM chip is set on the memory stick to store ECC code, and then the error checking and correction technology is implemented in the controller through an additional data bus for ECC. On-die ECC is implemented in the DRAM chip, and an additional ECC storage area is set outside the main storage area used to store data to store ECC check data. Since on-chip ECC is integrated inside the chip, data can be directly corrected by this technology during calculation or transmission without additional processing or transmission, which greatly reduces transmission delay and energy consumption. However, on-chip ECC can only check and correct single-bit errors.

[0043] The disclosed embodiment provides a memory, characterized in that it includes: a plurality of storage banks, each storage bank includes a plurality of data storage blocks and ECC storage blocks; a plurality of error detection circuits, corresponding to the plurality of storage banks one by one; each error detection circuit is configured to read storage data and verification data from the plurality of data storage blocks and ECC storage blocks of the corresponding storage bank respectively, and generate a corresponding error detection signal according to the storage data and verification data, wherein the error detection signal is used to indicate whether a qualified error has occurred in the storage data and / or verification data of the corresponding storage bank; an error address generation circuit is configured to receive a plurality of error detection signals from the plurality of error detection circuits, and when any error detection signal is at an invalid level, store the address information corresponding to the error that does not meet the condition into a mode register for storage; wherein the address signal information includes: error row address information and error column address information. In this way, the on-chip ECC can be used to pre-identify the errors occurring in the memory, and after identifying the errors that cannot be corrected by the on-chip ECC, the error address information is recorded in time according to the indication of the generated error detection signal, so as to facilitate the subsequent correction of the errors and improve the accuracy of the memory.

[0044] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0045] In one embodiment of the present disclosure, reference Figure 1 , which shows a schematic diagram of the composition structure of a memory 10 provided by an embodiment of the present disclosure. Figure 1 As shown, the memory 10 includes: a plurality of storage libraries, each storage library includes a plurality of data storage blocks and ECC storage blocks; a plurality of error detection circuits 100, corresponding one to one with the plurality of storage libraries; each error detection circuit is configured to read storage data and verification data from the plurality of data storage blocks and ECC storage blocks of the corresponding storage library, respectively, and generate a corresponding error detection signal according to the storage data and verification data, wherein the error detection signal is used to indicate whether a qualified error has occurred in the storage data and / or verification data of the corresponding storage library; an error address generation circuit 200, configured to receive a plurality of error detection signals from the plurality of error detection circuits, and when any error detection signal is at an invalid level, store the address information corresponding to the unqualified error into the mode register for storage; wherein the address signal information includes: error row address information and error column address information.

[0046] like Figure 1As shown, the memory 10 includes a plurality of storage banks, each of which includes a plurality of data storage blocks and ECC storage blocks (not shown in the figure). For DRAM, the plurality of storage banks can be divided into a plurality of storage groups (Bank Group, BG) according to the operation requirements, and each storage group includes a plurality of storage banks (Bank, BA). For example, for a memory 10 with 32 storage banks, when the memory 10 is in the X4 / X8 operation mode, the memory 10 can be divided into 8 storage groups, each of which includes 4 storage banks (as shown in the dotted box in the figure, a storage group can include 4 storage banks BA0, BA1, BA2, BA3). Each storage bank can be divided into a plurality of storage strips (sections) according to the layout, and each storage strip includes a plurality of storage blocks (memory array tile, MAT) and at least one ECC storage block (ECC mat), the storage block is used to store data, and the ECC storage block is used to store verification data. In each storage bank, there is a corresponding on-chip ECC calculation module, which is used to calculate the storage data read from the storage bank according to a preset algorithm. If the storage data read from the storage memory and the check data read from the ECC storage block are inconsistent after calculation and comparison, it indicates that an error has occurred. If it is a 1-bit error, the on-chip ECC can correct it. However, for errors greater than or equal to 2 bits, the on-chip ECC cannot correct them due to insufficient check capability. It should be explained that the check capability of the on-chip ECC is determined by the number of bits of the check code and the encoding method. For the on-chip ECC using the Hamming code encoding method, an N-bit (bit) check code can be used to correct 1 bit of 2^N-1 bits of data. Taking an 8-bit check code as an example, 2^8-1=255, that is, an 8-bit check code can be used to correct 1 bit of 255 bits of data. For 128 bits of data, 2^7-1=127<128<2^8-1, so an 8-bit ECC check code is also required to achieve 1-bit check and correction. For errors greater than or equal to 2 bits, if on-chip ECC is used to correct them, more check codes need to be set, the ECC encoding circuit will be more complicated, and the ECC calculation module will occupy more memory space, which is not conducive to improving the integration of the memory.

[0047] Specifically, when the error detection signal is at a valid level, it indicates that a qualified error has occurred in the storage data and / or verification data of the corresponding storage library, and when the error detection signal is at an invalid level, it indicates that a non-qualified error has occurred in the storage data and / or verification data of the corresponding storage library.

[0048] Multiple error detection circuits 100 can be arranged in the peripheral adjacent area of ​​the storage memory bank, and are configured to receive storage data read from the corresponding storage memory bank and verification data read from the corresponding ECC storage block. If the storage data and / or verification data have an error that can be corrected by the on-chip ECC, that is, an error less than or equal to 1 bit, then it is called a qualified error, and the error detection circuit 100 generates an error detection signal of a valid level. If the storage data and / or verification data have an error that cannot be corrected by the on-chip ECC, that is, an error greater than or equal to 2 bits, then it is called an unqualified error, and the error detection circuit 100 generates an invalid error detection signal. The number of the multiple error detection circuits 100 here can correspond one-to-one to the number of storage memory banks, that is, each storage memory bank corresponds to an error detection circuit 100. In this way, the on-chip ECC is used to pre-identify the errors that may occur in the memory 10, and for qualified errors, a valid error detection signal is generated, and for unqualified errors, an invalid error detection signal is generated. Among them, the invalid level can be a high level, logic 1, and the valid level can be a low level, logic 0. As Figure 1 As shown, the error detection circuit 100 can be set in the peripheral area on the left or right side of the storage library, so that the storage data read from the storage library and the verification data read from the ECC storage block can be received as quickly as possible, avoiding the misidentification of errors caused by the flipping of data on the long data bus, and improving the accuracy of error identification.

[0049] The error address generation circuit 200 can be set in the middle area of ​​the memory 10, and is configured to receive address information, and in response to any error detection signal, store the address information corresponding to the error that does not meet the conditions in the mode register. The error address generation circuit 200 here is used to receive the error detection signals generated by multiple error detection circuits 100. If any one of the error detection signals is an invalid level, that is, the error detection signal is valid, indicating that an on-chip ECC uncorrectable error has occurred in the memory 10, then the error address generation circuit 200 will store the address information corresponding to the error. In this way, the address information corresponding to the pre-identified on-chip ECC uncorrectable error is recorded in a timely manner, which facilitates the subsequent memory controller to correct the error based on the check data stored in the external ECC chip, thereby improving the accuracy of the memory. The error address generation circuit 200 is set in the middle area of ​​the memory 10, so that the delay of the error detection signal transmitted from the storage banks on the left and right sides of the memory 10 to the error address generation circuit 200 is consistent, avoiding the mis-collection of errors.

[0050] In some embodiments, the address information corresponding to the error that does not meet the conditions is stored in a reserved (Reserved for future use, RUF) mode register, and the memory controller can read the address information corresponding to the error from the mode register of the memory through a mode register read command (Mode Register Read, MRR) or a mode register set command (Mode Register Set, MRS). In some other embodiments, a specific register can also be added to the memory to store the address information corresponding to the detected error that does not meet the conditions, which is not specifically limited here.

[0051] In some embodiments, Figure 4 As shown, the error column address information also includes: error storage group information (BG<2:0>) and error storage memory bank information (BA<1:0>). Since the CA address carried in the read command includes the storage group information, storage memory bank information and column address information at the same time, in the present disclosure, the storage group information (BG<2:0>) and storage memory bank information (BA<1:0>) are received, latched and stored together with the column address information (CA<10:4>) as column address information. In some other embodiments, the storage group information and storage memory bank information may also be processed separately based on the error detection information, which is not specifically limited here.

[0052] In one embodiment of the present disclosure, reference Figure 2 and Figure 4 The error address generation circuit 200 is also configured to generate and store error identification information UCE FLAG when any error detection signal is at an invalid level; wherein the error identification information UCE FLAG is used to indicate whether an unqualified error has occurred in the storage data and / or verification data corresponding to the address information stored by the error address generation circuit 200.

[0053] Specifically, the error identification information UCE FLAG is used to mark whether an unqualified error has occurred in the storage data and / or the check data corresponding to the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200. The external memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 through a read command (for example, a mode register read command MRR), but the memory controller does not know whether the read address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) is the error address information corresponding to the unqualified error. Therefore, when the memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit, the corresponding error identification information UCE FLAG stored in the error address generation circuit 200 is also read out. When the error identification information UCE FLAG is at a first level, the corresponding address information (RA_UCE / CA_UCE / When the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has an error that does not conform to the conditions, the memory controller performs error detection / correction in combination with the check data in the ECC chip. When the error identification information UCE FLAG is at the second level, the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has no error that does not conform to the conditions, and the memory controller does not need to perform error detection / correction processing. The first level can be a high level, logic 1, and the second level can be a low level, logic 0, which is not specifically limited here.

[0054] It should be noted that if Figure 4As shown, each mode register can store 8 data bits (OP<7:0>), corresponding to 8-bit address information or other information. Specifically, mode register MR70-73 records NEW RA_UCE<16:0> / NEWCA_UCE<10:4> / NEW BG_UCE<2:0> / NEW BA_UCE<1:0> and mode register MR74-77 records OLD RA_UCE<16:0> / OLD CA_UCE<10:4> / OLD BG_UCE<2:0> / OLD BA_UCE<1:0>, respectively indicating the two address information corresponding to the two read data where the errors that do not meet the conditions have occurred. NEW and OLD are only used to distinguish between the two address information, and can also be used (RA1_UCE<16:0> / CA1_UCE<10:4> / BG1_UCE<2:0> / BA1_UCE<1:0>) and (RA0_UCE<16:0> / In addition to the address information, the mode registers MR70-73 and MR74-77 also record the corresponding error identification information UCE FLAG to identify whether the storage data and verification data corresponding to the address information stored in the corresponding mode register have errors that do not meet the conditions. In addition, the Serial Number recorded in the mode register MR69 is used to indicate the number of address information stored in the memory that has errors that do not meet the conditions. For example, if the memory can only store two address information that have errors that do not meet the conditions, Serial Number = 2.

[0055] In one embodiment of the present disclosure, reference Figure 2 , which shows a schematic diagram of the structure of an error detection circuit 100 provided by an embodiment of the present disclosure. Figure 2 As shown, the error detection circuit 100 includes: a first detection circuit 101, configured to receive storage data OP<127:0> and check data ECC<7:0>, and compare the check code generated based on the storage data OP<127:0> with the check data ECC<7:0> to generate a comparison result Parity<7:0>; a first judgment circuit 102, configured to receive the comparison result Parity<7:0> and judge whether the comparison result meets the conditions, and when the comparison result meets the conditions, generate an error detection signal UCE_flag at an invalid level, and when the comparison result does not meet the conditions, generate an error detection signal UCE_flag at a valid level.

[0056] The first detection circuit 101 may include a multi-level XOR gate, which is used to receive the storage data OP<127:0> read from the storage memory and the check data ECC<7:0> read from the ECC storage block, and compare the check code generated based on the storage data OP<127:0> with the check data ECC<7:0> to generate a comparison result Parity<7:0>. Here, taking the storage data as 128 bits and the check data as 8 bits as an example, a 7-level XOR gate may be set to receive the storage data OP<127:0>, and then perform an XOR operation to generate an 8-bit check code, and then compare the check data ECC<7:0> with the check code to generate a comparison result Parity<7:0>.

[0057] The first judgment circuit 102 is used to receive the comparison result Parity<7:0> generated by the first detection circuit 101 and judge whether the comparison result meets the condition, and generate an error detection signal UCE_flag at an invalid level when the comparison result meets the condition, and generate an error detection signal UCE_flag at a valid level when the comparison result does not meet the condition. Specifically, it can be judged whether the comparison result Parity<7:0> meets the first condition first, where the first condition can be whether the comparison result Parity<7:0> is all 0 (=00000000), if the comparison result Parity<7:0> is all 0, indicating that the check code calculated by the storage data OP<127:0> is consistent with the check data ECC<7:0>, that is, the storage memory has no error, so the error detection signal UCE_flag at a valid level is generated, otherwise, indicating that the check code calculated by the storage data OP<127:0> is inconsistent with the check data ECC<7:0>, that is, the storage memory has an error, then the first judgment circuit 102 continues to judge whether the comparison result Parity<7:0> meets the second condition. The second condition here may be that one bit of the 128-bit storage data OP<127:0> has an error or one bit of the 8-bit check data ECC<7:0> has an error. Since the errors here are all errors that can be corrected by the on-chip ECC, an error detection signal UCE_flag with a valid level is generated. Otherwise, it indicates that the check code and / or check data ECC calculated and generated by the storage data OP<127:0> have more than or equal to two bits of errors, that is, an error that cannot be corrected by the on-chip ECC occurs in the storage library. In this way, an error detection signal UCE_flag with an invalid level is generated.

[0058] The first judgment circuit 102 can be composed of multi-stage logic circuit operations, such as a NAND gate, an XOR gate, etc. The specific circuit of the first judgment circuit 102 corresponds to the first condition and the second condition one by one. It should be understood by those skilled in the art that when different ECC calculation encoding methods are adopted, the corresponding first condition and the second condition will also be different, so the implementation circuit of the first judgment circuit 102 is also different. The embodiment of the present disclosure does not impose any limitation on the specific circuit of the first judgment circuit 102.

[0059] It should be noted that there is a special case, that is, when there are more than or equal to 2 bits of errors in the stored data and / or the check data, but the codes of multiple error positions are superimposed and still correspond to one error position, the on-chip ECC believes that a 1-bit error has occurred in the stored data and / or the check data, that is, an error that does not meet the conditions has been missed. In order to increase the probability of correct identification of errors, the coding matrix of the on-chip ECC can be modified to avoid this situation as much as possible. The embodiment of the present disclosure does not discuss too much about the specific implementation method of the coding matrix of the on-chip ECC.

[0060] In one embodiment of the present disclosure, reference Figure 3 and Figure 4 , which shows a schematic diagram of the composition structure of the error address generation circuit 200 provided in an embodiment of the present disclosure. Figure 3 As shown, the error address generation circuit 200 includes: a merging circuit 201, configured to receive a plurality of error detection signals UCE_flag<31:0> corresponding to a plurality of memory banks, and merge to generate a total error detection signal UCE_flag_all, wherein if any error detection signal UCE_flag is at an invalid level, the generated total error detection signal UCE_flag_all is at an invalid level; a row address generation circuit 202, configured to receive a plurality of error detection signals UCE_flag<31:0> and the total error detection signal UCE_flag_all l. When any error detection signal UCE_flag is at an invalid level, the row address information RA of the corresponding storage memory is output as the error row address information (RA_UCE), and the error row address information (RA_UCE) is stored in response to the error detection total signal UCE_flag_all at an invalid level; the column address generation circuit 203 is configured to store the error column address information (CA_UCE / BG_UCE / BA_UCE) corresponding to the error that does not meet the conditions in response to the error detection total signal UCE_flag_all at an invalid level.

[0061] Since each memory bank corresponds to an error detection circuit 100, and generates a corresponding error detection signal UCE_flag. Figure 1As shown, when a memory 10 includes 32 memory banks, 32 error detection signals UCE_flag<31:0> will be generated accordingly. In order to reduce the space occupied by the error address generation circuit 200 in the memory 10, a merging circuit 201 can be provided to receive multiple error detection signals UCE_flag<31:0> corresponding to multiple memory banks, and merge to generate a total error detection signal UCE_flag_all. When any error detection signal UCE_flag is at an invalid level, that is, when an error that cannot be corrected by the on-chip ECC occurs in any memory bank, the total error detection signal UCE_flag_all generated by the merging circuit 201 is also at an invalid level, which can enable the subsequent row address generation circuit 202 and column address generation circuit 203 to store the row address information and column address information corresponding to the error, respectively.

[0062] In some embodiments, the merging circuit 201 may be a multi-input OR gate, the input end of which receives a plurality of error detection signals UCE_flag<31:0>, and the output end of which outputs the error detection total signal UCE_flag_all.

[0063] The row address generation circuit 202 can select the received row address information RA in response to multiple error detection signals UCE_flag<31:0>, generate error row address information, and store it in the corresponding mode register in response to the error detection total signal UCE_flag_all; while the column address generation circuit 203 directly stores the corresponding error column address information in the corresponding mode register in response to the error detection total signal UCE_flag_all.

[0064] It should be noted that, for the row address information RA and the column address information CA, according to the DRAM truth table, the row address information RA is obtained by decoding the command / address signal corresponding to the activation command, and the column address information CA is obtained by decoding the command / address signal corresponding to the read command. For the error detection signal UCE_flag, it is generated by performing a logical operation through the error detection circuit 100 after the memory 10 receives the read command. Therefore, it is necessary to select or delay the reading of the received address information RA / CA through multiple error detection signals UCE_flag<31:0> to ensure that the current error has an accurate correspondence with the stored error row address information and error column address information. Specifically, Figure 3As shown, in the row address generation circuit 202, it is also necessary to select multiple row address information RA received in parallel through multiple error detection signals UCE_flag<31:0> to avoid the occurrence of cross-reading and writing, that is, when the memory 10 has not completed the reading operation on one storage bank, it simultaneously activates another storage bank, so that the row address information RA corresponding to the next activation operation is mistakenly selected by the error address generation circuit 200 in response to the current error detection total signal UCE_flag_all. Since the column address information CA and the error detection signal UCE_flag are both generated according to the read command, the delay between the two has a fixed corresponding relationship. By delaying the reading of the corresponding column address information, the possibility of mistaken selection is relatively small. Therefore, the received column address information CA can be directly delayed and read as the error column address information. For the mode register, as long as any one of the error detection signals UCE_flag is at an invalid level, that is, any one of the storage banks has an error that cannot be corrected by the on-chip ECC, the address information corresponding to the error is stored in the mode register in response to the error detection total signal UCE_flag at an invalid level, so as to facilitate the subsequent location and correction of the error.

[0065] In some embodiments, the column address generation circuit 203 may also adopt a design similar to that of the row address generation circuit 202, that is, the column address generation circuit 203 also selects the received column address information CA in response to the multiple error detection signals UCE_flag<31:0>, generates error column address information, and stores it in the corresponding mode register in response to the error detection total signal UCE_flag_all. Figure 5 , which shows a schematic diagram of the composition structure of a row address generation circuit 202 provided by an embodiment of the present disclosure. Figure 4 As shown, the row address generation circuit 202 includes: a plurality of row address latch circuits 2021, corresponding to a plurality of memory banks one by one, each row address latch circuit 2021 being configured to respond to an activation signal ACT of a corresponding memory bank. <31> , the activation signal ACT <31> The corresponding row address information RA31 is latched; the row address selection circuit 2022 is configured to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latch circuits 2021, and when any error detection signal UCE_flag is at an invalid level, the corresponding row address information RA is output as error row address information RA_UCE; the row address storage circuit 2023 is configured to store the error row address information RA_UCE in response to the total error detection signal UCE_flag_all at an invalid level.

[0066] As mentioned above, since the row address information RA of the storage data and the activation signal ACT are obtained by decoding the command / address signal corresponding to the activation signal ACT, in order to match the delay of the error detection signal UCE_flag, a plurality of row address latch circuits 2021 corresponding to the plurality of storage banks can be set, and each row address latch circuit 2021 is used to respond to the corresponding activation signal ACT. <31> , decodes the corresponding command / address signal to obtain the row address information RA31 of the corresponding storage memory for latching. The row address selection circuit 2022 is configured to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latch circuits 2021, and when any error detection signal UCE_flag is at an invalid level, outputs the corresponding row address information RA as error row address information RA_UCE. The row address selection circuit 2022 is used to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latch circuits 2021, and select to generate error row address information RA_UCE according to multiple error detection signals UCE_flag<31:0>, for example: UCE_flag<31:0> in multiple error detection signals UCE_flag<31:0> <30> is an invalid level, the corresponding row address information RA31 is output as the error row address information RA_UCE. Among them, the error detection signal UCE_flag corresponding to any storage library is at an invalid level, indicating that an on-chip ECC uncorrectable error has occurred in the storage library, so the row address selection circuit 2022 is enabled to select and generate the row address information corresponding to the storage library, which is the error row address information RA_UCE. The row address storage circuit 2023 receives the error row address information RA_UCE generated by the row address selection circuit 2022, and responds to the total error detection signal UCE_flag_all at an invalid level, and stores the error row address information RA_UCE in the corresponding mode register. It should be noted that if Figure 4 As shown, the mode register corresponding to the row address information here may be a redundant mode register preset in the memory, for example, mode registers MR70 to MR72, 3 mode registers, used to store 17 bits of error row address information, each mode register can store 8 bits.

[0067] In some embodiments, reference Figure 6 , which shows a circuit diagram of a row address generation circuit 202 provided by an embodiment of the present disclosure. Figure 6As shown, each row address latch circuit 2021 may include a group of latches, the data input end of each latch receives a bit of data in a group of row address signals RA<16:0> of the corresponding memory bank, the clock end of each latch receives an activation signal ACT31 of the corresponding memory bank (herein, a group of latches included in the row address latch circuit 2021 corresponding to the 32nd memory bank is used for illustration), and in response to the activation signal ACT31, the corresponding memory bank BA is latched. <31> Therefore, the number of latches included in the row address latch circuit 2021 can be set to be the same as the number of bits of the row address information RA<16:0> of the memory bank, and each bit of the row address information RA<16:0> is latched one by one.

[0068] like Figure 6 As shown, the row address selection circuit 2022 is used to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 latched by multiple row address latch circuits 2021, and select to generate error row address information RA_UCE according to the multiple error detection signals UCE_flag<31:0>, for example: UCE_flag<31:0> in the multiple error detection signals UCE_flag<31:0> <30> If the level is invalid, the corresponding row address information RA31 is output as error row address information RA_UCE. Figure 6 The row address selection circuit 2022 may include a group of (17) selectors, and the multiple (32) input terminals of each selector are respectively used to receive the same bit of data in the multiple (32) row address information RA31-RA0 latched by the multiple (32) row address latch circuits 2021. For example, the first selector MUX receives RA0 <0> …RA31 <0> , the second selector MUX receives RA0 <1> …RA31 <1> , and so on, the control end of each selector MUX receives multiple error detection signals UCE_Flag<31:0> corresponding to multiple memory banks. If any memory bank has an error that does not meet the conditions, that is, an error that cannot be corrected by the on-chip ECC, the error detection signal UCE_flag corresponding to the memory bank is at an invalid level (UCE_flag=1), then the selector is controlled to output the 1-bit row address information corresponding to the memory bank. Therefore, the row address selection circuit 2022 includes a group of selectors MUX corresponding to the output of a group of (17 bits) row address information recorded as error row address information RA_UCE<16:0>. Continue to refer to Figure 6, the row address storage circuit 2023 may include a group (17) of triggers, the data input end of each trigger receives 1 bit of the error row address information RA_UCE<16:0>, and the clock end of the trigger receives the error detection total signal UCE_flag_all, which is used to respond to the error detection total signal UCE_flag_all at an invalid level, and store 1 bit of the error row address information RA_UCE<16:0> in the corresponding mode register. The row address storage circuit 2023 includes a group (17) of triggers that store 17 bits of the error row address information RA_UCE<16:0> in parallel in the corresponding mode register. It should be noted that the number of a group of triggers here corresponds to a plurality of bits in the mode register, and every 8 triggers constitute a mode register. For example, if the error row address information RA_UCE<16:0> includes 17 bits, then 17 triggers are required to constitute 3 8-bit (capacity) mode registers to store it. For the sake of simplicity in the diagram, only one latch and one trigger are shown in the accompanying drawings. In the actual circuit, the memory includes 32 storage banks, the row address information RA includes 17 bits of data, the row address latch circuit 2021 may include 32 groups of latches, each group includes 17 latches, corresponding to the 17 bits of data of the row address signal RA<16:0>, the row address selection circuit 2022 also includes 32 groups of selectors, each group includes 17 selectors, corresponding to the 17 bits of data of the row address signal RA<16:0>, and the row address storage circuit 2023 may include 17 triggers, corresponding to the 17 bits of data of the error row address signal RA_UCE<16:0>.

[0069] In one embodiment of the present disclosure, reference Figure 7 , which shows a schematic diagram of the composition structure of a column address generation circuit 203 provided by an embodiment of the present disclosure. Figure 7 As shown, the column address generation circuit 203 includes: a column address latch circuit 2031, which is configured to input the column address information corresponding to the signal into a buffer in response to a read signal, and output the column address information corresponding to the read signal from the buffer as error column address information in response to a read delay signal; wherein the read delay signal is a delayed signal of the read signal; and a column address storage circuit 2032, which is configured to store the error column address information into a corresponding mode register in response to a total error detection signal at an invalid level.

[0070] As mentioned above, since the column address information CA of the stored data is obtained by decoding the command / address signal corresponding to the read command, a column address latch circuit 2031 can be set to respond to the read signal READ, decode the command / address signal to obtain the corresponding column address information CA and input it into the buffer, and respond to the read delay signal READ_DL, output the column address information CA corresponding to the read signal READ from the buffer as the error column address information CA_UCE. It can be understood that in the process of DRAM reading data, there is a delay from decoding the read signal READ by the command / address signal decoder, to reading the stored data from the storage library, and then to transmitting the stored data to the data port. The read delay signal READ_DL is the read signal READ after matching these delays. For the error detection signal UCE_flag and the total error detection signal UCE_flag_all, these delays are also required, so the read delay signal READ_DL can be used as the output trigger signal of the column address latch circuit 2031, so that the error detection signal UCE_flag and the total error detection signal UCE_flag_all can match the error column address information CA_UCE released from the column address latch circuit 2031. Therefore, the error column address information CA_UCE here does not need to be selected, that is, the column address information CA received by the column address latch circuit 2031.

[0071] The column address storage circuit 2032 receives the error column address information CA_UCE output by the column address latch circuit 2031 , and in response to the error detection general signal UCE_flag_all at an invalid level, stores the error column address information CA_UCE in a corresponding mode register.

[0072] In some embodiments, the error column address information CA_UCE<11:0> includes 7-bit column address information CA<10:4>, 3-bit storage group address information BG<2:0> and 2-bit storage bank address information BA<1:0>. Therefore, the redundant mode register preset in the memory can be used, such as Figure 4 As shown, for example, MR72 to MR73, two mode registers, are used to store 12-bit error column address information CA_UCE<12:0>, wherein the error column address information CA_UCE<11:0> and the error row address information RA_UCE<16:0> can share the mode register MR72.

[0073] In some embodiments, reference Figure 8 , which shows a circuit diagram of a column address generation circuit 203 provided by an embodiment of the present disclosure. Figure 8As shown, the column address latch circuit 2031 may include a plurality of first-in first-out buffers FIFO, the data input end of the first-in first-out buffer receives the column address information CA (not shown in the figure) generated by decoding the command / address signal corresponding to the read command, the input clock end receives the read signal READ, and is used to input the corresponding column address information CA into the first-in first-out buffer in response to the read signal READ, and the output clock end receives the read delay signal READ_DL, and is used to output the error column address information CA_UCE<11:0> from the first-in first-out buffer in response to the read delay signal READ_DL. Since the delay from the read signal READ to the read delay signal READ_DL is affected by the column access selection delay tAA, during this delay, the memory 10 may receive the next read command, and the column address will change accordingly. In order to store the column address corresponding to each read command, a first-in first-out buffer may be set, and the depth of the first-in first-out buffer satisfies the following condition: depth = t(READ toREAD_DL) / tccds. For example, the depth of the first-in first-out buffer may be set to 10. The number of the FIFO buffers is consistent with the number of bits of the error column address information CA_UCE<11:0>, which may be 12. Each FIFO buffer receives and outputs one bit of column address information.

[0074] The column address storage circuit 2032 may include multiple triggers, the data input end of the trigger receives the error column address information CA_UCE<11:0>, and the clock end of the trigger receives the error detection total signal UCE_flag_all, which is used to respond to the error detection total signal UCE_flag_all at an invalid level, and store the error column address information CA_UCE<11:0> in the corresponding mode register. Similarly, the multiple triggers here correspond to multiple bits in the mode register. For example, if the error column address information CA_UCE<11:0> includes 12 bits, then 12 triggers and 2 8-bit (capacity) mode registers are required to store it. For the sake of simplicity in the diagram, only one trigger is shown in the figure. In the actual circuit, the column address storage circuit 2032 may include 12 triggers, corresponding to the 12-bit data of the error column address information CA_UCE<11:0>.

[0075] In one embodiment of the present disclosure, reference Fig. 9 , which shows a schematic diagram of the composition structure of a row address storage circuit 2023 and a column address storage circuit 2032 provided by an embodiment of the present disclosure. Fig. 9As shown, the row address storage circuit 2023 includes: N serially connected row address storage sub-circuits, the first row address storage sub-circuit 2023_1, configured to store the received error row address information when the error detection total signal UCE_flag_all_dn-1 after N-1 first delays is at an invalid level; the i-th row address storage sub-circuit 2023_i, configured to receive and store the error row address information stored by the i-1-th row address storage sub-circuit 2023_i-1 when the error detection total signal UCE_flag_all_dn-i after Ni first delays is at an invalid level; the N-th row address storage sub-circuit 2023_N, configured to receive and store the error row address information stored by the N-1-th row address storage sub-circuit 2023_N-1 when the error detection total signal UCE_flag_all is at an invalid level; wherein the first delay is a number of clock cycles, N is greater than or equal to 2, and i is greater than 1 and is a positive integer less than N; the first column address storage sub-circuit 2032_1 is configured to store the received error row column address information when the total error detection signal UCE_flag_all_Dn-1 is at an invalid level after executing N-1 times of the second delay; the j-th column address storage sub-circuit 2032_j is configured to receive and store the error column address information stored by the j-1-th column address storage sub-circuit 2032_j when the total error detection signal UCE_flag_all_Dn-j is at an invalid level after executing Nj times of the second delay; the N-th column address storage sub-circuit 2032_N is configured to receive and store the error column address information stored by the N-1-th column address storage sub-circuit when the total error detection signal UCE_flag_all is at an invalid level; wherein the second delay is a number of clock cycles, and j is a positive integer greater than 1 and less than N.

[0076] In the row address storage circuit 2023, N serially connected row address storage subcircuits may be provided. The first row address storage subcircuit may respond to the total error detection signal UCE_flag_all at an invalid level, and store the error row address information RA_UCE corresponding to the current error in the corresponding mode register. In order to distinguish the previous error from the current error, the total error detection signal UCE_flag_all_dn-i received by the i-th row address storage subcircuit 2023_i may be set to be delayed by several clock cycles than the total error detection signal UCE_flag_all_dn-i-1 received by the i+1-th row address storage subcircuit 2023_i+1, where N is greater than or equal to 2. In this way, the total error detection signal used to respond and store by each row address storage subcircuit is different, and is several clock cycles slower than the previous one, thereby realizing the separate storage of the address information corresponding to the N errors, and the storage device may read the address information corresponding to the multiple errors through multiple rounds of mode register read commands, and perform error correction on the same.

[0077] In some embodiments, continue to refer to Fig. 9 , the row address storage circuit 2023 also includes: a first delay chain 2024; the first delay chain is configured to sequentially perform multiple first delays on the error detection total signal to generate multiple delayed error detection total signals, wherein the first delay is a number of clock cycles. Specifically, the first delay chain 2024 performs N-1 first delays on the received error detection total signal, and generates and outputs a corresponding delayed error detection total signal each time, for example: the delayed error detection total signal generated by the first delay chain 2024 after performing 1 first delay on the error detection total signal is sent to the N-1th row address storage sub-circuit, the delayed error detection total signal generated after performing 2 first delays on the error detection total signal is sent to the N-2th row address storage sub-circuit... and so on, the delayed error detection total signal generated after performing N-1 first delays on the error detection total signal is sent to the 1st row address storage sub-circuit.

[0078] It should be noted that the first delay is performed N-1 times in sequence to ensure that the total error detection signal received by each row address storage sub-circuit is delayed by several clock cycles compared to the previous one. The specific number of clock cycles of the first delay can be achieved by adjusting the parameters of the buffer in the delay chain according to requirements, and is not specifically limited here.

[0079] In some embodiments, continue to refer to Fig. 9, the column address storage circuit 2032 further includes: a second delay chain 2033; the second delay chain 2033 is configured to sequentially perform multiple second delays on the error detection total signal to generate multiple delayed error detection total signals, wherein the second delay is a number of clock cycles. Specifically, the second delay chain performs N-1 second delays on the received error detection total signal, and generates and outputs a corresponding delayed error detection total signal for each delay, for example: the second delay chain 2033 performs 1 second delay on the error detection total signal, and generates a delayed error detection total signal, which is sent to the N-1th column address storage sub-circuit, and the second delay chain 2033 performs 2 second delays on the error detection total signal, and generates a delayed error detection total signal, which is sent to the N-2th column address storage sub-circuit... and so on, the delayed error detection total signal generated after the error detection total signal is performed N-1 times the second delay is sent to the 1st column address storage sub-circuit.

[0080] It should be noted that the second delay is performed N-1 times in sequence to ensure that the total error detection signal received by each column address storage sub-circuit is delayed by several clock cycles compared to the previous one. The specific number of clock cycles of the second delay can be achieved by adjusting the parameters of the buffer in the delay chain according to requirements, and the second delay and the first delay can be set to the same number of clock cycles. The second delay and the first delay can also be set to the same number of clock cycles, which is not specifically limited here.

[0081] In some embodiments, reference Fig.10 , which shows a circuit diagram of a row address storage circuit 2023 and a column address storage circuit 2032 provided by an embodiment of the present disclosure. Fig.10As shown, the row address storage circuit 2023 may include 2 groups of serially connected triggers (a group of serially connected triggers can be used as a row address storage subcircuit), each group of triggers includes 17 parallel triggers, wherein the data input end of each trigger in the first group of triggers receives the 17-bit data of the error row address signal RA_UCE<16:0>, the clock end receives the delayed signal of the error detection total signal UCE_flag_all, and the output end of each trigger in the first group of triggers is connected to the data input end of a corresponding trigger in the second group of triggers. The clock end of each trigger in the second group of triggers receives the error detection total signal UCE_flag_all. The column address storage circuit 2032 may include 2 groups of serially connected triggers (a group of serially connected triggers can be used as a column address storage subcircuit), each group of triggers includes 12 parallel triggers, wherein the data input end of each trigger in the first group of triggers receives the 12-bit data of the error column address signal CA_UCE<11:0>, the clock end receives the delayed signal of the error detection total signal UCE_flag_all, and the output end of each trigger in the first group of triggers is connected to the data input end of a corresponding trigger in the second group of triggers. The clock end of each trigger in the second group of triggers receives the error detection total signal UCE_flag_all. The row address storage circuit 2023 and the column address storage circuit 2032 are set to have a depth of 2 (N=2), which can store 2 groups of error address information (each group of error address information includes error row address information RA_UCE and error column address information CA_UCE). The storage device can read 2 pieces of error information that do not meet the conditions through multiple mode register read commands, thereby improving the efficiency of error correction.

[0082] It should be noted that when the row address storage circuit 2023 and the column address storage circuit 2032 respectively include N serially connected storage sub-circuits, at least one trigger is required, that is, at least one bit in the mode register is used to store N (such as Figure 4 As shown, the 8 triggers of the mode register MR69 are used to store the serial number, that is, to record how many error address information is stored in the memory. In this way, the controller can determine how many error address information in the memory needs to be corrected by reading a specific bit in the mode register. For example, the mode register MR69 OP <0> =0, indicating that there is an erroneous address information in the memory that does not meet the conditions and needs to be corrected. The mode register MR69 OP <0> =1, indicating that there are 2 unqualified error address information in the memory that need to be corrected.

[0083] The memory 10 may further include a counting circuit for counting the total error detection signal UCE_flag_all, thereby recording the number of times that non-compliant errors occur in the memory. The controller may perform error correction on the memory 10 by reading the value of the counting circuit.

[0084] The disclosed embodiment also provides a method for operating a memory, wherein the memory includes a plurality of storage libraries, each storage library includes a plurality of data storage blocks and ECC storage blocks, and the operating method includes: receiving storage data and verification data respectively read from a plurality of data storage blocks and ECC storage blocks of any storage library, and generating a corresponding error detection signal according to the storage data and the verification data; wherein the error detection signal is used to indicate whether a qualified error has occurred in the storage data and / or verification data of the corresponding storage library; receiving the error detection signal, and when the error detection signal is at an invalid level, storing address information corresponding to the error that does not meet the conditions; wherein the address information includes: error row address information and error column address information.

[0085] In one embodiment of the present disclosure, reference Fig.11 , which shows a schematic diagram of the process steps of a memory operation method provided by an embodiment of the present disclosure. Fig.11 As shown, the operation method includes the following steps:

[0086] Step S1: receiving storage data and verification data respectively read from a plurality of data storage blocks and ECC storage blocks of any storage library, and generating a corresponding error detection signal according to the storage data and the verification data; wherein the error detection signal is used to indicate whether a qualified error occurs in the storage data and / or verification data of the corresponding storage library;

[0087] Step S2: receiving an error detection signal, and storing address information corresponding to errors that do not meet the conditions when the error detection signal is at an invalid level; wherein the address information includes: error row address information and error column address information.

[0088] In some embodiments, in combination Figure 1 and Fig.11 The specific process of step S1 includes: each error detection circuit 100 receives storage data and verification data respectively read from multiple data storage blocks and ECC storage blocks of the corresponding storage library, and generates a corresponding error detection signal according to the storage data and the verification data; wherein, if a qualified error occurs in the storage data and / or the verification data, an error detection signal of a valid level is generated, otherwise, an error detection signal of an invalid level is generated.

[0089] In some embodiments, in combination Figure 1 and Fig.11The specific process of step S2 includes: the error address generation circuit 200 receives the error detection signal, and when the error detection signal is at an invalid level, stores the address information corresponding to the error that does not meet the conditions in the mode register. The error address generation circuit 200 receives multiple error detection signals corresponding to multiple error detection circuits 100. If any of the error detection signals is at an invalid level, it indicates that the storage data and / or verification data in the corresponding storage memory bank has an error that does not meet the conditions. Therefore, the error address generation circuit 200 is enabled to store the address information corresponding to the error that does not meet the conditions in the mode register.

[0090] In this way, it is possible to detect whether a qualified error has occurred in the memory bank and / or the ECC memory block, and store the address information corresponding to the unqualified error in the mode register. In this way, the on-chip ECC can be used to pre-identify the errors that occur in the memory, and after identifying the errors that cannot be corrected by the on-chip ECC, the error address information is recorded in a timely manner, which is convenient for subsequent error correction and improves the accuracy of the memory.

[0091] Combination Figure 1 , Figure 4 and Fig.12 , while executing step S2, the operation method also includes:

[0092] Step S3: when the error detection signal UCE_flag is at an invalid level, generating and storing error identification information UCEFLAG, wherein the error identification information UCE FLAG is used to indicate whether an unqualified error has occurred in the storage data and / or the check data corresponding to the stored address information.

[0093] Here, the error address generation circuit 200 is also configured to generate and store error identification information UCE FLAG when any error detection signal is at an invalid level; wherein the error identification information UCE FLAG is used to mark whether an unqualified error has occurred in the storage data and / or verification data corresponding to the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200. The external memory controller will read the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit 200 through a read command (for example, a mode register read command MRR), but the memory controller does not know whether the read address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) is the error address information corresponding to the unqualified error. Therefore, when the memory controller reads the address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) stored in the error address generation circuit, the corresponding error identification information UCE FLAG stored in the error address generation circuit 200 is stored in the error address generation circuit 200. FLAG is also read out. When the error identification information UCE FLAG is at the first level, the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has an error that does not meet the conditions, and the memory controller performs error detection / correction in combination with the check data in the ECC chip. When the error identification information UCE FLAG is at the second level, the data of the corresponding address information (RA_UCE / CA_UCE / BG_UCE / BA_UCE) has not an error that does not meet the conditions, and the memory controller does not need to perform error detection / correction processing.

[0094] refer to Fig.13 , which shows another process step schematic diagram of a memory operation method provided by an embodiment of the present disclosure. Fig.11 As shown, the operation method further includes, before receiving the storage data read from the corresponding storage memory bank and the check data read from the ECC storage block and generating the error detection signal;

[0095] Step S00: In response to an activation signal, receiving and latching row address information of a memory bank corresponding to the activation signal;

[0096] Step S01: In response to a read signal, column address information corresponding to the read signal is received and input into a buffer.

[0097] In some embodiments, in combination Figure 4 and Fig.13The specific process of step S00 includes: a row address latch circuit 2021 is used to respond to the activation signal ACT and latch the row address information RA of the storage library obtained by decoding the command / address signal corresponding to the activation signal ACT.

[0098] In some embodiments, in combination Figure 6 and Fig.11 The specific process of step S01 includes: the column address latch circuit 2031 is used to respond to the read signal READ, and input the column address information CA of the storage library obtained by decoding the command / address signal corresponding to the read signal READ into the buffer.

[0099] Since the error detection signal is generated after UCE_flag performs logical operations based on the stored data and / or check data, in order to match the delay of the error detection signal UCE_flag, the address information needs to be latched first, and then the address information corresponding to the error is generated based on the potential selection of the error detection signal UCE_flag.

[0100] refer to Fig.14 , which shows another process step diagram of a memory operation method provided by an embodiment of the present disclosure. Fig.14 As shown, in step S1 of the operation method: generating a corresponding error detection signal according to the stored data and the verification data, specifically including:

[0101] Step S11: Generate a verification code according to the stored data, and compare the verification code with the verification data to generate a comparison result;

[0102] Step S12: receiving the comparison result and determining whether it meets the conditions, and generating an error detection signal at an invalid level when the comparison result meets the conditions, and generating an error detection signal at a valid level when the comparison result does not meet the conditions.

[0103] In some embodiments, in combination Figure 2 and Fig.14 The specific process of step S11 includes: the first detection circuit 101 receives the storage data OP<127:0> and the check data ECC<7:0>, and compares the check code generated according to the storage data OP<127:0> with the check data ECC<7:0> to generate a comparison result Parity<7:0>.

[0104] In some embodiments, in combination Figure 2 and Fig.14, the specific process of step S12 includes: the first judgment circuit 102 receives the comparison result Parity<7:0> and judges whether it meets the condition, and generates an error detection signal UCE_flag at an invalid level when the comparison result meets the condition, and generates an error detection signal UCE_flag at a valid level when the comparison result does not meet the condition. Specifically, it can be judged whether the comparison result Parity<7:0> meets the first condition first, where the first condition can be whether the comparison result Parity<7:0> is all 0 (=00000000), if the comparison result Parity<7:0> is all 0, indicating that the check code calculated by the storage data OP<127:0> is consistent with the check data ECC<7:0>, that is, the storage memory has no error, so the error detection signal UCE_flag at a valid level is generated, otherwise, indicating that the check code calculated by the storage data OP<127:0> is inconsistent with the check data ECC<7:0>, that is, the storage memory has an error, then the first judgment circuit 102 continues to judge whether the comparison result Parity<7:0> meets the second condition. The second condition here may be that one bit of the 128-bit storage data OP<127:0> has an error or one bit of the 8-bit check data ECC<7:0> has an error. Since the errors here are all errors that can be corrected by the on-chip ECC, an error detection signal UCE_flag with a valid level is generated. Otherwise, it indicates that the check code and / or check data ECC calculated and generated by the storage data OP<127:0> have more than or equal to two bits of errors, that is, an error that cannot be corrected by the on-chip ECC occurs in the storage library. In this way, an error detection signal UCE_flag with an invalid level is generated.

[0105] refer to Fig.15 , which shows another process step diagram of a memory operation method provided by an embodiment of the present disclosure. Fig.15 As shown, step S2 of the operation method: receiving an error detection signal, and when the error detection signal is at an invalid level, storing address information corresponding to errors that do not meet the conditions, specifically includes;

[0106] Step S21: receiving multiple error detection signals corresponding to multiple storage bins, and combining them to generate a total error detection signal, wherein if any error detection signal is at an invalid level, then a total error detection signal at an invalid level is generated;

[0107] Step S22: Selecting the received address information in response to a plurality of error detection signals to generate error row address information and error column address information;

[0108] Step S23: storing the error row address information and the error column address information in response to the error detection signal.

[0109] In some embodiments, in combination Figure 3 and Fig.15 The specific process of step S21 includes: a merging circuit 201 is used to receive multiple error detection signals UCE_flag<31:0> corresponding to multiple memory banks, and merge them to generate an error detection total signal UCE_flag_all. When any error detection signal UCE_flag is at an invalid level, that is, when an on-chip ECC uncorrectable error occurs in any memory bank, the error detection total signal UCE_flag_all generated by the merging circuit 201 is also at an invalid level.

[0110] In some embodiments, in combination Figure 3 and Fig.15 The specific process of step S22 includes: a row address generation circuit 202 and a column address generation circuit 203, which are used to select the received address information RA / CA in response to multiple error detection signals UCE_flag<31:0> to generate error row address information and error column address information.

[0111] In some embodiments, in combination Figure 3 and Fig.15 The specific process of step S23 includes: the row address generation circuit 202 and the column address generation circuit 203 store the error row address information and the error column address information in the corresponding mode registers in response to the error detection general signal UCE_flag_all. For the mode register, as long as any one of the error detection signals UCE_flag is at an invalid level, that is, any one of the memory banks has an error that cannot be corrected by the on-chip ECC, the address information corresponding to the error is stored in the mode register in response to the error detection general signal UCE_flag at an invalid level, so as to facilitate the subsequent location and correction of the error.

[0112] refer to Fig.16 , which shows another process step diagram of a memory operation method provided by an embodiment of the present disclosure. Fig.16 As shown, step S22 of the operation method: selecting the received address information in response to the plurality of error detection signals to generate error row address information and error column address information, specifically includes:

[0113] Step S221: receiving a plurality of error detection signals and a plurality of row address information corresponding to a plurality of memory banks, and when any error detection signal is at an invalid level, outputting the row address information of the corresponding memory bank as error row address information;

[0114] Step S222: In response to the read delay signal, outputting the column address information corresponding to the read signal from the buffer as error column address information, wherein the read delay signal is a delayed signal of the read signal.

[0115] In some embodiments, in combination Figure 5 and Fig.16 The specific process of step S221 includes: the row address selection circuit 2022 is used to receive multiple error detection signals UCE_flag<31:0> and multiple row address information RA31-RA0 corresponding to multiple memory banks, and select to generate error row address information RA_UCE according to multiple error detection signals UCE_flag<31:0> corresponding to multiple memory banks. Among them, the error detection signal UCE_flag corresponding to any memory bank is at an invalid level, indicating that an error that cannot be corrected by the on-chip ECC has occurred in the memory bank, so the row address selection circuit 2022 is enabled to select and generate the row address information corresponding to the memory bank, that is, the error row address information RA_UCE.

[0116] In some embodiments, in combination Figure 7 and Fig.16 The specific process of step S222 includes: the column address latch circuit 2031, in response to the read delay signal READ_DL, outputs the column address information CA corresponding to the read signal READ from the buffer as the error column address information CA_UCE.

[0117] It should be noted that this embodiment can be implemented in cooperation with the memory provided in the previous embodiment. The relevant technical details mentioned in the previous embodiment are still valid in this embodiment, and will not be repeated here to reduce repetition.

[0118] The disclosed embodiments further provide a storage device, comprising the memory provided in the above embodiments, and a plurality of ECC chips, wherein the ECC chip corrects non-compliant errors in the memory according to addresses in a mode register in the memory.

[0119] In one embodiment of the present disclosure, reference Fig.15 , which shows a schematic diagram of the composition structure of a storage device 20 provided by another embodiment of the present disclosure. Fig.15 As shown, the storage device 20 includes: multiple memories 10 provided based on the above-mentioned embodiments, and multiple ECC chips 30. The error row address information and the error column address information in the memory 10 are used to locate the data position where an error that does not meet the conditions has occurred. The check data stored in the ECC chip 30 is used to perform error detection and correction on the storage data and / or check data corresponding to the error row address information and the error column address information.

[0120] Specifically, the memory controller can read the error identification information UCE FLAG and the corresponding address information RA / CA stored in each memory chip from the storage device through the mode register read command (MRR or MRS), and determine whether the error identification information UCE FLAG in each memory marks that a non-compliant error has occurred in the corresponding memory chip. Specifically, when the error identification information UCE FLAG is at a first level, it indicates that a non-compliant error has occurred in the corresponding memory chip 10. The memory controller obtains the storage data of the corresponding address information and the check data in the ECC chip 30, and performs error detection / correction on the non-compliant error occurring in the memory chip 10. At this time, the check data in the ECC chip 30 is only used to perform error detection and correction on the specified memory chip 10, and there is no need to perform error detection and correction on all memory chips 10, and the error detection and correction capabilities are greatly improved. When the error identification information UCE FLAG is at a second level, no non-compliant error has occurred in the corresponding memory chip 10, and the memory controller does not need to process the address information obtained from the corresponding memory 10, nor does it need to perform error detection and correction on its data.

[0121] The storage device 20 may be a dual inline memory module (DIMM), including a plurality of memories 10 and a plurality of ECC chips 30. For example, Fig.15 As shown, for the left and right sub-channels, both sides include 2 ECC chips and 8 DRAM chips. The ECC chip here is the sideband ECC. For the sideband ECC using the RS coding mode, when the position of the error is uncertain, the error correction capability of the RS algorithm is half of the check bit. Therefore, 2 ECC chips can correct 2-bit errors of a DRAM chip (one ECC chip is used to determine the position, and one ECC chip is used for error correction). When the error position is determined, the error correction capability of the RS algorithm is equal to the check bit. Therefore, 2 ECC chips can correct 2-bit errors of two DRAM chips. Here, a sub-channel includes 2 ECC chips as an example. The memory 10 in the storage device 20 can pre-identify errors greater than or equal to 2 bits through the error detection circuit 100 and the error address generation circuit 200, and record the position corresponding to the error. The ECC chip 30 can directly correct the error, thereby achieving a doubling of the error correction capability of the sideband ECC while keeping the structure of the storage device 20 unchanged, thereby improving the accuracy of the storage device. It will be understood by those skilled in the art that multiple ECC chips may be provided in one sub-channel to improve the error correction capability.

[0122] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the present application. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present application, so the scope of protection of the present application shall be based on the scope defined in the claims.

Claims

1. A memory, characterized in that: include: A plurality of storage libraries, each of the storage libraries comprising a plurality of data storage blocks and ECC storage blocks; A plurality of error detection circuits corresponding one-to-one to the plurality of storage banks; Each of the error detection circuits is configured to read storage data and check data from the plurality of data storage blocks and the ECC storage blocks of the corresponding storage bank, respectively, and generate a corresponding error detection signal according to the storage data and the check data, wherein the error detection signal is used to indicate whether a qualified error occurs in the storage data and / or the check data of the corresponding storage bank; The error address generation circuit is configured to receive multiple error detection signals from multiple error detection circuits, and when any of the error detection signals is at an invalid level, store the address information corresponding to the error that does not meet the conditions; wherein the address information includes: error row address information and error column address information.

2. The memory according to claim 1, characterized in that: The error address generation circuit is also configured to generate and store error identification information when any of the error detection signals is at an invalid level; wherein the error identification information is used to indicate whether an unqualified error has occurred in the storage data and / or verification data corresponding to the stored address information.

3. The memory according to claim 1, characterized in that: The error detection circuit comprises: A first detection circuit is configured to receive the stored data and the verification data, and compare a verification code generated based on the stored data with the verification data to generate a comparison result; The first judgment circuit is configured to receive the comparison result and judge whether it meets the conditions, and generate the error detection signal at an invalid level when the comparison result meets the conditions, and generate the error detection signal at a valid level when the comparison result does not meet the conditions.

4. The memory according to claim 1, characterized in that: The error address generating circuit comprises: a merging circuit configured to receive a plurality of the error detection signals corresponding to a plurality of the memory banks, and merge them to generate a total error detection signal, wherein if any of the error detection signals is at an invalid level, the generated total error detection signal is at an invalid level; a row address generating circuit configured to receive a plurality of the error detection signals and the error detection total signal, output the row address information of the corresponding memory bank as error row address information when any of the error detection signals is at an invalid level, and store the error row address information in response to the error detection total signal at an invalid level; The column address generating circuit is configured to store error column address information corresponding to errors that do not meet the conditions in response to the error detection total signal at an invalid level.

5. The memory according to claim 4, characterized in that: The row address generation circuit comprises: A plurality of row address latch circuits corresponding to the plurality of memory banks one by one, each of the row address latch circuits being configured to latch row address information corresponding to the activation signal in response to an activation signal of a corresponding memory bank; a row address selection circuit configured to receive a plurality of the error detection signals and a plurality of row address information latched by the row address latch circuits, and output the corresponding row address information as error row address information when any of the error detection signals is at an invalid level; The row address storage circuit is configured to store the error row address information in response to the error detection total signal being at an invalid level.

6. The memory according to claim 5, characterized in that: The column address generation circuit comprises: A column address latch circuit, configured to input column address information corresponding to the read signal into a buffer in response to a read signal, and output the column address information corresponding to the read signal from the buffer as error column address information in response to a read delay signal; wherein the read delay signal is a delayed signal of the read signal; The column address storage circuit is configured to store the error column address information into a corresponding mode register in response to the error detection total signal being at an invalid level.

7. The memory according to claim 6, characterized in that: The row address storage circuit comprises: N serially connected row address storage sub-circuits; The first row address storage subcircuit is configured to store the received error row address information when the total error detection signal after N-1 times of the first delay is at an invalid level; the i-th row address storage subcircuit is configured to receive and store the error row address information stored by the i-1-th row address storage subcircuit when the total error detection signal after Ni times of the first delay is at an invalid level; the N-th row address storage subcircuit is configured to receive and store the error row address information stored by the N-1-th row address storage subcircuit when the total error detection signal is at an invalid level; wherein the first delay is a number of clock cycles, N is greater than or equal to 2, and i is a positive integer greater than 1 and less than N; The column address storage circuit comprises: N serially connected column address storage sub-circuits; The 1st column address storage sub-circuit is configured to store the received error row column address information when the total error detection signal after executing N-1 times of the second delay is at an invalid level; the jth column address storage sub-circuit is configured to receive and store the error column address information stored by the j-1th column address storage sub-circuit when the total error detection signal after executing Nj times of the second delay is at an invalid level; the Nth column address storage sub-circuit is configured to receive and store the error column address information stored by the N-1th column address storage sub-circuit when the total error detection signal is at an invalid level; wherein the second delay is a number of clock cycles, and j is a positive integer greater than 1 and less than N.

8. A method for operating a memory, wherein the memory comprises a plurality of storage banks, each of the storage banks comprises a plurality of data storage blocks and ECC storage blocks, characterized in that: The operation method comprises: Receiving storage data and verification data respectively read from the plurality of data storage blocks and the ECC storage blocks of any of the storage libraries, and generating corresponding error detection signals according to the storage data and the verification data; wherein the error detection signal is used to indicate whether a qualified error occurs in the storage data and / or the verification data of the corresponding storage library; The error detection signal is received, and when the error detection signal is at an invalid level, address information corresponding to the error that does not meet the condition is stored; wherein the address information includes: error row address information and error column address information.

9. The operating method according to claim 8, characterized in that: When the error detection signal is at an invalid level, error identification information is generated and stored, wherein the error identification information is used to indicate whether an unqualified error has occurred in the stored data and / or the verification data corresponding to the stored address information.

10. The operating method according to claim 8, characterized in that: Before receiving the storage data and the verification data respectively read from the plurality of data storage blocks and the ECC storage blocks of the corresponding storage library, the method further includes: In response to an activation signal, receiving and latching row address information of a memory bank corresponding to the activation signal; In response to a read signal, column address information corresponding to the read signal is received and input into a buffer.

11. The operating method according to claim 8, characterized in that: The generating a corresponding error detection signal according to the stored data and the verification data comprises: Generate a verification code according to the stored data, and compare the verification code with the verification data to generate a comparison result; The comparison result is received and it is determined whether it meets the conditions, and when the comparison result meets the conditions, the error detection signal is generated at an invalid level, and when the comparison result does not meet the conditions, the error detection signal level is generated at a valid level.

12. The operating method according to claim 10, characterized in that: The receiving the error detection signal and storing address information corresponding to the error that does not meet the condition when the error detection signal is at an invalid level includes: Receiving multiple error detection signals corresponding to multiple storage bins, and combining them to generate a total error detection signal, wherein when any error detection signal is at an invalid level, an invalid level total error detection signal is generated; Selecting received address information in response to a plurality of the error detection signals to generate error row address information and error column address information; The error row address information and the error column address information are stored in response to the error detection signal.

13. The operating method according to claim 12, characterized in that: The step of selecting the received address information in response to the plurality of error detection signals to generate error row address information and error column address information comprises: receiving a plurality of the error detection signals and a plurality of row address information corresponding to a plurality of memory banks, and outputting the row address information of the corresponding memory bank as error row address information when any of the error detection signals is at an invalid level; In response to a read delay signal, the column address information corresponding to the read signal is output from the buffer as error column address information, wherein the read delay signal is a delayed signal of the read signal.

14. A storage device comprising a plurality of memories according to any one of claims 1 to 7, and a plurality of ECC chips; The error row address information and the error column address information in the memory are used to locate the data position where an error that does not meet the conditions has occurred, and the check data stored in the ECC chip is used to perform error detection and correction on the storage data and / or check data corresponding to the error row address information and the error column address information.

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