Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, wherein the forming method comprises: providing a substrate, the substrate comprising a plurality of active regions, each active region having at least two gate structures on the substrate; forming a sidewall on both sides of the gate structure; forming a silicon oxide layer on the substrate and the gate structure; forming a silicon nitride layer on the silicon oxide layer; forming a photoresist layer with a metal silicide pattern on the silicon nitride layer; using the photoresist layer as a mask, and using a dry and wet combined etching process with etching selectivity to etch the silicon nitride layer and the silicon oxide layer along the metal silicide pattern to expose the top of the substrate and the gate structure. The above-mentioned etching process with etching selectivity is used to etch the silicon nitride layer and the silicon oxide layer, and at the same time, the silicon nitride in part of the sidewall is etched, so as to increase the width of the contact hole between adjacent gate structures, and reduce the contact resistance between the conductive plug and the substrate.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Currently, in the back-end of semiconductor manufacturing, metal wiring, a relatively high-conductivity metal material, is typically used to connect the various components that form integrated circuits. Conductive plugs are typically used to connect these metal wirings. As the link between front-end devices and back-end copper interconnects, the size of the conductive plugs affects their resistance, which directly impacts the device's operating speed.

[0003] However, the conductive plugs in current semiconductor structures have the problem of increased resistance, which affects device performance. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, comprising: providing a substrate, the substrate comprising a plurality of active areas, each active area having at least two gate structures on the substrate, with a common source / drain region between two adjacent gate structures; forming sidewalls on both sides of the gate structure; forming a silicon oxide layer on the substrate and the gate structure; forming a silicon nitride layer on the silicon oxide layer; forming a photoresist layer having a metal silicide pattern on the silicon nitride layer; and according to a silicide self-aligned barrier layer process, using the photoresist layer as a mask, etching the silicon nitride layer and the silicon oxide layer along the metal silicide pattern using an etching process with an etching selectivity ratio until the substrate and the top of the gate structure are exposed.

[0006] Optionally, the step of forming the sidewall includes: forming a sidewall layer on the gate structure and the substrate; etching the sidewall layer on the sidewall of the gate structure until the thickness of the sidewall layer along a direction perpendicular to the sidewall of the gate structure reaches a predetermined size, thereby forming the sidewall.

[0007] Optionally, the method for etching the sidewall layer on the sidewall of the gate structure is dry etching, and the process parameters of the dry etching are chamber pressure 3mt to 40mt, power supply power 0W to 400W, bias voltage 0V to 200V, and etching gas flow rate of 50sccm to 500sccm.

[0008] Optionally, the material of the sidewall spacer is silicon oxide and silicon nitride, and the thickness of the sidewall spacer ranges from 25 nanometers to 35 nanometers.

[0009] Optionally, the method for forming the silicon nitride layer and the silicon oxide layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: the deposition rate of the silicon nitride layer is 2000 angstroms to 3000 angstroms per minute, and the deposition time of the silicon nitride layer is 3 seconds to 10 seconds, the deposition rate of the silicon oxide layer is 400 angstroms to 600 angstroms per minute, and the deposition time of the silicon oxide layer is 10 seconds to 20 seconds; the thickness range of the silicon nitride layer is 200 angstroms to 300 angstroms, and the thickness range of the silicon oxide is 100 angstroms to 200 angstroms.

[0010] Optionally, the steps of etching the silicon nitride layer and the silicon oxide layer include: using a first sub-etching process to etch the silicon nitride layer along the metal silicide pattern until the silicon oxide layer is exposed; using a second sub-etching process to etch a portion of the silicon oxide layer along the metal silicide pattern; and using a third sub-etching process to etch the silicon oxide layer along the metal silicide pattern until the substrate and the top of the gate structure are exposed.

[0011] Optionally, the first sub-etching process is a plasma dry etching process, and the process parameters of the first sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100 V to 200 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 30 seconds to 45 seconds. The first sub-etching process has a first etching selectivity ratio of 2:1 for the silicon nitride layer and the silicon oxide layer.

[0012] Optionally, the second sub-etching process is a plasma dry etching process, and the process parameters of the second sub-etching process include: the etching gas is a combination of one or more of CH3F, O2 and Ar, the gas flow rate of the etching gas is 100sccm to 500sccm, the bias voltage is 150V to 280V, the etching pressure is 40mTorr to 60mTorr, and the etching time is 15 seconds to 25 seconds. The second sub-etching process has a second etching selectivity ratio of 5:1 to 7:1 for the silicon nitride layer and the silicon oxide layer.

[0013] Optionally, the third sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, the reaction time is 3 minutes to 4 minutes, and the second sub-etching process has a third etching selectivity ratio of 3:1 to 6:1 for the silicon oxide layer and the silicon nitride layer.

[0014] Correspondingly, the technical solution of the present invention further provides a semiconductor structure, which is formed by the above-mentioned method for forming a semiconductor structure.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] The technical solution of the present invention forms a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer on the gate structure and the substrate, and the silicon oxide layer and the silicon nitride layer serve as a silicide self-aligned barrier layer. According to the silicide self-aligned barrier layer process, an etching process with an etching selectivity is adopted to etch the silicon nitride layer and the silicon oxide layer. Since the material of the sidewall includes silicon nitride, when the silicon nitride layer and the silicon oxide layer are etched by the etching process, the silicon nitride in part of the sidewall will be etched, thereby increasing the width between adjacent gate structures, and then adjusting the distance between adjacent gate structures, further increasing the contact area between the subsequently formed conductive plug and the substrate, reducing the contact resistance between the conductive plug and the substrate, and improving the performance of the semiconductor structure.

[0017] Furthermore, the technical solution of the present invention first etches the silicon nitride layer using a dry etching process with a first etching selection ratio (2:1). At this time, the etching rate of the silicon nitride layer is faster, so as to remove the silicon nitride layer; then the first etching selection ratio is adjusted to a second etching selection ratio (5:1 to 7:1) to dry-etch part of the silicon oxide layer. At this time, the etching rate of the silicon oxide layer is slower, so as to remove the possible residual silicon nitride layer and part of the silicon oxide layer; finally, the entire silicon oxide layer is wet-etched with a third etching selection ratio (3:1 to 6:1). At this time, the etching rate of the silicon oxide layer is greater than the etching rate of silicon nitride, so that the silicon oxide layer is completely removed while part of the side wall is etched, thereby increasing the width between adjacent gate structures and adjusting the distance between adjacent gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a structural diagram of a semiconductor structure;

[0019] Figures 2 to 17 FIG. 1 is a schematic diagram of a process for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0020] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to whether there is direct contact.

[0021] The formation of semiconductor structures can be referred to Figure 1A first substrate 100 is provided, wherein the first substrate 100 includes a plurality of active areas, each of the active areas having at least two first gate structures 102, a first common source / drain region 1012 between two adjacent gate structures, and first source / drain regions 1011 located on both sides of the first gate structure 102; first sidewalls 103 are formed on both sides of the first gate structure 102; a first metal silicide layer 104 is formed on the first substrate 100 and on top of the first gate structure 102, and a first dielectric layer 105 is formed on the first substrate 100; a photoresist layer (not shown in the figure) having a metal silicide pattern is formed on the first dielectric layer 105; and the first dielectric layer 105 is etched using the photoresist layer (not shown in the figure) as a mask until the first substrate 100 and the top of the first gate structure 102 are exposed, thereby forming a first contact hole 1051.

[0022] In this embodiment, the first contact hole 1051 is a contact hole between adjacent first gate structures.

[0023] In the above scheme, at the 55nm technology node and below, the design distance between adjacent first gate structures is getting smaller and smaller. In addition, with the semiconductor sidewall process, when etching the first contact hole, due to the influence of the distance between adjacent first gate structures, the bottom size of the contact hole is squeezed by the first sidewall (silicon nitride), resulting in a reduction in the bottom size of the first contact hole, which in turn causes the resistance of the conductive plug subsequently formed in the first contact hole to increase, affecting device performance.

[0024] In order to solve the above technical problems, the technical solution of the present invention forms a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer on the gate structure and the substrate, and adopts an etching process with an etching selectivity ratio to etch the silicon nitride layer and the silicon oxide layer. Therefore, while etching the silicon nitride layer and the silicon oxide layer, part of the silicon nitride in the side wall will be etched, thereby adjusting the distance between adjacent gate structures, further increasing the contact area between the subsequently formed conductive plug and the substrate, and reducing the contact resistance between the conductive plug and the substrate.

[0025] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0026] Figures 2 to 17 FIG. 1 is a schematic diagram of a process for forming a semiconductor structure according to an embodiment of the present invention.

[0027] Please refer to Figure 2 , please refer to Figure 2 , providing a substrate 200, wherein the substrate 200 includes several active regions I.

[0028] In this embodiment, the substrate 200 is made of silicon.

[0029] In other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium; in other embodiments, the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0030] Please refer to Figure 3 A gate oxide layer 2011 and a gate layer 2012 located on the gate oxide layer 2011 are sequentially formed on the surface of the substrate 200 .

[0031] In this embodiment, the gate oxide layer 2011 and the gate layer 2012 are formed by a chemical vapor deposition process or a physical vapor deposition process.

[0032] In this embodiment, the thickness of the gate oxide layer 2011 ranges from 60 angstroms to 80 angstroms, and the thickness of the gate layer 2012 ranges from 950 angstroms to 1050 angstroms.

[0033] Please refer to Figure 4 , the gate oxide layer 2011 and the gate layer 2012 are etched until the substrate 200 is exposed, and a gate structure 201 is formed on each of the active regions I.

[0034] Specifically, the method for forming the gate structure 201 includes: forming a first photoresist layer 202 on the surface of the gate oxide layer 2011; using the first photoresist layer 202 as a mask, etching and removing the gate oxide layer 2011 and the gate layer 2012, and forming at least two gate structures 201 on each active area I.

[0035] In this embodiment, the gate oxide layer 2011 is made of silicon nitride or silicon oxide.

[0036] In this embodiment, the gate layer 2012 is made of single crystal silicon or polycrystalline silicon.

[0037] In this embodiment, the critical dimension range between adjacent gate structures 201 is greater than or equal to 120 nanometers.

[0038] In this embodiment, a dry etching process is used to sequentially etch away the gate layer 2012 and the gate oxide layer 2011 until the substrate 200 is exposed. The process parameters of the dry etching process are as follows: the chamber pressure is 5.5mT to 50mT, the source power is 180W to 1000W, the etching gas includes one or more of CH2F2, CL2, HBr, He and O2, the gas flow rate is 20sccm to 200sccm, and the etching time is 6s to 40s. Please refer to Figure 5After etching the gate oxide layer 2011 and the gate layer 2012, the method further includes: forming a sidewall layer (not shown) on the gate structure 201 and the substrate 200; etching the sidewall layer on the sidewall of the gate structure 201 until the thickness of the sidewall layer along a direction perpendicular to the sidewall of the gate structure 201 reaches a predetermined size, thereby forming the sidewall 203.

[0039] In this embodiment, the sidewall spacer 203 includes: a first sidewall spacer 2031 located on the sidewall surface of the gate structure 201 , a second sidewall spacer 2032 located on the surface of the first sidewall spacer 2031 , and a third sidewall spacer 2033 located on the surface of the second sidewall spacer 2032 .

[0040] In this embodiment, the material of the first sidewall spacer 2031 is silicon oxide, the material of the second sidewall spacer 2032 is silicon nitride, and the material of the third sidewall spacer 2033 is silicon nitride.

[0041] In this embodiment, the sidewall spacer 203 is formed by a chemical vapor deposition process.

[0042] In this embodiment, the process parameters for forming the side wall 203 are: the process for forming the first side wall 2031 is thermal oxygen growth, the reaction temperature is 950 degrees Celsius to 1050 degrees Celsius, and the growth thickness is 20 angstroms to 30 angstroms; the process for forming the second side wall 2032 is chemical vapor deposition growth, the reaction temperature is 600 degrees Celsius to 700 degrees Celsius), the deposition rate is 1.5 angstroms per minute to 2.5 angstroms per minute, and the growth thickness is 100 angstroms to 120 angstroms; the process for forming the third side wall 2033 is chemical vapor deposition growth, the reaction temperature is 550 degrees Celsius to 650 degrees Celsius, the deposition rate is 3 angstroms per minute to 4 angstroms per minute, and the growth thickness is 400 angstroms to 500 angstroms.

[0043] In this embodiment, the difference between the silicon nitride in the second sidewall spacer 2032 and the silicon nitride in the third sidewall spacer 2033 lies in the different formation process temperatures.

[0044] In this embodiment, the method for etching the sidewall layer on the sidewall of the gate structure 201 is dry etching, and the process parameters of the dry etching process are: the chamber pressure is 20mT to 100mT, the source power is 500W to 2800W, the bias power is 300W to 2800W, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 20s.

[0045] In this embodiment, the thickness of the sidewall spacer 203 ranges from 25 nanometers to 35 nanometers.

[0046] In the above scheme, the side wall adopts an ONN structure, that is, a layer of silicon oxide and two layers of silicon nitride, and the side wall surface of the side wall is silicon nitride, so that when the silicide self-aligned barrier layer is subsequently etched using an etching process with an etching selectivity ratio, part of the silicon nitride on the side wall surface of the side wall can be removed, thereby achieving adjustment of the distance between adjacent gate structures.

[0047] Please refer to Figure 6 Conductive ions are injected into the substrate 200 on both sides of the gate structure 201 to form a source / drain structure 2041 located on the source / drain region III and a common source / drain structure 2042 on the common source / drain region II between two adjacent gate structures 201.

[0048] In this embodiment, the method for forming the source / drain structure 2041 and the common source / drain structure 2042 includes: using an ion implantation process, injecting ions of opposite types into the substrate 200 on the source / drain region III on both sides of the gate structure 201 and on the common source / drain region II.

[0049] In this embodiment, the process parameters of the ion implantation process include: the ion doping types in the source / drain structure 2041 and the common source / drain structure 2042 are opposite, the ion doping types in the source / drain structure 2041 and the common source / drain structure 2042 are N-type ions or P-type ions, and the ion implantation concentration of the P-type ions is 1E15atom / cm 3 to 3E15atom / cm 3 The concentration of the N-type ion implantation is 0.9E15atom / cm 3 to 2.7E15atom / cm 3 .

[0050] Please refer to Figure 7 , a silicon oxide layer 2051 is formed on the substrate 200 and the gate structure 201.

[0051] In this embodiment, the process of forming the silicon oxide layer 2051 is a chemical vapor deposition process.

[0052] In this embodiment, the process parameters for forming the silicon oxide layer 2051 are as follows: a deposition rate of the silicon oxide layer 2051 is 400 angstroms per minute to 600 angstroms per minute, and a deposition time of the silicon oxide layer 2051 is 10 seconds to 20 seconds.

[0053] In this embodiment, the thickness of the silicon oxide layer 2051 ranges from 100 angstroms to 200 angstroms.

[0054] Please refer to Figure 8 , a silicon nitride layer 2052 is formed on the silicon oxide layer 2051.

[0055] In this embodiment, the process of forming the silicon nitride layer 2052 is a chemical vapor deposition process.

[0056] In this embodiment, the process parameters for forming the silicon nitride layer 2052 are as follows: a deposition rate of the silicon nitride layer 2052 is 2000 angstroms per minute to 3000 angstroms per minute, and a deposition time of the silicon nitride layer 2052 is 3 seconds to 10 seconds.

[0057] In this embodiment, the thickness of the silicon nitride layer 2052 ranges from 200 angstroms to 300 angstroms.

[0058] In this embodiment, the silicon nitride layer 2052 and the silicon oxide layer 2051 are a silicide self-aligned barrier layer 205, which is used to remove the silicon nitride layer 2052 and the silicon oxide layer 2051 not covered by the second photoresist layer 206 through a combination of dry etching and wet etching, exposing the substrate 200 on the active area I, source / drain area III and common source / drain area II where the metal silicide layer 207 needs to be formed, in preparation for the next step of forming the metal silicide layer 207.

[0059] In other embodiments, the silicide self-aligned barrier layer 205 is a single-layer structure.

[0060] Please refer to Figure 9 , a second photoresist layer 206 having a metal silicide pattern is formed on the silicon nitride layer 2052 .

[0061] In this embodiment, the metal silicide pattern is located on the gate structure 201 , on the source / drain region III, and on the common source / drain region II.

[0062] Please refer to Figure 10 According to the silicide self-aligned barrier (SAB) process, the second photoresist layer 206 is used as a mask and an etching process with an etching selectivity ratio is adopted to etch the silicon nitride layer 2052 and the silicon oxide layer 2051 along the metal silicide pattern until the substrate 200 and the top of the gate structure 201 are exposed.

[0063] In this embodiment, the dry etching process has an etching selectivity of 2:1 to 7:1 for the silicon nitride layer 2051 and the silicon oxide layer 2052 ; the wet etching process has an etching selectivity of 3:1 to 6:1 for the silicon oxide layer 2051 and part of the sidewall 203 .

[0064] Of course, the present invention is not limited thereto, and other parameters of etching selectivity are within the protection scope of the present invention.

[0065] In one embodiment, the silicon nitride layer 2052 and the silicon oxide layer 2051 on the sidewalls of the spacer 203 are etched along an etching direction parallel to the substrate 200 to adjust the distance between adjacent gate structures 201 .

[0066] In another embodiment, the silicon nitride layer 2052 , the silicon oxide layer 2051 and part of the sidewall 203 (the second sidewall 2032 and the third sidewall 2033 ) on the sidewall of the sidewall 203 are etched along an etching direction parallel to the substrate 200 to adjust the distance between adjacent gate structures 201 .

[0067] In other embodiments, the silicon nitride layer 2052 and the silicon oxide layer 2051 on the metal silicide layer 207 are etched along an etching direction perpendicular to the substrate 200 until the metal silicide layer 207 is exposed.

[0068] In this embodiment, the steps of etching the silicon nitride layer 2052 and the silicon oxide layer 2051 include: using a first sub-etching process to etch the silicon nitride layer 2052 along the metal silicide pattern until the silicon oxide layer 2051 is exposed; using a second sub-etching process to etch a portion of the silicon oxide layer 2051 along the metal silicide pattern, and using a third sub-wet etching process to etch the entire silicon oxide layer along the metal silicide pattern until the substrate 200 and the top of the gate structure 201 are exposed.

[0069] In this embodiment, the first sub-etching process is a plasma dry etching process, and the process parameters of the first sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100 V to 200 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 30 seconds to 45 seconds. The first sub-etching process has a first etching selectivity ratio of 2:1 for the silicon nitride layer and the silicon oxide layer.

[0070] In this embodiment, the second sub-etching process is a plasma dry etching process, and the process parameters of the second sub-etching process include: the etching gas is a combination of one or more of CH3F, O2 and Ar, the gas flow rate of the etching gas is 100sccm to 500sccm, the bias voltage is 150V to 280V, the etching pressure is 40mTorr to 60mTorr, and the etching time is 15 seconds to 25 seconds. The second sub-etching process has a second etching selectivity ratio of 5:1 to 7:1 for the silicon nitride layer and the silicon oxide layer.

[0071] In this embodiment, the third sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, the reaction time is 3 minutes to 4 minutes, and the second sub-etching process has a third etching selectivity ratio of 3:1 to 6:1 for the silicon oxide layer and the silicon nitride layer.

[0072] The third sub-etching process in the etching process of the present invention etches the silicon nitride in part of the sidewall 203, and since the silicon oxide layer, the silicon nitride layer and part of the sidewall 203 are removed during the etching process, the width between adjacent gate structures 201 is increased, and the distance between adjacent gate structures 201 is adjusted, further increasing the contact area between the subsequently formed conductive plug 2111 and the substrate 200, reducing the contact resistance between the conductive plug 2111 and the substrate 200, and improving the performance of the semiconductor structure.

[0073] In this embodiment, the critical dimension of the contact hole 211 is in a range of 68 nanometers to 77 nanometers.

[0074] Please refer to Figure 11 , a metal layer 2071 is deposited on top of the substrate 200 and the gate structure 201 .

[0075] In this embodiment, the metal layer 2071 is formed by chemical vapor deposition. The material of the metal layer 2071 is nickel-platinum alloy, titanium or cobalt. The thickness of the metal layer 2071 ranges from 80 angstroms to 130 angstroms.

[0076] Please refer to Figure 12 , an annealing process is performed to allow the metal layer 2071 to react with the substrate 200 or the top of the gate structure 201 to form a metal silicide layer 207.

[0077] In this embodiment, the steps of performing annealing process treatment include: performing a first sub-annealing process treatment on the metal layer 2071 and part of the gate layer 2012 or part of the substrate 200, so that the metal layer 2071 and the gate layer 2012 or the substrate 200 react to form a high-resistance metal silicide layer (not shown in the figure); performing a second sub-annealing process treatment on the high-resistance metal silicide layer to cause the high-resistance metal silicide layer to undergo a phase change reaction to form a metal silicide layer 207.

[0078] In this embodiment, the first annealing process adopts a rapid thermal annealing furnace, and the process parameters of the first annealing process are: annealing temperature of 200° C. to 350° C., and annealing time of 15 seconds to 45 seconds.

[0079] In this embodiment, the second annealing process adopts a rapid thermal annealing furnace, and the process parameters of the second annealing process are: annealing temperature of 300° C. to 600° C., and time of 15 seconds to 45 seconds.

[0080] In this embodiment, after the first partial annealing process, the method further includes: removing the metal layer 2071 that has not reacted with silicon by wet etching to prevent bridging and causing circuit short circuit.

[0081] The temperature of the first annealing process is lower than the temperature of the second annealing process. In the first annealing process, the annealing temperature is 200°C to 350°C. The metal layer 2071 will only react with the substrate 200 or the top of the gate structure 201 to form a high-resistance metal silicide layer. If the annealing temperature is outside the range of 200°C to 350°C, it will cause the metal layer 2071 to react incompletely or over-react with the substrate 200 or the top of the gate structure 201.

[0082] In the second annealing process, the annealing temperature is 300°C to 600°C, which converts the high-resistance metal silicide layer into a low-resistance metal silicide layer. If the annealing temperature is outside the range of 300°C to 600°C, the high-resistance metal silicide layer will not be completely converted into a low-resistance metal silicide layer.

[0083] In the above scheme, two annealing processes are used to form the metal silicide layer 207, avoiding the problem of short circuit caused by generating a low-resistance metal silicide layer through only one annealing process. Specifically, the process temperature under the one annealing process will be very high. In such a high-temperature environment, silicon can diffuse along the grain boundaries of the metal silicide layer 207, resulting in excessive growth of the metal silicide layer 207 above the silicon oxide boundary, and subsequent wet etching cannot remove the metal silicide layer 207 on the oxide, causing a short circuit.

[0084] In this embodiment, the material of the metal silicide layer 207 is NiSi containing Pt.

[0085] In this embodiment, after the metal silicide layer 207 is formed, the silicon oxide layer 2051 and the silicon nitride layer 2052 are removed.

[0086] Please refer to Figure 13 , forming an etch stop layer 208 on the metal silicide layer 207 .

[0087] In this embodiment, the process of forming the etch stop layer 208 is: chemical vapor deposition process or physical vapor deposition process.

[0088] In this embodiment, the material of the etch stop layer 208 is silicon oxide or silicon nitride.

[0089] In this embodiment, the thickness of the etch stop layer 208 ranges from 250 angstroms to 450 angstroms.

[0090] Please refer to Figure 14 , a dielectric layer 2081 is formed on the etch stop layer 208 , and the dielectric layer 2081 covers the gate structure 201 and the source / drain region III.

[0091] Please refer to Figure 15 , a third photoresist layer 210 is formed on the dielectric layer 2081 .

[0092] In this embodiment, an anti-reflection layer 209 is further included between the third photoresist layer 210 and the dielectric layer 2081. The anti-reflection coating 209 includes: a protective layer 2091 located on the dielectric layer 2081, a first anti-reflection layer 2092 located on the protective layer 2091, and a second anti-reflection layer 2093 located on the first anti-reflection layer 2092.

[0093] In this embodiment, the thickness of the first anti-reflection layer 2092 ranges from 15 nm to 50 nm, the thickness of the second anti-reflection layer 2093 ranges from 15 nm to 50 nm, and the thickness of the protective layer 2091 ranges from 40 nm to 200 nm.

[0094] The first anti-reflective layer 2092, the second anti-reflective layer 2093 and the protective layer 2091 are used to form a protective film during the photolithography process to prevent chemical substances from corroding the bottom layer material and play a protective role. The anti-reflective layer can reduce the light reflected back from the photoresist layer during the exposure process, thereby improving the clarity and accuracy of the photolithography pattern. In addition, the protective layer 2091 can fill uneven surface defects and improve the flatness of the photoresist layer, which is beneficial to the accurate replication of the photolithography pattern.

[0095] Please refer to Figure 16 , performing exposure and development processing on the third photoresist layer 210, etching the dielectric layer 2081 using the third photoresist layer 210 as a mask to form a contact hole 211, wherein the contact hole 211 exposes the metal silicide layer 207 on the surface of the common source / drain region II.

[0096] In other embodiments, the contact hole 211 further exposes the surface of the source / drain region III and the metal silicide layer 207 on the gate structure 201 .

[0097] In this embodiment, the process of etching the dielectric layer 2081 is dry etching, and the process parameters of the dry etching include: the chamber pressure is 20mT to 100mT, the source power is 500W to 2800W, the bias power is 30W to 2800W, the gas flow rate is 20sccm to 200sccm, and the etching time is 8s to 20s.

[0098] In other embodiments, since metal oxide exists on the surface of the metal silicide layer 207, over-etching to the metal silicide layer 207 is required when etching the dielectric layer 2081, so that the oxide layer on the metal silicide layer 207 is etched away to expose the metal silicide.

[0099] Please refer to Figure 17 , a conductive material is filled into the contact hole 211 through a deposition process to form a conductive plug 2111.

[0100] In this embodiment, the conductive plug 2111 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0101] In this embodiment, the conductive plug 2111 is made of copper, aluminum or tungsten.

[0102] Please refer to Figure 17 The technical solution of the present invention also provides a semiconductor structure, including a semiconductor structure formed by the above-mentioned method for forming a semiconductor structure.

[0103] In summary, the technical solution of the present invention forms a silicon oxide layer and a silicon nitride layer located on the silicon oxide layer on the gate structure and the substrate, and the silicon oxide layer and the silicon nitride layer serve as a silicide self-aligned barrier layer. According to the silicide self-aligned barrier layer process, the silicon nitride layer is first etched by a dry etching process with a first etching selectivity ratio (2:1). At this time, the etching speed of the silicon nitride layer is faster to remove the silicon nitride layer; then the first etching selectivity ratio is adjusted to a dry etching process with a second etching selectivity ratio (5:1 to 7:1) to partially etch the silicon oxide layer. At this time, the etching speed of the silicon oxide layer is faster. The etching rate is slow to remove the possible residual silicon nitride layer and part of the silicon oxide layer; finally, the entire silicon oxide layer is wet-etched with a third etching selection ratio (3:1 to 6:1). At this time, the etching rate of the silicon oxide layer is greater than the etching rate of silicon nitride, so that the silicon oxide layer is completely removed and part of the sidewall is etched at the same time, thereby increasing the width between adjacent gate structures, and then adjusting the distance between adjacent gate structures, further increasing the contact area between the subsequently formed conductive plug and the substrate, reducing the contact resistance between the conductive plug and the substrate, and improving the performance of the semiconductor structure.

[0104] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active regions, the substrate of the plurality of active regions having at least two gate structures, and a common source / drain region between two adjacent gate structures; forming sidewalls on both sides of the gate structure, wherein the sidewalls are made of silicon oxide and silicon nitride; forming a silicon oxide layer on the substrate and the gate structure, and on the sidewalls; forming a silicon nitride layer on the silicon oxide layer; forming a photoresist layer having a metal silicide pattern on the silicon nitride layer; According to the silicide self-aligned barrier process, the photoresist layer is used as a mask, and an etching process with an etching selectivity ratio is adopted to etch the silicon nitride layer and the silicon oxide layer along the metal silicide pattern until the substrate and the top of the gate structure are exposed. While etching the silicon oxide layer and the silicon nitride layer, part of the silicon nitride in the side wall is also etched.

2. The method for forming a semiconductor structure according to claim 1, wherein: The steps of forming the sidewalls include: forming a spacer layer on the gate structure and the substrate; The sidewall spacer layer on the sidewall of the gate structure is etched until the thickness of the sidewall spacer layer in a direction perpendicular to the sidewall of the gate structure reaches a predetermined size, thereby forming the sidewall spacer.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for etching the sidewall layer on the sidewall of the gate structure is dry etching, and the process parameters of the dry etching are chamber pressure 3mt to 40mt, power supply power 0W to 400W, bias voltage 0V to 200V, and etching gas flow rate 50sccm to 500sccm.

4. The method for forming a semiconductor structure according to claim 2, wherein: The thickness of the sidewall spacer ranges from 25 nanometers to 35 nanometers.

5. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the silicon nitride layer and the silicon oxide layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: the deposition rate of the silicon nitride layer is 2000 angstroms to 3000 angstroms per minute, and the deposition time of the silicon nitride layer is 3 seconds to 10 seconds; the deposition rate of the silicon oxide layer is 400 angstroms to 600 angstroms per minute, and the deposition time of the silicon oxide layer is 10 seconds to 20 seconds; the thickness range of the silicon nitride layer is 200 angstroms to 300 angstroms, and the thickness range of the silicon oxide layer is 100 angstroms to 200 angstroms.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of etching the silicon nitride layer and the silicon oxide layer comprises: Etching the silicon nitride layer along the metal silicide pattern using a first sub-etching process until the silicon oxide layer is exposed; Etching a portion of the silicon oxide layer along the metal silicide pattern using a second partial etching process; The silicon oxide layer is etched along the metal silicide pattern using a third sub-etching process until the substrate and the top of the gate structure are exposed.

7. The method for forming a semiconductor structure according to claim 6, wherein: The first sub-etching process is a plasma dry etching process. The process parameters of the first sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100 V to 200 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 30 seconds to 45 seconds. The first sub-etching process has a first etching selectivity ratio of 2:1 for the silicon nitride layer and the silicon oxide layer.

8. The method for forming a semiconductor structure according to claim 6, wherein: The second sub-etching process is a plasma dry etching process. The process parameters of the second sub-etching process include: the etching gas is a combination of one or more of CH3F, O2 and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 150 V to 280 V, the etching pressure is 40 mTorr to 60 mTorr, and the etching time is 15 seconds to 25 seconds. The second sub-etching process has a second etching selectivity ratio of 5:1 to 7:1 for the silicon nitride layer and the silicon oxide layer.

9. The method for forming a semiconductor structure according to claim 6, wherein: The third sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of hydrofluoric acid solution, ammonia solution and water, the reaction temperature range is 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes. The second sub-etching process has a third etching selectivity ratio of 3:1 to 6:1 for the silicon oxide layer and the silicon nitride layer.

10. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 9.

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