A testing device and a turret type sorting machine

Abstract

The present invention relates to the field of semiconductor testing technology, and discloses a testing device and a turret sorting machine, the device comprising: a test seat and a testing machine; the test seat comprises a placement position for placing a chip to be tested and a double-layer chip testing piece; the testing machine comprises a first chip testing piece; the double-layer chip testing piece is used to connect the chip to be tested to the first chip testing piece, and the first chip testing piece is used to test the performance of the chip to be tested. The present invention realizes high temperature testing of the chip to be tested, a one-time contact test, and a functional test to check the contact of each high-current probe. When testing the chip, multiple contacts are not required, which prevents the chip surface from being damaged by multiple contacts, and solves the problem of damage to the chip surface caused by multiple contacts when testing the chip.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor testing, and in particular to a testing device and a turret type sorting machine. Background Art

[0002] Silicon carbide MOS (Metal-Oxide-Semiconductor) is the most widely used wide bandgap power device. With the large-scale commercialization of silicon carbide devices, KGD (Known Good Die) technology plays an important role in improving packaging yield and reducing production costs.

[0003] Currently, there are two main types of KGD test sorters on the market: turret type and translation type. The turret type sorter is characterized by high speed, but does not support high temperature testing. The translation type sorter is characterized by high temperature testing, but the speed is slow, which restricts the improvement of production capacity. Whether it is a turret type or a translation type sorter, during multi-station testing, the probe will contact the chip multiple times, which is easy to cause damage to the chip surface.

[0004] In addition, the short-circuit test current of KGD can reach more than 2000A. During the test, the source of the device under test (DUT) is usually contacted by multiple probes. When some probes have poor contact, most of the current will pass through the probes with good contact, and the local current density will be too large, damaging the chip device and the probes. Summary of the invention

[0005] In view of this, the present invention provides a testing device and a turret sorting machine to solve the problem of damage to the chip surface caused by multiple contacts during chip testing.

[0006] In a first aspect, the present invention provides a chip testing device, the device comprising: a test seat and a test machine; the test seat comprises a placement position for placing a chip to be tested and a double-layer chip test sheet; the test machine comprises a first chip test sheet;

[0007] The double-layer chip test piece is used to connect the tested chip to the first chip test piece, and the first chip test piece is used to test the performance of the tested chip.

[0008] The chip testing device provided by the present invention has a double-layer chip testing piece used to connect the tested chip to a first chip testing piece, and the first chip testing piece is used to test the performance of the tested chip. It can realize high-temperature testing of the tested chip, one-time contact testing, and functional testing of checking each high-current probe contact. When testing the chip, there is no need for multiple contacts, which prevents the chip surface from being damaged by multiple contacts, thus solving the problem of damage to the chip surface caused by multiple contacts when testing the chip.

[0009] In an optional embodiment, the chip under test includes a gate, a source and a drain; the test seat includes an upper test seat and a lower test seat, and the double-layer chip test piece includes a second chip test piece and a third chip test piece;

[0010] The upper test seat and the lower test seat are combined into one by a fixture;

[0011] The second chip test piece is arranged on the upper test seat;

[0012] The third chip test piece is arranged on the lower test seat; the gate and source of the tested chip are connected to the first chip test piece through the second chip test piece and the third chip test piece in turn; the drain of the tested chip is connected to the first chip test piece through the third chip test piece.

[0013] The chip testing device provided by the present invention is a device in which an upper test seat and a lower test seat are combined into one by a clamp, so that the chip under test is fixed on the lower test seat, achieving a single contact of the chip under test during the test process, preventing damage to the chip surface caused by multiple contacts, reducing the probability of damage to the chip under test, and improving chip production capacity. The second chip test piece is set on the upper test seat; the third chip test piece is set on the lower test seat; the gate and source of the chip under test are connected to the first chip test piece through the second chip test piece and the third chip test piece in turn; the drain of the chip under test is connected to the first chip test piece through the third chip test piece, providing connection conditions for subsequent testing machines to test the performance of the chip under test.

[0014] In an optional embodiment, the upper test seat further includes a first heat insulation material layer; the second chip test piece includes a second gate test piece and a second source test piece;

[0015] The second gate test piece is disposed in the first heat insulation material layer, the first end of the second gate test piece is connected to the gate of the tested chip in the placement position, and the second end of the second gate test piece is connected to the first end of the third chip test piece;

[0016] The second source test piece is arranged in the first thermal insulation material layer, and the second source test piece includes multiple second sub-test pieces or second sub-test needles. The first end of each second sub-test piece or second sub-test needle is connected to the source of the tested chip in the placement position, and the second end of each second sub-test piece or second sub-test needle is connected to the first end of the third chip test piece.

[0017] The chip testing device provided by the present invention comprises a second gate test piece arranged in a first thermal insulation material layer and a second source test piece arranged in the first thermal insulation material layer, thereby ensuring that the second gate test piece and the second source test piece are in a thermal insulation environment at a required temperature, providing conditions for high temperature testing of the chip under test, wherein the first end of the second gate test piece is connected to the gate of the chip under test in the placement position, the second end of the second gate test piece is connected to the first end of the third chip test piece, the second source test piece comprises a plurality of second sub-test pieces or second sub-test needles, the first end of each second sub-test piece or second sub-test needle is connected to the source of the chip under test in the placement position, and the second end of each second sub-test piece or second sub-test needle is connected to the first end of the third chip test piece, thereby realizing the connection between the chip under test and the corresponding test pieces of the upper test seat and the lower test seat respectively, providing conditions for subsequent performance testing of the chip under test.

[0018] In an optional embodiment, the lower test seat further includes a second thermal insulation material layer, an upper surface and a lower surface, and the third chip test piece includes a third gate test piece, a third source test piece and a second drain test piece; the placement position is set in the second thermal insulation material layer;

[0019] The third grid test piece is arranged in the second heat insulation material layer, the first end of the third grid test piece is connected to the second end of the second grid test piece, and the second end of the third grid test piece is connected to the test machine;

[0020] The second drain test piece is arranged in the second heat insulation material layer, the first end of the second drain test piece is connected to the drain of the tested chip in the placement position, and the second end of the second drain test piece is connected to the test machine;

[0021] The third source test piece is arranged in the second thermal insulation material layer, and the third source test piece includes multiple third sub-test pieces or third sub-test needles. The first end of each third sub-test piece or third sub-test needle corresponds to the second end of the second sub-test piece or second sub-test needle connected to the second source test piece, and the second end of each third sub-test piece or third sub-test needle is connected to the testing machine.

[0022] The chip testing device provided by the present invention, the third gate test piece, the second drain test piece and the third source test piece, and the placement position are all arranged in the second thermal insulation material layer, ensuring that the third gate test piece, the second drain test piece and the third source test piece, and the placement position are all in a thermal insulation environment of the required temperature, providing conditions for high-temperature testing of the tested chip, and connecting the tested chip to the test machine through the third gate test piece, the second drain test piece and the third source test piece, providing connection conditions for subsequent performance testing of the tested chip by the test machine.

[0023] In an optional embodiment, the lower test seat further includes a one-way nitrogen input interface, a vacuum suction hole, a nitrogen pressure detection hole, a temperature control circuit and a microcontroller circuit;

[0024] The one-way nitrogen input interface vertically penetrates the second thermal insulation material layer, and the one-way nitrogen input interface is used to fill nitrogen into the lower test seat;

[0025] The vacuum suction hole is arranged in the second heat insulation material layer, and the vacuum suction hole is used to fix the tested chip on the lower test seat by vacuum adsorption;

[0026] The nitrogen pressure detection hole vertically penetrates the second heat insulation material layer; the nitrogen pressure detection hole is used to detect the nitrogen pressure of the lower test seat;

[0027] The temperature control circuit is arranged in the second heat insulation material layer, and the temperature control circuit is used to adjust the temperature of the tested chip in the placement position during the test process;

[0028] The microcontroller circuit is connected to the temperature control circuit and is used to control the temperature control circuit to adjust the temperature of the test seat.

[0029] The chip testing device provided by the present invention has a one-way nitrogen input interface that vertically penetrates the second thermal insulation material layer, and the one-way nitrogen input interface is used to fill nitrogen into the lower test seat, so that the electrical insulation of the tested chip is enhanced, oxidation is avoided, humidity is controlled, and impurities are eliminated; the vacuum suction hole is arranged in the second thermal insulation material layer, and the vacuum suction hole is used to fix the tested chip on the lower test seat by vacuum adsorption, thereby achieving the purpose of fixing the placement position on the lower test seat through the vacuum suction hole, and providing conditions for subsequent performance testing of the tested chip; the nitrogen pressure detection hole vertically penetrates the second thermal insulation material layer; the nitrogen pressure detection hole is used to detect the nitrogen pressure of the lower test seat, thereby achieving the purpose of detecting the nitrogen pressure of the lower test seat; the microcontroller circuit is connected to the temperature control circuit, which is used to control the temperature control circuit to adjust the temperature of the lower test seat, and provides conditions for high-temperature testing of the tested chip.

[0030] In an optional embodiment, the first chip test piece includes a first gate test piece, a first source test piece and a first drain test piece;

[0031] The first grid test piece is disposed on the upper surface of the tester and connected to the second end of the third grid test piece;

[0032] The first source test piece is arranged on the upper surface of the tester, the first source test piece comprises a plurality of first sub-test pieces or first sub-test needles, each of which is connected to the second end of the third sub-test piece or the third sub-test needle;

[0033] The first drain test piece is arranged on the upper surface of the test machine and is connected to the second end of the second drain test piece.

[0034] The chip testing device provided by the present invention connects the second chip testing piece and the third chip testing piece through the first gate testing piece, the first source testing piece and the first drain testing piece, thereby indirectly achieving the purpose of connecting the tested chip to the testing machine without adding other equipment, reducing the cost of the testing device, and providing connection conditions for the subsequent testing machine to perform performance testing on the tested chip.

[0035] In an optional embodiment, the temperature control circuit includes a heating tube, a first cooling plate and a temperature sensor arranged at the bottom of the placement position;

[0036] The heating tube is used to heat the placement position to a preset temperature;

[0037] The first cooling plate is used to cool the heated placement position to the ambient temperature;

[0038] The temperature sensor is used to detect the temperature of the placement location.

[0039] The chip testing device provided by the present invention comprises a heating tube for heating the placement position to a preset temperature; a first cooling plate for cooling the heated placement position to the ambient temperature; and a temperature sensor for detecting the temperature of the placement position, thereby providing a reliable temperature environment for the performance test of the chip being tested and providing conditions for the high-temperature test of the chip being tested.

[0040] In an optional embodiment, the microcontroller circuit includes a power interface, a super capacitor, a microcontroller, a voltage detection module, a constant current source, a thermistor, a heating tube driver and a cooling plate driver;

[0041] The power interface is used to charge the supercapacitor and to power the microcontroller circuit and the temperature control circuit;

[0042] The supercapacitor is used to supply power to the microcontroller circuit and the temperature control circuit when the power interface is working offline;

[0043] The microcontroller is used to detect the temperature of the lower test seat and perform thermal insulation control;

[0044] The voltage detection module detects the voltage of the thermistor and feeds it back to the microcontroller;

[0045] The constant current source provides a constant current to the thermistor;

[0046] The thermistor is connected to the placement location, and the thermistor is used to detect the temperature of the placement location;

[0047] The heating tube driver is used to drive the heating tube of the temperature control circuit to heat;

[0048] The cooling plate drives the first cooling plate used to drive the temperature control circuit to perform cooling.

[0049] The chip testing device provided by the present invention realizes the purposes of powering the testing device, temperature control, voltage detection of thermistor, driving the heating tube for heating, and driving the cooling plate for cooling through the power interface of the microcontroller circuit, supercapacitor, microcontroller, voltage detection module, constant current source, thermistor, heating tube drive, and cooling plate drive, thereby providing auxiliary conditions for the performance of the tested chip and enabling the tested chip to achieve better performance testing.

[0050] In an optional embodiment, the testing machine further includes a nitrogen output interface, a second cooling plate and a pressure sensor;

[0051] The nitrogen output interface is used to fill the test socket with nitrogen when testing the performance of the chip to be tested;

[0052] The second cooling fin is connected to the first cooling fin and is used to transfer the heat generated by the first cooling fin during cooling to the testing machine;

[0053] The air pressure sensor is connected to the nitrogen pressure detection hole and is used to detect the nitrogen pressure inside the lower test seat.

[0054] The chip testing device provided by the present invention has a nitrogen output interface for filling nitrogen into a test seat when testing the performance of the chip to be tested; an air pressure sensor is connected to the nitrogen pressure detection hole for detecting the nitrogen pressure inside the test seat, so as to provide an oxygen-free environment for the test machine when testing to avoid oxidation of the chip to be tested; a second cooling plate is connected to the first cooling plate for transferring heat generated by the first cooling plate during cooling to the test machine, which is beneficial to the heat dissipation of the test seat and achieves the purpose of rapid cooling.

[0055] In a second aspect, the present invention provides a turret sorting machine, comprising a chip under test input station, a manipulator, a test station, a temperature setting station, a chip under test output station, a test device according to the first aspect or any corresponding embodiment thereof, and a conveyor belt; the chip under test input station is used to place the chip under test into a placement position of the test device through the manipulator, and fix the placement position on the lower test seat of the test device through the vacuum adsorption hole of the test device;

[0056] The test station is used to perform performance tests on the test device on which the chip to be tested is placed;

[0057] The temperature setting station is used to provide a power supply interface for the temperature control circuit of the test device so that multiple test devices can be heated simultaneously;

[0058] The chip output station is used to take out the chip that has completed the performance test from the test device through a robot;

[0059] The conveyor belt is used to transport the test device without the tested chip to the tested chip input station for the next test.

[0060] The turret sorting machine provided by the present invention cooperates with the test device to realize performance testing of the tested chips in batches, improves the test efficiency, realizes high-temperature testing of the tested chips, one-contact testing and functional testing of checking the contact of each high-current probe, and does not require multiple contacts when testing the chip, thereby preventing the chip surface from being damaged by multiple contacts, thus solving the problem of chip surface damage caused by multiple contacts when testing the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 is a schematic structural diagram of a chip testing device according to an embodiment of the present invention;

[0063] Figure 2 is a schematic structural diagram of another chip testing device according to an embodiment of the present invention;

[0064] Figure 3 is a schematic structural diagram of another chip testing device according to an embodiment of the present invention;

[0065] Figure 4 is a schematic structural diagram of a microcontroller circuit in a chip testing device according to an embodiment of the present invention;

[0066] Figure 5 It is a schematic structural diagram of a turret type sorting machine according to an embodiment of the present invention. DETAILED DESCRIPTION

[0067] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0068] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0069] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0070] In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0071] In this embodiment, a chip testing device is provided. Figure 1 is a structural diagram of a chip testing device according to an embodiment of the present invention, such as Figure 1 As shown, the device includes: a test socket 105 and a test machine 101; the test socket includes a placement position 4 for placing a tested chip 33 and a double-layer chip test piece 104; the test machine 101 includes a first chip test piece 34; a temperature control circuit 9 is connected to the placement position 4, and is used to adjust the temperature of the placement position during the test process; the double-layer chip test piece is used to connect the tested chip to the first chip test piece, and the first chip test piece is used to test the performance of the tested chip.

[0072] Specifically, the chip under test may be a bare wafer chip.

[0073] Before the test, the chip under test is placed in the placement position and connected to the first chip test piece. During the test, the chip under test is not moved, and the multiple contacts with the chip under test are not repeated. The performance of the chip under test is tested using the first chip test piece. The performance of the chip under test includes high temperature performance, AC parameter performance, and DC parameter performance, etc., which are tested according to actual conditions and are not specifically limited here.

[0074] The chip testing device provided by the present invention has a double-layer chip testing piece used to connect the tested chip to a first chip testing piece, and the first chip testing piece tests the performance of the tested chip, thereby realizing high-temperature testing of the tested chip and a one-contact test. When testing the chip, there is no need for multiple contacts, thus preventing damage to the chip surface caused by multiple contacts, and solving the problem of damage to the chip surface caused by multiple contacts when testing the chip.

[0075] In an optional embodiment, if Figure 2 As shown, the chip under test includes a gate, a source and a drain and corresponding gate pins 30, source pins 31 and drain pins 32. The test seat includes an upper test seat 102 and a lower test seat 103, and the double-layer chip test piece 104 includes a second chip test piece and a third chip test piece; the upper test seat and the lower test seat are combined into one by a fixture; the second chip test piece is arranged on the upper test seat; the third chip test piece is arranged on the lower test seat; the gate and source of the chip under test are connected to the first chip test piece through the second chip test piece and the third chip test piece in turn; the drain of the chip under test is connected to the first chip test piece through the third chip test piece.

[0076] In an optional embodiment, if Figure 3 As shown, the upper test seat 102 also includes a first thermal insulation material layer 3, and the second chip test piece includes a second gate test piece 1 and a second source test piece 2; the second gate test piece is arranged in the first thermal insulation material layer, the first end of the second gate test piece is connected to the gate of the tested chip in the placement position, and the second end of the second gate test piece is connected to the first end of the third chip test piece. In this embodiment, the first end of the second gate test piece contacts the gate of the tested chip in the placement position, and the second end extends to the bottom of the upper test seat for connecting to the first end of the third chip test piece of the lower test seat. The second source test piece is arranged in the first thermal insulation material layer, and the second source test piece includes a plurality of second sub-test pieces or second sub-test needles, the first end of each second sub-test piece or second sub-test needle is connected to the source of the tested chip in the placement position, and the second end of each second sub-test piece or second sub-test needle is connected to the first end of the third chip test piece.

[0077] Specifically, the thickness of the first heat-insulating material layer is set to be more than 3mm, which is used to maintain the temperature of the second gate test piece and the second source test piece. The first end of each second sub-test piece or second sub-test needle contacts the source of the tested chip in the placement position, and the second end of each second sub-test piece or second sub-test needle extends to the bottom of the upper test seat to contact the first end of the third chip test piece. The two ends of any two second sub-test pieces or the two ends of any two second sub-test needles in the second source test piece are not arranged in parallel, that is, the distance between any two second sub-test pieces or any two second sub-test needles connecting one end of the source of the tested chip in the placement position is less than the distance between any two second sub-test pieces or any two second sub-test needles connecting one end of the third chip test piece. The distance between any two second sub-test pieces or any two second sub-test needles connecting one end of the source of the tested chip in the placement position can be set to within 0.5mm, and the distance between any two second sub-test pieces or any two second sub-test needles connecting the first end of the third chip test piece can be set to more than 1mm.

[0078] In an optional embodiment, if Figure 3 As shown, the lower test seat 103 also includes a second thermal insulation material layer, and the third chip test piece includes a third gate test piece 6, a third source test piece 10 and a second drain test piece 7; the placement position is set in the second thermal insulation material layer; the thickness of the second thermal insulation material layer is set to be more than 3mm. Figure 2 As shown, the lower test socket is also provided with a communication interface 35 for providing power and a communication interface for the microcontrol circuit and the temperature control circuit.

[0079] The third gate test piece 6 is arranged in the second thermal insulation material layer, the first end of the third gate test piece is connected to the second end of the second gate test piece, and the second end of the third gate test piece is connected to the testing machine; specifically, in this embodiment, the first end of the third gate test piece extends to the upper surface of the lower test seat, which is used to contact the second gate test piece of the upper test seat, and the second end of the third gate test piece extends to the lower surface of the lower test seat, which is used to contact the first gate test piece in the testing machine.

[0080] The second drain test piece 7 is arranged in the second thermal insulation material layer, the first end of the second drain test piece is connected to the drain of the tested chip in the placement position, and the second end of the second drain test piece is connected to the testing machine; specifically, in this embodiment, the first end of the second drain test piece extends to the upper surface of the lower test seat, which is used to contact the drain of the tested chip in the placement position, and the second end of the second drain test piece extends to the lower surface of the lower test seat, which is used to contact the first drain test piece in the testing machine.

[0081] The third source test piece 10 is arranged in the second heat insulation material layer, and the third source test piece includes a plurality of third sub-test pieces or third sub-test needles, and the first end of each third sub-test piece or third sub-test needle corresponds to the second end of the second sub-test piece or second sub-test needle connected to the second source test piece, and the second end of each third sub-test piece or third sub-test needle is connected to the test machine. Specifically, in this embodiment, the distance between any two third sub-test pieces or the distance between any two third sub-test needles is consistent with the distance between any two second sub-test pieces or the distance between the second ends of any two second sub-test needles.

[0082] like Figure 2 As shown, the gate pin of the third gate test piece 6 , the drain pin of the second drain test piece 7 and the source pin of the third source test piece 10 are also arranged on the upper surface of the lower test seat.

[0083] It should be noted that if Figure 3 As shown, the double-layer chip test piece 104 includes a second gate test piece 1, a second source test piece 2, a third gate test piece 6, a third source test piece 10 and a second drain test piece 7; the first end of the third chip test piece is the first end of the third gate test piece 6, the first end of the second drain test piece 7 or the first end of the third source test piece 10.

[0084] In an optional embodiment, if Figure 3 As shown, the lower test seat also includes a one-way nitrogen input interface 5, a vacuum suction hole 8, a nitrogen pressure detection hole 11, a temperature control circuit and a microcontroller circuit 12;

[0085] The one-way nitrogen input interface 5 vertically penetrates the second thermal insulation material layer, and is used to fill nitrogen into the lower test seat; specifically, the one-way nitrogen input interface 5 can be implemented by a one-way valve. The vacuum suction hole 8 is set in the second thermal insulation material layer, and is used to fix the tested chip on the lower test seat by vacuum adsorption.

[0086] The nitrogen pressure detection hole 11 penetrates the second thermal insulation material layer longitudinally; the nitrogen pressure detection hole is used to detect the nitrogen pressure of the lower test seat; specifically, one end of the nitrogen pressure detection hole 11 extends to the upper surface of the lower test seat, and the other end extends to the lower surface of the lower test seat, which is used to connect to the pressure detection interface of the testing machine.

[0087] The temperature control circuit is arranged in the second thermal insulation material layer. The temperature control circuit is used to adjust the temperature of the tested chip in the placement position during the test process, and supports heating, cooling and heat preservation. The temperature control circuit 9 includes a heating tube, a first cooling plate and a temperature sensor. Among them, the heating tube is arranged in the bottom area of ​​the placement position, and is used to heat the placement position to 175°C. The first cooling plate adopts a semiconductor cooling plate, and the first cooling plate is arranged in the bottom area of ​​the placement position 4, and is used to cool the heated placement position to the ambient temperature. The temperature sensor adopts a precision platinum metal temperature sensor, and the temperature sensor is arranged in the bottom area of ​​the placement position to detect the temperature of the placement position.

[0088] The microcontroller circuit 12 is connected to the temperature control circuit 9 and is used to control the temperature control circuit 9 to adjust the temperature of the test socket. Figure 4 As shown, the microcontroller circuit includes a power interface 14, a super capacitor 15, a microcontroller 16, a voltage detection module 17, a constant current source 18, a thermistor 19, a heating tube driver 20 and a cooling plate driver 21. The power interface 14 is used to charge the super capacitor and to supply power to the microcontroller circuit and the temperature control circuit. The super capacitor 15 is used to supply power to the microcontroller circuit and the temperature control circuit when the power interface is working offline. The microcontroller 16 is used to detect the temperature of the lower test seat and perform heat preservation control; the voltage detection module 17 is used to detect the voltage of the thermistor and feed it back to the microcontroller 16; the constant current source 18 provides a constant current to the thermistor 19; the thermistor 19 is connected to the placement position 4, and the thermistor 19 is used to detect the temperature of the placement position 4; the heating tube driver 20 is used to drive the heating tube of the temperature control circuit 9 for heating; the cooling plate driver 21 is used to drive the first cooling plate of the temperature control circuit 9 for cooling.

[0089] In an optional embodiment, if Figure 3 As shown, the first chip test piece includes a first gate test piece 26, a first source test piece 28 and a first drain test piece 27;

[0090] The first gate test piece 26 is arranged on the upper surface of the test machine and connected to the second end of the third gate test piece; the first source test piece 28 is arranged on the upper surface of the test machine, and the first source test piece includes multiple first sub-test pieces or first sub-test needles, and each first sub-test piece or first sub-test needle corresponds to the second end of the third sub-test piece or the third sub-test needle; the first drain test piece 27 is arranged on the upper surface of the test machine and connected to the second end of the second drain test piece.

[0091] Specifically, during testing, the first gate test piece 26 is connected to the second gate test piece through the third gate test piece 6, and then connected to the source of the placement position, and finally the purpose of connecting the first gate test piece 26 to the gate of the chip under test is achieved.

[0092] The first source test piece 28 is connected to the second source test piece through the third source test piece 10, and further connected to the source of the tested chip in the placement position, and finally the purpose of connecting the first source test piece 28 to the source of the tested chip is achieved.

[0093] The first drain test piece 27 is connected to the drain of the placement position through the second drain test piece 7, and finally the purpose of connecting the first drain test piece 27 to the drain of the chip under test is achieved.

[0094] In an optional embodiment, if Figure 3 As shown, the test machine also includes a nitrogen output interface 22, a second cooling plate 23 and an air pressure sensor 25; the nitrogen output interface 22 is used to fill the test seat with nitrogen when testing the performance of the chip to be tested; the second cooling plate 23 is connected to the first cooling plate, and is used to transfer the heat generated by the first cooling plate when cooling to the test machine; the air pressure sensor 25 is connected to the nitrogen pressure detection hole 11, and is used to detect the nitrogen pressure inside the lower test seat. In order to detect and control the temperature of the test seat, another temperature control circuit 24 is also provided on the test machine, which is also used to drive the heating tube and the first cooling plate in the lower test seat. A voltage detection circuit 29 connected to the thermistor 19 is also provided on the test machine, which is used to detect the voltage of the thermistor.

[0095] The present invention also provides a turret type sorting machine, such as Figure 5 As shown, it includes a chip under test input station, a manipulator, a test station, a temperature setting station, a chip under test output station, the above Figures 1 to 3 The test device and conveyor belt shown; the tested chip input station is used to place the tested chip into the placement position of the test device through a manipulator, and fix the tested chip on the lower test seat of the test device through the vacuum adsorption hole of the test device; the test station is used to perform performance tests on the test device with the tested chip placed; the temperature setting station is used to provide a power supply interface for the temperature control circuit of the test device so that multiple test devices can be heated at the same time; the tested chip output station is used to take the chip that has completed the performance test out of the test device through a manipulator; the conveyor belt is used to transport the test device without the tested chip placed to the placement input station for the next test.

[0096] The operation process of the turret sorting machine is as follows:

[0097] (1) Run the input station of the chip under test: the robot places the chip under test into the lower test seat, opens the vacuum suction hole 8 under the drain of the placement position, and fixes the chip under test on the lower test seat. The upper test seat and the lower test seat are combined into one by a clamp. The tester performs a contact resistance test on each first source sub-test piece or first sub-test needle. After the test passes, the placement of the chip under test is completed.

[0098] (2) Operation temperature setting station: The test device containing the chip to be tested is transported to the temperature setting station, which is equipped with power supply interfaces for the heating tube and the first cooling plate in the temperature control circuit and a voltage measurement interface for the thermistor. The internal temperature of the test seat in the test device is set according to the program. This station is equipped with a waiting track, which can heat / cool multiple test devices at the same time.

[0099] (3) Run test station 1: The test device is transported to test station 1 by the manipulator to perform a DC / AC test in a high temperature environment. During this process, the high temperature inside the test device is controlled by the temperature control circuit 9.

[0100] (4) Run test station 2: The test device is transported to test station 2 by the manipulator to perform a DC / AC test in a high temperature environment. During this process, the high temperature inside the test device is controlled by the temperature control circuit 9.

[0101] (5) Run the temperature setting station again: The test device that has completed the high-temperature test is transferred to the temperature setting station through the manipulator to cool the test device. The station is equipped with a waiting track and can cool multiple test devices at the same time.

[0102] (6) Run test station three: The test device is transported to test station three by a robot arm to perform DC / AC testing under normal room temperature.

[0103] (7) Run test station four: The test device is transported to test station four by a robot arm to perform DC / AC testing under normal room temperature.

[0104] (8) Run the chip output station: The test device that has completed all tests is transported to the chip output station by the robot, the fixture of the test device is released, the upper test seat and the lower test seat are separated, the vacuum suction hole 8 under the drain of the chip under test is closed, and the chip in the placement position is taken out by the robot. The chips that have completed the test are visually inspected and then placed on the discharge tray.

[0105] (9) Run the conveyor belt: transport the test device without the chip to be tested to the placement input station to prepare for the next test.

[0106] The turret sorter provided in this embodiment has the characteristics of high speed, high temperature, one-time contact test, and checking the contact of each high-current probe. It has a more flexible temperature control mode. The turret sorter supports high and low temperature testing of the test device when in use. During the entire test process, the test probe only contacts the exposed wafer chip once. Compared with the traditional multi-station test, it can better avoid the problem of needle marks on the wafer surface caused by multiple contacts. At the same time, checking the contact of each high-current probe before the test can also avoid the problem of device and probe damage caused by uneven probe contact; it can reduce the cost of the test device, reduce the probability of damage to the wafer chip, and improve production capacity, paving the way for the popularization and application of silicon carbide SiC chips.

[0107] The further functional description of each of the above components is the same as that of the above corresponding embodiments and will not be repeated here.

[0108] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A chip testing device, characterized in that: The device comprises: a test seat and a test machine; the test seat comprises a placement position for placing a chip to be tested and a double-layer chip test sheet; the test machine comprises a first chip test sheet; The double-layer chip test sheet is used to connect the tested chip to the first chip test sheet, and the first chip test sheet is used to test the performance of the tested chip; The chip under test includes a gate, a source and a drain; the test seat includes an upper test seat and a lower test seat, and the double-layer chip test piece includes a second chip test piece and a third chip test piece; The upper test seat and the lower test seat are combined into one by a fixture; The second chip test piece is arranged on the upper test seat; The third chip test piece is arranged on the lower test seat; the gate and source of the tested chip are connected to the first chip test piece through the second chip test piece and the third chip test piece in sequence; the drain of the tested chip is connected to the first chip test piece through the third chip test piece; The upper test seat also includes a first heat insulation material layer; the second chip test piece includes a second gate test piece and a second source test piece; The second gate test piece is arranged in the first heat insulation material layer, the first end of the second gate test piece is connected to the gate of the tested chip in the placement position, and the second end of the second gate test piece is connected to the first end of the third chip test piece; The second source electrode test piece is arranged in the first heat insulation material layer, and the second source electrode test piece includes a plurality of second sub-test pieces or second sub-test needles, and the first end of each second sub-test piece or second sub-test needle is connected to the source electrode of the tested chip in the placement position, and the second end of each second sub-test piece or second sub-test needle is connected to the first end of the third chip test piece; The lower test seat further comprises a second thermal insulation material layer, the third chip test piece comprises a third gate test piece, a third source test piece and a second drain test piece; the placement position is arranged in the second thermal insulation material layer; The third grid test piece is arranged in the second heat insulation material layer, the first end of the third grid test piece is connected to the second end of the second grid test piece, and the second end of the third grid test piece is connected to the test machine; The second drain test piece is arranged in the second heat insulation material layer, the first end of the second drain test piece is connected to the drain of the tested chip in the placement position, and the second end of the second drain test piece is connected to the test machine; The third source test piece is arranged in the second thermal insulation material layer, and the third source test piece includes multiple third sub-test pieces or third sub-test needles. The first end of each third sub-test piece or third sub-test needle is correspondingly connected to the second sub-test piece or the second end of the second sub-test needle of the second source test piece, and the second end of each third sub-test piece or third sub-test needle is connected to the test machine.

2. The device according to claim 1, characterized in that The lower test seat also includes a one-way nitrogen input interface, a vacuum suction hole, a nitrogen pressure detection hole, a temperature control circuit and a microcontroller circuit; The one-way nitrogen input interface longitudinally penetrates the second heat insulation material layer, and the one-way nitrogen input interface is used to fill nitrogen into the lower test seat; The vacuum suction hole is arranged in the second heat insulation material layer, and the vacuum suction hole is used to fix the chip under test on the lower test seat by vacuum adsorption; The nitrogen pressure detection hole vertically penetrates the second heat insulation material layer; The nitrogen pressure detection hole is used to detect the nitrogen pressure of the lower test seat; The temperature control circuit is arranged in the second heat insulation material layer, and the temperature control circuit is used to adjust the temperature of the tested chip in the placement position during the test process; The microcontroller circuit is connected to the temperature control circuit and is used to control the temperature control circuit to adjust the temperature of the test socket.

3. The device according to claim 1, characterized in that The first chip test piece includes a first gate test piece, a first source test piece and a first drain test piece; The first gate test piece is disposed on the upper surface of the tester and connected to the second end of the third gate test piece; The first source test piece is arranged on the upper surface of the tester, and the first source test piece includes a plurality of first sub-test pieces or first sub-test needles, and each first sub-test piece or first sub-test needle is connected to the second end of the third sub-test piece or the third sub-test needle; The first drain test piece is disposed on the upper surface of the test machine and is connected to the second end of the second drain test piece.

4. The device according to claim 2, characterized in that The temperature control circuit includes a heating tube, a first cooling plate and a temperature sensor arranged at the bottom of the placement position; The heating tube is used to heat the placement position to a preset temperature; The first cooling sheet is used to cool the heated placement location to the ambient temperature; The temperature sensor is used to detect the temperature of the placement location.

5. The device according to claim 4, characterized in that The microcontroller circuit includes a power interface, a super capacitor, a microcontroller, a voltage detection module, a constant current source, a thermistor, a heating tube driver and a cooling plate driver; The power interface is used to charge the supercapacitor and to supply power to the microcontroller circuit and the temperature control circuit; The supercapacitor is used to supply power to the microcontroller circuit and the temperature control circuit when the power interface works offline; The microcontroller is used to detect the temperature of the lower test seat and perform heat preservation control; The voltage detection module detects the voltage of the thermistor and feeds back to the microcontroller; The constant current source provides a constant current to the thermistor; The thermistor is connected to the chip under test in the placement position, and the thermistor is used to detect the temperature of the chip under test in the placement position; The heating tube driver is used to drive the heating tube of the temperature control circuit to heat; The refrigeration plate drives the first refrigeration plate of the temperature control circuit to perform refrigeration.

6. The device according to claim 5, characterized in that The testing machine also includes a nitrogen output interface, a second cooling plate and a pressure sensor; The nitrogen output interface is used to fill the test seat with nitrogen when testing the performance of the chip to be tested; The second cooling fin is connected to the first cooling fin and is used to transfer the heat generated by the first cooling fin during cooling to the testing machine; The air pressure sensor is connected to the nitrogen pressure detection hole and is used to detect the nitrogen pressure inside the lower test seat.

7. A turret type sorting machine, characterized in that: The invention comprises a chip under test input station, a manipulator, a test station, a temperature setting station, a chip under test output station, a test device as claimed in any one of claims 1 to 6, and a conveyor belt; the chip under test input station is used to place the chip under test into the placement position of the test device through the manipulator, and fix the chip under test on the lower test seat of the test device through the vacuum adsorption hole of the test device; The test station is used to perform performance testing on a test device on which a chip to be tested is placed; The temperature setting station is used to provide a power supply interface for the temperature control circuit of the test device, so that multiple test devices can be heated simultaneously; The chip under test output station is used to take out the chip under test that has completed the performance test from the testing device through a robot; The conveyor belt is used to transport the test device without the tested chip to the tested chip input station for the next test.

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