Semiconductor packaging structure

Abstract

The present invention provides a semiconductor packaging structure, wherein the semiconductor packaging structure comprises: a packaging shell, comprising a substrate and a panel connected to the substrate; a semiconductor chip connected to the substrate; a first terminal connected to a first side of the semiconductor chip; a second terminal connected to a second side of the semiconductor chip; an insulating reinforcement portion connected to the panel, the insulating reinforcement portion comprising a first insulating reinforcement rib and a second insulating reinforcement rib, the first insulating reinforcement rib being arranged between the first terminal and the second terminal, the two ends of the second insulating reinforcement rib being respectively connected to two opposite inner surfaces of the panel, the first insulating reinforcement rib and the second insulating reinforcement rib being intersected and connected. The technical solution of the present application can effectively solve the problem that it is difficult to take both the insulation performance and the structural strength of the housing into account in the related art.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] With the continuous development of science and technology, the application scope of semiconductor devices is becoming wider and wider. For example, semiconductor devices can be used as rectifiers, oscillators, light emitters, amplifiers or photometers in the fields of radio frequency, microwave and optical semiconductor products.

[0003] In this field, a power semiconductor device generally includes a housing, a substrate and a power semiconductor chip (such as a silicon carbide chip); the housing and the substrate form a mounting cavity, and the power semiconductor chip is disposed in the mounting cavity. The power semiconductor chip generally includes a source and a drain. When the power semiconductor device is working, there is a large voltage difference between the source and the drain, which requires higher requirements on the insulation performance of the housing and the substrate. Generally speaking, some grooves are provided on the housing to increase the surface distance between the source and the drain or between the source terminal and the drain terminal, thereby enhancing the insulation performance of the housing. However, this will more or less have a certain adverse effect on the structural strength of the housing. Summary of the invention

[0004] The main purpose of the present invention is to provide a semiconductor packaging structure to solve the problem in the related art that it is difficult to balance the insulation performance and structural strength of the shell.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a semiconductor packaging structure, including: a packaging shell, including a substrate and a surrounding plate connected to the substrate; a semiconductor chip, connected to the substrate; a first terminal, connected to the first side of the semiconductor chip; a second terminal, connected to the second side of the semiconductor chip; an insulating reinforcement portion, connected to the surrounding plate, the insulating reinforcement portion including a first insulating reinforcement rib and a second insulating reinforcement rib, the first insulating reinforcement rib is arranged between the first terminal and the second terminal, two ends of the second insulating reinforcement rib are respectively connected to two opposite inner surfaces of the surrounding plate, and the first insulating reinforcement rib and the second insulating reinforcement rib intersect and are connected.

[0006] Furthermore, the enclosure is a rectangular frame structure, the first end of the first insulating reinforcement rib is connected to the enclosure, and the second end of the first insulating reinforcement rib is connected to the middle of the second insulating reinforcement rib.

[0007] Furthermore, the semiconductor packaging structure also includes an insulating colloid layer, the insulating colloid layer is connected to the substrate, and the semiconductor chip is located in the insulating colloid layer.

[0008] Furthermore, a mounting seat is arranged between the second insulating reinforcement rib and the inner surface of the enclosure, and the packaging shell also includes a cover plate, which is provided with a mounting hole, and the cover plate is connected to the mounting seat via a fastener penetrating the mounting seat and the mounting hole.

[0009] Furthermore, the semiconductor packaging structure also includes a first metal plate, which is connected between the substrate and the semiconductor chip, the first metal plate is electrically connected to the drain of the semiconductor chip, and the first terminal is electrically connected to the first metal plate.

[0010] Furthermore, the semiconductor packaging structure also includes a second metal plate and an insulating bump arranged on the substrate, the second metal plate is electrically connected to the source of the semiconductor chip, the second terminal is electrically connected to the second metal plate, the second metal plate is spaced apart from the first metal plate, and the insulating bump is arranged between the first metal plate and the second metal plate.

[0011] Furthermore, the semiconductor packaging structure also includes a third terminal and a third metal plate arranged on the substrate, the third metal plate is electrically connected to the gate of the semiconductor chip, the third terminal is electrically connected to the third metal plate, and the third metal plate and the second metal plate are located on the same side of the insulating bump.

[0012] Furthermore, the semiconductor packaging structure also includes a bonding wire, which is connected between the second metal plate and the source electrode of the semiconductor chip, and at least a portion of the bonding wire is located above the insulating bump.

[0013] Furthermore, the semiconductor packaging structure also includes a conductive plate, which is connected between the second metal plate and the source electrode of the semiconductor chip, and penetrates the insulating bump and is located in the insulating colloid layer.

[0014] Furthermore, the width of the insulating bump is greater than 0 and less than or equal to 2 mm; and / or the height of the insulating bump is greater than 0 and less than or equal to 3 mm.

[0015] Further, the insulating colloid layer is made of silicone rubber; and / or the packaging shell and the insulating reinforcement part are both made of ceramics.

[0016] Furthermore, a first through hole is arranged on the enclosure, and the first terminal includes a first plate segment and a second plate segment arranged at an angle, the first end of the first plate segment is electrically connected to the drain of the semiconductor chip, the second end of the first plate segment is connected to the first end of the second plate segment, the second end of the second plate segment passes through the first through hole, and the first plate segment is shielded at the first through hole.

[0017] Furthermore, there is a gap between the insulation reinforcement part and the semiconductor chip, the surface of the insulation reinforcement part facing the substrate is arranged away from the substrate relative to the second plate segment, and the surface of the insulation reinforcement part facing the substrate is located in the insulation colloid layer.

[0018] Furthermore, the semiconductor packaging structure also includes a cover plate connected to the enclosure plate, a gap is provided between the insulation reinforcement portion and the semiconductor chip, and a surface of the insulation colloid layer facing the cover plate is spaced apart from the cover plate.

[0019] Furthermore, the semiconductor package structure further includes a first insulating enclosure, which is arranged on the outer surface of the enclosure and surrounds the outer periphery of the second plate segment.

[0020] By applying the technical solution of the present invention, the packaging shell provides an installation basis for various components of the semiconductor packaging structure, wherein the packaging shell includes a substrate and a surrounding plate connected to the substrate; the arrangement of the semiconductor chip can realize the basic functions of the semiconductor packaging structure, the semiconductor chip is connected to the substrate, the semiconductor chip has a drain and a source and is respectively located on both sides of the semiconductor chip, the first terminal is connected to the first side of the semiconductor chip; the second terminal is connected to the second side of the semiconductor chip, the first terminal and the second terminal enable the drain and source of the semiconductor chip to be electrically connected to the outside world; the insulating reinforcement part is connected to the surrounding plate, the insulating reinforcement part includes a first insulating reinforcement rib and a second insulating reinforcement rib, the first insulating reinforcement rib is arranged between the first terminal and the second terminal, specifically, the first insulating reinforcement rib is arranged between the first terminal and the packaging shell The inner part of the second terminal and the part of the second terminal in the packaging shell make the surface distance between the first terminal and the second terminal include the outer surface of the first insulating reinforcement rib in addition to the inner surface of the packaging shell, so that the surface distance between the first terminal and the second terminal can be effectively enhanced, thereby enhancing the insulation performance of the packaging shell, and will not have an adverse effect on the structural strength of the packaging shell; in addition, the two ends of the second insulating reinforcement rib are respectively connected to the two opposite inner surfaces of the enclosure, and the second insulating reinforcement rib can also enhance the structural strength of the packaging shell. The setting of the insulating reinforcement part makes the packaging shell have both good insulating performance and good structural strength. The first insulating reinforcement rib and the second insulating reinforcement rib intersect and are connected, so that the first insulating reinforcement rib and the second insulating reinforcement rib also have good structural strength. Therefore, the technical solution of the present application can effectively solve the problem that it is difficult to take both the insulation performance and the structural strength of the shell into account in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0022] Figure 1 A schematic diagram of a three-dimensional structure of an embodiment of a semiconductor packaging structure according to the present invention is shown;

[0023] Figure 2 Shows Figure 1 A schematic top view of a semiconductor package structure;

[0024] Figure 3 Shows Figure 1 A schematic side view of a semiconductor package structure;

[0025] Figure 4 Shows Figure 1 A schematic front view of a semiconductor package structure;

[0026] Figure 5 Shows Figure 1 A schematic diagram of the split structure of a semiconductor packaging structure;

[0027] Figure 6 Shows Figure 5 A schematic three-dimensional structural diagram of a first terminal of a semiconductor package structure;

[0028] Figure 7 Shows Figure 5 A schematic diagram of a three-dimensional structure of a substrate, a first metal plate, a second metal plate and a third metal plate of a semiconductor packaging structure;

[0029] Figure 8 Shows Figure 1 A three-dimensional structural schematic diagram of a partial structure of a semiconductor packaging structure;

[0030] Fig. 9 Shows Figure 8 A schematic top view of a semiconductor package structure;

[0031] Fig.10 Shows Figure 8 A side view schematic diagram of a semiconductor package structure.

[0032] The above drawings include the following reference numerals:

[0033] 10. Encapsulation shell; 11. Cover plate; 111. Mounting hole; 12. Base plate; 13. Enclosure plate; 131. First plate body; 132. Second plate body; 133. Third plate body; 1331. First through hole; 1332. Second through hole; 134. Mounting seat; 14. Mounting cavity;

[0034] 20. Semiconductor chips;

[0035] 30. first terminal; 31. first plate segment; 32. second plate segment;

[0036] 40. Second terminal;

[0037] 50. Insulation reinforcement portion; 51. First insulation reinforcement rib; 52. Second insulation reinforcement rib;

[0038] 60. Fasteners;

[0039] 71. a first metal plate; 72. a second metal plate; 73. a third metal plate;

[0040] 82. bonding wire; 83. first insulating enclosure; 84. second insulating enclosure;

[0041] 90. The third terminal. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0044] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0045] like Figure 2 , Figure 3 as well as Fig. 9As shown, the present application provides a semiconductor packaging structure. An embodiment of the semiconductor packaging structure of the present application includes: a packaging shell 10, a semiconductor chip 20, a first terminal 30, a second terminal 40, and an insulating reinforcement part 50; the packaging shell 10 includes a substrate 12 and a surrounding plate 13 connected to the substrate 12; the semiconductor chip 20 is connected to the substrate 12; the first terminal 30 is connected to the first side of the semiconductor chip 20; the second terminal 40 is connected to the second side of the semiconductor chip 20; the insulating reinforcement part 50 is connected to the surrounding plate 13, and the insulating reinforcement part 50 includes a first insulating reinforcement rib 51 and a second insulating reinforcement rib 52, the first insulating reinforcement rib 51 is arranged between the first terminal 30 and the second terminal 40, and the two ends of the second insulating reinforcement rib 52 are respectively connected to the two opposite inner surfaces of the surrounding plate 13, and the first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 intersect and are connected.

[0046] By applying the technical solution of this embodiment, the packaging shell 10 provides an installation basis for various components of the semiconductor packaging structure, wherein the packaging shell 10 includes a substrate 12 and a surrounding plate 13 connected to the substrate 12; the arrangement of the semiconductor chip 20 can realize the basic functions of the semiconductor packaging structure, the semiconductor chip 20 is connected to the substrate 12, the semiconductor chip 20 has a drain and a source and is respectively located on both sides of the semiconductor chip 20, the first terminal 30 is connected to the first side of the semiconductor chip 20; the second terminal 40 is connected to the second side of the semiconductor chip 20, the first terminal 30 and the second terminal 40 enable the drain and source of the semiconductor chip 20 to be electrically connected to the outside world; the insulating reinforcement part 50 is connected to the surrounding plate 13, the insulating reinforcement part 50 includes a first insulating reinforcement rib 51 and a second insulating reinforcement rib 52, the first insulating reinforcement rib 51 is arranged between the first terminal 30 and the second terminal 40, specifically, the first insulating reinforcement rib 51 is arranged at the first end The portion of the first terminal 30 in the package shell 10 and the portion of the second terminal 40 in the package shell 10 make the surface distance between the first terminal 30 and the second terminal 40 include the portion of the outer surface of the first insulating reinforcement rib 51 in addition to the inner surface of the package shell 10, so that the surface distance between the first terminal 30 and the second terminal 40 can be effectively enhanced, thereby enhancing the insulation performance of the package shell 10, and will not cause adverse effects on the structural strength of the package shell 10; in addition, the two ends of the second insulating reinforcement rib 52 are respectively connected to the two opposite inner surfaces of the enclosure 13, and the second insulating reinforcement rib 52 can also enhance the structural strength of the package shell 10. The setting of the insulating reinforcement part 50 makes the package shell 10 have both good insulation performance and good structural strength. The first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 intersect and are connected, so that the first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 also have good structural strength. Therefore, the technical solution of this embodiment can effectively solve the problem that it is difficult to take both the insulation performance and the structural strength of the shell in the related art into consideration.

[0047] Specifically, in the present embodiment, the packaging shell 10 further includes a cover plate 11, and a mounting cavity 14 is formed between the cover plate 11, the substrate 12, and the surrounding plate 13; the first end of the first terminal 30 is electrically connected to the drain of the semiconductor chip 20, and the second end of the first terminal 30 extends through the packaging shell 10 to the outside of the mounting cavity 14; the first end of the second terminal 40 is electrically connected to the source of the semiconductor chip 20, and the second end of the second terminal 40 extends through the packaging shell 10 to the outside of the mounting cavity 14; the insulating reinforcement portion 50 is disposed between the semiconductor chip 20 and the cover plate 11, and the first insulating reinforcement rib 51 is disposed between a portion of the first terminal 30 in the mounting cavity 14 and a portion of the second terminal 40 in the mounting cavity 14.

[0048] It should be noted that "surface distance" refers to the shortest path along the surface of the insulating material between two conductive parts. "Surface distance" is mainly used to evaluate the insulation performance of the electrical gap at different voltage levels to ensure the safety of the semiconductor packaging structure during normal operation or failure. In this embodiment, the source of the semiconductor chip 20 is mainly used to provide current and form a current path together with the drain. In this embodiment, the semiconductor chip 20 is a power semiconductor chip.

[0049] In addition, in the present embodiment, the semiconductor packaging structure further includes an insulating colloid layer, which is arranged in the mounting cavity 14 and connected to the substrate 12, and the semiconductor chip 20 is located in the insulating colloid layer. Specifically, the mounting cavity 14 is also filled with insulating colloid to form an insulating colloid layer, and the semiconductor chip 20 is located in the insulating colloid layer to ensure the insulation performance of the semiconductor packaging structure. Preferably, the insulating colloid layer can be made of silicone rubber. Silicone rubber is used as the material for the insulating colloid layer to increase the operating temperature of the semiconductor packaging structure to 250°C. Compared with the insulating colloid layer made of traditional silicone gel (maximum tolerance of 230°C), the insulating colloid layer made of silicone rubber can easily withstand an operating temperature of 250°C. Silicone rubber is a polymer material with excellent performance, mainly composed of silicon atoms and oxygen atoms, and has high high temperature resistance and excellent insulation performance. Its advantages in high temperature resistance and insulation are mainly reflected in the following aspects: 1. High temperature resistance: It can be used for a long time in the temperature range of -60°C to +250°C, and can even withstand higher temperatures in a short time. This property enables silicone rubber to maintain its original physical and chemical properties in high temperature environments, is not prone to aging and deformation, and can work stably. 2. Insulation performance: Silicone rubber has a high resistivity and dielectric constant, which can effectively prevent the flow of current and ensure the safe operation of electrical equipment. At the same time, the insulation performance of silicone rubber is not affected by temperature changes, and it can maintain its good insulation performance even in high temperature environments. 3. Chemical resistance: Silicone rubber has good chemical resistance, can resist the erosion of chemicals such as acids, alkalis, and salts, and is not prone to corrosion and deterioration. This property enables silicone rubber to maintain its stable performance in harsh chemical environments and prolongs the service life of the material. In general, the advantages of silicone rubber in high temperature resistance and insulation are mainly reflected in its excellent high temperature resistance, good insulation performance and chemical resistance, which makes it widely used in electrical, aerospace and other fields.

[0050] like Figures 1 to 5 as well as Figures 8 to 10As shown, the enclosure 13 is a rectangular frame structure, and the enclosure 13 includes a first plate 131, a second plate 132, and a third plate 133. The first plate 131 and the second plate 132 are arranged opposite to each other, and the third plate 133 is connected between the first plate 131 and the second plate 132. The first end of the first insulating reinforcement rib 51 is connected to the third plate 133, the second end of the first insulating reinforcement rib 51 is connected to the middle of the second insulating reinforcement rib 52, and the two ends of the second insulating reinforcement rib 52 are respectively connected to the first plate 131 and the second plate 132. Specifically, in this embodiment, the first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 are arranged vertically, the first insulating reinforcement rib 51 extends along the length direction of the enclosure 13 and is connected to the middle of the second insulating reinforcement rib 52, and the second insulating reinforcement rib 52 extends along the width direction of the enclosure 13, so that the first insulating reinforcement rib 51 and the second insulating reinforcement rib 52 can both play a role in improving the structural strength of the packaging shell 10.

[0051] like Figures 1 to 5 as well as Figures 8 to 10 As shown, a mounting seat 134 is provided between the second insulating reinforcement rib 52 and the inner surface of the enclosure 13 , a mounting hole 111 is provided on the cover plate 11 , and the cover plate 11 is connected to the mounting seat 134 via a fastener 60 penetrating through the mounting seat 134 and the mounting hole 111 . Specifically, the width of the mounting seat 134 is greater than the width of the second insulating reinforcement rib 52, so that the mounting seat 134 can strengthen the connection strength between the second insulating reinforcement rib 52 and the inner surface of the enclosure 13, and the mounting seat 134 can also provide a mounting base for the fastener 60, so that the cover plate 11 is connected to the mounting seat 134 through the fastener 60 penetrating the mounting seat 134 and the mounting hole 111, thereby connecting the cover plate 11 to the enclosure 13; compared with the traditional method of fixing the cover plate and the enclosure with adhesive, this embodiment not only simplifies the packaging process steps of the semiconductor packaging structure but also increases the high temperature resistance of the semiconductor packaging structure. Compared with the traditional method of fixing the cover plate and the enclosure with snaps, this embodiment allows the user to easily open the cover plate 11 and observe the internal working condition or the condition after failure of the semiconductor packaging structure.

[0052] like Figures 5 to 8As shown, the semiconductor packaging structure also includes a first metal plate 71, which is connected between the substrate 12 and the semiconductor chip 20, the first metal plate 71 is electrically connected to the drain of the semiconductor chip 20, and the first end of the first terminal 30 is electrically connected to the first metal plate 71. Specifically, the semiconductor chip 20 is directly connected to the substrate 12 through the first metal plate 71, that is, the semiconductor chip 20 is directly connected to the packaging shell 10 through the first metal plate 71. Compared with the solution of connecting the substrate and the semiconductor chip through the lining plate and the connecting part between the lining plate and the substrate in the related art, this embodiment simplifies the heat dissipation path between the semiconductor chip 20 and the substrate 12, and reduces the thermal resistance on the heat dissipation path, so that the heat generated by the semiconductor chip 20 during operation can be better transferred to the substrate 12 and even the packaging shell 10, which is more conducive to the heat dissipation of the semiconductor chip 20.

[0053] like Figures 5 to 8 As shown, the semiconductor package structure further includes a second metal plate 72 and an insulating bump disposed on the substrate 12, the second metal plate 72 is electrically connected to the source of the semiconductor chip 20, the first end of the second terminal 40 is electrically connected to the second metal plate 72, the second metal plate 72 is spaced apart from the first metal plate 71, and the insulating bump is disposed between the first metal plate 71 and the second metal plate 72. Specifically, since the second metal plate 72 is electrically connected to the source of the semiconductor chip 20, and the first metal plate 71 is electrically connected to the drain of the semiconductor chip 20, the voltage difference between the first metal plate 71 and the second metal plate 72 is also relatively large, and the insulating bump effectively enhances the creepage distance between the first metal plate 71 and the second metal plate 72, thereby improving the insulation performance of the semiconductor package structure.

[0054] like Figures 5 to 8 As shown, the semiconductor package structure further includes a third terminal 90 and a third metal plate 73 disposed on the substrate 12, the third metal plate 73 is electrically connected to the gate of the semiconductor chip 20, the first end of the third terminal 90 is electrically connected to the third metal plate 73, the second end of the third terminal 90 extends through the package shell 10 to the outside of the mounting cavity 14, and the third metal plate 73 and the second metal plate 72 are located on the same side of the insulating bump. Specifically, since the voltage difference between the third metal plate 73 and the first metal plate 71 is small, the insulation requirements of the semiconductor package structure can be met by locating the third metal plate 73 and the first metal plate 71 on the same side of the insulating bump.

[0055] like Figures 5 to 8As shown, the semiconductor packaging structure also includes a bonding wire 82, which is connected between the second metal plate 72 and the source of the semiconductor chip 20, and at least part of the bonding wire 82 is located above the insulating bump. Specifically, the bonding wire 82 is located in the insulating colloid layer, and the bonding wire 82 can stably electrically connect the second metal plate 72 and the source of the semiconductor chip 20. In addition, the semiconductor chip 20 and the second metal plate 72 are connected by a sintering process. The sintering process can be a nano-silver sintering process. The semiconductor chip 20 and the second metal plate 72 are made by the nano-silver sintering process so that the semiconductor packaging structure can withstand an operating temperature of more than 300°C, which is higher than the operating temperature (220°C) of the semiconductor chip and the second connecting plate made by the traditional welding process. It should be noted that the nano-silver sintering process is an innovative material connection technology, which is particularly suitable for the manufacture of electronic packaging and high-power devices. This process forms a connection layer with high electrical conductivity and high thermal conductivity by sintering nano-scale silver particles at low temperature, which has significant technical advantages and wide application potential. The nanosilver sintering process has become an important technology in the manufacture of electronic packaging and high-power devices due to its low-temperature sintering, high conductivity, high thermal conductivity, structural strength and environmental protection characteristics. The nanosilver sintering process not only improves the performance and reliability of semiconductor packaging structures, but also provides a green and environmentally friendly solution. The benefits of using the nanosilver sintering process are as follows: 1. Low-temperature sintering: A major advantage of the nanosilver sintering process is its low-temperature sintering characteristics. Traditional metal sintering processes usually require high temperatures (over 800°C) to achieve effective sintering, while nanosilver sintering can be completed between 200°C and 300°C. This low-temperature sintering characteristic makes the process particularly suitable for temperature-sensitive electronic components and materials, such as certain semiconductors and organic materials, thereby avoiding thermal damage and material degradation that may be caused by high temperatures. 2. High conductivity: The connection layer formed by nanosilver particles after sintering has excellent conductive properties. As a metal, silver has the highest conductivity among all metals. The nanosilver sintering process can achieve close connection between silver particles at a lower temperature, thereby forming a low-resistance connection layer. This can significantly improve the performance and efficiency of electronic devices and circuit boards that require efficient electrical transmission. 3. High thermal conductivity: In addition to high conductivity, the nanosilver sintered layer also has high thermal conductivity. This means that it can effectively dissipate heat and avoid failure or performance degradation of electronic devices due to overheating. In high-power devices such as power semiconductors, LEDs, and high-frequency communication equipment, good thermal management is a key factor in ensuring their stability and long life. 4. Structural strength and stability: The nanosilver sintering process can achieve close bonding of silver particles at a lower temperature to form a connection layer with high structural strength and stability. Compared with traditional welding methods, the nanosilver sintered layer has higher reliability and durability, and can better resist fatigue and damage caused by stress and thermal cycles. 5. Environmental protection characteristics: The nanosilver sintering process does not contain lead and meets environmental protection requirements.Traditional soldering processes often use lead-containing solder, which, despite its superior performance, is harmful to the environment and health. Nanosilver sintering provides a green alternative that is in line with the environmental development trend in the future electronic packaging and manufacturing fields. 6. Process flexibility: Nanosilver sintering materials are usually in the form of pastes and can be coated and printed by a variety of methods such as screen printing, spraying or dispensing. This flexibility enables the process to adapt to different manufacturing needs and design requirements, providing higher design freedom and manufacturing efficiency.

[0056] In addition, the first metal plate 71 may be made of copper, and the substrate 12 may be made of ceramics, that is, the first metal plate 71 and the substrate 12 may be made of copper clad on a ceramic substrate.

[0057] The copper-clad ceramic structure described above can be made in the following ways:

[0058] DBC (Direct Bonded Copper): A composite substrate is made by sintering copper foil directly to the surface of Al2O3 and AlN ceramics at high temperature through hot melt bonding. Thanks to the high eutectic bonding strength between copper foil and ceramic, the copper thickness of DBC substrates can generally be 100μm-600μm. At the same time, ceramics and copper have good thermal conductivity, and the thermal stability of DBC substrates is also good. The benefits of DBC technology include: High thermal conductivity: DBC substrates have excellent thermal conductivity, which is crucial for heat dissipation of high-power electronic devices. For example, the thermal conductivity of aluminum nitride is much higher than that of aluminum oxide, making DBC substrates more effective in high-power applications. High insulation: The ceramic material itself has high insulation, making DBC substrates very reliable in high-voltage applications. High structural strength: DBC substrates combine the high strength of ceramics and the high conductivity of copper, providing good structural stability. Low thermal expansion coefficient: The thermal expansion coefficient of DBC substrates is similar to that of silicon chips, which helps reduce thermal stress and improve the reliability of packaging. Simplified manufacturing process: DBC technology simplifies the traditional multilayer ceramic substrate manufacturing process because it does not require additional metallization steps. High current carrying capacity: Since the thickness of the copper layer can be made thicker, the DBC substrate has a higher current carrying capacity and is suitable for high current applications. Excellent solder resistance: The DBC substrate can withstand multiple soldering processes without damage. Customizable layout: The DBC substrate can customize the circuit layout as needed, similar to traditional PCBs. Economical: In some applications, DBC substrates may be more economical than using other high-performance materials (such as AIN and Si3N4). Environmental adaptability: The DBC substrate can work stably under harsh environmental conditions, such as high temperature, high pressure and chemical corrosion environments.

[0059] DPC (Direct Plating Copper): It is a ceramic circuit processing technology developed on the basis of ceramic thin film processing. With ceramic as the circuit substrate, a metal layer is composited on the surface of the substrate by sputtering, and the circuit is formed by electroplating and photolithography. The benefits of DPC technology include: High thermal conductivity: DPC substrate uses ceramic as the base material, which has excellent thermal conductivity, can effectively conduct and dissipate the heat generated by high-power electronic equipment, and improve the reliability and performance of the equipment. Superior high-frequency characteristics: The dielectric constant and dielectric loss of DPC substrate are low, which can achieve low signal transmission loss in high-frequency and microwave frequency bands, and is suitable for high-frequency and radio frequency applications. High-density packaging capability: DPC substrate has high circuit density and fine line width / fine line spacing capabilities, which can achieve more compact circuit layout and higher circuit density, which is conducive to the miniaturization and integrated design of devices. Excellent structural performance: DPC substrate has high structural strength and hardness, can resist environmental stresses such as vibration, impact and thermal expansion, and improve the reliability and durability of equipment. Good dimensional stability: DPC substrates have a low thermal expansion coefficient in high temperature environments, which can maintain good dimensional stability and reduce the risk of mismatch and cracks caused by thermal stress. Excellent welding performance: The copper film on the surface of the DPC substrate has good welding performance, which can achieve reliable circuit connection and welding. High reliability and durability: The material and structural design of the DPC substrate make it highly reliable and durable, and can meet the requirements of harsh working environments and long-term use.

[0060] AMB (Active Metal Brazing): AMB is developed on the basis of DBC technology. At high temperature, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby achieving heterogeneous bonding between ceramic and metal. The AMB process has the following benefits: 1. High bonding strength and reliability. The core of the AMB process is to add active elements to the brazing material, and form a dense reaction layer on the surface of the ceramic through chemical reactions at high temperatures. This reaction layer greatly improves the wettability of the brazing material on the ceramic surface, making the bonding between ceramic and metal tighter and stronger. Compared with the traditional DBC technology, the ceramic substrate prepared by the AMB process has higher thermal conductivity, better copper layer bonding and lower thermal resistance, which significantly improves the reliability and service life of the product. In power electronic devices, such as high-power semiconductor devices such as IGBT (insulated gate bipolar transistor) modules, AMB copper-clad substrates have become the preferred packaging material due to their excellent bonding strength and reliability. As a core component in electric vehicles, rail transportation, wind power generation and other fields, IGBT modules have extremely high requirements for heat dissipation and reliability. The application of the AMB process effectively improves the heat dissipation performance of the IGBT module, reduces thermal resistance, and thus extends the service life of the module. 2. Wide range of material applicability. The AMB process has a wide range of applications for ceramic materials and can process a variety of ceramic substrates including alumina (Al2O3), aluminum nitride (AlN) and silicon nitride (Si3N4). These ceramic materials each have their own unique physical and chemical properties and are suitable for different application scenarios. For example, Al2O3 ceramics are widely used in low-power heat dissipation devices such as LEDs due to their low cost and mature process; while AlN and Si3N4 ceramics have become the preferred materials for high-power IGBT modules such as high-speed rail and wind power generation due to their high thermal conductivity, low dielectric constant and thermal expansion coefficient matching that of single crystal silicon. In addition, the AMB process can also process different types of metal materials, such as copper, nickel, silver, etc., further expanding its application range. This wide range of material applicability makes the AMB process extremely flexible and adaptable in the field of electronic device packaging. 3. Simple operation process and high production efficiency. The processing of the AMB process is relatively simple and can be completed in one heating process, which greatly shortens the production cycle. This is undoubtedly a huge advantage for the modern manufacturing industry that pursues efficient production. In addition, the operation process of the AMB process is relatively simple, and the technical requirements for operators are relatively low, which is conducive to reducing production costs and improving production efficiency. 4. Excellent thermal performance and heat dissipation capabilities. The ceramic substrate prepared by the AMB process has excellent thermal performance and heat dissipation capabilities. Taking the AMB-SiN ceramic substrate as an example, its thermal conductivity is as high as 90W / mK, which is much higher than the traditional Al2O3 ceramic substrate. This makes the AMB-SiN ceramic substrate perform well in electronic devices with high power density and high heat dissipation requirements.Especially in application scenarios such as new energy vehicles, photovoltaic inverters, and wind turbines, AMB-SiN ceramic substrates can effectively reduce the operating temperature of devices and improve the stability and reliability of the system. 5. Good thermal matching and structural performance. The ceramic substrate prepared by the AMB process also has good thermal matching and structural performance. Taking the AMB-SiN ceramic substrate as an example, its thermal expansion coefficient is close to that of the SiC chip, which is beneficial to reduce the impact of thermal stress on the packaging structure. In addition, the AMB-SiN ceramic substrate also has high bending strength and wear resistance, and can withstand greater structural stress and vibration shock. These excellent properties make the AMB-SiN ceramic substrate an ideal packaging material for electronic devices with high reliability and high heat dissipation requirements.

[0061] In addition, in the present embodiment, the semiconductor package structure further includes a conductive plate, which is connected between the second metal plate 72 and the source of the semiconductor chip 20, and the conductive plate is arranged in the insulating bump and is located in the insulating colloid layer. Specifically, the arrangement of the conductive plate can also play the effect of stably electrically connecting the second metal plate 72 and the source of the semiconductor chip 20. The width of the insulating bump is greater than 0 and less than or equal to 2mm; the height of the insulating bump is greater than 0 and less than or equal to 3mm. In this way, the insulating bump has sufficient width and height to increase the creepage distance between the first metal plate 71 and the second metal plate 72. It should be noted that the width of the insulating bump refers to the size of the insulating bump in the direction parallel to the substrate 12, and the height of the insulating bump refers to the size of the insulating bump in the direction perpendicular to the substrate 12. Specifically, the width of the insulating bump can be 0.5mm, 1mm, 1.2mm, 1.4mm, 1.5mm or 2mm, and the height of the insulating bump can be 0.6mm, 1mm, 1.2mm, 2mm, 2.5mm or 3mm.

[0062] like Figure 1 as well as Figures 5 to 8As shown, a first through hole 1331 is provided on the enclosure 13, and the first terminal 30 includes a first plate segment 31 and a second plate segment 32 which are arranged at an angle, the first end of the first plate segment 31 is electrically connected to the drain of the semiconductor chip 20, the second end of the first plate segment 31 is connected to the first end of the second plate segment 32, the second end of the second plate segment 32 passes through the first through hole 1331, and the first plate segment 31 is shielded at the first through hole 1331. Specifically, the formation of the insulating colloid layer needs to be achieved through a glue pouring process. When the insulating colloid is in a flowing state, it is easy to overflow from the first through hole 1331 to the outside of the packaging shell 10 during glue pouring. By making the first plate segment 31 block the first through hole 1331, the first terminal 30 can block the first through hole 1331, so that the insulating colloid will not overflow from the first through hole 1331 during glue pouring, thereby enhancing the reliability of glue pouring and facilitating degassing after glue pouring. In this embodiment, the structures of the second terminal 40 and the third terminal 90 are similar to those of the first terminal 30, and also have similar effects on the second through hole 1332 and the third through hole (both structures are similar to the first through hole 1331). In this embodiment, the first plate segment 31 and the second plate segment 32 are vertically arranged. If the semiconductor packaging structure is in Figure 2 In terms of the posture in the figure, the first plate segment 31 extends in the vertical direction, and the second plate segment 32 extends in the lateral direction.

[0063] like Figures 1 to 5 as well as Figures 8 to 10 As shown, the semiconductor package structure further includes a first insulating enclosure 83, which is arranged on the outer surface of the enclosure 13 and surrounds the outer periphery of the second plate segment 32. Specifically, the first insulating enclosure 83 is connected to the outer surface of the enclosure 13, and the first insulating enclosure 83 is surrounded at the first through hole 1331. Specifically, the first insulating enclosure 83 is surrounded by the outer periphery of the portion of the first terminal 30 passing through the mounting cavity 14 (that is, the outer periphery of the second plate segment 32). The surface distance between the portion of the first terminal 30 passing through the mounting cavity 14 and the portion of the second terminal 40 passing through the mounting cavity 14 includes not only the portion passing through the outer surface of the enclosure 13 but also the portion passing through the outer surface of the first insulating enclosure 83. Compared with the solution in which the surface distance only includes the portion passing through the outer surface of the enclosure 13, the surface distance between the first terminal 30 and the second terminal 40 in this embodiment can be effectively increased, thereby enhancing the insulation performance between the portion of the first terminal 30 passing through the mounting cavity 14 and the portion of the second terminal 40 passing through the mounting cavity 14, thereby further enhancing the insulation performance of the semiconductor package structure. In addition, the second insulating enclosure 13 is disposed at the second through hole 1332 and surrounds the outer periphery of the second terminal 40 . The function of the second insulating enclosure 13 is similar to that of the first insulating enclosure 83 , which will not be described in detail herein.

[0064] In addition, in this embodiment, Figure 3As shown, there is a gap between the insulating reinforcement part 50 and the semiconductor chip 20, wherein the surface of the insulating reinforcement part 50 facing the substrate 12 is arranged away from the substrate 12 relative to the second plate segment 32, and the surface of the insulating reinforcement part 50 facing the substrate 12 is located in the insulating colloid layer. Specifically, the first terminal 30, the second terminal 40 and the third terminal 90 all have similar structures and have similar relationships between the insulating reinforcement part 50 and the insulating colloid layer. In this way, the first terminal 30, the second terminal 40 and the third terminal 90 are all located in the insulating colloid layer, and no pure air path is formed between the first terminal 30, the second terminal 40 and the third terminal 90, but a solid path of the insulating colloid is formed between each other, thereby ensuring the insulation performance of the semiconductor packaging structure.

[0065] In addition, in the present embodiment, the surface of the insulating colloid layer facing the cover plate 11 is spaced from the cover plate 11. This is because there is a step of vacuuming and removing bubbles during the process of injecting the insulating colloid. In this step, the bubbles will gradually grow larger and burst. If too much insulating colloid is injected (that is, there is no space between the surface of the insulating colloid layer facing the cover plate 11 and the cover plate 11), the enlarged bubbles will squeeze the solidified insulating colloid out of the packaging shell 10.

[0066] In addition, in the present embodiment, the packaging shell 10 and the insulating reinforcement part 50 are both made of ceramics. Specifically, the packaging shell 10 and the insulating reinforcement part 50 can be made of materials such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, silicon carbide, etc., so that the packaging shell 10 has the advantages of high temperature resistance, corrosion resistance, good thermal conductivity, and high structural strength. Aluminum oxide has excellent structural strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconium oxide is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. Silicon carbide not only has high hardness and high wear resistance, but also can remain stable at extremely high temperatures, making it very popular in high-temperature electronic devices and high-frequency applications. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of semiconductor packaging structures.

[0067] In addition, a coating is provided on the semiconductor chip 20. In addition, a coating can be provided on the periphery of the bonding wire 82, between the insulating colloid part and the substrate 12, and between the first metal plate 71 and the substrate 12. The preferred coating may be a PI coating, which may include multiple layers. PI is polyimide. The PI coating can ensure the insulation, long-term temperature resistance, and water vapor isolation of the semiconductor chip 20. There are many significant benefits to coating the semiconductor chip 20 with a PI coating, especially in improving the performance, reliability, and durability of the semiconductor chip 20. The following are several main advantages of using a PI coating: 1. Excellent thermal stability: Polyimide materials have excellent thermal stability and can maintain their physical and chemical properties in high temperature environments. For chips working under high temperature conditions, the PI coating can effectively protect the chip from thermal stress, thereby extending the service life of the chip. PI materials are generally able to withstand high temperatures, which makes it very valuable in high-temperature electronic devices and high-power applications. 2. Electrical insulation performance: The PI coating has good electrical insulation performance, which can prevent electrical short circuits and leakage inside the chip. Its high insulation ensures the safe operation of the chip in high voltage and high frequency environments, reducing the risk of electrical failures. This is especially important for electronic devices that require high reliability. 3. Structural strength and flexibility: Polyimide materials have both high structural strength and flexibility, and can resist external stress and impact. The PI coating applied to the surface of the chip can provide additional protection to prevent the chip from being damaged during manufacturing, transportation and use. At the same time, the flexibility of the PI coating enables it to adapt to slight deformations and stress changes on the surface of the chip, maintaining the integrity and effectiveness of the coating. 4. Chemical corrosion resistance: PI materials have excellent chemical corrosion resistance and can resist erosion by various chemical reagents, solvents and corrosive gases. Applying PI coating can effectively protect the chip from chemical corrosion, especially in some harsh working environments such as industrial control, chemical production and environmental monitoring equipment. 5. Low dielectric constant: Polyimide has a low dielectric constant, which is an important advantage for high-speed and high-frequency circuits. Low dielectric constant helps reduce loss and delay during signal transmission, improve signal transmission speed and integrity, and thus improve chip performance and efficiency. 6. Process compatibility: PI coating can be applied by a variety of process methods, such as spin coating, spray coating and dip coating, and the process is relatively simple and suitable for large-scale production. This process compatibility enables PI coating to be widely used in the manufacture of different types of chips and electronic devices, providing a flexible solution.

[0068] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0069] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0070] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0071] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A packaging shell (10) comprising a base plate (12) and a surrounding plate (13) connected to the base plate (12); A semiconductor chip (20) connected to the substrate (12); A first terminal (30) connected to a first side of the semiconductor chip (20); A second terminal (40) connected to a second side of the semiconductor chip (20); an insulating reinforcement portion (50) connected to the enclosure (13), the insulating reinforcement portion (50) comprising a first insulating reinforcement rib (51) and a second insulating reinforcement rib (52), the first insulating reinforcement rib (51) being arranged between the first terminal (30) and the second terminal (40) to enhance the creepage distance between the first terminal (30) and the second terminal (40), the two ends of the second insulating reinforcement rib (52) being respectively connected to two opposite inner surfaces of the enclosure (13), the first insulating reinforcement rib (51) and the second insulating reinforcement rib (52) being intersected and connected; The first end of the first insulating reinforcement rib (51) is connected to the enclosure (13), and the second end of the first insulating reinforcement rib (51) is connected to the middle of the second insulating reinforcement rib (52); The semiconductor packaging structure further comprises an insulating colloid layer, the insulating colloid layer is connected to the substrate (12), and the semiconductor chip (20) is located in the insulating colloid layer; The enclosure plate (13) is provided with a first through hole (1331); the first terminal (30) comprises a first plate segment (31) and a second plate segment (32) which are arranged at an angle; the first end of the first plate segment (31) is electrically connected to the drain of the semiconductor chip (20); the second end of the first plate segment (31) is connected to the first end of the second plate segment (32); the second end of the second plate segment (32) passes through the first through hole (1331); and the first plate segment (31) is arranged to block the first through hole (1331); The semiconductor packaging structure further comprises a first insulating enclosure (83), wherein the first insulating enclosure (83) is arranged on the outer surface of the enclosure (13) and surrounds the outer periphery of the second plate segment (32).

2. The semiconductor package structure according to claim 1, wherein: A mounting seat (134) is provided between the second insulating reinforcement rib (52) and the inner surface of the enclosure (13); the packaging shell (10) further comprises a cover plate (11); a mounting hole (111) is provided on the cover plate (11); the cover plate (11) is connected to the mounting seat (134) via a fastener (60) that penetrates the mounting seat (134) and the mounting hole (111).

3. The semiconductor package structure according to claim 1 or 2, characterized in that: The semiconductor packaging structure further comprises a first metal plate (71), wherein the first metal plate (71) is connected between the substrate (12) and the semiconductor chip (20), the first metal plate (71) is electrically connected to a drain of the semiconductor chip (20), and the first terminal (30) is electrically connected to the first metal plate (71).

4. The semiconductor package structure according to claim 3, characterized in that: The semiconductor packaging structure further comprises a second metal plate (72) and an insulating bump arranged on the substrate (12); the second metal plate (72) is electrically connected to the source of the semiconductor chip (20); the second terminal (40) is electrically connected to the second metal plate (72); the second metal plate (72) is spaced apart from the first metal plate (71); and the insulating bump is arranged between the first metal plate (71) and the second metal plate (72).

5. The semiconductor package structure according to claim 4, characterized in that: The semiconductor packaging structure also includes a third terminal (90) and a third metal plate (73) arranged on the substrate (12), the third metal plate (73) being electrically connected to the gate of the semiconductor chip (20), the third terminal (90) being electrically connected to the third metal plate (73), and the third metal plate (73) and the second metal plate (72) being located on the same side of the insulating bump.

6. The semiconductor package structure according to claim 4, characterized in that: The semiconductor packaging structure also includes a bonding wire (82), the bonding wire (82) being connected between the second metal plate (72) and the source electrode of the semiconductor chip (20), and at least a portion of the bonding wire (82) being located above the insulating bump.

7. The semiconductor package structure according to claim 4, characterized in that: The semiconductor packaging structure also includes a conductive plate, the conductive plate is connected between the second metal plate (72) and the source electrode of the semiconductor chip (20), and the conductive plate is penetrated through the insulating bump and is located in the insulating colloid layer.

8. The semiconductor package structure according to claim 4, characterized in that: The width of the insulating protrusion is greater than 0 and less than or equal to 2 mm; and / or, The height of the insulating protrusion is greater than 0 and less than or equal to 3 mm.

9. The semiconductor package structure according to claim 4, characterized in that: The insulating colloid layer is made of silicone rubber; and / or, The packaging shell (10) and the insulation reinforcement part (50) are both made of ceramic.

10. The semiconductor package structure according to claim 1, wherein: There is a gap between the insulation reinforcement part (50) and the semiconductor chip (20); a surface of the insulation reinforcement part (50) facing the substrate (12) is arranged away from the substrate (12) relative to the second plate segment (32); and a surface of the insulation reinforcement part (50) facing the substrate (12) is located within the insulation colloid layer.

11. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further comprises a cover plate (11) connected to the enclosure plate (13), a gap is provided between the insulation reinforcement portion (50) and the semiconductor chip (20), and a surface of the insulation colloid layer facing the cover plate (11) is spaced apart from the cover plate (11).

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