Test structure, test method for test structure

Abstract

A test structure and a test method for the test structure are disclosed. The test structure includes: a substrate having an active region; a test gate located on the substrate, the test gate spanning the active region and covering a portion of the surface of the active region; a test source region located within the active region on one side of the test gate; a test drain region located within the active region on the other side of the test gate; and a first gate test bond and a second gate test bond located on the test gate and electrically connected to the test gate, respectively. By adding the first gate test bond and the second gate test bond to the test gate of the MOS transistor, the resistance value of the test gate can be measured based on the first gate test bond and the second gate test bond, eliminating the need to separately fabricate the test gate to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a test structure and a test method for the test structure. Background Technology

[0002] In the semiconductor manufacturing field, with the development of technology, semiconductor devices are becoming smaller and smaller while their complexity is increasing. In order to monitor the manufacturing process of semiconductor devices and ensure their reliability, the common practice is to form test structures (test keys) in the semiconductor devices for testing and simulating some key parameters of the semiconductor devices, so as to ensure the quality of the semiconductor devices leaving the factory.

[0003] Test structures are typically fabricated using the same semiconductor process as the semiconductor devices on the wafer, and there is a direct correspondence between the test structures and the semiconductor devices. Each interconnect layer in the semiconductor device corresponds to a test line on the same layer in the test structure, and each plug in the semiconductor device corresponds to a test plug on the same layer in the test structure. Because the test structures and semiconductor devices are fabricated using the same process and have a direct correspondence, the performance of the semiconductor devices on the wafer can be obtained by testing the performance of the test structures. Using test structures to reflect the performance of the semiconductor devices on the wafer avoids damaging the semiconductor devices on the wafer.

[0004] However, existing test structures still have many problems during the testing process. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a test structure and a test method for the test structure, so as to reduce the area occupied by the test structure on the chip.

[0006] To address the aforementioned problems, the present invention provides a test structure comprising: a substrate having an active region; a test gate located on the substrate, the test gate spanning the active region and covering a portion of the surface of the active region; a test source region located within the active region on one side of the test gate; a test drain region located within the active region on the other side of the test gate; and a first gate test bond and a second gate test bond located on the test gate and electrically connected to the test gate, respectively.

[0007] Optionally, it further includes: a source test key located on and electrically connected to the test source region; a drain test key located on and electrically connected to the test drain region; and a substrate test key located on and electrically connected to the substrate.

[0008] Optionally, the first gate test key and the second gate test key are electrically connected to opposite ends of the test gate, respectively.

[0009] Optionally, both the first gate test key and the second gate test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate.

[0010] Optionally, each of the metal layers has a plurality of parallel anti-dent openings.

[0011] Optionally, the anti-dent openings in adjacent metal layers are perpendicular to each other.

[0012] Accordingly, the present invention also provides a testing method for a testing structure, comprising: providing the testing structure described in any of the above technical solutions; and obtaining the gate resistance value of the testing gate based on the first gate test key and the second gate test key.

[0013] Optionally, the method for obtaining the gate resistance value of the test gate includes: applying a preset voltage to the test gate based on the first gate test key; measuring the measurement current of the test gate based on the second gate test key; and using the ratio of the preset voltage to the measurement current as the gate resistance value.

[0014] Optionally, the test structure further includes: a source test bond located on and electrically connected to the test source region; a drain test bond located on and electrically connected to the test drain region; and a substrate test bond located on and electrically connected to the substrate.

[0015] Optionally, it also includes: performing transistor leakage current testing.

[0016] Optionally, the method for performing the transistor leakage current test includes: applying a maximum operating voltage to the test drain region based on the drain region test key; measuring the leakage current of the test source region based on the source region test key; measuring the leakage current of the test drain region based on the drain region test key; measuring the leakage current of the substrate based on the substrate test key; and measuring the leakage current of the test gate based on the first gate test key or the second gate test key.

[0017] Optionally, it also includes: performing transistor saturation current testing.

[0018] Optionally, the method for performing the transistor saturation current test includes: applying a maximum operating voltage to the test gate based on the first gate test key or the second gate test key; applying a maximum operating voltage to the test drain based on the drain test key; and measuring the saturation current of the test drain based on the drain test key.

[0019] Optionally, it also includes: performing transistor linear current testing.

[0020] Optionally, the method for performing the transistor linear current test includes: applying a maximum operating voltage to the test gate based on the first gate test key or the second gate test key; applying a fixed voltage less than the maximum operating voltage to the test drain based on the drain test key; and measuring the linear current of the test drain based on the drain test key.

[0021] Optionally, it also includes: performing a transistor saturation threshold voltage test.

[0022] Optionally, the method for testing the transistor saturation threshold voltage includes: applying a maximum operating voltage to the test drain region based on the drain test key; linearly applying a scan voltage from 0V to the maximum operating voltage to the test gate based on the first gate test key or the second gate test key; detecting the current of the test drain region based on the drain test key; and when the current of the test drain region is detected to be greater than a preset current, the voltage applied to the test gate is the transistor saturation threshold voltage.

[0023] Optionally, it also includes: performing a transistor linear threshold voltage test.

[0024] Optionally, the method for testing the transistor linear threshold voltage includes: applying a fixed voltage less than the maximum operating voltage to the test drain region based on the drain test key; linearly applying a scan voltage from 0V to the maximum operating voltage to the test gate based on the first gate test key or the second gate test key; detecting the current of the test drain region based on the drain test key; and when the current of the test drain region is detected to be greater than a preset current, the voltage applied to the test gate is the transistor linear threshold voltage.

[0025] Optionally, it also includes: performing source-drain breakdown voltage testing.

[0026] Optionally, the source-drain breakdown voltage test method includes: linearly applying a scanning voltage to the test drain region starting from 0V based on the drain region test key; measuring the current of the test drain region based on the drain region test key; when a sudden change in the current of the test drain region is detected, the voltage applied to the test drain region accordingly is the source-drain breakdown voltage.

[0027] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0028] In the test structure of the present invention, by adding a first gate test key and a second gate test key on the test gate of the MOS transistor, the resistance value of the test gate can be measured based on the first gate test key and the second gate test key, eliminating the need to separately manufacture the test gate to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

[0029] Furthermore, by adding a source test bond on the test source region of the MOS transistor, a source test bond on the test drain region, and a substrate test bond on the substrate, it is possible to monitor or measure other parameters on the same MOS transistor, thereby achieving the goal of testing multiple parameters on the same device and reducing the additional chip area occupied.

[0030] Furthermore, the first gate test key and the second gate test key are electrically connected to opposite ends of the test gate, respectively. By placing the first gate test key and the second gate test key at opposite ends of the test gate, it is possible to prevent the test current from flowing through the entire area of ​​the test gate when measuring its resistance, thereby ensuring more accurate measurement results.

[0031] Furthermore, each metal layer has several parallel anti-dent openings. These anti-dent openings prevent dents in the middle area of ​​the metal layer during the planarization process, thereby improving the electrical contact of the metal layer.

[0032] Furthermore, the anti-dent openings in adjacent metal layers are perpendicular. By arranging the anti-dent openings in adjacent layers perpendicularly, the overall structure of the test bond is more uniformly distributed, thereby improving the conductivity of the test bond.

[0033] In the test method of the test structure of the present invention, by adding a first gate test key and a second gate test key on the test gate of the MOS transistor, the resistance value of the test gate can be measured based on the first gate test key and the second gate test key, eliminating the need to separately manufacture the test gate to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

[0034] Furthermore, the test structure also includes: a source test bond located on and electrically connected to the test source region; a drain test bond located on and electrically connected to the test drain region; and a substrate test bond located on and electrically connected to the substrate. By adding source, drain, and substrate test bonds to the MOS transistor, it is possible to test parameters such as transistor drain current, transistor saturation current, transistor linear current, transistor saturation threshold voltage, transistor linear threshold voltage, and source-drain breakdown voltage. This achieves the goal of testing multiple parameters on the same device, thereby reducing the additional chip area required. Attached Figure Description

[0035] Figures 1 to 3 This is a schematic diagram of the test structure according to an embodiment of the present invention;

[0036] Figure 4 and Figure 5 This is a schematic diagram of the structure of the first gate test bond and the second gate test bond in the test structure of an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the structure of adjacent metal layers in the first gate test bond and the second gate test bond in an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, existing test structures still have many problems during the testing process. These will be explained in detail below.

[0039] With advancements in manufacturing processes, the continuous reduction in device feature size allows for the fabrication of more chips on a single wafer, reducing manufacturing costs. However, test structures occupy additional chip area. To save area, a single test structure can be used to test multiple parameters. Gate resistance can monitor and reduce current surges caused by gate voltage variations, as well as transient gate voltage changes. However, current MOS transistors primarily test parameters such as threshold voltage, saturation current, source-drain current, and breakdown voltage. Gate resistance is not directly measured on the MOS transistor; measuring it requires fabricating a separate gate structure in another area of ​​the chip, further consuming additional chip area.

[0040] Based on this, the present invention provides a test structure and a test method for the test structure. By adding a first gate test key and a second gate test key to the test gate of the MOS transistor, the resistance value of the test gate can be measured based on the first gate test key and the second gate test key, eliminating the need to separately manufacture the test gate to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

[0041] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 1 to 3 This is a schematic diagram of the test structure according to an embodiment of the present invention; Figure 4 and Figure 5 This is a schematic diagram of the structure of the first gate test bond and the second gate test bond in the test structure of an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of adjacent metal layers in the first gate test bond and the second gate test bond in an embodiment of the present invention.

[0043] Please refer to Figures 1 to 3 , Figure 1 This is a top view of the test structure, omitting the first and second gate test keys. Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA. Figure 3 yes Figure 1 A cross-sectional view along the BB line; a test structure, comprising: a substrate 100 having an active region 1001; a test gate 101 located on the substrate 100, the test gate 101 spanning the active region 1001 and covering a portion of the surface of the active region 1001; a test source region 102 located in the active region 1001 on one side of the test gate 101; a test drain region 103 located in the active region 1001 on the other side of the test gate 101; a first gate test bond 104 and a second gate test bond 105 located on the test gate 101 and electrically connected to the test gate 101 respectively.

[0044] By adding a first gate test key 104 and a second gate test key 105 to the test gate 101 of the MOS transistor, the gate resistance value of the test gate 101 can be measured based on the first gate test key 104 and the second gate test key 105, eliminating the need to separately manufacture the test gate 101 to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

[0045] It's important to note that test structures are typically fabricated using the same semiconductor process as the semiconductor devices on the wafer, and there is a direct correspondence between them. Each interconnect layer in the semiconductor device corresponds to a test line on the same layer in the test structure, and each plug in the semiconductor device corresponds to a test plug on the same layer in the test structure. Because the test structure and the semiconductor device are fabricated using the same process and have a direct correspondence, the performance of the semiconductor device on the wafer can be obtained by testing the performance of the test structure. Using the test structure to reflect the performance of the semiconductor device on the wafer avoids damaging the semiconductor device.

[0046] Since the test structure is only used to test the performance of semiconductor devices in the wafer and will not be ultimately manufactured into a product for practical use, in order to prevent the test structure from occupying the area of ​​the semiconductor devices that are actually put into practical use on the wafer, the test structure can be formed in the dicing area of ​​the wafer. After the test is completed, the test structure will also be damaged during the wafer dicing process.

[0047] It should be noted that, in this embodiment, the active region 1001 is isolated by an isolation structure 109 formed in the substrate 100.

[0048] In this embodiment, the substrate 100 is made of silicon.

[0049] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0050] Please continue to refer to this. Figure 1 In this embodiment, the first gate test key 104 and the second gate test key 105 are electrically connected to opposite ends of the test gate 101, respectively. By setting the first gate test key 104 and the second gate test key 105 at opposite ends of the test gate 101, it is possible to prevent the test current from flowing through the entire area of ​​the test gate 101 when measuring the gate resistance value of the test gate 101, thereby ensuring more accurate measurement results.

[0051] Please refer to Figure 4 and Figure 5 , Figure 5 yes Figure 4 A schematic diagram of the cross-section along the CC line is shown. In this embodiment, the first gate test key 104 and the second gate test key 105 both include: a plurality of metal layers 1041 arranged sequentially along a direction perpendicular to the top surface of the substrate 100, adjacent metal layers 1041 being electrically connected, and the plurality of metal layers 1041 having the same projection area toward the substrate 100.

[0052] Please continue to refer to this. Figure 4 In this embodiment, each metal layer 1041 has a plurality of parallel anti-dent openings 1042. The anti-dent openings 1042 can prevent the problem of dents in the middle area of ​​the metal layer 1041 during the planarization process, thereby improving the electrical contact of the metal layer 1041.

[0053] Please refer to Figure 6 In this embodiment, the anti-dent openings 1042 in adjacent metal layers 1041 are perpendicular. By arranging the anti-dent openings 1042 in adjacent layers perpendicularly, the overall structure of the test key is more uniformly distributed, thereby improving the conductivity of the test key.

[0054] Please continue to refer to this. Figure 2 and Figure 3 In this embodiment, it further includes: a source region test key 106 located on and electrically connected to the test source region 102; a drain region test key 107 located on and electrically connected to the test drain region 103; and a substrate test key 108 located on and electrically connected to the substrate 100.

[0055] In this embodiment, the structures of the source test bond 106, the drain test bond 107, and the substrate test bond 108 are the same as those of the first gate test bond 104 and the second gate test bond 105, and will not be described again here. For details, please refer to [reference needed]. Figures 4 to 6 And related explanations.

[0056] Accordingly, this invention also provides a testing method for the test structure; please refer to further details. Figures 1 to 3 The method includes: providing a test structure as described in any of the above embodiments; and obtaining the gate resistance value of the test gate 101 based on the first gate test key 104 and the second gate test key 105.

[0057] By adding a first gate test key 104 and a second gate test key 105 to the test gate 101 of the MOS transistor, the gate resistance value of the test gate 101 can be measured based on the first gate test key 104 and the second gate test key 105, eliminating the need to separately manufacture the test gate 101 to measure the gate resistance value, thereby effectively reducing the additional chip area occupied.

[0058] In this embodiment, the method for obtaining the gate resistance value of the test gate 101 includes: applying a preset voltage to the test gate 101 based on the first gate test key 104; measuring the measurement current of the test gate 101 based on the second gate test key 105; and using the ratio of the preset voltage to the measurement current as the gate resistance value.

[0059] Please continue to refer to this. Figures 1 to 3 In this embodiment, the test structure further includes: a source region test key 106 located on and electrically connected to the test source region 102; a drain region test key 107 located on and electrically connected to the test drain region 103; and a substrate test key 108 located on and electrically connected to the substrate 100.

[0060] In this embodiment, the method further includes: performing a transistor leakage current test; the method for performing the transistor leakage current test includes: applying a maximum operating voltage to the test drain region 103 based on the drain test key 107; measuring the leakage current of the test source region 102 based on the source test key 106; measuring the leakage current of the test drain region 103 based on the drain test key 107; measuring the leakage current of the substrate 100 based on the substrate test key 108; and measuring the leakage current of the test gate 101 based on the first gate test key 104 or the second gate test key 105.

[0061] It should be noted that during the transistor leakage current test, only the maximum operating voltage needs to be applied to the test drain region 103. The test gate 101, the test source region 102, and the substrate 100 all need to be grounded through their respective test keys.

[0062] In this embodiment, the method further includes: performing a transistor saturation current test; the method for performing the transistor saturation current test includes: applying a maximum operating voltage to the test gate 101 based on the first gate test key 104 or the second gate test key 105; applying a maximum operating voltage to the test drain 103 based on the drain test key 107; and measuring the saturation current of the test drain 103 based on the drain test key 107.

[0063] It should be noted that during the transistor saturation current test, the test gate 101 and the test drain region 103 need to be subjected to the maximum operating voltage, and the test source region 102 and the substrate 100 need to be grounded through their respective test keys.

[0064] In this embodiment, the method further includes: performing a transistor linear current test; the method for performing the transistor linear current test includes: applying a maximum operating voltage to the test gate 101 based on the first gate test key 104 or the second gate test key 105; applying a fixed voltage less than the maximum operating voltage to the test drain region 103 based on the drain test key 107; and measuring the linear current of the test drain region 103 based on the drain test key 107.

[0065] It should be noted that during the transistor linear current test, the test gate 101 needs to be subjected to the maximum operating voltage, the test drain region 103 needs to be subjected to a fixed voltage less than the maximum operating voltage, and the test source region 102 and the substrate 100 need to be grounded through their respective test keys.

[0066] In this embodiment, the method further includes: performing a transistor saturation threshold voltage test; the method for performing the transistor saturation threshold voltage test includes: applying a maximum operating voltage to the test drain region 103 based on the drain test key 107; linearly applying a scan voltage from 0V to the maximum operating voltage to the test gate 101 based on the first gate test key 104 or the second gate test key 105; detecting the current of the test drain region 103 based on the drain test key 107; when the current of the test drain region 103 is detected to be greater than a preset current, the voltage applied to the test gate 101 is the transistor saturation threshold voltage.

[0067] It should be noted that during the transistor saturation threshold voltage test, the test drain region 103 needs to be subjected to the maximum operating voltage, the test gate 101 needs to be subjected to a linear scan voltage, and the test source region 102 and the substrate 100 need to be grounded through their respective test keys.

[0068] In this embodiment, the method further includes: performing a transistor linear threshold voltage test; the method for performing the transistor linear threshold voltage test includes: applying a fixed voltage less than the maximum operating voltage to the test drain region 103 based on the drain test key 107; linearly applying a scan voltage from 0V to the maximum operating voltage to the test gate 101 based on the first gate test key 104 or the second gate test key 105; detecting the current of the test drain region 103 based on the drain test key 107; when the current of the test drain region 103 is detected to be greater than the preset current, the voltage applied to the test gate 101 is the transistor linear threshold voltage.

[0069] It should be noted that during the transistor linear threshold voltage test, a fixed voltage less than the maximum operating voltage needs to be applied to the test drain region 103, a linear scan voltage needs to be applied to the test gate 101, and the test source region 102 and the substrate 100 need to be grounded through their respective test keys.

[0070] In this embodiment, the method further includes: performing a source-drain breakdown voltage test; the method for performing the source-drain breakdown voltage test includes: applying a scanning voltage linearly from 0V to the test drain region 103 based on the drain region test key 107; measuring the current of the test drain region 103 based on the drain region test key 107; when a sudden change in the current of the test drain region 103 is detected, the voltage applied to the test drain region 103 is the source-drain breakdown voltage.

[0071] It should be noted that during the source-drain breakdown voltage test, a linear scanning voltage needs to be applied to the test drain region 103, and the test gate 101, the test source region 102 and the substrate 100 all need to be grounded through their respective test keys.

[0072] By adding a source test key 106, a drain test key 107, and a substrate test key 108 to the MOS transistor, it is possible to test parameters such as transistor leakage current, transistor saturation current, transistor linear current, transistor saturation threshold voltage, transistor linear threshold voltage, and source-drain breakdown voltage of the MOS transistor. This achieves the goal of testing multiple parameters on the same device, thereby reducing the additional chip area occupied.

[0073] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Substrate, the substrate having an active region; A test gate located on the substrate, the test gate spanning the active region and covering a portion of the surface of the active region; The test source region located within the active region on one side of the test gate; The test drain region is located in the active region on the other side of the test gate; A first gate test key and a second gate test key are located on the test gate and electrically connected to the test gate, respectively; wherein... Both the first gate test key and the second gate test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate; Each of the metal layers has several parallel anti-dent openings; The anti-dent openings in adjacent metal layers are perpendicular to each other.

2. The test structure as described in claim 1, characterized in that, Also includes: A source area test key located on and electrically connected to the test source area; A leak test key located on and electrically connected to the test leak area; A substrate test bond located on and electrically connected to the substrate.

3. The test structure as described in claim 1, characterized in that, The first gate test key and the second gate test key are electrically connected to the opposite ends of the test gate, respectively.

4. A test method for a test structure, characterized in that, include: Provide a test structure as described in any one of claims 1 to 3; The gate resistance value of the test gate is obtained based on the first gate test key and the second gate test key.

5. The test method for the test structure as described in claim 4, characterized in that, The method for obtaining the gate resistance value of the test gate includes: applying a preset voltage to the test gate based on the first gate test key; measuring the measurement current of the test gate based on the second gate test key; and using the ratio of the preset voltage to the measurement current as the gate resistance value.

6. The test method for the test structure as described in claim 4, characterized in that, The test structure further includes: a source region test key located on and electrically connected to the test source region; a drain region test key located on and electrically connected to the test drain region; and a substrate test key located on and electrically connected to the substrate.

7. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform transistor leakage current testing.

8. The test method for the test structure as described in claim 7, characterized in that, The method for performing the transistor leakage current test includes: applying a maximum operating voltage to the test drain region based on the drain region test key; measuring the leakage current of the test source region based on the source region test key; measuring the leakage current of the test drain region based on the drain region test key; measuring the leakage current of the substrate based on the substrate test key; and measuring the leakage current of the test gate based on the first gate test key or the second gate test key.

9. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform transistor saturation current testing.

10. The test method for the test structure as described in claim 9, characterized in that, The method for performing the transistor saturation current test includes: applying a maximum operating voltage to the test gate based on the first gate test key or the second gate test key; applying a maximum operating voltage to the test drain based on the drain test key; and measuring the saturation current of the test drain based on the drain test key.

11. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform transistor linear current testing.

12. The test method for the test structure as described in claim 11, characterized in that, The method for performing the linear current test of the transistor includes: applying a maximum operating voltage to the test gate based on the first gate test key or the second gate test key; applying a fixed voltage less than the maximum operating voltage to the test drain region based on the drain region test key; and measuring the linear current of the test drain region based on the drain region test key.

13. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform transistor saturation threshold voltage testing.

14. The test method for the test structure as described in claim 13, characterized in that, The method for testing the transistor saturation threshold voltage includes: applying a maximum operating voltage to the test drain region based on the drain test key; linearly applying a scan voltage from 0V to the maximum operating voltage to the test gate based on the first gate test key or the second gate test key; detecting the current of the test drain region based on the drain test key; and when the current of the test drain region is detected to be greater than a preset current, the voltage applied to the test gate is the transistor saturation threshold voltage.

15. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform transistor linear threshold voltage testing.

16. The test method for the test structure as described in claim 15, characterized in that, The method for testing the linear threshold voltage of a transistor includes: applying a fixed voltage less than the maximum operating voltage to the test drain region based on the drain test key; applying a scan voltage from 0V to the maximum operating voltage to the test gate linearly based on the first gate test key or the second gate test key; detecting the current of the test drain region based on the drain test key; and when the current of the test drain region is detected to be greater than a preset current, the voltage applied to the test gate is the linear threshold voltage of the transistor.

17. The test method for the test structure as described in claim 6, characterized in that, Also includes: Perform source-drain breakdown voltage testing.

18. The test method for the test structure as described in claim 17, characterized in that, The method for testing the source-drain breakdown voltage includes: linearly applying a scanning voltage to the test drain region starting from 0V based on the drain region test key; measuring the current of the test drain region based on the drain region test key; and when a sudden change in the current of the test drain region is detected, the voltage applied to the test drain region is the source-drain breakdown voltage.

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