Test structure and its formation method

Abstract

A test structure and a method for forming the same, wherein the test structure includes: a substrate having a test region; a first test structure located on the test region; a second test structure located on the test region; the second test structure being located on the first test structure along a direction perpendicular to the top surface of the substrate, the second test structure and the first test structure being stacked and electrically isolated from each other; a plurality of first test keys electrically connected to the first test structure; and a plurality of second test keys electrically connected to the second test structure. By stacking the large-sized first test structure and the second test structure from different process stages in a three-dimensional direction, the chip area occupied by the first test structure and the second test structure can be effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a test structure and its formation method. Background Technology

[0002] In the semiconductor manufacturing field, with the development of technology, semiconductor devices are becoming smaller and smaller while their complexity is increasing. In order to monitor the manufacturing process of semiconductor devices and ensure their reliability, the common practice is to form test structures (test keys) in the semiconductor devices for testing and simulating some key parameters of the semiconductor devices, so as to ensure the quality of the semiconductor devices leaving the factory.

[0003] Test structures are typically fabricated using the same semiconductor process as the semiconductor devices on the wafer, and there is a direct correspondence between the test structures and the semiconductor devices. Each interconnect layer in the semiconductor device corresponds to a test line on the same layer in the test structure, and each plug in the semiconductor device corresponds to a test plug on the same layer in the test structure. Because the test structures and semiconductor devices are fabricated using the same process and have a direct correspondence, the performance of the semiconductor devices on the wafer can be obtained by testing the performance of the test structures. Using test structures to reflect the performance of the semiconductor devices on the wafer avoids damaging the semiconductor devices on the wafer.

[0004] However, existing test structures still have many problems. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a test structure and a method for forming the same, so as to reduce the area occupied by the test structure in the chip.

[0006] To address the above problems, the present invention provides a test structure comprising: a substrate having a test region; a first test structure located on the test region; a second test structure located on the test region; the second test structure being located on the first test structure along a direction perpendicular to the top surface of the substrate, the second test structure and the first test structure being stacked and electrically isolated from each other; a plurality of first test keys electrically connected to the first test structure; and a plurality of second test keys electrically connected to the second test structure.

[0007] Optionally, the first test structure includes: a plurality of test gates arranged in parallel along a first direction on the test region, the test gates extending along a second direction, the first direction being perpendicular to the second direction; test source / drain doped layers located on both sides of the test gates within the test region; a first metal interconnect layer electrically connected to the plurality of test gates; and a second metal interconnect layer electrically connected to the plurality of source / drain doped layers, wherein the first metal interconnect layer and the second metal interconnect layer are electrically isolated from each other, and the first metal interconnect layer and the second metal interconnect layer are located on the same process layer.

[0008] Optionally, a plurality of the first test keys are electrically connected to the first metal interconnect layer and the second metal interconnect layer, respectively.

[0009] Optionally, the second test structure includes: a first metal bus and a second metal bus arranged in parallel along a first direction; a plurality of first metal strips arranged in parallel along a second direction, wherein the first metal bus connects to the plurality of first metal strips, and the first direction is perpendicular to the second direction; a plurality of second metal strips arranged in parallel along the second direction, wherein the second metal bus connects to the plurality of second metal strips, wherein the first metal strips and the second metal strips are staggered, and the projections of the first metal strips and the second metal strips along the second direction have an overlapping area.

[0010] Optionally, several of the second test keys are electrically connected to the first metal bus and the second metal bus, respectively.

[0011] Optionally, it further includes: a third test structure located on the test area; the third test structure is located on the first test structure along a direction perpendicular to the top surface of the substrate, the third test structure and the first test structure are stacked and electrically isolated from each other; the third test structure is interspersed between the second test structures and electrically isolated from each other; and a plurality of third test keys electrically connected to the third test structure.

[0012] Optionally, the third test structure includes a resistor strip, which is interspersed among a plurality of first metal strips and a plurality of second metal strips, wherein the resistor strip, the first metal bus, the second metal bus, the first metal strip, and the second metal strip are located on the same process layer.

[0013] Optionally, several of the third test keys are electrically connected to the two ends opposite to the resistor strip.

[0014] Optionally, both the first test key and the second test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate.

[0015] Optionally, each of the metal layers has a plurality of parallel anti-dent openings.

[0016] Optionally, the anti-dent openings in adjacent metal layers are perpendicular to each other.

[0017] Accordingly, the present invention also provides a method for forming a test structure, comprising: providing a substrate having a test region; forming a first test structure on the test region; after forming the first test structure, forming a second test structure on the test region, wherein the second test structure is stacked on the first test structure along a direction perpendicular to the top surface of the substrate, and the first test structure and the second test structure are electrically isolated from each other; forming a plurality of first test bonds and a plurality of second test bonds, wherein the first test structure is electrically connected to the plurality of first test bonds respectively, and the second test structure is electrically connected to the plurality of second test bonds respectively.

[0018] Optionally, the first test structure includes: a plurality of test gates arranged in parallel along a first direction on the test region, the test gates extending along a second direction, the first direction being perpendicular to the second direction; test source / drain doped layers located on both sides of the test gates within the test region; a first metal interconnect layer electrically connected to the plurality of test gates; and a second metal interconnect layer electrically connected to the plurality of source / drain doped layers, wherein the first metal interconnect layer and the second metal interconnect layer are electrically isolated from each other, and the first metal interconnect layer and the second metal interconnect layer are located on the same process layer.

[0019] Optionally, a plurality of the first test keys are electrically connected to the first metal interconnect layer and the second metal interconnect layer, respectively.

[0020] Optionally, the second test structure includes: a first metal bus and a second metal bus arranged in parallel along a first direction; a plurality of first metal strips arranged in parallel along a second direction, wherein the first metal bus connects to the plurality of first metal strips, and the first direction is perpendicular to the second direction; a plurality of second metal strips arranged in parallel along the second direction, wherein the second metal bus connects to the plurality of second metal strips, wherein the first metal strips and the second metal strips are staggered, and the projections of the first metal strips and the second metal strips along the second direction have an overlapping area.

[0021] Optionally, several of the second test keys are electrically connected to the first metal bus and the second metal bus, respectively.

[0022] Optionally, the process of forming the second test structure further includes: forming a third test structure on the test area, along a direction perpendicular to the top surface of the substrate, the third test structure being stacked on the first test structure, and the first test structure and the third test structure being electrically isolated from each other, the third test structure being interspersed between the second test structures, and the second test structure and the third test structure being electrically isolated from each other; the process of forming the first test bond and the second test bond further includes: forming a plurality of third test bonds, the third test structure being electrically connected to the plurality of the third test bonds respectively.

[0023] Optionally, the third test structure includes a resistor strip, which is interspersed among a plurality of first metal strips and a plurality of second metal strips, wherein the resistor strip, the first metal bus, the second metal bus, the first metal strip, and the second metal strip are located on the same process layer.

[0024] Optionally, several of the third test keys are electrically connected to the two ends opposite to the resistor strip.

[0025] Optionally, both the first test key and the second test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate.

[0026] Optionally, each of the metal layers has a plurality of parallel anti-dent openings.

[0027] Optionally, the anti-dent openings in adjacent metal layers are perpendicular to each other.

[0028] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0029] In the test structure of this invention, the second test structure is located on the first test structure, and the second test structure and the first test structure are stacked along a direction perpendicular to the top surface of the substrate, and are electrically isolated from each other. By stacking the large-sized first and second test structures from different process stages in a three-dimensional direction, the chip area occupied by the first and second test structures can be effectively reduced.

[0030] Furthermore, it also includes: a third test structure located on the test area; the third test structure is located on the first test structure, along a direction perpendicular to the top surface of the substrate, the third test structure and the first test structure are stacked, and the first test structure and the third test structure are electrically isolated from each other; the third test structure is interspersed between the second test structures, and the second test structure and the third test structure are electrically isolated from each other. By stacking large-sized first and third test structures of different process stages in a three-dimensional direction, and interspersing large-sized second and third test structures of the same process stage, more test structures can be added without further occupying chip area.

[0031] Furthermore, each metal layer has several parallel anti-dent openings. These anti-dent openings prevent dents in the middle area of ​​the metal layer during the planarization process, thereby improving the electrical contact of the metal layer.

[0032] Furthermore, the anti-dent openings in adjacent metal layers are perpendicular. By arranging the anti-dent openings in adjacent layers perpendicularly, the overall distribution of the first and second test keys is more uniform, thereby improving the conductivity of the test keys.

[0033] In the method for forming the test structure of the present invention, after forming the first test structure, a second test structure is formed on the test area. The second test structure is stacked on the first test structure along a direction perpendicular to the top surface of the substrate, and the first and second test structures are electrically isolated from each other. By stacking the large-sized first and second test structures from different process stages in a three-dimensional direction, the chip area occupied by the first and second test structures can be effectively reduced.

[0034] Furthermore, the process of forming the second test structure also includes: forming a third test structure on the test area. Along a direction perpendicular to the top surface of the substrate, the third test structure is stacked on top of the first test structure, and the first and third test structures are electrically isolated from each other. The third test structures are interspersed among the second test structures, and the second and third test structures are also electrically isolated from each other. By stacking large-sized first and third test structures from different process stages in a three-dimensional direction, and interspersing large-sized second and third test structures from the same process stage, more test structures can be added without further occupying chip area.

[0035] Furthermore, each metal layer has several parallel anti-dent openings. These anti-dent openings prevent dents in the middle area of ​​the metal layer during the planarization process, thereby improving the electrical contact of the metal layer.

[0036] Furthermore, the anti-dent openings in adjacent metal layers are perpendicular. By arranging the anti-dent openings in adjacent layers perpendicularly, the overall distribution of the first and second test keys is more uniform, thereby improving the conductivity of the test keys. Attached Figure Description

[0037] Figures 1 to 10 This is a schematic diagram of the steps in the method for forming the test structure according to an embodiment of the present invention. Detailed Implementation

[0038] As described in the background section, existing test structures still have many problems. These will be explained in detail below.

[0039] Currently, overlay capacitance testing structures are mainly used to monitor the capacitance of the overlapping portion between the gate and source / drain doped layers in MOS transistors. In later-stage processes, copper serves as the metal lead wiring layer, requiring monitoring of the isolation effect between metal strips to prevent through-through between strips in the same layer, which could lead to short circuits in the device.

[0040] Because the overlap between the gate and source / drain doped layers in a MOS transistor is small, the overlay capacitance signal obtained from testing a single MOS transistor is extremely weak. Therefore, it is usually necessary to connect hundreds of MOS transistors in parallel, sharing the source / drain doped layers, to amplify the test signal and obtain an accurate overlay capacitance. A similar approach is used in metal-isolated test structures in back-end processes. The leakage current signal between two adjacent metal strips is extremely small, so hundreds of metal strips are typically connected in parallel to obtain a larger leakage current.

[0041] Due to the special nature of these test structures, they require a much larger area than ordinary test structures, which in turn compresses the space required for the layout of other important structures and chips during the tape-out stage.

[0042] Based on this, the present invention provides a test structure and a method for forming the same. A second test structure is located on top of a first test structure, along a direction perpendicular to the top surface of the substrate. The second test structure and the first test structure are stacked together, and the first and second test structures are electrically isolated from each other. By stacking large-sized first and second test structures from different process stages in a three-dimensional direction, the chip area occupied by the first and second test structures can be effectively reduced.

[0043] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0044] Figures 1 to 10This is a schematic diagram of the steps in the method for forming the test structure according to an embodiment of the present invention.

[0045] Please refer to Figure 1 A substrate 100 is provided, which has a test area I.

[0046] In this embodiment, the substrate 100 is made of silicon.

[0047] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0048] It should be noted that in this embodiment, since the test structures are only used to detect some parameters of the functional device structure in the chip, these test structures will not be applied to the actual product after the detection. Therefore, test area I can be selected in the dicing area between chip areas, and the test structures formed on test area I will be damaged as the chip is diced after the detection is completed.

[0049] Please refer to Figures 2 to 4 , Figure 3 yes Figure 2 A schematic diagram of the specific structure of the first test structure. Figure 4 yes Figure 3 A three-dimensional schematic diagram of the middle part of the structure, forming the first test structure 101 on the test area I.

[0050] Please continue to refer to this. Figure 3 and Figure 4 In this embodiment, the first test structure 101 includes: a plurality of test gates 1011 arranged in parallel along a first direction X on a test region I, the test gates 1011 extending along a second direction Y, the first direction X being perpendicular to the second direction Y; test source / drain doped layers 1012 located in the test region I on both sides of the test gates 1011; a first metal interconnect layer 1013 electrically connected to the plurality of test gates 1011; and a second metal interconnect layer 1014 electrically connected to the plurality of test source / drain doped layers 1012, wherein the first metal interconnect layer 1013 and the second metal interconnect layer 1014 are electrically isolated from each other, and the first metal interconnect layer 1013 and the second metal interconnect layer 1014 are located on the same process layer.

[0051] It should be noted that in this embodiment, the first test structure 101 is used to detect the overlay capacitance of the overlapping portion between the gate and the test source / drain doped layer in the MOS transistor. The size of the overlapping portion is calculated based on the overlay capacitance value, and then the channel length in the actual MOS transistor is calculated. Since the overlapping portion between the gate and the test source / drain doped layer in the MOS transistor is small, the overlay capacitance signal obtained from testing a single MOS transistor is very weak. Therefore, it is usually necessary to connect hundreds of MOS transistors in parallel, sharing the same source / drain doped layer, to amplify the test signal and obtain an accurate overlay capacitance.

[0052] Please refer to Figure 5 and Figure 6 , Figure 6 yes Figure 5 The schematic diagram of the second and third test structures shows that after the first test structure 101 is formed, the second test structure 102 is formed on the test area I. The second test structure 102 is stacked on the first test structure 101 along a direction perpendicular to the top surface of the substrate 100, and the first test structure 101 and the second test structure 102 are electrically isolated from each other.

[0053] By stacking the large-sized first test structure 101 and second test structure 102 of different process stages in a three-dimensional direction, the chip area occupied by the first test structure 101 and the second test structure 102 can be effectively reduced.

[0054] In this embodiment, the second test structure 102 includes: a first metal bus 1021 and a second metal bus 1022 arranged in parallel along a first direction X; a plurality of first metal strips 1023 arranged in parallel along a second direction Y, wherein the first metal bus 1021 connects the plurality of first metal strips 1023, and the first direction X is perpendicular to the second direction Y; and a plurality of second metal strips 1024 arranged in parallel along the second direction Y, wherein the second metal bus 1022 connects the plurality of second metal strips 1024, wherein the first metal strips 1023 and the second metal strips 1024 are staggered, and the projections of the first metal strips 1023 and the second metal strips 1024 along the second direction Y have an overlapping area.

[0055] It should be noted that in this embodiment, the second test structure 102 is used to detect the isolation between metals. If a short circuit occurs between the metals, leakage current will be detected. Since the leakage current signal between two adjacent metal strips is extremely small, hundreds of metal strips are connected in parallel to obtain a larger leakage current.

[0056] In this embodiment, the process of forming the second test structure 102 further includes: forming a third test structure 103 on the test region I. The third test structure 103 is stacked on the first test structure 101 along a direction perpendicular to the top surface of the substrate 100, and the first test structure 101 and the third test structure 103 are electrically isolated from each other. The third test structure 103 is interposed between the second test structures 102, and the second test structures 102 and the third test structure 103 are electrically isolated from each other.

[0057] By stacking large-sized first test structures 101 and third test structures 103 at different process stages in a three-dimensional direction, and interleaving large-sized second test structures 102 and third test structures 103 at the same process stage, more test structures can be added without further occupying chip area.

[0058] In this embodiment, the third test structure 103 includes a resistor strip 1031, which is interspersed between a plurality of first metal strips 1023 and a plurality of second metal strips 1024. The resistor strip 1031, the first metal bus 1021, the second metal bus 1022, the first metal strip 1023 and the second metal strip 1024 are located on the same process layer.

[0059] It should be noted that in this embodiment, the third test structure 103 is used to detect the resistance value of the sheet resistor. Since the resistance value of a single sheet resistor is extremely small, hundreds of sheet resistors are connected in series to obtain a more accurate resistance value.

[0060] In this embodiment, the process order of the second test structure 102 and the third test structure 103 is after the process order of the first metal interconnect layer 1013 and the second metal interconnect layer 1014. Furthermore, the second test structure 102 and the third test structure 103 are electrically isolated from the first metal interconnect layer 1013 and the second metal interconnect layer 1014 by an insulating dielectric layer 107.

[0061] In other embodiments, a third test structure may not be formed.

[0062] Please refer to Figure 7 This forms a plurality of first test keys 104 and a plurality of second test keys 105. The first test structure 101 is electrically connected to the plurality of first test keys 104 respectively, and the second test structure 102 is electrically connected to the plurality of second test keys 105 respectively.

[0063] In this embodiment, a plurality of first test keys 104 are electrically connected to the first metal interconnect layer 1013 and the second metal interconnect layer 1014, respectively. Specifically, there are two first test keys 104, and the two first test keys 104 are electrically connected to the first metal interconnect layer 1013 and the second metal interconnect layer 1014, respectively.

[0064] In this embodiment, a plurality of second test keys 105 are electrically connected to the first metal bus 1021 and the second metal bus 1022, respectively. Specifically, there are two second test keys 105, and the two second test keys 105 are electrically connected to the first metal bus 1021 and the second metal bus 1022, respectively.

[0065] Please continue to refer to this. Figure 7 In the process of forming the first test key 104 and the second test key 105, the process also includes forming a plurality of third test keys 106, and the third test structure 103 is electrically connected to the plurality of third test keys 106 respectively.

[0066] In this embodiment, a plurality of third test keys 106 are electrically connected to the two opposite ends of the resistor strip 1031. Specifically, there are two third test keys 106, and the two third test keys 106 are electrically connected to the two opposite ends of the resistor strip 1031.

[0067] Please refer to Figure 8 and Figure 9 , Figure 9 yes Figure 8 A schematic diagram of the cross section along line AA is shown. In this embodiment, both the first test key 104 and the second test key 105 include: a plurality of metal layers 1041 arranged sequentially along a direction perpendicular to the top surface of the substrate 100, adjacent metal layers 1041 being electrically connected, and the plurality of metal layers 1041 having the same projection area toward the substrate 100.

[0068] In this embodiment, adjacent metal layers 1041 are electrically connected by a number of conductive plugs (not shown).

[0069] Please continue to refer to this. Figure 8 In this embodiment, each metal layer 1041 has a plurality of parallel anti-dent openings 1042. The anti-dent openings 1042 can prevent the problem of dents in the middle area of ​​the metal layer 1041 during the planarization process, thereby improving the electrical contact of the metal layer 1041.

[0070] Please refer to Figure 10In this embodiment, the anti-dent openings 1042 in adjacent metal layers 1041 are perpendicular. By arranging the anti-dent openings 1042 in adjacent layers perpendicularly, the overall distribution of the first test key 104 and the second test key 105 is more uniform, thereby improving the conductivity of the test keys.

[0071] In this embodiment, since the second test structure 102 and the third test structure 103 are located in the same process layer, the second test bond 105 and the third test bond 106 have the same extension length and the same structure along the direction perpendicular to the top surface of the substrate 100. Therefore, the specific structure of the third test bond 106 will not be described in detail here.

[0072] It should be noted that, in this embodiment, since the first test structure 101 is located below the second test structure 102 and the third test structure 103, the extension length of the first test bond 104 is greater than the extension lengths of the second test bond 105 and the third test bond 106 in the direction perpendicular to the top surface of the substrate 100, meaning the number of stacked metal layers 1041 is different. Furthermore, during the formation of the second test structure 102 and the third test structure 103, a portion of the metal layer 1041 of the first test bond 104 is also formed simultaneously.

[0073] Accordingly, this invention also provides a test structure, please refer to the following: Figure 10 The device includes: a substrate 100 having a test region I; a first test structure 101 located on the test region I; a second test structure 102 located on the test region I; the second test structure 102 is located on the first test structure 101 and is arranged in a direction perpendicular to the top surface of the substrate 100, the second test structure 102 and the first test structure 101 are stacked and electrically isolated from each other; a plurality of first test keys 104 electrically connected to the first test structure 101; and a plurality of second test keys 105 electrically connected to the second test structure 102.

[0074] By stacking the large-sized first test structure 101 and second test structure 102 of different process stages in a three-dimensional direction, the chip area occupied by the first test structure 101 and the second test structure 102 can be effectively reduced.

[0075] Please continue to refer to this. Figure 3 and Figure 4In this embodiment, the first test structure 101 includes: a plurality of test gates 1011 arranged in parallel along a first direction X on a test region I, the test gates 1011 extending along a second direction Y, the first direction X being perpendicular to the second direction Y; test source / drain doped layers 1012 located in the test region I on both sides of the test gates 1011; a first metal interconnect layer 1013 electrically connected to the plurality of test gates 1011; and a second metal interconnect layer 1014 electrically connected to the plurality of test source / drain doped layers 1012, wherein the first metal interconnect layer 1013 and the second metal interconnect layer 1014 are electrically isolated from each other, and the first metal interconnect layer 1013 and the second metal interconnect layer 1014 are located on the same process layer.

[0076] In this embodiment, a plurality of first test keys 104 are electrically connected to the first metal interconnect layer 1013 and the second metal interconnect layer 1014, respectively.

[0077] Please continue to refer to this. Figure 6 In this embodiment, the second test structure 102 includes: a first metal bus 1021 and a second metal bus 1022 arranged in parallel along a first direction X; a plurality of first metal strips 1023 arranged in parallel along a second direction Y, wherein the first metal bus 1021 connects the plurality of first metal strips 1023, and the first direction X is perpendicular to the second direction Y; and a plurality of second metal strips 1024 arranged in parallel along the second direction Y, wherein the second metal bus 1022 connects the plurality of second metal strips 1024, wherein the first metal strips 1023 and the second metal strips 1024 are staggered, and the projections of the first metal strips 1023 and the second metal strips 1024 along the second direction Y have an overlapping area.

[0078] In this embodiment, several second test keys 105 are electrically connected to the first metal bus 1021 and the second metal bus 1022, respectively.

[0079] Please refer to 5. In this embodiment, it further includes: a third test structure 103 located on the test area I; the third test structure 103 is located on the first test structure 101, and along a direction perpendicular to the top surface of the substrate 100, the third test structure 103 and the first test structure 101 are stacked and electrically isolated from each other; the third test structure 103 is interposed between the second test structures 102, and the second test structures 102 and the third test structure 103 are electrically isolated from each other; and a plurality of third test keys 106 electrically connected to the third test structure 103.

[0080] By stacking large-sized first test structures 101 and third test structures 103 at different process stages in a three-dimensional direction, and interleaving large-sized second test structures 102 and third test structures 103 at the same process stage, more test structures can be added without further occupying chip area.

[0081] In other embodiments, a third test structure may not be formed.

[0082] Please continue to refer to this. Figure 6 In this embodiment, the third test structure 103 includes a resistor strip 1031, which is interspersed between a plurality of first metal strips 1023 and a plurality of second metal strips 1024. The resistor strip 1031, the first metal bus 1021, the second metal bus 1022, the first metal strip 1023 and the second metal strip 1024 are located on the same process layer.

[0083] In this embodiment, several third test keys 106 are electrically connected to the two ends opposite to the resistor bar 1031.

[0084] Please continue to refer to this. Figure 8 and Figure 9 In this embodiment, both the first test key 104 and the second test key 105 include: a plurality of metal layers 1041 arranged sequentially along a direction perpendicular to the top surface of the substrate 100, adjacent metal layers 1041 being electrically connected, and the plurality of metal layers 1041 having the same projection area toward the substrate 100.

[0085] Please continue to refer to this. Figure 8 In this embodiment, each metal layer 1041 has a plurality of parallel anti-dent openings 1042. The anti-dent openings 1042 can prevent the problem of dents in the middle area of ​​the metal layer 1041 during the planarization process, thereby improving the electrical contact of the metal layer 1041.

[0086] Please continue to refer to this. Figure 10 In this embodiment, the anti-dent openings 1042 in adjacent metal layers 1041 are perpendicular. By arranging the anti-dent openings 1042 in adjacent layers perpendicularly, the overall distribution of the first test key 104 and the second test key 105 is more uniform, thereby improving the conductivity of the test keys.

[0087] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Substrate, the substrate having a test area; A first test structure located on the test area; The second test structure is located on the test area; The second test structure is located on the first test structure along a direction perpendicular to the top surface of the substrate. The second test structure and the first test structure are stacked and electrically isolated from each other. A plurality of first test keys electrically connected to the first test structure; A plurality of second test keys electrically connected to the second test structure.

2. The test structure as described in claim 1, characterized in that, The first test structure includes: a plurality of test gates arranged in parallel along a first direction on the test region, the test gates extending along a second direction, the first direction being perpendicular to the second direction; test source / drain doped layers located on both sides of the test gates within the test region; a first metal interconnect layer electrically connected to the plurality of test gates; and a second metal interconnect layer electrically connected to the plurality of source / drain doped layers, wherein the first metal interconnect layer and the second metal interconnect layer are electrically isolated from each other, and the first metal interconnect layer and the second metal interconnect layer are located on the same process layer.

3. The test structure as described in claim 2, characterized in that, A plurality of the first test keys are electrically connected to the first metal interconnect layer and the second metal interconnect layer, respectively.

4. The test structure as described in claim 1, characterized in that, The second test structure includes: a first metal bus and a second metal bus arranged in parallel along a first direction; a plurality of first metal strips arranged in parallel along a second direction, wherein the first metal bus connects to the plurality of first metal strips, and the first direction is perpendicular to the second direction; a plurality of second metal strips arranged in parallel along the second direction, wherein the second metal bus connects to the plurality of second metal strips, wherein the first metal strips and the second metal strips are staggered, and the projections of the first metal strips and the second metal strips along the second direction have an overlapping area.

5. The test structure as described in claim 4, characterized in that, Several of the second test keys are electrically connected to the first metal bus and the second metal bus, respectively.

6. The test structure as described in claim 4, characterized in that, Also includes: A third test structure located on the test area; The third test structure is located on the first test structure along a direction perpendicular to the top surface of the substrate. The third test structure and the first test structure are stacked together, and the first test structure and the third test structure are electrically isolated from each other. The third test structure is interspersed between the second test structures, and the second test structures and the third test structure are electrically isolated from each other. A plurality of third test keys electrically connected to the third test structure.

7. The test structure as described in claim 6, characterized in that, The third test structure includes a resistor strip, which is interspersed between a plurality of first metal strips and a plurality of second metal strips. The resistor strip, the first metal bus, the second metal bus, the first metal strip, and the second metal strip are located on the same process layer.

8. The test structure as described in claim 7, characterized in that, Several of the third test keys are electrically connected to the two ends opposite to the resistor strip.

9. The test structure as described in claim 1, characterized in that, Both the first test key and the second test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate.

10. The test structure as described in claim 9, characterized in that, Each of the metal layers has several parallel dent-proof openings.

11. The test structure as described in claim 10, characterized in that, The anti-dent openings in adjacent metal layers are perpendicular to each other.

12. A method for forming a test structure, characterized in that, include: A substrate is provided, the substrate having a test area; A first test structure is formed on the test area; After the first test structure is formed, a second test structure is formed on the test area. The second test structure is stacked on the first test structure along a direction perpendicular to the top surface of the substrate, and the first test structure and the second test structure are electrically isolated from each other. A plurality of first test keys and a plurality of second test keys are formed. The first test structure is electrically connected to the plurality of first test keys, and the second test structure is electrically connected to the plurality of second test keys.

13. The method for forming the test structure as described in claim 12, characterized in that, The first test structure includes: a plurality of test gates arranged in parallel along a first direction on the test region, the test gates extending along a second direction, the first direction being perpendicular to the second direction; test source / drain doped layers located on both sides of the test gates within the test region; a first metal interconnect layer electrically connected to the plurality of test gates; and a second metal interconnect layer electrically connected to the plurality of source / drain doped layers, wherein the first metal interconnect layer and the second metal interconnect layer are electrically isolated from each other, and the first metal interconnect layer and the second metal interconnect layer are located on the same process layer.

14. The method for forming the test structure as described in claim 13, characterized in that, A plurality of the first test keys are electrically connected to the first metal interconnect layer and the second metal interconnect layer, respectively.

15. The method for forming the test structure as described in claim 12, characterized in that, The second test structure includes: a first metal bus and a second metal bus arranged in parallel along a first direction; a plurality of first metal strips arranged in parallel along a second direction, wherein the first metal bus connects to the plurality of first metal strips, and the first direction is perpendicular to the second direction; a plurality of second metal strips arranged in parallel along the second direction, wherein the second metal bus connects to the plurality of second metal strips, wherein the first metal strips and the second metal strips are staggered, and the projections of the first metal strips and the second metal strips along the second direction have an overlapping area.

16. The method for forming the test structure as described in claim 15, characterized in that, Several of the second test keys are electrically connected to the first metal bus and the second metal bus, respectively.

17. The method for forming the test structure as described in claim 15, characterized in that, The process of forming the second test structure further includes: forming a third test structure on the test area, wherein the third test structure is stacked on the first test structure along a direction perpendicular to the top surface of the substrate, and the first test structure and the third test structure are electrically isolated from each other; the third test structure is interposed between the second test structures, and the second test structure and the third test structure are electrically isolated from each other; the process of forming the first test bond and the second test bond further includes: forming a plurality of third test bonds, wherein the third test structure is electrically connected to the plurality of the third test bonds respectively.

18. The method for forming the test structure as described in claim 17, characterized in that, The third test structure includes a resistor strip, which is interspersed between a plurality of first metal strips and a plurality of second metal strips. The resistor strip, the first metal bus, the second metal bus, the first metal strip, and the second metal strip are located on the same process layer.

19. The method for forming the test structure as described in claim 18, characterized in that, Several of the third test keys are electrically connected to the two ends opposite to the resistor strip.

20. The method for forming the test structure as described in claim 12, characterized in that, Both the first test key and the second test key include: a plurality of metal layers arranged sequentially along a direction perpendicular to the top surface of the substrate, adjacent metal layers being electrically connected, and the plurality of metal layers having the same projection area toward the substrate.

21. The method for forming the test structure as described in claim 20, characterized in that, Each of the metal layers has several parallel dent-proof openings.

22. The method for forming the test structure as described in claim 21, characterized in that, The anti-dent openings in adjacent metal layers are perpendicular to each other.

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