Display substrate, preparation method thereof and display device

Abstract

Embodiments of the present disclosure provide a display substrate, a preparation method thereof and a display device. The display substrate comprises, in sequence from one side of a substrate, a first metal layer, a first insulating layer, a semiconductor layer, a second insulating layer, a second metal layer, a third insulating layer, a third metal layer, an insulating protective layer and a bridge electrode. The first metal layer comprises a first metal trace. The semiconductor layer comprises a first active layer. The first active layer comprises a first channel region. The second metal layer comprises a first gate electrode and a second metal trace connected to each other. A first electrode and a second electrode are connected to the first active layer through a first via and a second via of the third insulating layer, respectively. The insulating protective layer has a third via and a fourth via. The third via exposes a part of a surface of the first gate metal trace. The fourth via exposes a part of a surface of the second metal trace. The bridge electrode is connected to the first metal trace and the second metal trace through the third via and the fourth via, respectively. The technical solution of the present disclosure can improve yield.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display device, and particularly relates to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0002] Thin film transistors are widely used as switching components and driving components in various display devices. In the related art, the semiconductor layer of the thin film transistor of the display substrate still has the problem that the film is reduced due to damage in the forming process, thereby reducing the yield of the display substrate. SUMMARY

[0003] Embodiments of the present disclosure provide a display substrate, a preparation method thereof and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display substrate, comprising:

[0005] A first metal layer is located on one side of the substrate, and the first metal layer comprises a first metal trace;

[0006] A first insulating layer is located on the side of the first metal layer away from the substrate;

[0007] A semiconductor layer is located on the side of the first insulating layer away from the substrate, and the semiconductor comprises a first active layer, and the first active layer comprises a first channel region, and the orthographic projection of the first channel region on the substrate is located within the orthographic projection of the first metal trace on the substrate;

[0008] A second insulating layer is located on the side of the semiconductor layer away from the substrate;

[0009] A second metal layer is located on the side of the second insulating layer away from the substrate, and the second metal layer comprises a first gate electrode and a second metal trace, and the second metal trace is connected to the first gate electrode;

[0010] A third insulating layer is located on the side of the second metal layer away from the substrate, and the third insulating layer is provided with a first via hole and a second via hole, and the first via hole and the second via hole both expose part of the surface of the first active layer;

[0011] A third metal layer is located on the side of the third insulating layer away from the substrate, and the third metal layer comprises a first electrode and a second electrode, and the first electrode and the second electrode are connected to the first active layer through the first via hole and the second via hole, respectively;

[0012] An insulating protective layer is located on the side of the third metal layer away from the substrate, and the insulating protective layer is provided with a third via hole and a fourth via hole, the third via hole penetrates the insulating protective layer and the first insulating layer to expose part of the surface of the first metal trace, and the fourth via hole exposes part of the surface of the second metal trace;

[0013] The bridge electrode is located on a side of the insulation protection layer away from the substrate, and the bridge electrode is connected with the first metal trace and the second metal trace through the third via hole and the fourth via hole respectively.

[0014] In some possible implementation manners, the third insulation layer further has a fifth via hole penetrating through the third insulation layer to expose a surface of the first insulation layer, and a projection of the third via hole on the substrate is located within a projection of the fifth via hole on the substrate.

[0015] The third insulation layer further has a sixth via hole, and a projection of the fourth via hole on the substrate is located within a projection of the sixth via hole on the substrate.

[0016] In some possible implementation manners, the display substrate further includes a pixel electrode located in the display area, the pixel electrode is located on a side of the insulation protection layer away from the substrate, and the bridge electrode is arranged in the same layer as the pixel electrode.

[0017] In some possible implementation manners, the display substrate further includes a non-display area located outside the display area, and the first active layer and the bridge electrode are located in the non-display area.

[0018] In some possible implementation manners, the semiconductor layer further includes a second active layer located in the display area, the second metal layer further includes a second gate electrode located in the display area, the third metal layer further includes a third electrode and a fourth electrode, the third insulation layer has a seventh via hole and an eighth via hole, the seventh via hole and the eighth via hole both expose part of a surface of the second active layer, and the third electrode and the fourth electrode are connected with the second active layer through the seventh via hole and the eighth via hole respectively.

[0019] The insulation protection layer further has a ninth via hole exposing at least part of a surface of the fourth electrode, and the pixel electrode is connected with the fourth electrode through the ninth via hole.

[0020] In some possible implementation manners, the first metal layer further includes an opaque portion, and the second active layer includes a second channel region, a projection of the second channel region on the substrate is located within a projection of the opaque portion on the substrate.

[0021] In some possible implementation manners, the insulation protection layer includes, in sequence and arranged on a side of the third metal layer away from the substrate, a fourth insulation layer and a planar layer, the insulation protection layer further has a ninth via hole exposing at least part of a surface of the fourth electrode, the display substrate further includes a fifth insulation layer located on a side of the planar layer away from the substrate, the pixel electrode includes a first transparent electrode located between the planar layer and the fifth insulation layer, and a second transparent electrode located on a side of the fifth insulation layer away from the substrate, one of the first transparent electrode and the second transparent electrode is connected with the fourth electrode through the ninth via hole, and the bridge electrode is arranged in the same layer as the first transparent electrode or the second transparent electrode.

[0022] In some possible implementations, the material of the semiconductor layer includes an oxide semiconductor.

[0023] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a preparation method of a display substrate, the method comprising:

[0024] forming a first metal layer on one side of the substrate, the first metal layer comprising a first metal trace;

[0025] forming a first insulating layer on a side of the first metal layer away from the substrate;

[0026] forming a semiconductor layer on a side of the first insulating layer away from the substrate, the semiconductor layer comprising a first active layer, the first active layer comprising a first channel region, a footprint of the first channel region on the substrate being located within a footprint of the first metal trace on the substrate;

[0027] forming a second insulating layer on a side of the semiconductor layer away from the substrate;

[0028] forming a second metal layer on a side of the second insulating layer away from the substrate, the second metal layer comprising a first gate electrode and a second metal trace, the second metal trace being connected to the first gate electrode;

[0029] forming a third insulating layer on a side of the second metal layer away from the substrate, the third insulating layer being provided with a first via hole and a second via hole, the first via hole and the second via hole both exposing part of a surface of the first active layer;

[0030] forming a third metal layer on a side of the third insulating layer away from the substrate, the third metal layer comprising a first electrode and a second electrode, the first electrode and the second electrode being connected to the first active layer through the first via hole and the second via hole respectively;

[0031] forming an insulating protective layer on a side of the third metal layer away from the substrate, the insulating protective layer being provided with a third via hole and a fourth via hole, the third via hole penetrating through the insulating protective layer and the first insulating layer to expose part of a surface of the first metal trace, the fourth via hole exposing part of a surface of the first gate electrode;

[0032] forming a bridging electrode on a side of the insulating protective layer away from the substrate, the bridging electrode being connected to the first metal trace and the second metal trace through the third via hole and the fourth via hole respectively.

[0033] In some possible implementations, the method further comprises, in the process of forming the third insulating layer, forming a fifth via hole and a sixth via hole penetrating through the third insulating layer, the fifth via hole exposing a surface of the first insulating layer, a footprint of the third via hole on the substrate being located within a footprint of the fifth via hole on the substrate;

[0034] The orthogonal projection of the fourth via on the substrate substrate is located within the orthogonal projection of the sixth via on the substrate substrate.

[0035] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the display substrate of any one of the first aspect.

[0036] The technical solutions of the embodiments of the present disclosure can achieve the following beneficial effects: the semiconductor layer can be prevented from being damaged, the semiconductor layer film can be reduced, and the product yield can be improved.

[0037] The above summary is intended to illustrate the present description and is not intended to limit in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features will be readily apparent to those skilled in the art by reference to the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0038] In the drawings, like reference numerals refer to same or similar functionalities throughout the several views. The drawings are not necessarily to scale. It is to be understood that the drawings only depict several embodiments in accordance with the present disclosure and should not be considered limiting.

[0039] Figure 1 A schematic plan view of a display substrate of a related art;

[0040] Figure 2 A schematic A-A cross-sectional view of the display substrate of the related art; Figure 1

[0041] Figure 3 A schematic plan view of a display substrate of the embodiments of the present disclosure;

[0042] Figure 4 A schematic B-B cross-sectional view of the display substrate of the embodiments of the present disclosure; Figure 3

[0043] A schematic microscope view of a first opening M1 position of the display substrate of the related art shown in FIG. 1; Figure 5A Figure 1 A schematic microscope view of a first via K1 position of the display substrate of the embodiments of the present disclosure;

[0044] Figure 5B A schematic microscope view of a connection position between the connection electrode and the first metal trace in the related art shown in FIG. 1;

[0045] Figure 6A Figure 2 A schematic microscope view of a connection position between the connection electrode and the first metal trace in the related art shown in FIG. 1;

[0046] Figure 6B A schematic microscope view of a connection position between the connection electrode and the first metal trace in the related art shown in FIG. 1; Figure 2 ​​​Microscope diagram of the connection position of the connection electrode and the second metal trace in the related art;

[0047] Figure 6C Microscope diagram of the connection position of the first metal trace and the bridge electrode in the embodiment of the present disclosure;

[0048] Figure 6D Microscope diagram of the connection position of the second metal trace and the bridge electrode in the embodiment of the present disclosure;

[0049] Figure 7 Sectional view diagram of the display substrate in another embodiment of the present disclosure;

[0050] Figure 8 Plan view diagram of the display substrate in another embodiment of the present disclosure;

[0051] Figure 9 C-C sectional view diagram of the display substrate in the embodiment of the present disclosure; Figure 8

[0052] Figure 10 Etching via hole diagram of the third insulating layer of the display substrate in the embodiment of the present disclosure;

[0053] Figure 11 Un-etching via hole diagram of the insulating protective layer of the display substrate in the embodiment of the present disclosure;

[0054] Figure 12 Etching via hole diagram of the insulating protective layer of the display substrate in the embodiment of the present disclosure.

[0055] Explanation of the reference signs:

[0056] 10, first metal layer; 20, first insulating layer; 30, semiconductor layer; 40, second insulating layer; 50, second metal layer; 60, third insulating layer; 70, third metal layer; 80, insulating protective layer;

[0057] 11, first metal trace; 12, light shielding layer;

[0058] 31, first active layer; 31, second active layer;

[0059] 51, first gate electrode; 52, second metal trace; 53, second gate electrode;

[0060] 71, first pole; 72, second pole; 73, third pole; 74, fourth pole;

[0061] 81, fourth insulating layer; 82, planar layer; 83, fifth insulating layer;

[0062] 91, bridge electrode; 92, pixel electrode; 921, first transparent electrode; 922, second transparent electrode.​ DETAILED DESCRIPTION

[0063] Hereinafter, only certain exemplary embodiments will be described simply. As can be appreciated by those skilled in the art, the described embodiments can be modified in various different ways without departing from the spirit or scope of the disclosure. Therefore, the drawings and descriptions are to be regarded as illustrative in nature rather than restrictive.

[0064] A display substrate is controlled by a thin film transistor control element or a peripheral driving circuit. The thin film transistor of the display substrate includes a bottom-gate thin film transistor and a top-gate thin film transistor. The back channel etching (BCE) of the bottom-gate thin film transistor is inconvenient to control, and is prone to affect the performance of the bottom-gate thin film transistor due to over-etching. The use of an etching stopper (ES) to solve the problem of over-etching increases the process complexity. The bottom-gate thin film transistor is not easy to realize self-alignment, the back exposure technology has compatibility problems with the existing process, and the traditional preparation method will cause a larger overlap area in the bottom-gate thin film transistor, resulting in a larger overlap capacitance, which is not conducive to reducing the channel size. The overlap capacitance will reduce the working speed of the driving circuit, and is not suitable for driving high-resolution active matrix organic light-emitting diode display devices.

[0065] The top-gate thin film transistor does not have the problem of over-etching damage. The gate insulating layer in the top-gate thin film transistor can protect the active layer above the active layer. Moreover, the top-gate thin film transistor can realize self-alignment, the process is relatively simple, the overlap area can be avoided, there is no overlap capacitance, the channel size of the thin film transistor can be more accurately controlled, and a shorter channel can be realized.

[0066] Figure 1 FIG. 1 is a plan view of a display substrate of the related art, Figure 2 FIG. 2 is a cross-sectional view of the display substrate of FIG. 1 along line A-A. Figure 1 FIG. 3 is a cross-sectional view of the display substrate of FIG. 1 along line B-B. Figure 1 FIG. 4 is a cross-sectional view of the display substrate of FIG. 1 along line C-C. Figure 2 As shown in FIGS. 1 to 4, in the related art, the display substrate can include a substrate P, a first metal layer 10, a first insulating layer 20, a semiconductor layer 30, a second insulating layer 40, a second metal layer 50, a third insulating layer 60, and a third metal layer 70.

[0067] The first metal layer 10 is located on one side of the substrate P, the first metal layer 10 includes a first metal trace 11, the first insulating layer 20 is located on the side of the first metal layer 10 away from the substrate P, the semiconductor layer 30 is located on the side of the first insulating layer 20 away from the substrate P, the semiconductor layer 30 includes a first active layer 31, the second insulating layer 40 is located on the side of the semiconductor layer 30 away from the substrate P, the second metal layer 50 is located on the side of the second insulating layer 40 away from the substrate P, the second metal layer 50 includes a first gate electrode 51 and a second metal trace 52, the second metal trace 52 and the first gate electrode 51 are connected, the third insulating layer 60 is located on the side of the second metal layer 50 away from the substrate P, the third insulating layer 60 is provided with a first opening M1 and a second opening M2, and the first opening M1 and the second opening M2 both expose part of the surface of the first active layer 31.

[0068] The third metal layer 70 is located on the side of the third insulating layer 60 away from the substrate P, the third metal layer 70 includes a first pole 71, a second pole 72 and a connecting electrode L, the first pole 71 and the second pole 72 are connected with the first active layer 31 through the first opening M1 and the second opening M2 respectively, the third insulating layer 60 is further provided with a third opening M3, the first insulating layer 20 is provided with a fourth opening M4, the orthographic projection of the third opening M3 on the substrate P is located within the orthographic projection of the fourth opening M4 on the substrate P, the third insulating layer 60 is further provided with a fifth opening M5, and the connecting electrode L is connected with the first metal trace 11 through the third opening M3 and the fourth opening M4, and the connecting electrode L is connected with the second metal trace 52 through the fifth opening M5.

[0069] In the preparation process of the display substrate, in order to connect the first metal trace 11 and the second metal trace 52, in the process of etching the third insulating layer 60 and the first insulating layer 20 together to form the openings, the third insulating layer 60 is etched first to form the first opening M1, the second opening M2, the third opening M3 and the fifth opening M5, after the first opening M1 and the second opening M2 are formed, part of the surface of the first active layer 31 is exposed through the first opening M1 and the second opening M2, and when the fourth opening M4 of the first insulating layer 20 is etched subsequently, the first active layer 31 partially exposed through the first opening M1 and the second opening M2 will continue to be exposed in the etching environment, thereby causing the first active layer 31 to be damaged, causing the first active layer 31 to have a significant film reduction after the fourth opening M4 is formed, and reducing the yield of the display substrate.

[0070] In order to solve the problem of damage to the active layer of the display substrate in the related art, the embodiments of the present disclosure provide a display substrate. The technical solutions of the display substrate will be described below with reference to the drawings.

[0071] Figure 3 A plan view of the display substrate of the embodiments of the present disclosure, Figure 4For Figure 3 a display substrate. Referring to FIG. 1, a display substrate can include a substrate P, a first metal layer 10, a first insulating layer 20, a semiconductor layer 30, a second insulating layer 40, a second metal layer 50, a third insulating layer 60, a third metal layer 70, an insulating protective layer 80, and a bridge electrode 91. Figure 3 and Figure 4 The display substrate can include a substrate P, a first metal layer 10, a first insulating layer 20, a semiconductor layer 30, a second insulating layer 40, a second metal layer 50, a third insulating layer 60, a third metal layer 70, an insulating protective layer 80, and a bridge electrode 91.

[0072] The first metal layer 10 is located on one side of the substrate P, and the first metal layer 10 includes a first metal trace 11. The first insulating layer 20 is located on a side of the first metal layer 10 away from the substrate P. The semiconductor layer 30 is located on a side of the first insulating layer 20 away from the substrate P, and the semiconductor layer 30 includes a first active layer 31, and the first active layer 31 includes a first channel region, and a projection of the first channel region on the substrate P is located within a projection of the first metal trace 11 on the substrate P.

[0073] The second insulating layer 40 is located on a side of the semiconductor layer 30 away from the substrate P, and the second insulating layer 40 is a gate insulating layer. The second metal layer 50 is located on a side of the second insulating layer 40 away from the substrate P, and the second metal layer 50 includes a first gate electrode 51 and a second metal trace 52, the second metal trace 52 and the first gate electrode 51 are connected, and the second metal trace 52 and the first gate electrode 51 are located on the same layer and are formed by the same patterning process.

[0074] The third insulating layer 60 is located on a side of the second metal layer 50 away from the substrate P, and the third insulating layer 60 is provided with a first via K1 and a second via K2, and the first via K1 and the second via K2 both expose part of the surface of the first active layer 31. The third metal layer 70 is located on a side of the third insulating layer 60 away from the substrate P, and the third metal layer 70 includes a first pole 71 and a second pole 72, and the first pole 71 and the second pole 72 are connected to the first active layer 31 through the first via K1 and the second via K2, respectively. Exemplarily, the first active layer 31 further includes a first conductorization region and a second conductorization region located on both sides of the first channel region, the first pole 71 is connected to the first conductorization region through the first via K1, and the second pole 72 is connected to the second conductorization region through the second via K2.

[0075] The insulating protective layer 80 is located on the side of the third metal layer 70 away from the substrate P, and the insulating protective layer 80 is provided with a third via hole K3 and a fourth via hole K4. The third via hole K3 exposes part of the surface of the first metal trace 11 through the insulating protective layer 80 and the first insulating layer 20. The fourth via hole K4 exposes part of the surface of the second metal trace 52. The bridge electrode 91 is located on the side of the insulating protective layer 80 away from the substrate P, and the bridge electrode 91 is connected with the first metal trace 11 and the second metal trace 52 through the third via hole K3 and the fourth via hole K4, respectively.

[0076] The first metal trace 11 and the second metal trace 52 are connected through the bridge electrode 91, so that the first metal trace 11 and the first gate electrode 51 are connected, and part of the first metal trace 11 and the first gate electrode 51 form a double-gate layer structure. In this way, the first gate electrode 51, the first metal trace 11, the first active layer 31, the first electrode 71, and the second electrode 72 form a double-gate thin film transistor. The first metal trace 11 and the first gate electrode 51 can simultaneously receive the same gate signal, thereby ensuring that the first active layer 31 is simultaneously driven. When the display substrate receives an opening signal, the first active layer 31 generates induced charges on the surface under the joint action of the first metal trace 11 and the first gate electrode 51, thereby forming a large current open state, and the double-gate thin film transistor is turned on. The first active layer 31 in such a thin film transistor can be driven by the same electrical signal of the first metal trace 11 and the first gate electrode 51, thereby increasing the open-state current of the thin film transistor and improving the stability and driving ability of the thin film transistor.

[0077] The semiconductor layer 30 includes the first active layer 31, and the first active layer 31 includes a first channel region. The orthogonal projection of the first channel region on the substrate P is located within the orthogonal projection of the first metal trace 11 on the substrate P. The first metal trace 11 includes a first portion and a second portion connected to each other. The orthogonal projection of the first portion on the substrate P coincides with the orthogonal projection of the first channel region on the substrate P. The orthogonal projection of the second portion on the substrate P does not overlap with the orthogonal projection of the first channel region on the substrate P. The second portion and the second metal trace 52 are connected through the bridge electrode 91, i.e., the second portion serves as a bridge portion, and the first portion serves as a gate electrode. The first portion and the first gate electrode 51 form a double-gate layer structure.

[0078] Exemplarily, the first electrode 71 can be a drain electrode, and the second electrode 72 can be a source electrode, or the first electrode 71 can be a source electrode, and the second electrode 72 can be a drain electrode.

[0079] The second metal layer 50 includes the first gate electrode 51 and the second metal trace 52. The second metal trace 52 is connected with the first gate electrode 51. The second metal trace 52 and the first gate electrode 51 are connected through the bridge electrode 91. Figure 4The second metal trace 52 is arranged at intervals on the cross-sectional view shown, and is connected as a bridge to the first metal trace 11.

[0080] Figure 5A For Figure 1 A microscope diagram of a first opening M1 position of a display substrate of the related art shown, Figure 5B A microscope diagram of a first via K1 position of a display substrate of an embodiment of the present disclosure. As shown in Figure 2 And Figure 5A As shown, the active layer part of the display substrate is damaged and presents a jagged shape. When a fourth opening M4 of the first insulating layer 20 is etched subsequently, the first active layer 31 exposed by the first opening M1 will continue to be exposed in the etching environment, causing the first active layer 31 at the first opening M1 position to present a jagged damage, reducing the yield of the display substrate. As shown in Figure 4 And Figure 5B As shown, the etching of the third insulating layer 60 is stopped after the first via K1 is formed, avoiding over-etching of the first active layer 31 at the first via K1 position, so that the active layer of the display substrate presents a flat shape. Comparing Figure 5A And Figure 5B It can be seen that the display substrate of the embodiment of the present disclosure can avoid damage to the active layer and improve the yield of the product.

[0081] As shown in Figure 5A The first insulating layer 10 is provided with a first opening M1, which exposes part of the surface of the first active layer 31. The sidewall angle of the first opening M1 is arranged to be large first and small later along the vertical substrate direction by the first insulating layer 10. The sidewall angle of the first opening M1 close to the first active layer 31 can be 62° or 64°, and the sidewall angle of the first opening M1 away from the first active layer 31 can be 25° or 28°

[0082] As shown in Figure 5B The first insulating layer 10 is provided with a first via K1, which exposes part of the surface of the first active layer 31. The sidewall angle of the first via K1 is arranged to be large first and small later along the vertical substrate direction by the first insulating layer 10.

[0083] Exemplarily, the sidewall angle of the first via K1 close to the first active layer 31 can be 50°-60°, and the sidewall angle of the first via K1 away from the first active layer 31 can be 25°-35°. For example, the sidewall angle of the first via K1 close to the first active layer 31 can be 54° or 55°, and the sidewall angle of the first via K1 away from the first active layer 31 can be 26° or 27°, which is smaller than the sidewall angle of the first via close to the first active layer 31 of the related art.

[0084] Referring to Figure 1 And Figure 2As shown, in the related art display substrate, the first metal trace 11 and the second metal trace 52 are connected by the connection electrode L, and the connection electrode L is arranged in the same layer as the first electrode 71 and the second electrode 72. When the third insulating layer 60 and the first insulating layer 20 are etched together, the first active layer part surface exposed by the first opening M1 and the first opening M2 is continuously in the etching environment when the fourth opening M4 is etched, which causes the first active layer to be damaged and the film to be reduced. The connection electrode L arranged in the same layer as the first electrode 71 and the second electrode 72 can be understood as being located on the surface of the same film layer, or being formed by the same patterning process.

[0085] The display substrate of the embodiment of the present disclosure is provided with an insulating protective layer 80 on the side of the third metal layer 70 away from the substrate P, the insulating protective layer 80 is provided with a third via hole K3 and a fourth via hole K4, the third via hole K3 penetrates the insulating protective layer 80 and the first insulating layer 20 to expose part of the surface of the first metal trace 11, the fourth via hole K4 exposes part of the surface of the second metal trace 52, the bridge electrode 91 is located on the side of the insulating protective layer 80 away from the substrate P, the third metal layer 70 is located on the side of the third insulating layer away from the substrate P, and the bridge electrode 91 is connected with the first metal trace 11 and the second metal trace 52 through the third via hole K3 and the fourth via hole K4, respectively. Figure 3 and Figure 4 As shown, the first metal trace 11 and the second metal trace 52 are connected by the bridge electrode 91, so that the first insulating layer 20 is not etched when the first via hole K1 and the second via hole K2 are formed in the third insulating layer 60, the first electrode 71 and the second electrode 72 are formed in the third metal layer 70 through the patterning process, and the insulating protective layer 80 is deposited on the side of the third metal layer 70 away from the substrate P, the insulating protective layer 80 is provided with a third via hole K3 and a fourth via hole K4, the third via hole K3 penetrates the insulating protective layer 80 and the first insulating layer 20 to expose part of the surface of the first metal trace 11, and the third metal layer 70 and the insulating protective layer 80 are on the first active layer 31 of the first via hole K1 and the second via hole K2 when the third via hole K3 is etched, which can protect the first active layer 31 from being exposed to the etching environment, thereby avoiding the damage to the first active layer 31 caused by the etching of the first insulating layer 20 and the third insulating layer 60 together in the related art, improving the film reduction of the first active layer 31, and improving the product yield and quality stability.

[0086] Exemplarily, the substrate P can be a transparent insulating substrate, such as a glass substrate, a quartz substrate, or other suitable substrates. The first insulating layer 10 serves as a buffer layer, and the material of the first insulating layer 20 can be an inorganic material, for example, the first insulating layer 20 can be one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0087] In one embodiment, the first metal layer 10 can be made of a light shielding material, and the first metal layer 10 can form a light shielding portion, so as to effectively shield the first active layer 31 and avoid light from irradiating on the first active layer 31 and causing the generation of carriers and leakage current.

[0088] Exemplarily, the material of the first metal layer 10 can include molybdenum, and the first metal layer 10 can be made of other metal materials or multi-layer composite metal materials. Exemplarily, the first metal layer 10 can also be made of one or more of titanium (Ti), copper (Cu), molybdenum-niobium alloy (MoNb), etc.

[0089] In one embodiment, the material of the second metal layer 50 can include one or more of molybdenum, copper, aluminum, titanium, or an alloy formed by any combination of the above metals, or other suitable materials.

[0090] Exemplarily, the second metal layer 50 can be a copper-based metal alloy with stable performance, such as copper-zinc alloy, copper-nickel alloy, or copper-zinc-nickel alloy, etc.

[0091] In one embodiment, the material of the bridge electrode 91 is a transparent conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), gallium zinc oxide (GZO), or carbon nanotube, etc.

[0092] The second insulating layer 40 is located on the side of the semiconductor layer 30 away from the substrate P, and the third insulating layer 60 is located on the side of the second metal layer 50 away from the substrate P, and the third insulating layer 60 is an interlayer insulating layer.

[0093] Exemplarily, the materials of the third insulating layer 60 and the second insulating layer 40 can both be inorganic materials, such as one or more combinations of silicon oxide, silicon nitride, or silicon oxynitride. The second insulating layer 40 and the third insulating layer 60 can be a single-layer structure composed of silicon nitride or silicon oxide, or a multi-layer structure composed of silicon nitride and silicon oxide.

[0094] Figure 6A For Figure 2 The microscope diagram of the connection position of the connection electrode and the first metal trace in the related art is shown. Referring to Figure 2 and Figure 6A As shown in FIGS. 1 and 2, the first metal trace 11 and the connection electrode L of the display substrate in the related art are connected, the first insulating layer 20 is provided with a fourth opening M4, the third insulating layer 60 is provided with a third opening M3, the connection electrode L is connected with the first metal trace 11 through the fourth opening M4 and the third opening M3, and the side wall angle of the section of the fourth opening M4 and the third opening M3 can be 50°.

[0095] Figure 6B ForFigure 2 A microscope diagram of the connection position of the connection electrode and the second metal trace in the related art is shown. Referring to Figure 2 and Figure 6B As shown, the second metal trace 52 and the connection electrode L of the display substrate in the related art are connected, the third insulating layer 60 is provided with a fifth opening M5, the connection electrode L is connected with the second metal trace 52 through the fifth opening M5, and the angle of the fifth opening M5 can be 39°.

[0096] Figure 6C A microscope diagram of the connection position of the first metal trace and the bridge electrode in an embodiment of the present disclosure is shown. Referring to Figure 6C In an embodiment, the side wall angle of the third via K3 profile is set to be unequal along the direction perpendicular to the substrate P by the first metal layer 10. For example, the side wall angle of the third via K3 profile of the portion of the first insulating layer 20 is greater than the side wall angle of the third via K3 profile of the portion of the fourth insulating layer 81, and the side wall angle of the third via K3 profile of the portion of the fifth insulating layer 83 is greater than the side wall angle of the third via K3 profile of the portion of the fourth insulating layer 81. In this way, the connection reliability of the bridge electrode 91 and the first metal trace 11 can be improved.

[0097] Exemplarily, the side wall angle of the third via K3 profile of the portion of the first insulating layer 20 can be 60-70°, the side wall angle of the third via K3 profile of the portion of the fourth insulating layer 81 can be 25-35°, and the side wall angle of the third via K3 profile of the portion of the fifth insulating layer 83 can be 70-80°. Exemplarily, the side wall angle of the third via K3 profile of the portion of the first insulating layer 20 can be 65° or 63°, the side wall angle of the third via K3 profile of the portion of the fourth insulating layer 81 can be 28° or 32°, and the side wall angle of the third via K3 profile of the portion of the fifth insulating layer 83 can be 70° or 71°.

[0098] Figure 6D A microscope diagram of the connection position of the second metal trace and the bridge electrode in an embodiment of the present disclosure is shown. Referring to Figure 6D In an embodiment, the side wall angle of the fourth via K4 profile is set to be unequal along the direction perpendicular to the substrate P by the second metal layer 52. For example, the side wall angle of the fourth via K4 profile formed by the portion of the fourth insulating layer 81 is less than the side wall angle of the fourth via K4 profile formed by the portion of the fifth insulating layer 83, so that the connection reliability of the second metal trace 52 and the bridge electrode 91 can be improved. For example, the side wall angle of the fourth via K4 profile formed by the portion of the fourth insulating layer 81 can be 30-40°, and the side wall angle of the fourth via K4 profile formed by the portion of the fifth insulating layer 83 can be 60-70°. Exemplarily, the side wall angle of the fourth via K4 profile formed by the portion of the fourth insulating layer 81 can be 34° or 35°, and the side wall angle of the fourth via K4 profile formed by the portion of the fifth insulating layer 83 can be 66° or 70°.

[0099] Figure 7 FIG. 6 is a cross-sectional view of a display substrate according to another embodiment of the present disclosure, and FIG. 7 is a plan view of the display substrate according to the embodiment of FIG. 6. Figure 7 In an embodiment, the third insulating layer 60 further has a fifth via K5 formed therethrough to expose a surface of the first insulating layer 20, and a projection of the third via K3 on the substrate P is located within a projection of the fifth via K5 on the substrate P, i.e., an aperture of the third via K3 is less than or equal to an aperture of the fifth via K5. The third insulating layer 60 further has a sixth via K6 formed therethrough, and a projection of the fourth via K4 on the substrate P is located within a projection of the sixth via K6 on the substrate P, i.e., an aperture of the fourth via K4 is less than an aperture of the sixth via K6.

[0100] In the embodiment shown in FIG. 6, the third via K3 is formed by etching the insulating protective layer 80, the third insulating layer 60 and the first insulating layer 20, which increases the etching time. Figure 4 In the embodiment shown in FIG. 6, the third via K3 is formed by etching the insulating protective layer 80, the third insulating layer 60 and the first insulating layer 20, which increases the etching time.

[0101] In the embodiment shown in FIG. 6, the fifth via K5 and the sixth via K6 are formed by etching together with the first via K1 and the second via K2, and the insulating protective layer 80 is deposited in the fifth via K5 and the sixth via K6, so that when the third via K3 is formed, only the insulating protective layer 80 and the first insulating layer 20 need to be etched, and the third insulating layer 60 does not need to be etched, which reduces the forming time of the third via K3, and does not need to change the number of masks used, and reduces the film thickness at the bridging position of the first metal trace 11 and the second metal trace 52. Figure 7

[0102] FIG. 8 is a plan view of a display substrate according to another embodiment of the present disclosure, Figure 8 FIG. 9 is a cross-sectional view of the display substrate according to the embodiment of FIG. 8 along line C-C. Figure 9 FIG. 9 is a cross-sectional view of the display substrate according to the embodiment of FIG. 8 along line C-C. Figure 8 In an embodiment, the display substrate further includes a pixel electrode 92 located in the display area A1, and the pixel electrode 92 is located on a side of the insulating protective layer 80 facing away from the substrate P, and the bridging electrode 91 is disposed in the same layer as the pixel electrode 92, i.e., the bridging electrode 91 and the pixel electrode 92 are formed by one patterning process, or the bridging electrode 91 and the pixel electrode 92 are located on the same film layer of the insulating protective layer 80. Figure 8 Figure 9 In an embodiment, the display substrate further includes a pixel electrode 92 located in the display area A1, and the pixel electrode 92 is located on a side of the insulating protective layer 80 facing away from the substrate P, and the bridging electrode 91 is disposed in the same layer as the pixel electrode 92, i.e., the bridging electrode 91 and the pixel electrode 92 are formed by one patterning process, or the bridging electrode 91 and the pixel electrode 92 are located on the same film layer of the insulating protective layer 80.

[0103] ​Exemplarily, the pixel electrode 92 is an electrode for a light-emitting pixel in a liquid crystal display device. For example, the pixel electrode 92 can be connected with a common electrode signal or connected with a drain of a thin film transistor to control liquid crystal deflection. In an organic light-emitting diode (OLED) display device, the pixel electrode 92 can also serve as an anode of an organic light-emitting diode of the display substrate to control the organic light-emitting diode to emit light.

[0104] Referring to Figure 9 In an embodiment, the display substrate further includes a non-display region A2 (the right part of the dashed line) outside the display region A1 (the left part of the dashed line), the first active layer 31 and the bridge electrode 91 are located in the non-display region A2, that is Figure 4 and Figure 7 The double-gate thin film transistor in the embodiment is located in the non-display region A2. The display substrate includes the first thin film transistor located in the display region A1 and the second thin film transistor located in the non-display region A2, and the second thin film transistor connects the first metal trace 11 and the second metal trace 52 through the bridge electrode 91 to form a double-gate thin film transistor. The double-gate thin film transistor can be used in a gate driving circuit (GOA circuit). The display region includes a plurality of pixel units, each of which includes a first thin film transistor, and the pixel electrode 92 and the bridge electrode 91 can be formed by a one-time patterning process through a transparent conductive layer, which can simplify the manufacturing process steps of the display substrate and improve the production capacity.

[0105] The first metal trace 11 and the second metal trace 52 of the second thin film transistor are connected through the bridge electrode 91, and the first metal layer and the second metal layer of the first thin film transistor in the display region are not connected, so that the aperture ratio of the display region can be avoided. By arranging the first active layer 31 and the bridge electrode 91 in the non-display region A2, the aperture ratio of the display substrate can be improved without affecting the aperture ratio of the display substrate.

[0106] Referring to Figure 9 In an embodiment, the semiconductor layer 30 further includes a second active layer 32 located in the display region A1, the second metal layer 50 further includes a second gate electrode 53 located in the display region A1, the third metal layer 70 further includes a third pole 73 and a fourth pole 74, the third insulating layer 60 is provided with a seventh via hole K7 and an eighth via hole K8, the seventh via hole K7 and the eighth via hole K8 both expose part of the surface of the second active layer 32, the third pole K7 and the fourth pole K8 are connected with the second active layer 32 through the seventh via hole K7 and the eighth via hole K8 respectively, and the insulating protective layer 80 is further provided with a ninth via hole K9, the ninth via hole K9 exposes at least part of the surface of the fourth pole 74, the pixel electrode 92 is connected with the fourth pole 74 through the ninth via hole K9, and the third pole 73 and the fourth pole 74 are controlled to be in communication through the second gate electrode 53, so as to control the display of the display region A1.

[0107] Exemplarily, the third electrode 72 can be a source electrode, and the fourth electrode 74 can be a drain electrode, or the third electrode 72 can be a drain electrode, and the fourth electrode 73 can be a source electrode.

[0108] It should be noted that the material of the first active layer 31 and the second active layer 32 can be the same, or the material of the first active layer 31 and the second active layer 32 can be different. The material of the first active layer 31 and the second active layer 32 can be any one of amorphous silicon, polycrystalline silicon, and oxide semiconductor.

[0109] Exemplarily, the material of the first active layer 31 can be polycrystalline silicon, and the material of the second active layer 32 can be oxide semiconductor, or the material of the first active layer 31 can be amorphous silicon, and the material of the second active layer 32 can be polycrystalline silicon, or the material of the first active layer 31 can be oxide semiconductor, and the material of the second active layer 32 can be polycrystalline silicon.

[0110] Exemplarily, the material of the first active layer 31 and the second active layer 32 can both be polycrystalline silicon, or the material of the first active layer 31 and the second active layer 32 can both be oxide semiconductor, or the material of the first active layer 31 and the second active layer 32 can both be amorphous silicon.

[0111] In one embodiment, the material of the semiconductor layer 30 includes oxide semiconductor, and the first active layer 31 and the second active layer 32 are formed by a one-time patterning process. Amorphous silicon has low mobility, polycrystalline silicon has poor uniformity, the process is complex and high in cost, is sensitive to visible light, and cannot work under visible light irradiation, so it is difficult to be used in large-size and high-resolution display substrates. The display substrate of the embodiment of the present disclosure adopts oxide semiconductor thin film transistors formed of oxide semiconductor material, for example, indium zinc gallium oxide semiconductor material, which has large mobility, good uniformity, low process temperature, high light transmittance in the visible light region, and is suitable for flexible display.

[0112] Exemplarily, the oxide semiconductor can be indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), or gallium zinc oxide (GZO), etc.

[0113] Reference Figure 9In an embodiment, the insulating protective layer 80 includes a fourth insulating layer 81 and a planar layer 82 which are sequentially stacked on a side of the third metal layer 70 away from the substrate P, and the insulating protective layer 80 is provided with a ninth via hole K9 which exposes at least part of the surface of the fourth electrode 74. The display substrate further includes a fifth insulating layer 83 on a side of the planar layer 82 away from the substrate P. The pixel electrode 92 includes a first transparent electrode 921 between the planar layer 82 and the fifth insulating layer 83, and a second transparent electrode 922 on a side of the fifth insulating layer 83 away from the substrate P. One of the first transparent electrode 921 and the second transparent electrode 922 is connected to the fourth electrode 74 through the ninth via hole K9. The bridge electrode 91 is provided in the same layer as the first transparent electrode 921 or the second transparent electrode 922.

[0114] For example, the planar layer 82 can be made of an organic material, such as photoresist or polyimide.

[0115] The display substrate of the embodiment of the present disclosure provides the bridge electrode 91 in the same layer as the first transparent electrode 921 or the second transparent electrode 922, without increasing the number of masks. In the embodiment of FIG. 6, the bridge electrode 91 is provided in the same layer as the second transparent electrode 922. The first transparent electrode 921 is connected to the common electrode signal, and the second transparent electrode 922 is connected to the drain of the first thin film transistor.

[0116] Referring to Figure 9 In an embodiment, the first metal layer 10 further includes a light shielding portion 12, and the second active layer 32 includes a second channel region, a normal projection of the second channel region on the substrate P being located within a normal projection of the light shielding portion 12 on the substrate P. The light shielding portion 12 can prevent light from irradiating the second channel region of the second active layer 32, thereby preventing the generation of carriers and leakage current. The light shielding portion 12 and the first metal trace 11 are provided in the same layer, and can be formed by the same patterning process.

[0117] Another embodiment of the present disclosure provides a preparation method of a display substrate, the method comprising: forming a first metal layer 10 on one side of a substrate P, the first metal layer 10 comprising a first metal trace 11; forming a first insulating layer 20 on a side of the first metal layer 10 away from the substrate P; forming a semiconductor layer 30 on a side of the first insulating layer 20 away from the substrate P, the semiconductor layer 30 comprising a first active layer 31, the first active layer 31 comprising a first channel region, a footprint of the first channel region on the substrate P being located within a footprint of the first metal trace 11 on the substrate P; forming a second insulating layer 40 on a side of the semiconductor layer 30 away from the substrate P; forming a second metal layer 50 on a side of the second insulating layer 40 away from the substrate P, the second metal layer 50 comprising a first gate electrode 51 and a second metal trace 52, the second metal trace 52 being connected to the first gate electrode 51; forming a third insulating layer 60 on a side of the second metal layer 50 away from the substrate P, the third insulating layer 60 being provided with a first via hole K1 and a second via hole K2, the first via hole K1 and the second via hole K2 both exposing part of a surface of the first active layer 31; forming a third metal layer 70 on a side of the third insulating layer 60 away from the substrate P, the third metal layer 70 comprising a first electrode 71 and a second electrode 72, the first electrode 71 and the second electrode 72 being connected to the first active layer 31 through the first via hole K1 and the second via hole K2 respectively; forming an insulating protective layer 80 on a side of the third metal layer 70 away from the substrate P, the insulating protective layer 80 being provided with a third via hole K3 and a fourth via hole K4, the third via hole K3 penetrating through the insulating protective layer 80 and the first insulating layer 20 to expose part of a surface of the first metal trace 11, the fourth via hole K4 exposing part of a surface of the first gate electrode 51; and forming a bridge electrode 91 on a side of the insulating protective layer 80 away from the substrate P, the bridge electrode 91 being connected to the first metal trace 11 and the second metal trace 52 through the third via hole K3 and the fourth via hole K4 respectively.

[0118] The display substrate formed by the preparation method of the display substrate according to the embodiments of the present disclosure can avoid damage to the semiconductor layer caused by etching of the third insulating layer and the first insulating layer together in the related art, improve the semiconductor layer film, and improve the yield.

[0119] The preparation method of the display substrate according to the embodiments of the present disclosure comprises: in the process of forming the third insulating layer 60, a fifth via hole K5 and a sixth via hole K6 penetrating through the third insulating layer 60 are also formed, the fifth via hole K5 exposing a surface of the first insulating layer 20, a footprint of the third via hole K3 on the substrate P being located within a footprint of the fifth via hole K5 on the substrate P; a footprint of the fourth via hole K4 on the substrate P being located within a footprint of the sixth via hole K6 on the substrate P.

[0120] The following describes an embodiment of the present disclosure Figure 9The preparation process of the display substrate is further used to illustrate the technical solutions of the embodiments of the present disclosure. It can be understood that, in the present disclosure, the "patterning process" can include coating photoresist, mask exposure, development, etching, stripping photoresist, and the like when the material to be patterned is an inorganic material or a metal layer. When the material to be patterned is an organic material (for example, photoresist or organic resin), the "patterning process" can include mask exposure, development processing, and the like. The evaporation, deposition, coating, and the like in the present disclosure are all mature preparation processes in the related art.

[0121] A metal thin film is deposited on one side of the substrate P to form a first metal layer 10. A patterning process is performed on the first metal layer 10, thereby forming a first metal trace 11 and a light shielding portion 12 on the substrate P, and the first metal trace 11 and the light shielding portion 12 are arranged at intervals. The substrate P can be a glass substrate, a quartz substrate, or other suitable materials. The material of the first metal layer 10 can be one or a combination of titanium (Ti), copper (Cu), molybdenum-niobium alloy (MoNb), and the like.

[0122] An insulating layer thin film is deposited on the substrate P on which the light shielding portion 12 and the first metal trace 11 are formed, and a first insulating layer 20 is formed by a patterning process. The material of the first insulating layer 20 can be one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0123] A semiconductor layer thin film is deposited on the side of the first insulating layer 20 away from the substrate P, and a first active layer 31 and a second active layer 32 are formed by a patterning process. The first active layer 31 is located in the non-display area A1, and the second active layer 32 is located in the display area A2. The first active layer 31 includes a first channel region, and the orthogonal projection of the first channel region on the substrate P is located within the orthogonal projection of the first metal trace 11 on the substrate P. The second active layer 32 includes a second channel region, and the orthogonal projection of the second channel region on the substrate P is located within the orthogonal projection of the light shielding portion 12 on the substrate P. Exemplarily, the materials of the first active layer 31 and the second active layer 32 are both oxide semiconductors.

[0124] An insulating layer thin film is deposited on the side of the first active layer 31 and the second active layer 32 away from the substrate P, and a second insulating layer 40 is formed by a patterning process. The material of the second insulating layer 40 can be one or a combination of silicon oxide, silicon nitride, or silicon oxynitride.

[0125] A layer of metal film is deposited on the side of the second insulating layer 40 facing away from the substrate P to form a second metal layer 50. The second metal layer 50 is patterned to form a first gate electrode 51, a second metal trace 52, and a second gate electrode 53. The second metal trace 52 is connected to the first gate electrode 51. The second insulating layer is patterned by top gate self-alignment, and the exposed semiconductor layer is treated to be conductive by ion implantation, plasma treatment, or the like. The material of the second metal layer 50 can include one of molybdenum, copper, aluminum, titanium, or an alloy formed by any combination of the above metals.

[0126] Figure 10 A third insulating layer of the display substrate of the embodiment of the present disclosure is etched to form a via hole. As shown in Figure 11 An insulating layer film is deposited on the side of the second metal layer 50 facing away from the substrate P, and a third insulating layer 60 is formed by a patterning process. The first via hole K1, the second via hole K2, the fifth via hole K5, the sixth via hole K6, the seventh via hole K7, and the eighth via hole K8 are formed through the third insulating layer 60 by an etching process during the formation of the third insulating layer 60. The first via hole K1 and the second via hole K2 both expose part of the surface of the first active layer 31. The seventh via hole K7 and the eighth via hole K8 both expose part of the surface of the second active layer 32. The fifth via hole K5 exposes the surface of the first insulating layer 20.

[0127] A layer of metal film is deposited on the side of the third insulating layer 60 facing away from the substrate P to form a third metal layer 70. The third metal layer 70 is patterned to form a first electrode 71, a second electrode 72, a third electrode 73, and a fourth electrode 74. The first electrode 71 and the second electrode 72 are connected to the first active layer 31 through the first via hole K1 and the second via hole K2, respectively. The third electrode 73 and the fourth electrode 74 are connected to the second active layer 32 through the seventh via hole K7 and the eighth via hole K8.

[0128] Figure 11 A schematic diagram of the insulating protective layer of the display substrate of the embodiment of the present disclosure without etching a via hole is shown in Figure 12 A schematic diagram of the insulating protective layer of the display substrate of the embodiment of the present disclosure after etching a via hole is shown in Figure 11 and Figure 12As shown, a layer of insulating layer film is deposited on the side of the third metal layer 70 away from the substrate base plate P, forming a fourth insulating layer 81, and an organic material film is deposited on the side of the fourth insulating layer 81 away from the substrate base plate P, and the organic material film is subjected to a patterning process to remove the organic material at the positions of the fifth via hole K5, the sixth via hole K6 and the ninth via hole K9, forming a planar layer 82; a metal film is deposited on the side of the planar layer 82 away from the substrate base plate P to form a first transparent electrode 921; an insulating film layer is deposited on the side of the first transparent electrode 921 away from the substrate base plate P to form a fifth insulating layer 83, and the insulating protective layer 80 can include the fourth insulating layer 81, the planar layer 82 and the fifth insulating layer 83, and the third via hole K3, the fourth via hole K4 and the ninth via hole K9 are formed in the insulating protective layer, the third via hole K3 exposes part of the surface of the first metal trace 11 through the insulating protective layer 80 and the first insulating layer 20, and the fourth via hole K4 exposes part of the surface of the first gate electrode 51. The orthographic projection of the third via hole K3 on the substrate base plate P is located within the orthographic projection of the fifth via hole K5 on the substrate base plate P. The orthographic projection of the fourth via hole K4 on the substrate base plate P is located within the orthographic projection of the sixth via hole K6 on the substrate base plate P. The ninth via hole K9 exposes at least part of the surface of the fourth electrode 74.

[0129] A transparent metal film is deposited on the side of the fifth insulating layer 83 away from the substrate base plate P, and the transparent metal film is subjected to a patterning process to form a second transparent electrode 922 and a bridge electrode 91, the second transparent electrode 922 is connected to the fourth electrode 74 through the ninth via hole K9, the first transparent electrode 921 and the second transparent electrode 922 form a pixel electrode, and the bridge electrode 91 is connected to the first metal trace 11 and the second metal trace 52 through the third via hole K3 and the fourth via hole K4, respectively.

[0130] A display device according to another embodiment of the present disclosure includes the display substrate according to any of the embodiments of the present disclosure.

[0131] The display device according to the embodiments of the present disclosure can be any product or component having a display and touch function, such as a smart phone, a wearable smart watch, smart glasses, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a vehicle-mounted display, an electronic book, a biometric identification device such as a smart skin device, a soft robot and a biomedical device, etc.

[0132] The display device according to the embodiments of the present disclosure adopts the display substrate according to the first aspect of the present disclosure, and can avoid damage to the active layer caused by forming a bridge hole in the related art without affecting the characteristics of the thin film transistor, the aperture ratio, etc., improve the active layer film, improve the yield of the product, and improve the performance and competitiveness of the product.

[0133] The display substrate and display device of the above embodiments can adopt various technical solutions known to those skilled in the art at present and in the future, and will not be described in detail here.

[0134] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.

[0135] In addition, the terms "first" and "second" are only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.

[0136] In the present disclosure, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixed connection, or detachable connection, or integral; it can be mechanical connection, or electrical connection, or communication; it can be direct connection, or indirect connection through intermediate medium, or internal communication of two elements or interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0137] In the present disclosure, unless otherwise explicitly specified and limited, the first feature "above" or "below" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "above", "above" and "above" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "below" and "below" the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0138] The above disclosure provides many different embodiments or examples for implementing various aspects of the present disclosure. For simplicity of the disclosure, the foregoing description has focused on certain examples and / or on certain aspects of the examples. In the interest of clarity, not all aspects of the examples have been described. It will be appreciated that those skilled in the relevant arts will be able to devise many alternative arrangements, which have not been described in order to simplify and focus the present disclosure. Further, all the various embodiments described throughout this disclosure can be used in combination, and one of ordinary skill will understand that the various embodiments described throughout this disclosure can be used in combination. Additionally, the disclosure can refer to a number of items throughout the specification, which are not necessarily all listed in the summary. These items can be referred to throughout the specification, which should be understood to imply that these items are included in the disclosure. Conversely, these items can be referred to throughout the specification, which should be understood to imply that these items are excluded from the disclosure.

[0139] The above merely provides specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of various changes or replacements within the technical scope disclosed by the present disclosure, and these should be encompassed within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, characterized by, The display substrate comprises: a first metal layer located on one side of a substrate substrate, the first metal layer comprising a first metal trace; a first insulating layer located on a side of the first metal layer away from the substrate substrate; a semiconductor layer located on a side of the first insulating layer away from the substrate substrate, the semiconductor comprising a first active layer, the first active layer comprising a first channel region, a projection of the first channel region on the substrate substrate being located within a projection of the first metal trace on the substrate substrate; a second insulating layer located on a side of the semiconductor layer away from the substrate substrate; a second metal layer located on a side of the second insulating layer away from the substrate substrate, the second metal layer comprising a first gate electrode and a second metal trace, the second metal trace being connected to the first gate electrode; a third insulating layer located on a side of the second metal layer away from the substrate substrate, the third insulating layer being provided with a first via hole and a second via hole, the first via hole and the second via hole both exposing part of a surface of the first active layer; a third metal layer located on a side of the third insulating layer away from the substrate substrate, the third metal layer comprising a first electrode and a second electrode, the first electrode and the second electrode being connected to the first active layer through the first via hole and the second via hole respectively; an insulating protective layer located on a side of the third metal layer away from the substrate substrate, the insulating protective layer being provided with a third via hole and a fourth via hole, the third via hole penetrating through the insulating protective layer and the first insulating layer to expose part of a surface of the first metal trace, the fourth via hole exposing part of a surface of the second metal trace; a bridging electrode located on a side of the insulating protective layer away from the substrate substrate, the bridging electrode being connected to the first metal trace and the second metal trace through the third via hole and the fourth via hole respectively.

2. The display substrate of claim 1, wherein, The third insulating layer is further provided with a fifth via hole, the fifth via hole penetrating through the third insulating layer to expose a surface of the first insulating layer, a projection of the third via hole on the substrate substrate being located within a projection of the fifth via hole on the substrate substrate; The third insulating layer is further provided with a sixth via hole, a projection of the fourth via hole on the substrate substrate being located within a projection of the sixth via hole on the substrate substrate. 3.The display substrate of claim 1, wherein, The display substrate further comprises a pixel electrode located in a display region, the pixel electrode being located on a side of the insulating protective layer away from the substrate substrate, the bridging electrode and the pixel electrode being provided in the same layer.

4. The display substrate of claim 3, wherein, The display substrate further comprises a non-display region outside the display region, the first active layer and the bridging electrode being located in the non-display region.

5. The display substrate of claim 4, wherein, The semiconductor layer further comprises a second active layer located in the display area, the second metal layer further comprises a second gate electrode located in the display area, the third metal layer further comprises a third pole and a fourth pole, the third insulating layer is provided with a seventh via hole and an eighth via hole, the seventh via hole and the eighth via hole both expose part of the surface of the second active layer, and the third pole and the fourth pole are connected with the second active layer through the seventh via hole and the eighth via hole respectively. The insulating protective layer is further provided with a ninth via hole, the ninth via hole exposes at least part of the surface of the fourth pole, and the pixel electrode is connected with the fourth pole through the ninth via hole. 6.The display substrate of claim 5, wherein, The first metal layer further comprises an optical shielding part, and the second active layer comprises a second channel region, a projection of the second channel region on the substrate substrate is located in a projection of the optical shielding part on the substrate substrate. 7.The display substrate of claim 5, wherein, The insulating protective layer comprises a fourth insulating layer and a planar layer which are sequentially stacked on a side of the third metal layer away from the substrate substrate, the insulating protective layer is further provided with a ninth via hole, the ninth via hole exposes at least part of the surface of the fourth pole, the display substrate further comprises a fifth insulating layer located on a side of the planar layer away from the substrate substrate, the pixel electrode comprises a first transparent electrode located between the planar layer and the fifth insulating layer and a second transparent electrode located on a side of the fifth insulating layer away from the substrate substrate, one of the first transparent electrode and the second transparent electrode is connected with the fourth pole through the ninth via hole, and the bridge electrode is arranged in the same layer as the first transparent electrode or the second transparent electrode. 8.The display substrate of claim 1, wherein, The material of the semiconductor layer comprises an oxide semiconductor.

9. A method for preparing a display substrate, characterized in that, Comprise: a first metal layer is formed on one side of a substrate substrate, the first metal layer comprises a first metal trace; a first insulating layer is formed on a side of the first metal layer away from the substrate substrate; a semiconductor layer is formed on a side of the first insulating layer away from the substrate substrate, the semiconductor layer comprises a first active layer, the first active layer comprises a first channel region, and a projection of the first channel region on the substrate substrate is located in a projection of the first metal trace on the substrate substrate; a second insulating layer is formed on a side of the semiconductor layer away from the substrate substrate; a second metal layer is formed on a side of the second insulating layer away from the substrate substrate, the second metal layer comprises a first gate electrode and a second metal trace, and the second metal trace is connected with the first gate electrode; a third insulating layer is formed on a side of the second metal layer away from the substrate substrate, the third insulating layer is provided with a first via hole and a second via hole, and the first via hole and the second via hole both expose part of the surface of the first active layer; a third metal layer is formed on a side of the third insulating layer away from the substrate substrate, the third metal layer comprises a first pole and a second pole, and the first pole and the second pole are connected with the first active layer through the first via hole and the second via hole respectively; An insulating protective layer is formed on a side of the third metal layer facing away from the substrate substrate, the insulating protective layer is provided with a third via hole and a fourth via hole, the third via hole exposes part of a surface of the first metal trace through the insulating protective layer and the first insulating layer, and the fourth via hole exposes part of a surface of the first gate electrode; A bridge electrode is formed on a side of the insulating protective layer facing away from the substrate substrate, the bridge electrode is connected with the first metal trace and the second metal trace through the third via hole and the fourth via hole respectively.

10. The method of manufacturing a display substrate according to claim 9, wherein The display substrate comprises A fifth via hole and a sixth via hole are formed through the third insulating layer in the process of forming the third insulating layer, the fifth via hole exposes a surface of the first insulating layer, and a projection of the third via hole on the substrate substrate is located in a projection of the fifth via hole on the substrate substrate; A projection of the fourth via hole on the substrate substrate is located in a projection of the sixth via hole on the substrate substrate.

11. A display device comprising: The display substrate comprises any one of claims 1 to 8.

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